1 |
dirtyepic 11/01/19 06:11:54 |
2 |
|
3 |
Modified: README.history |
4 |
Added: 60_all_4.4.5_hppa-wrong-code.patch |
5 |
Log: |
6 |
Add HPPA patches for bug #349113 to 4.4.4 and 4.4.5. |
7 |
|
8 |
Revision Changes Path |
9 |
1.15 src/patchsets/gcc/4.4.4/gentoo/README.history |
10 |
|
11 |
file : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.4.4/gentoo/README.history?rev=1.15&view=markup |
12 |
plain: http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.4.4/gentoo/README.history?rev=1.15&content-type=text/plain |
13 |
diff : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.4.4/gentoo/README.history?r1=1.14&r2=1.15 |
14 |
|
15 |
Index: README.history |
16 |
=================================================================== |
17 |
RCS file: /var/cvsroot/gentoo/src/patchsets/gcc/4.4.4/gentoo/README.history,v |
18 |
retrieving revision 1.14 |
19 |
retrieving revision 1.15 |
20 |
diff -u -r1.14 -r1.15 |
21 |
--- README.history 29 Nov 2010 20:45:11 -0000 1.14 |
22 |
+++ README.history 19 Jan 2011 06:11:54 -0000 1.15 |
23 |
@@ -1,3 +1,6 @@ |
24 |
+1.4 pending |
25 |
+ + 60_all_4.4.5_hppa-wrong-code.patch |
26 |
+ |
27 |
1.3 29.11.2010 |
28 |
+ 05_all_gcc44-pr46173-all-tree.patch |
29 |
|
30 |
|
31 |
|
32 |
|
33 |
1.1 src/patchsets/gcc/4.4.4/gentoo/60_all_4.4.5_hppa-wrong-code.patch |
34 |
|
35 |
file : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.4.4/gentoo/60_all_4.4.5_hppa-wrong-code.patch?rev=1.1&view=markup |
36 |
plain: http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.4.4/gentoo/60_all_4.4.5_hppa-wrong-code.patch?rev=1.1&content-type=text/plain |
37 |
|
38 |
Index: 60_all_4.4.5_hppa-wrong-code.patch |
39 |
=================================================================== |
40 |
[HPPA] Wrong code is generated for conditional branch followed by zero length asm |
41 |
|
42 |
http://gcc.gnu.org/PR46915 |
43 |
https://bugs.gentoo.org/349113 |
44 |
|
45 |
--- a/gcc/config/pa/pa.c |
46 |
+++ b/gcc/config/pa/pa.c |
47 |
@@ -6118,6 +6118,95 @@ pa_scalar_mode_supported_p (enum machine_mode mode) |
48 |
} |
49 |
} |
50 |
|
51 |
+/* Return TRUE if INSN, a jump insn, has an unfilled delay slot and |
52 |
+ it branches into the delay slot. Otherwise, return FALSE. */ |
53 |
+ |
54 |
+static bool |
55 |
+branch_to_delay_slot_p (rtx insn) |
56 |
+{ |
57 |
+ rtx jump_insn; |
58 |
+ |
59 |
+ if (dbr_sequence_length ()) |
60 |
+ return FALSE; |
61 |
+ |
62 |
+ jump_insn = next_active_insn (JUMP_LABEL (insn)); |
63 |
+ while (insn) |
64 |
+ { |
65 |
+ insn = next_active_insn (insn); |
66 |
+ if (jump_insn == insn) |
67 |
+ return TRUE; |
68 |
+ |
69 |
+ /* We can't rely on the length of asms. So, we return FALSE when |
70 |
+ the branch is followed by an asm. */ |
71 |
+ if (!insn |
72 |
+ || GET_CODE (PATTERN (insn)) == ASM_INPUT |
73 |
+ || asm_noperands (PATTERN (insn)) >= 0 |
74 |
+ || get_attr_length (insn) > 0) |
75 |
+ break; |
76 |
+ } |
77 |
+ |
78 |
+ return FALSE; |
79 |
+} |
80 |
+ |
81 |
+/* Return TRUE if INSN, a forward jump insn, needs a nop in its delay slot. |
82 |
+ |
83 |
+ This occurs when INSN has an unfilled delay slot and is followed |
84 |
+ by an asm. Disaster can occur if the asm is empty and the jump |
85 |
+ branches into the delay slot. So, we add a nop in the delay slot |
86 |
+ when this occurs. */ |
87 |
+ |
88 |
+static bool |
89 |
+branch_needs_nop_p (rtx insn) |
90 |
+{ |
91 |
+ rtx jump_insn; |
92 |
+ |
93 |
+ if (dbr_sequence_length ()) |
94 |
+ return FALSE; |
95 |
+ |
96 |
+ jump_insn = next_active_insn (JUMP_LABEL (insn)); |
97 |
+ while (insn) |
98 |
+ { |
99 |
+ insn = next_active_insn (insn); |
100 |
+ if (!insn || jump_insn == insn) |
101 |
+ return TRUE; |
102 |
+ |
103 |
+ if (!(GET_CODE (PATTERN (insn)) == ASM_INPUT |
104 |
+ || asm_noperands (PATTERN (insn)) >= 0) |
105 |
+ && get_attr_length (insn) > 0) |
106 |
+ break; |
107 |
+ } |
108 |
+ |
109 |
+ return FALSE; |
110 |
+} |
111 |
+ |
112 |
+/* Return TRUE if INSN, a forward jump insn, can use nullification |
113 |
+ to skip the following instruction. This avoids an extra cycle due |
114 |
+ to a mis-predicted branch when we fall through. */ |
115 |
+ |
116 |
+static bool |
117 |
+use_skip_p (rtx insn) |
118 |
+{ |
119 |
+ rtx jump_insn = next_active_insn (JUMP_LABEL (insn)); |
120 |
+ |
121 |
+ while (insn) |
122 |
+ { |
123 |
+ insn = next_active_insn (insn); |
124 |
+ |
125 |
+ /* We can't rely on the length of asms, so we can't skip asms. */ |
126 |
+ if (!insn |
127 |
+ || GET_CODE (PATTERN (insn)) == ASM_INPUT |
128 |
+ || asm_noperands (PATTERN (insn)) >= 0) |
129 |
+ break; |
130 |
+ if (get_attr_length (insn) == 4 |
131 |
+ && jump_insn == next_active_insn (insn)) |
132 |
+ return TRUE; |
133 |
+ if (get_attr_length (insn) > 0) |
134 |
+ break; |
135 |
+ } |
136 |
+ |
137 |
+ return FALSE; |
138 |
+} |
139 |
+ |
140 |
/* This routine handles all the normal conditional branch sequences we |
141 |
might need to generate. It handles compare immediate vs compare |
142 |
register, nullification of delay slots, varying length branches, |
143 |
@@ -6129,7 +6218,7 @@ const char * |
144 |
output_cbranch (rtx *operands, int negated, rtx insn) |
145 |
{ |
146 |
static char buf[100]; |
147 |
- int useskip = 0; |
148 |
+ bool useskip; |
149 |
int nullify = INSN_ANNULLED_BRANCH_P (insn); |
150 |
int length = get_attr_length (insn); |
151 |
int xdelay; |
152 |
@@ -6143,7 +6232,7 @@ output_cbranch (rtx *operands, int negated, rtx insn) |
153 |
slot and the same branch target as this branch. We could check |
154 |
for this but jump optimization should eliminate nop jumps. It |
155 |
is always safe to emit a nop. */ |
156 |
- if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
157 |
+ if (branch_to_delay_slot_p (insn)) |
158 |
return "nop"; |
159 |
|
160 |
/* The doubleword form of the cmpib instruction doesn't have the LEU |
161 |
@@ -6167,12 +6256,7 @@ output_cbranch (rtx *operands, int negated, rtx insn) |
162 |
/* A forward branch over a single nullified insn can be done with a |
163 |
comclr instruction. This avoids a single cycle penalty due to |
164 |
mis-predicted branch if we fall through (branch not taken). */ |
165 |
- if (length == 4 |
166 |
- && next_real_insn (insn) != 0 |
167 |
- && get_attr_length (next_real_insn (insn)) == 4 |
168 |
- && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) |
169 |
- && nullify) |
170 |
- useskip = 1; |
171 |
+ useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE; |
172 |
|
173 |
switch (length) |
174 |
{ |
175 |
@@ -6192,7 +6276,12 @@ output_cbranch (rtx *operands, int negated, rtx insn) |
176 |
if (useskip) |
177 |
strcat (buf, " %2,%r1,%%r0"); |
178 |
else if (nullify) |
179 |
- strcat (buf, ",n %2,%r1,%0"); |
180 |
+ { |
181 |
+ if (branch_needs_nop_p (insn)) |
182 |
+ strcat (buf, ",n %2,%r1,%0%#"); |
183 |
+ else |
184 |
+ strcat (buf, ",n %2,%r1,%0"); |
185 |
+ } |
186 |
else |
187 |
strcat (buf, " %2,%r1,%0"); |
188 |
break; |
189 |
@@ -6455,7 +6544,7 @@ const char * |
190 |
output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which) |
191 |
{ |
192 |
static char buf[100]; |
193 |
- int useskip = 0; |
194 |
+ bool useskip; |
195 |
int nullify = INSN_ANNULLED_BRANCH_P (insn); |
196 |
int length = get_attr_length (insn); |
197 |
int xdelay; |
198 |
@@ -6465,7 +6554,7 @@ output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which) |
199 |
is only used when optimizing; jump optimization should eliminate the |
200 |
jump. But be prepared just in case. */ |
201 |
|
202 |
- if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
203 |
+ if (branch_to_delay_slot_p (insn)) |
204 |
return "nop"; |
205 |
|
206 |
/* If this is a long branch with its delay slot unfilled, set `nullify' |
207 |
@@ -6481,13 +6570,7 @@ output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which) |
208 |
/* A forward branch over a single nullified insn can be done with a |
209 |
extrs instruction. This avoids a single cycle penalty due to |
210 |
mis-predicted branch if we fall through (branch not taken). */ |
211 |
- |
212 |
- if (length == 4 |
213 |
- && next_real_insn (insn) != 0 |
214 |
- && get_attr_length (next_real_insn (insn)) == 4 |
215 |
- && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) |
216 |
- && nullify) |
217 |
- useskip = 1; |
218 |
+ useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE; |
219 |
|
220 |
switch (length) |
221 |
{ |
222 |
@@ -6511,11 +6594,21 @@ output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which) |
223 |
if (useskip) |
224 |
strcat (buf, " %0,%1,1,%%r0"); |
225 |
else if (nullify && negated) |
226 |
- strcat (buf, ",n %0,%1,%3"); |
227 |
+ { |
228 |
+ if (branch_needs_nop_p (insn)) |
229 |
+ strcat (buf, ",n %0,%1,%3%#"); |
230 |
+ else |
231 |
+ strcat (buf, ",n %0,%1,%3"); |
232 |
+ } |
233 |
else if (nullify && ! negated) |
234 |
- strcat (buf, ",n %0,%1,%2"); |
235 |
+ { |
236 |
+ if (branch_needs_nop_p (insn)) |
237 |
+ strcat (buf, ",n %0,%1,%2%#"); |
238 |
+ else |
239 |
+ strcat (buf, ",n %0,%1,%2"); |
240 |
+ } |
241 |
else if (! nullify && negated) |
242 |
- strcat (buf, "%0,%1,%3"); |
243 |
+ strcat (buf, " %0,%1,%3"); |
244 |
else if (! nullify && ! negated) |
245 |
strcat (buf, " %0,%1,%2"); |
246 |
break; |
247 |
@@ -6636,7 +6729,7 @@ const char * |
248 |
output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which) |
249 |
{ |
250 |
static char buf[100]; |
251 |
- int useskip = 0; |
252 |
+ bool useskip; |
253 |
int nullify = INSN_ANNULLED_BRANCH_P (insn); |
254 |
int length = get_attr_length (insn); |
255 |
int xdelay; |
256 |
@@ -6646,7 +6739,7 @@ output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which) |
257 |
is only used when optimizing; jump optimization should eliminate the |
258 |
jump. But be prepared just in case. */ |
259 |
|
260 |
- if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
261 |
+ if (branch_to_delay_slot_p (insn)) |
262 |
return "nop"; |
263 |
|
264 |
/* If this is a long branch with its delay slot unfilled, set `nullify' |
265 |
@@ -6662,13 +6755,7 @@ output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which) |
266 |
/* A forward branch over a single nullified insn can be done with a |
267 |
extrs instruction. This avoids a single cycle penalty due to |
268 |
mis-predicted branch if we fall through (branch not taken). */ |
269 |
- |
270 |
- if (length == 4 |
271 |
- && next_real_insn (insn) != 0 |
272 |
- && get_attr_length (next_real_insn (insn)) == 4 |
273 |
- && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) |
274 |
- && nullify) |
275 |
- useskip = 1; |
276 |
+ useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE; |
277 |
|
278 |
switch (length) |
279 |
{ |
280 |
@@ -6692,11 +6779,21 @@ output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which) |
281 |
if (useskip) |
282 |
strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}"); |
283 |
else if (nullify && negated) |
284 |
- strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}"); |
285 |
+ { |
286 |
+ if (branch_needs_nop_p (insn)) |
287 |
+ strcat (buf, "{,n %0,%3%#|,n %0,%%sar,%3%#}"); |
288 |
+ else |
289 |
+ strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}"); |
290 |
+ } |
291 |
else if (nullify && ! negated) |
292 |
- strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}"); |
293 |
+ { |
294 |
+ if (branch_needs_nop_p (insn)) |
295 |
+ strcat (buf, "{,n %0,%2%#|,n %0,%%sar,%2%#}"); |
296 |
+ else |
297 |
+ strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}"); |
298 |
+ } |
299 |
else if (! nullify && negated) |
300 |
- strcat (buf, "{%0,%3|%0,%%sar,%3}"); |
301 |
+ strcat (buf, "{ %0,%3| %0,%%sar,%3}"); |
302 |
else if (! nullify && ! negated) |
303 |
strcat (buf, "{ %0,%2| %0,%%sar,%2}"); |
304 |
break; |
305 |
@@ -6818,7 +6915,7 @@ output_dbra (rtx *operands, rtx insn, int which_alternative) |
306 |
/* A conditional branch to the following instruction (e.g. the delay slot) is |
307 |
asking for a disaster. Be prepared! */ |
308 |
|
309 |
- if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
310 |
+ if (branch_to_delay_slot_p (insn)) |
311 |
{ |
312 |
if (which_alternative == 0) |
313 |
return "ldo %1(%0),%0"; |
314 |
@@ -6855,7 +6952,12 @@ output_dbra (rtx *operands, rtx insn, int which_alternative) |
315 |
{ |
316 |
case 4: |
317 |
if (nullify) |
318 |
- return "addib,%C2,n %1,%0,%3"; |
319 |
+ { |
320 |
+ if (branch_needs_nop_p (insn)) |
321 |
+ return "addib,%C2,n %1,%0,%3%#"; |
322 |
+ else |
323 |
+ return "addib,%C2,n %1,%0,%3"; |
324 |
+ } |
325 |
else |
326 |
return "addib,%C2 %1,%0,%3"; |
327 |
|
328 |
@@ -6963,7 +7065,7 @@ output_movb (rtx *operands, rtx insn, int which_alternative, |
329 |
/* A conditional branch to the following instruction (e.g. the delay slot) is |
330 |
asking for a disaster. Be prepared! */ |
331 |
|
332 |
- if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
333 |
+ if (branch_to_delay_slot_p (insn)) |
334 |
{ |
335 |
if (which_alternative == 0) |
336 |
return "copy %1,%0"; |
337 |
@@ -7001,7 +7103,12 @@ output_movb (rtx *operands, rtx insn, int which_alternative, |
338 |
{ |
339 |
case 4: |
340 |
if (nullify) |
341 |
- return "movb,%C2,n %1,%0,%3"; |
342 |
+ { |
343 |
+ if (branch_needs_nop_p (insn)) |
344 |
+ return "movb,%C2,n %1,%0,%3%#"; |
345 |
+ else |
346 |
+ return "movb,%C2,n %1,%0,%3"; |
347 |
+ } |
348 |
else |
349 |
return "movb,%C2 %1,%0,%3"; |