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To:	weeve@g.o
From:	"David S. Miller" <davem@...>
Subject:	Re: 2.6 kernel and docs
Date:	Tue, 05 Jul 2005 21:35:27 -0400 (EDT)

Nevermind, I found the bug.  I subtly broke UltraSPARC-III and
later chips by accident.

This patch should fix it:

[SPARC64]: Fix __cheetah_flush_tlb_pending instruction count.

The recent membar changes broke the UltraSPARC-III code patching.

Signed-off-by: David S. Miller <davem@...>

--- 1/arch/sparc64/mm/ultra.S.~1~	2005-07-05 17:16:49.000000000 -0700
+++ 2/arch/sparc64/mm/ultra.S	2005-07-05 18:32:05.000000000 -0700
@@ -249,7 +249,7 @@
 	retl
 	 wrpr		%g7, 0x0, %pstate
 
-__cheetah_flush_tlb_pending:	/* 22 insns */
+__cheetah_flush_tlb_pending:	/* 23 insns */
 	/* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
 	rdpr		%pstate, %g7
 	sllx		%o1, 3, %o1
@@ -317,7 +317,7 @@
 	sethi		%hi(__cheetah_flush_tlb_pending), %o1
 	or		%o1, %lo(__cheetah_flush_tlb_pending), %o1
 	call		cheetah_patch_one
-	 mov		22, %o2
+	 mov		23, %o2
 
 #ifdef DCACHE_ALIASING_POSSIBLE
 	sethi		%hi(__flush_dcache_page), %o0
-- 
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Updated Jun 17, 2009

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