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From: Josh Grebe <squash@g.o> |
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Date: Wed, 29 Jun 2005 12:34:27 -0500 |
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> I'm sorry to say that I still crash reliably with this patch. Just |
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> to recap, it is a netra 1405, 4x440, 1G ram. Crashed after about 30 |
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> minutes of running my disk-loading crashme.sh. |
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Thanks for testing... |
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Hmmm, so what else fundamentally changed in 2.6.x vs. 2.4.x |
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sparc64 wise? One thing that sticks out is that we do batched |
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TLB flushing now. That's kind of tricky to get right because |
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UltraSPARC requires that one does a "membar #Sync" or |
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"flush" after any internal cpu register store before any |
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subsequent non-internal load or store is performed. |
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|
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We're slightly violating that in the new batched TLB flushing |
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code. So it's worth trying the patch below out. |
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This goes on top of the membar patch, and the UltraSPARC-III |
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fix for the membar patch. If there are some rejects, they'll |
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be minor and easy to fix up. |
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Let me know if this patch makes any difference. |
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[SPARC64]: Add missing "membar #Sync" to flush_tlb_pending(). |
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flush_tlb_pending() (both the spitfire and cheetah variants) |
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need to do a membar after writing the context register, before |
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we load the first PTE entry in the batch array. |
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Signed-off-by: David S. Miller <davem@×××××××××.net> |
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|
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diff --git a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S |
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--- a/arch/sparc64/mm/ultra.S |
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+++ b/arch/sparc64/mm/ultra.S |
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@@ -57,6 +57,7 @@ __flush_tlb_pending: |
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mov SECONDARY_CONTEXT, %o4 |
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ldxa [%o4] ASI_DMMU, %g2 |
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stxa %o0, [%o4] ASI_DMMU |
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+ membar #Sync |
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1: sub %o1, (1 << 3), %o1 |
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ldx [%o2 + %o1], %o3 |
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andcc %o3, 1, %g0 |
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@@ -250,7 +251,7 @@ __cheetah_flush_tlb_mm: /* 15 insns */ |
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retl |
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wrpr %g7, 0x0, %pstate |
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|
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-__cheetah_flush_tlb_pending: /* 23 insns */ |
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+__cheetah_flush_tlb_pending: /* 24 insns */ |
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/* %o0 = context, %o1 = nr, %o2 = vaddrs[] */ |
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rdpr %pstate, %g7 |
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sllx %o1, 3, %o1 |
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@@ -260,6 +261,7 @@ __cheetah_flush_tlb_pending: /* 23 insns |
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mov PRIMARY_CONTEXT, %o4 |
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ldxa [%o4] ASI_DMMU, %g2 |
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stxa %o0, [%o4] ASI_DMMU |
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+ membar #Sync |
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1: sub %o1, (1 << 3), %o1 |
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ldx [%o2 + %o1], %o3 |
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andcc %o3, 1, %g0 |
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@@ -318,7 +320,7 @@ cheetah_patch_cachetlbops: |
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sethi %hi(__cheetah_flush_tlb_pending), %o1 |
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or %o1, %lo(__cheetah_flush_tlb_pending), %o1 |
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call cheetah_patch_one |
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- mov 23, %o2 |
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+ mov 24, %o2 |
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|
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#ifdef DCACHE_ALIASING_POSSIBLE |
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sethi %hi(__flush_dcache_page), %o0 |
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@@ -367,6 +369,7 @@ xcall_flush_tlb_pending: |
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mov PRIMARY_CONTEXT, %g4 |
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ldxa [%g4] ASI_DMMU, %g2 |
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stxa %g5, [%g4] ASI_DMMU |
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+ membar #Sync |
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1: sub %g1, (1 << 3), %g1 |
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ldx [%g7 + %g1], %g5 |
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andcc %g5, 0x1, %g0 |
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-- |
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