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On Fri, 30 Apr 2010 15:20:02 +0200, Nikos Chantziaras wrote about |
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[gentoo-user] Re: Compiling 32 bit library on x86_64: |
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|
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>On 04/30/2010 03:09 PM, David W Noon wrote: |
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>> On Fri, 30 Apr 2010 12:10:02 +0200, Roger Mason wrote about |
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>> [gentoo-user] Compiling 32 bit library on x86_64: |
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>> |
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>>> Hello, |
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>>> |
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>>> I need to compile a 32 bit version of libtermcap on an x86_64 |
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>>> (multilib) system. Can someone tell me how to set up CFLAGS? This |
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>>> is what I have at the moment: |
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>>> |
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>>> CFLAGS="-O2 -m32 -march=native -msse3 -pipe" |
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>>> CXXFLAGS="-O2 -m32 -march=native -msse3 -pipe" |
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>> |
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>> The -march=native will shoot you in the foot. Pick a 32-bit |
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>> architecture and use that instead; e.g. -march=i686 |
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>> |
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>> Then, -msse3 could also be problematic, unless the target is a very |
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>> late model Pentium 4. I would ditch that too. |
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> |
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>None of those options are problematic. -march=native has nothing to |
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>do with 32/64 bit. Every 64-bit CPU is 32-bit compatible and has zero |
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>consequence. |
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> |
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>I think you fell into the logical trap that 32-bit CPUs are not 64-bit |
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>compatible but it's OK vice versa :) Meaning you can't use "-m64 |
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>-march=i686". But you *can* and *should* use "-m32 -march=core2". |
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|
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No, I stand by what I wrote. |
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|
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The -march=native option tells the compiler to issue the CPUID |
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instruction to determine the architecture. This means that on an amd64 |
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box it will return data for either an AMD K8 or an Intel Pentium D |
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architecture. This, in turn, allows the compiler to generate K8 |
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instructions that are not valid on IA32 processors. It even allows |
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the compiler to use 64-bit registers, including the additional |
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registers that were not in an IA32 processor. |
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|
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The -m32 option instructs the compiler to generate code with 32-bit |
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pointers and relocation dictionary. It does not constrain the compiler |
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to generate code that will definitely run on an IA32 processor, but it |
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does ensure that the code can be linked with 32-bit libraries. |
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|
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So, if one is compiling on, say, a Core2 Duo and one uses -march=native |
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and -m32, the compiler can use all kinds of instructions valid on the |
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Core2 Duo, but limits addressing to 32-bit. |
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|
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From the info pages for GCC: |
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|
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3.17.14 Intel 386 and AMD x86-64 Options |
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---------------------------------------- |
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|
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These `-m' options are defined for the i386 and x86-64 family of |
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computers: |
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|
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`-mtune=CPU-TYPE' |
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Tune to CPU-TYPE everything applicable about the generated code, |
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except for the ABI and the set of available instructions. The |
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choices for CPU-TYPE are: |
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_generic_ |
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Produce code optimized for the most common IA32/AMD64/EM64T |
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processors. If you know the CPU on which your code will run, |
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then you should use the corresponding `-mtune' option instead |
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of `-mtune=generic'. But, if you do not know exactly what |
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CPU users of your application will have, then you should use |
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this option. |
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|
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As new processors are deployed in the marketplace, the |
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behavior of this option will change. Therefore, if you |
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upgrade to a newer version of GCC, the code generated option |
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will change to reflect the processors that were most common |
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when that version of GCC was released. |
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|
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There is no `-march=generic' option because `-march' |
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indicates the instruction set the compiler can use, and there |
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is no generic instruction set applicable to all processors. |
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In contrast, `-mtune' indicates the processor (or, in this |
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case, collection of processors) for which the code is |
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optimized. |
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|
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_native_ |
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This selects the CPU to tune for at compilation time by |
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determining the processor type of the compiling machine. |
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Using `-mtune=native' will produce code optimized for the |
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local machine under the constraints of the selected |
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instruction set. Using `-march=native' will enable all |
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instruction subsets supported by the local machine (hence the |
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result might not run on different machines). |
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|
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_i386_ |
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Original Intel's i386 CPU. |
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|
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_i486_ |
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Intel's i486 CPU. (No scheduling is implemented for this |
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chip.) |
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|
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_i586, pentium_ |
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Intel Pentium CPU with no MMX support. |
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|
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_pentium-mmx_ |
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Intel PentiumMMX CPU based on Pentium core with MMX |
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instruction set support. |
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|
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_pentiumpro_ |
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Intel PentiumPro CPU. |
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|
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_i686_ |
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Same as `generic', but when used as `march' option, PentiumPro |
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instruction set will be used, so the code will run on all |
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i686 family chips. |
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|
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_pentium2_ |
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Intel Pentium2 CPU based on PentiumPro core with MMX |
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instruction set support. |
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|
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_pentium3, pentium3m_ |
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Intel Pentium3 CPU based on PentiumPro core with MMX and SSE |
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instruction set support. |
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|
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_pentium-m_ |
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Low power version of Intel Pentium3 CPU with MMX, SSE and |
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SSE2 instruction set support. Used by Centrino notebooks. |
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|
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_pentium4, pentium4m_ |
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Intel Pentium4 CPU with MMX, SSE and SSE2 instruction set |
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support. |
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|
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_prescott_ |
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Improved version of Intel Pentium4 CPU with MMX, SSE, SSE2 |
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and SSE3 instruction set support. |
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|
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_nocona_ |
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Improved version of Intel Pentium4 CPU with 64-bit |
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extensions, MMX, SSE, SSE2 and SSE3 instruction set support. |
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|
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_core2_ |
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Intel Core2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 |
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and SSSE3 instruction set support. |
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|
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_k6_ |
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AMD K6 CPU with MMX instruction set support. |
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|
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_k6-2, k6-3_ |
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Improved versions of AMD K6 CPU with MMX and 3dNOW! |
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instruction set support. |
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|
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_athlon, athlon-tbird_ |
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AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and SSE |
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prefetch instructions support. |
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|
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_athlon-4, athlon-xp, athlon-mp_ |
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Improved AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and |
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full SSE instruction set support. |
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|
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_k8, opteron, athlon64, athlon-fx_ |
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AMD K8 core based CPUs with x86-64 instruction set support. |
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(This supersets MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and |
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64-bit instruction set extensions.) |
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|
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_k8-sse3, opteron-sse3, athlon64-sse3_ |
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Improved versions of k8, opteron and athlon64 with SSE3 |
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instruction set support. |
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|
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_amdfam10, barcelona_ |
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AMD Family 10h core based CPUs with x86-64 instruction set |
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support. (This supersets MMX, SSE, SSE2, SSE3, SSE4A, |
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3dNOW!, enhanced 3dNOW!, ABM and 64-bit instruction set |
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extensions.) |
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|
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_winchip-c6_ |
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IDT Winchip C6 CPU, dealt in same way as i486 with additional |
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MMX instruction set support. |
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|
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_winchip2_ |
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IDT Winchip2 CPU, dealt in same way as i486 with additional |
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MMX and 3dNOW! instruction set support. |
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|
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_c3_ |
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Via C3 CPU with MMX and 3dNOW! instruction set support. (No |
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scheduling is implemented for this chip.) |
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|
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_c3-2_ |
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Via C3-2 CPU with MMX and SSE instruction set support. (No |
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scheduling is implemented for this chip.) |
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|
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_geode_ |
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Embedded AMD CPU with MMX and 3dNOW! instruction set support. |
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|
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While picking a specific CPU-TYPE will schedule things |
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appropriately for that particular chip, the compiler will not |
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generate any code that does not run on the i386 without the |
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`-march=CPU-TYPE' option being used. |
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|
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`-march=CPU-TYPE' |
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Generate instructions for the machine type CPU-TYPE. The choices |
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for CPU-TYPE are the same as for `-mtune'. Moreover, specifying |
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`-march=CPU-TYPE' implies `-mtune=CPU-TYPE'. |
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|
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[snip] |
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|
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The above options determine the instruction set and instruction |
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scheduling, and "native" uses whatever hardware platform is used for |
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compilation. |
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|
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[continuing] |
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|
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`-m32' |
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`-m64' |
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Generate code for a 32-bit or 64-bit environment. The 32-bit |
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environment sets int, long and pointer to 32 bits and generates |
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code that runs on any i386 system. The 64-bit environment sets |
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int to 32 bits and long and pointer to 64 bits and generates code |
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for AMD's x86-64 architecture. For darwin only the -m64 option |
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turns off the `-fno-pic' and `-mdynamic-no-pic' options. |
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|
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The above is slightly misleading, as it should say "code that loads on |
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any i386" rather than "code that runs on any i386". It is all about |
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setting the width for pointers and integers. |
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-- |
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Regards, |
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|
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Dave [RLU #314465] |
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====================================================================== |
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dwnoon@××××××××.com (David W Noon) |
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====================================================================== |