| 1 |
On Wed, May 06, 2009 at 02:30:52PM +0300, Nadav Horesh wrote: |
| 2 |
> |
| 3 |
> I recently added 4GB to the existing 2GB I had. The BIOS and lshw recognize the memory configuration (2 dimm of 1G and 2 of 2G), but /prc/meminfo and a test program I ran recognize 3.2GB. |
| 4 |
> |
| 5 |
> My system configuration: |
| 6 |
> cpu: core2 6600 |
| 7 |
> chipset: DP965LT (Intel's motherboard) |
| 8 |
|
| 9 |
I have a DP965LT w/ 4GB and even then the BIOS is behaving like an |
| 10 |
idiot. The chipset apparently has 8GB of address space but the BIOS |
| 11 |
doesn't make good use of that, probably for 32bit OS support. |
| 12 |
|
| 13 |
My MTRRs are like this: |
| 14 |
$ cat /proc/mtrr |
| 15 |
reg00: base=0x000000000 ( 0MB), size= 4096MB, count=1: write-back |
| 16 |
reg01: base=0x0f0000000 ( 3840MB), size= 256MB, count=1: uncachable |
| 17 |
reg02: base=0x0eff00000 ( 3839MB), size= 1MB, count=1: uncachable |
| 18 |
reg03: base=0x100000000 ( 4096MB), size= 128MB, count=1: write-back |
| 19 |
reg04: base=0x108000000 ( 4224MB), size= 64MB, count=1: write-back |
| 20 |
|
| 21 |
So it maps all I/O stuff in the upper 257MB of the 4 GB MTRR. |
| 22 |
Unfortunately it completely ignores the video framebuffer which ends up |
| 23 |
UC instead of WC and I think adding a WC MTRR on top of WB is undefined |
| 24 |
or illegal. Fortunately the CPU is fast enough to make the UC problem |
| 25 |
more or less irrelevant under my normal use. |
| 26 |
|
| 27 |
Furthermore it apparentlly has managed to misplace 65 MB of my RAM. The |
| 28 |
e820 map shows the same problem so it's just not some MTRR related BIOS |
| 29 |
problem. |
| 30 |
|
| 31 |
Last time I looked there was no BIOS fix for this issue. I think I read |
| 32 |
somewhere that an earlier BIOS might have behaved a bit better but then |
| 33 |
they made some Vista fixes and the current mess is what resulted. |
| 34 |
|
| 35 |
Do you have the MTRR cleanup thing enabled in your kernel? I'm not sure |
| 36 |
how it works but perhaps it's doing something to give you a WC mapping |
| 37 |
for you framebuffer and then it's forced to spend all of the MTRRs in |
| 38 |
ever smaller bits to cover the memory under 4 GB without realizing that |
| 39 |
it could get much more memory convered by using larger chunks mapped |
| 40 |
above the 4GB boundary. I suppose when it runs out of MTRRs it will |
| 41 |
reduce the memory size to what was covered by WB MTRRs, which is a good |
| 42 |
idea since UC RAM could cause horrible performance issues. |
| 43 |
|
| 44 |
A look at your e820 map might shed some light on the BIOS behaviour at |
| 45 |
least. |
| 46 |
|
| 47 |
-- |
| 48 |
Ville Syrjälä |
| 49 |
syrjala@×××.fi |
| 50 |
http://www.sci.fi/~syrjala/ |
Archives