Re: [gentoo-catalyst] Does subarch determine profile or stage3 seed?

[lin pro <linforpros@gmail.com>]

On Thu, Dec 12, 2013 at 11:44 AM, Rick "Zero_Chaos" Farina
<zerochaos@gentoo.org> wrote:
>
>
> We can try to help if you post your spec.


thank you for your reply.
Here is my spec file:  http://bpaste.net/show/158113/
And this is how it works after
catalyst -f generic_stage1_studio.spec http://bpaste.net/show/158115/


My goal is to be able to run catalyst to produce stage1, stage2,stage3
and then stage4 inn order to install
it on a intel i3. Like I mentioned before the build host is an amd:

processor       : 3
vendor_id       : AuthenticAMD
cpu family      : 18
model           : 1
model name      : AMD A8-3850 APU with Radeon(tm) HD Graphics
stepping        : 0
microcode       : 0x3000027
cpu MHz         : 2900.000
cache size      : 1024 KB
physical id     : 0
siblings        : 4
core id         : 3
cpu cores       : 4
apicid          : 3
initial apicid  : 3
fpu             : yes
fpu_exception   : yes
cpuid level     : 1
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext
fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow constant_tsc rep_good nopl
nonstop_tsc extd_apicid pni cx16 popcnt lahf_lm cmp_legacy svm extapic
cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt
arat hw_pstate npt lbrv svm_lock nrip_save pausefilter
bogomips        : 5800.30
TLB size        : 1536 4K pages
clflush size    : 64
cache_alignment : 64
address sizes   : 40 bits physical, 48 bits virtual
power management: ts ttp tm stc 100mhzsteps hwpstate



I realize that the road may be bumpy, but hey, I 've got a little bit
of patience here.
Thank you for any hints

Ben




-- 
best regards
linforpros