[gentoo-commits] proj/linux-patches:4.19 commit in: /

[Mike Pagano]

commit:     7f8cc789b776e0cf768d27cff4118be5960094c0
Author:     Mike Pagano <mpagano <AT> gentoo <DOT> org>
AuthorDate: Tue Feb 11 16:20:35 2020 +0000
Commit:     Mike Pagano <mpagano <AT> gentoo <DOT> org>
CommitDate: Tue Feb 11 16:20:35 2020 +0000
URL:        https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=7f8cc789

Linux patch 4.19.103

Signed-off-by: Mike Pagano <mpagano <AT> gentoo.org>

 0000_README               |     4 +
 1102_linux-4.19.103.patch | 17138 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 17142 insertions(+)

diff --git a/0000_README b/0000_README
index 0d9cae4..8ac0cbe 100644
--- a/0000_README
+++ b/0000_README
@@ -447,6 +447,10 @@ Patch:  1101_linux-4.19.102.patch
 From:   https://www.kernel.org
 Desc:   Linux 4.19.102
 
+Patch:  1102_linux-4.19.103.patch
+From:   https://www.kernel.org
+Desc:   Linux 4.19.103
+
 Patch:  1500_XATTR_USER_PREFIX.patch
 From:   https://bugs.gentoo.org/show_bug.cgi?id=470644
 Desc:   Support for namespace user.pax.* on tmpfs.

diff --git a/1102_linux-4.19.103.patch b/1102_linux-4.19.103.patch
new file mode 100644
index 0000000..7b0adc1
--- /dev/null
+++ b/1102_linux-4.19.103.patch
@@ -0,0 +1,17138 @@
+diff --git a/Makefile b/Makefile
+index 597a14e2127b..37f58becf5c2 100644
+--- a/Makefile
++++ b/Makefile
+@@ -1,7 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ VERSION = 4
+ PATCHLEVEL = 19
+-SUBLEVEL = 102
++SUBLEVEL = 103
+ EXTRAVERSION =
+ NAME = "People's Front"
+ 
+diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
+index 77121b713bef..7d2ca035d6c8 100644
+--- a/arch/arm/include/asm/kvm_emulate.h
++++ b/arch/arm/include/asm/kvm_emulate.h
+@@ -26,13 +26,25 @@
+ #include <asm/cputype.h>
+ 
+ /* arm64 compatibility macros */
++#define PSR_AA32_MODE_FIQ	FIQ_MODE
++#define PSR_AA32_MODE_SVC	SVC_MODE
+ #define PSR_AA32_MODE_ABT	ABT_MODE
+ #define PSR_AA32_MODE_UND	UND_MODE
+ #define PSR_AA32_T_BIT		PSR_T_BIT
++#define PSR_AA32_F_BIT		PSR_F_BIT
+ #define PSR_AA32_I_BIT		PSR_I_BIT
+ #define PSR_AA32_A_BIT		PSR_A_BIT
+ #define PSR_AA32_E_BIT		PSR_E_BIT
+ #define PSR_AA32_IT_MASK	PSR_IT_MASK
++#define PSR_AA32_GE_MASK	0x000f0000
++#define PSR_AA32_DIT_BIT	0x00200000
++#define PSR_AA32_PAN_BIT	0x00400000
++#define PSR_AA32_SSBS_BIT	0x00800000
++#define PSR_AA32_Q_BIT		PSR_Q_BIT
++#define PSR_AA32_V_BIT		PSR_V_BIT
++#define PSR_AA32_C_BIT		PSR_C_BIT
++#define PSR_AA32_Z_BIT		PSR_Z_BIT
++#define PSR_AA32_N_BIT		PSR_N_BIT
+ 
+ unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num);
+ 
+@@ -53,6 +65,11 @@ static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v)
+ 	*__vcpu_spsr(vcpu) = v;
+ }
+ 
++static inline unsigned long host_spsr_to_spsr32(unsigned long spsr)
++{
++	return spsr;
++}
++
+ static inline unsigned long vcpu_get_reg(struct kvm_vcpu *vcpu,
+ 					 u8 reg_num)
+ {
+@@ -189,6 +206,11 @@ static inline bool kvm_vcpu_dabt_issext(struct kvm_vcpu *vcpu)
+ 	return kvm_vcpu_get_hsr(vcpu) & HSR_SSE;
+ }
+ 
++static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu)
++{
++	return false;
++}
++
+ static inline int kvm_vcpu_dabt_get_rd(struct kvm_vcpu *vcpu)
+ {
+ 	return (kvm_vcpu_get_hsr(vcpu) & HSR_SRT_MASK) >> HSR_SRT_SHIFT;
+diff --git a/arch/arm/include/asm/kvm_mmio.h b/arch/arm/include/asm/kvm_mmio.h
+index f3a7de71f515..848339d76f9a 100644
+--- a/arch/arm/include/asm/kvm_mmio.h
++++ b/arch/arm/include/asm/kvm_mmio.h
+@@ -26,6 +26,8 @@
+ struct kvm_decode {
+ 	unsigned long rt;
+ 	bool sign_extend;
++	/* Not used on 32-bit arm */
++	bool sixty_four;
+ };
+ 
+ void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
+diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
+index dd4a67dabd91..b7cd41461e7d 100644
+--- a/arch/arm/mach-tegra/sleep-tegra30.S
++++ b/arch/arm/mach-tegra/sleep-tegra30.S
+@@ -382,6 +382,14 @@ _pll_m_c_x_done:
+ 	pll_locked r1, r0, CLK_RESET_PLLC_BASE
+ 	pll_locked r1, r0, CLK_RESET_PLLX_BASE
+ 
++	tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
++	cmp	r1, #TEGRA30
++	beq	1f
++	ldr	r1, [r0, #CLK_RESET_PLLP_BASE]
++	bic	r1, r1, #(1<<31)	@ disable PllP bypass
++	str	r1, [r0, #CLK_RESET_PLLP_BASE]
++1:
++
+ 	mov32	r7, TEGRA_TMRUS_BASE
+ 	ldr	r1, [r7]
+ 	add	r1, r1, #LOCK_DELAY
+@@ -641,7 +649,10 @@ tegra30_switch_cpu_to_clk32k:
+ 	str	r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
+ 
+ 	/* disable PLLP, PLLA, PLLC and PLLX */
++	tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
++	cmp	r1, #TEGRA30
+ 	ldr	r0, [r5, #CLK_RESET_PLLP_BASE]
++	orrne	r0, r0, #(1 << 31)	@ enable PllP bypass on fast cluster
+ 	bic	r0, r0, #(1 << 30)
+ 	str	r0, [r5, #CLK_RESET_PLLP_BASE]
+ 	ldr	r0, [r5, #CLK_RESET_PLLA_BASE]
+diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
+index 6106a85ae0be..778cb4f868d9 100644
+--- a/arch/arm64/include/asm/kvm_emulate.h
++++ b/arch/arm64/include/asm/kvm_emulate.h
+@@ -202,6 +202,38 @@ static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v)
+ 		vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1] = v;
+ }
+ 
++/*
++ * The layout of SPSR for an AArch32 state is different when observed from an
++ * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32
++ * view given an AArch64 view.
++ *
++ * In ARM DDI 0487E.a see:
++ *
++ * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426
++ * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256
++ * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280
++ *
++ * Which show the following differences:
++ *
++ * | Bit | AA64 | AA32 | Notes                       |
++ * +-----+------+------+-----------------------------|
++ * | 24  | DIT  | J    | J is RES0 in ARMv8          |
++ * | 21  | SS   | DIT  | SS doesn't exist in AArch32 |
++ *
++ * ... and all other bits are (currently) common.
++ */
++static inline unsigned long host_spsr_to_spsr32(unsigned long spsr)
++{
++	const unsigned long overlap = BIT(24) | BIT(21);
++	unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT);
++
++	spsr &= ~overlap;
++
++	spsr |= dit << 21;
++
++	return spsr;
++}
++
+ static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
+ {
+ 	u32 mode;
+@@ -261,6 +293,11 @@ static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
+ 	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SSE);
+ }
+ 
++static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu)
++{
++	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SF);
++}
++
+ static inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
+ {
+ 	return (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
+diff --git a/arch/arm64/include/asm/kvm_mmio.h b/arch/arm64/include/asm/kvm_mmio.h
+index 75ea42079757..0240290cf764 100644
+--- a/arch/arm64/include/asm/kvm_mmio.h
++++ b/arch/arm64/include/asm/kvm_mmio.h
+@@ -21,13 +21,11 @@
+ #include <linux/kvm_host.h>
+ #include <asm/kvm_arm.h>
+ 
+-/*
+- * This is annoying. The mmio code requires this, even if we don't
+- * need any decoding. To be fixed.
+- */
+ struct kvm_decode {
+ 	unsigned long rt;
+ 	bool sign_extend;
++	/* Witdth of the register accessed by the faulting instruction is 64-bits */
++	bool sixty_four;
+ };
+ 
+ void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
+diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h
+index 6bc43889d11e..163970d5c4b1 100644
+--- a/arch/arm64/include/asm/ptrace.h
++++ b/arch/arm64/include/asm/ptrace.h
+@@ -50,6 +50,7 @@
+ #define PSR_AA32_I_BIT		0x00000080
+ #define PSR_AA32_A_BIT		0x00000100
+ #define PSR_AA32_E_BIT		0x00000200
++#define PSR_AA32_PAN_BIT	0x00400000
+ #define PSR_AA32_SSBS_BIT	0x00800000
+ #define PSR_AA32_DIT_BIT	0x01000000
+ #define PSR_AA32_Q_BIT		0x08000000
+diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h
+index b0fd1d300154..978ff79fba2b 100644
+--- a/arch/arm64/include/uapi/asm/ptrace.h
++++ b/arch/arm64/include/uapi/asm/ptrace.h
+@@ -49,6 +49,7 @@
+ #define PSR_SSBS_BIT	0x00001000
+ #define PSR_PAN_BIT	0x00400000
+ #define PSR_UAO_BIT	0x00800000
++#define PSR_DIT_BIT	0x01000000
+ #define PSR_V_BIT	0x10000000
+ #define PSR_C_BIT	0x20000000
+ #define PSR_Z_BIT	0x40000000
+diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c
+index a55e91dfcf8f..41c80c311367 100644
+--- a/arch/arm64/kvm/inject_fault.c
++++ b/arch/arm64/kvm/inject_fault.c
+@@ -25,9 +25,6 @@
+ #include <asm/kvm_emulate.h>
+ #include <asm/esr.h>
+ 
+-#define PSTATE_FAULT_BITS_64 	(PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | \
+-				 PSR_I_BIT | PSR_D_BIT)
+-
+ #define CURRENT_EL_SP_EL0_VECTOR	0x0
+ #define CURRENT_EL_SP_ELx_VECTOR	0x200
+ #define LOWER_EL_AArch64_VECTOR		0x400
+@@ -61,6 +58,69 @@ static u64 get_except_vector(struct kvm_vcpu *vcpu, enum exception_type type)
+ 	return vcpu_read_sys_reg(vcpu, VBAR_EL1) + exc_offset + type;
+ }
+ 
++/*
++ * When an exception is taken, most PSTATE fields are left unchanged in the
++ * handler. However, some are explicitly overridden (e.g. M[4:0]). Luckily all
++ * of the inherited bits have the same position in the AArch64/AArch32 SPSR_ELx
++ * layouts, so we don't need to shuffle these for exceptions from AArch32 EL0.
++ *
++ * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429.
++ * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426.
++ *
++ * Here we manipulate the fields in order of the AArch64 SPSR_ELx layout, from
++ * MSB to LSB.
++ */
++static unsigned long get_except64_pstate(struct kvm_vcpu *vcpu)
++{
++	unsigned long sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1);
++	unsigned long old, new;
++
++	old = *vcpu_cpsr(vcpu);
++	new = 0;
++
++	new |= (old & PSR_N_BIT);
++	new |= (old & PSR_Z_BIT);
++	new |= (old & PSR_C_BIT);
++	new |= (old & PSR_V_BIT);
++
++	// TODO: TCO (if/when ARMv8.5-MemTag is exposed to guests)
++
++	new |= (old & PSR_DIT_BIT);
++
++	// PSTATE.UAO is set to zero upon any exception to AArch64
++	// See ARM DDI 0487E.a, page D5-2579.
++
++	// PSTATE.PAN is unchanged unless SCTLR_ELx.SPAN == 0b0
++	// SCTLR_ELx.SPAN is RES1 when ARMv8.1-PAN is not implemented
++	// See ARM DDI 0487E.a, page D5-2578.
++	new |= (old & PSR_PAN_BIT);
++	if (!(sctlr & SCTLR_EL1_SPAN))
++		new |= PSR_PAN_BIT;
++
++	// PSTATE.SS is set to zero upon any exception to AArch64
++	// See ARM DDI 0487E.a, page D2-2452.
++
++	// PSTATE.IL is set to zero upon any exception to AArch64
++	// See ARM DDI 0487E.a, page D1-2306.
++
++	// PSTATE.SSBS is set to SCTLR_ELx.DSSBS upon any exception to AArch64
++	// See ARM DDI 0487E.a, page D13-3258
++	if (sctlr & SCTLR_ELx_DSSBS)
++		new |= PSR_SSBS_BIT;
++
++	// PSTATE.BTYPE is set to zero upon any exception to AArch64
++	// See ARM DDI 0487E.a, pages D1-2293 to D1-2294.
++
++	new |= PSR_D_BIT;
++	new |= PSR_A_BIT;
++	new |= PSR_I_BIT;
++	new |= PSR_F_BIT;
++
++	new |= PSR_MODE_EL1h;
++
++	return new;
++}
++
+ static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr)
+ {
+ 	unsigned long cpsr = *vcpu_cpsr(vcpu);
+@@ -70,7 +130,7 @@ static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr
+ 	vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu));
+ 	*vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync);
+ 
+-	*vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
++	*vcpu_cpsr(vcpu) = get_except64_pstate(vcpu);
+ 	vcpu_write_spsr(vcpu, cpsr);
+ 
+ 	vcpu_write_sys_reg(vcpu, addr, FAR_EL1);
+@@ -105,7 +165,7 @@ static void inject_undef64(struct kvm_vcpu *vcpu)
+ 	vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu));
+ 	*vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync);
+ 
+-	*vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
++	*vcpu_cpsr(vcpu) = get_except64_pstate(vcpu);
+ 	vcpu_write_spsr(vcpu, cpsr);
+ 
+ 	/*
+diff --git a/arch/mips/Makefile.postlink b/arch/mips/Makefile.postlink
+index 4eea4188cb20..13e0beb9eee3 100644
+--- a/arch/mips/Makefile.postlink
++++ b/arch/mips/Makefile.postlink
+@@ -12,7 +12,7 @@ __archpost:
+ include scripts/Kbuild.include
+ 
+ CMD_RELOCS = arch/mips/boot/tools/relocs
+-quiet_cmd_relocs = RELOCS $@
++quiet_cmd_relocs = RELOCS  $@
+       cmd_relocs = $(CMD_RELOCS) $@
+ 
+ # `@true` prevents complaint when there is nothing to be done
+diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
+index 35704c28a28b..0ccc20320099 100644
+--- a/arch/mips/boot/Makefile
++++ b/arch/mips/boot/Makefile
+@@ -123,7 +123,7 @@ $(obj)/vmlinux.its.S: $(addprefix $(srctree)/arch/mips/$(PLATFORM)/,$(ITS_INPUTS
+ targets += vmlinux.its
+ targets += vmlinux.gz.its
+ targets += vmlinux.bz2.its
+-targets += vmlinux.lzmo.its
++targets += vmlinux.lzma.its
+ targets += vmlinux.lzo.its
+ 
+ quiet_cmd_cpp_its_S = ITS     $@
+diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
+index a80669209155..6f475dc5829b 100644
+--- a/arch/powerpc/Kconfig
++++ b/arch/powerpc/Kconfig
+@@ -230,6 +230,7 @@ config PPC
+ 	select NEED_SG_DMA_LENGTH
+ 	select NO_BOOTMEM
+ 	select OF
++	select OF_DMA_DEFAULT_COHERENT		if !NOT_COHERENT_CACHE
+ 	select OF_EARLY_FLATTREE
+ 	select OF_RESERVED_MEM
+ 	select OLD_SIGACTION			if PPC32
+diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c
+index f7da65169124..3c8774163c7e 100644
+--- a/arch/powerpc/boot/4xx.c
++++ b/arch/powerpc/boot/4xx.c
+@@ -232,7 +232,7 @@ void ibm4xx_denali_fixup_memsize(void)
+ 		dpath = 8; /* 64 bits */
+ 
+ 	/* get address pins (rows) */
+- 	val = SDRAM0_READ(DDR0_42);
++	val = SDRAM0_READ(DDR0_42);
+ 
+ 	row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT);
+ 	if (row > max_row)
+diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
+index dbfe32327212..5dc592fb4f5f 100644
+--- a/arch/powerpc/kvm/book3s_hv.c
++++ b/arch/powerpc/kvm/book3s_hv.c
+@@ -2065,7 +2065,7 @@ static struct kvm_vcpu *kvmppc_core_vcpu_create_hv(struct kvm *kvm,
+ 	mutex_unlock(&kvm->lock);
+ 
+ 	if (!vcore)
+-		goto free_vcpu;
++		goto uninit_vcpu;
+ 
+ 	spin_lock(&vcore->lock);
+ 	++vcore->num_threads;
+@@ -2082,6 +2082,8 @@ static struct kvm_vcpu *kvmppc_core_vcpu_create_hv(struct kvm *kvm,
+ 
+ 	return vcpu;
+ 
++uninit_vcpu:
++	kvm_vcpu_uninit(vcpu);
+ free_vcpu:
+ 	kmem_cache_free(kvm_vcpu_cache, vcpu);
+ out:
+diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
+index de9702219dee..7869112a8f3c 100644
+--- a/arch/powerpc/kvm/book3s_pr.c
++++ b/arch/powerpc/kvm/book3s_pr.c
+@@ -1772,10 +1772,12 @@ static struct kvm_vcpu *kvmppc_core_vcpu_create_pr(struct kvm *kvm,
+ 
+ 	err = kvmppc_mmu_init(vcpu);
+ 	if (err < 0)
+-		goto uninit_vcpu;
++		goto free_shared_page;
+ 
+ 	return vcpu;
+ 
++free_shared_page:
++	free_page((unsigned long)vcpu->arch.shared);
+ uninit_vcpu:
+ 	kvm_vcpu_uninit(vcpu);
+ free_shadow_vcpu:
+diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c
+index c2c6f32848e1..fc01a2c0f8ed 100644
+--- a/arch/powerpc/platforms/pseries/hotplug-memory.c
++++ b/arch/powerpc/platforms/pseries/hotplug-memory.c
+@@ -366,8 +366,10 @@ static bool lmb_is_removable(struct drmem_lmb *lmb)
+ 
+ 	for (i = 0; i < scns_per_block; i++) {
+ 		pfn = PFN_DOWN(phys_addr);
+-		if (!pfn_present(pfn))
++		if (!pfn_present(pfn)) {
++			phys_addr += MIN_MEMORY_BLOCK_SIZE;
+ 			continue;
++		}
+ 
+ 		rc &= is_mem_section_removable(pfn, PAGES_PER_SECTION);
+ 		phys_addr += MIN_MEMORY_BLOCK_SIZE;
+diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
+index f0fa22e7d36c..3291e5fb94bc 100644
+--- a/arch/powerpc/xmon/xmon.c
++++ b/arch/powerpc/xmon/xmon.c
+@@ -1878,15 +1878,14 @@ static void dump_300_sprs(void)
+ 
+ 	printf("pidr   = %.16lx  tidr  = %.16lx\n",
+ 		mfspr(SPRN_PID), mfspr(SPRN_TIDR));
+-	printf("asdr   = %.16lx  psscr = %.16lx\n",
+-		mfspr(SPRN_ASDR), hv ? mfspr(SPRN_PSSCR)
+-					: mfspr(SPRN_PSSCR_PR));
++	printf("psscr  = %.16lx\n",
++		hv ? mfspr(SPRN_PSSCR) : mfspr(SPRN_PSSCR_PR));
+ 
+ 	if (!hv)
+ 		return;
+ 
+-	printf("ptcr   = %.16lx\n",
+-		mfspr(SPRN_PTCR));
++	printf("ptcr   = %.16lx  asdr  = %.16lx\n",
++		mfspr(SPRN_PTCR), mfspr(SPRN_ASDR));
+ #endif
+ }
+ 
+diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h
+index 0d753291c43c..ac3c86b21d79 100644
+--- a/arch/s390/include/asm/page.h
++++ b/arch/s390/include/asm/page.h
+@@ -33,6 +33,8 @@
+ #define ARCH_HAS_PREPARE_HUGEPAGE
+ #define ARCH_HAS_HUGEPAGE_CLEAR_FLUSH
+ 
++#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
++
+ #include <asm/setup.h>
+ #ifndef __ASSEMBLY__
+ 
+diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
+index db3196aebaa1..11c3cd906ab4 100644
+--- a/arch/s390/kvm/kvm-s390.c
++++ b/arch/s390/kvm/kvm-s390.c
+@@ -2564,9 +2564,7 @@ static void kvm_s390_vcpu_initial_reset(struct kvm_vcpu *vcpu)
+ 	vcpu->arch.sie_block->gcr[14] = CR14_UNUSED_32 |
+ 					CR14_UNUSED_33 |
+ 					CR14_EXTERNAL_DAMAGE_SUBMASK;
+-	/* make sure the new fpc will be lazily loaded */
+-	save_fpu_regs();
+-	current->thread.fpu.fpc = 0;
++	vcpu->run->s.regs.fpc = 0;
+ 	vcpu->arch.sie_block->gbea = 1;
+ 	vcpu->arch.sie_block->pp = 0;
+ 	vcpu->arch.sie_block->fpf &= ~FPF_BPBC;
+@@ -3994,7 +3992,7 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
+ 	switch (ioctl) {
+ 	case KVM_S390_STORE_STATUS:
+ 		idx = srcu_read_lock(&vcpu->kvm->srcu);
+-		r = kvm_s390_vcpu_store_status(vcpu, arg);
++		r = kvm_s390_store_status_unloaded(vcpu, arg);
+ 		srcu_read_unlock(&vcpu->kvm->srcu, idx);
+ 		break;
+ 	case KVM_S390_SET_INITIAL_PSW: {
+diff --git a/arch/s390/mm/hugetlbpage.c b/arch/s390/mm/hugetlbpage.c
+index b0246c705a19..5674710a4841 100644
+--- a/arch/s390/mm/hugetlbpage.c
++++ b/arch/s390/mm/hugetlbpage.c
+@@ -2,7 +2,7 @@
+ /*
+  *  IBM System z Huge TLB Page Support for Kernel.
+  *
+- *    Copyright IBM Corp. 2007,2016
++ *    Copyright IBM Corp. 2007,2020
+  *    Author(s): Gerald Schaefer <gerald.schaefer@××××××.com>
+  */
+ 
+@@ -11,6 +11,9 @@
+ 
+ #include <linux/mm.h>
+ #include <linux/hugetlb.h>
++#include <linux/mman.h>
++#include <linux/sched/mm.h>
++#include <linux/security.h>
+ 
+ /*
+  * If the bit selected by single-bit bitmask "a" is set within "x", move
+@@ -267,3 +270,98 @@ static __init int setup_hugepagesz(char *opt)
+ 	return 1;
+ }
+ __setup("hugepagesz=", setup_hugepagesz);
++
++static unsigned long hugetlb_get_unmapped_area_bottomup(struct file *file,
++		unsigned long addr, unsigned long len,
++		unsigned long pgoff, unsigned long flags)
++{
++	struct hstate *h = hstate_file(file);
++	struct vm_unmapped_area_info info;
++
++	info.flags = 0;
++	info.length = len;
++	info.low_limit = current->mm->mmap_base;
++	info.high_limit = TASK_SIZE;
++	info.align_mask = PAGE_MASK & ~huge_page_mask(h);
++	info.align_offset = 0;
++	return vm_unmapped_area(&info);
++}
++
++static unsigned long hugetlb_get_unmapped_area_topdown(struct file *file,
++		unsigned long addr0, unsigned long len,
++		unsigned long pgoff, unsigned long flags)
++{
++	struct hstate *h = hstate_file(file);
++	struct vm_unmapped_area_info info;
++	unsigned long addr;
++
++	info.flags = VM_UNMAPPED_AREA_TOPDOWN;
++	info.length = len;
++	info.low_limit = max(PAGE_SIZE, mmap_min_addr);
++	info.high_limit = current->mm->mmap_base;
++	info.align_mask = PAGE_MASK & ~huge_page_mask(h);
++	info.align_offset = 0;
++	addr = vm_unmapped_area(&info);
++
++	/*
++	 * A failed mmap() very likely causes application failure,
++	 * so fall back to the bottom-up function here. This scenario
++	 * can happen with large stack limits and large mmap()
++	 * allocations.
++	 */
++	if (addr & ~PAGE_MASK) {
++		VM_BUG_ON(addr != -ENOMEM);
++		info.flags = 0;
++		info.low_limit = TASK_UNMAPPED_BASE;
++		info.high_limit = TASK_SIZE;
++		addr = vm_unmapped_area(&info);
++	}
++
++	return addr;
++}
++
++unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
++		unsigned long len, unsigned long pgoff, unsigned long flags)
++{
++	struct hstate *h = hstate_file(file);
++	struct mm_struct *mm = current->mm;
++	struct vm_area_struct *vma;
++	int rc;
++
++	if (len & ~huge_page_mask(h))
++		return -EINVAL;
++	if (len > TASK_SIZE - mmap_min_addr)
++		return -ENOMEM;
++
++	if (flags & MAP_FIXED) {
++		if (prepare_hugepage_range(file, addr, len))
++			return -EINVAL;
++		goto check_asce_limit;
++	}
++
++	if (addr) {
++		addr = ALIGN(addr, huge_page_size(h));
++		vma = find_vma(mm, addr);
++		if (TASK_SIZE - len >= addr && addr >= mmap_min_addr &&
++		    (!vma || addr + len <= vm_start_gap(vma)))
++			goto check_asce_limit;
++	}
++
++	if (mm->get_unmapped_area == arch_get_unmapped_area)
++		addr = hugetlb_get_unmapped_area_bottomup(file, addr, len,
++				pgoff, flags);
++	else
++		addr = hugetlb_get_unmapped_area_topdown(file, addr, len,
++				pgoff, flags);
++	if (addr & ~PAGE_MASK)
++		return addr;
++
++check_asce_limit:
++	if (addr + len > current->mm->context.asce_limit &&
++	    addr + len <= TASK_SIZE) {
++		rc = crst_table_upgrade(mm, addr + len);
++		if (rc)
++			return (unsigned long) rc;
++	}
++	return addr;
++}
+diff --git a/arch/sparc/include/uapi/asm/ipcbuf.h b/arch/sparc/include/uapi/asm/ipcbuf.h
+index 9d0d125500e2..084b8949ddff 100644
+--- a/arch/sparc/include/uapi/asm/ipcbuf.h
++++ b/arch/sparc/include/uapi/asm/ipcbuf.h
+@@ -15,19 +15,19 @@
+ 
+ struct ipc64_perm
+ {
+-	__kernel_key_t	key;
+-	__kernel_uid_t	uid;
+-	__kernel_gid_t	gid;
+-	__kernel_uid_t	cuid;
+-	__kernel_gid_t	cgid;
++	__kernel_key_t		key;
++	__kernel_uid32_t	uid;
++	__kernel_gid32_t	gid;
++	__kernel_uid32_t	cuid;
++	__kernel_gid32_t	cgid;
+ #ifndef __arch64__
+-	unsigned short	__pad0;
++	unsigned short		__pad0;
+ #endif
+-	__kernel_mode_t	mode;
+-	unsigned short	__pad1;
+-	unsigned short	seq;
+-	unsigned long long __unused1;
+-	unsigned long long __unused2;
++	__kernel_mode_t		mode;
++	unsigned short		__pad1;
++	unsigned short		seq;
++	unsigned long long	__unused1;
++	unsigned long long	__unused2;
+ };
+ 
+ #endif /* __SPARC_IPCBUF_H */
+diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
+index 050368db9d35..3c1e51ead072 100644
+--- a/arch/x86/include/asm/apic.h
++++ b/arch/x86/include/asm/apic.h
+@@ -448,6 +448,14 @@ static inline void ack_APIC_irq(void)
+ 	apic_eoi();
+ }
+ 
++
++static inline bool lapic_vector_set_in_irr(unsigned int vector)
++{
++	u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
++
++	return !!(irr & (1U << (vector % 32)));
++}
++
+ static inline unsigned default_get_apic_id(unsigned long x)
+ {
+ 	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
+diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
+index 155be8adb934..21a58fcc3dd4 100644
+--- a/arch/x86/include/asm/kvm_host.h
++++ b/arch/x86/include/asm/kvm_host.h
+@@ -350,12 +350,12 @@ struct kvm_mmu {
+ 	void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root);
+ 	unsigned long (*get_cr3)(struct kvm_vcpu *vcpu);
+ 	u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index);
+-	int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err,
++	int (*page_fault)(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u32 err,
+ 			  bool prefault);
+ 	void (*inject_page_fault)(struct kvm_vcpu *vcpu,
+ 				  struct x86_exception *fault);
+-	gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access,
+-			    struct x86_exception *exception);
++	gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gpa_t gva_or_gpa,
++			    u32 access, struct x86_exception *exception);
+ 	gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
+ 			       struct x86_exception *exception);
+ 	int (*sync_page)(struct kvm_vcpu *vcpu,
+@@ -1354,7 +1354,7 @@ void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu);
+ 
+ int kvm_emulate_hypercall(struct kvm_vcpu *vcpu);
+ 
+-int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u64 error_code,
++int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
+ 		       void *insn, int insn_len);
+ void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva);
+ void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid);
+diff --git a/arch/x86/kernel/apic/msi.c b/arch/x86/kernel/apic/msi.c
+index 72a94401f9e0..1f5df339e48f 100644
+--- a/arch/x86/kernel/apic/msi.c
++++ b/arch/x86/kernel/apic/msi.c
+@@ -26,10 +26,8 @@
+ 
+ static struct irq_domain *msi_default_domain;
+ 
+-static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
++static void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg)
+ {
+-	struct irq_cfg *cfg = irqd_cfg(data);
+-
+ 	msg->address_hi = MSI_ADDR_BASE_HI;
+ 
+ 	if (x2apic_enabled())
+@@ -50,6 +48,127 @@ static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
+ 		MSI_DATA_VECTOR(cfg->vector);
+ }
+ 
++static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
++{
++	__irq_msi_compose_msg(irqd_cfg(data), msg);
++}
++
++static void irq_msi_update_msg(struct irq_data *irqd, struct irq_cfg *cfg)
++{
++	struct msi_msg msg[2] = { [1] = { }, };
++
++	__irq_msi_compose_msg(cfg, msg);
++	irq_data_get_irq_chip(irqd)->irq_write_msi_msg(irqd, msg);
++}
++
++static int
++msi_set_affinity(struct irq_data *irqd, const struct cpumask *mask, bool force)
++{
++	struct irq_cfg old_cfg, *cfg = irqd_cfg(irqd);
++	struct irq_data *parent = irqd->parent_data;
++	unsigned int cpu;
++	int ret;
++
++	/* Save the current configuration */
++	cpu = cpumask_first(irq_data_get_effective_affinity_mask(irqd));
++	old_cfg = *cfg;
++
++	/* Allocate a new target vector */
++	ret = parent->chip->irq_set_affinity(parent, mask, force);
++	if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
++		return ret;
++
++	/*
++	 * For non-maskable and non-remapped MSI interrupts the migration
++	 * to a different destination CPU and a different vector has to be
++	 * done careful to handle the possible stray interrupt which can be
++	 * caused by the non-atomic update of the address/data pair.
++	 *
++	 * Direct update is possible when:
++	 * - The MSI is maskable (remapped MSI does not use this code path)).
++	 *   The quirk bit is not set in this case.
++	 * - The new vector is the same as the old vector
++	 * - The old vector is MANAGED_IRQ_SHUTDOWN_VECTOR (interrupt starts up)
++	 * - The new destination CPU is the same as the old destination CPU
++	 */
++	if (!irqd_msi_nomask_quirk(irqd) ||
++	    cfg->vector == old_cfg.vector ||
++	    old_cfg.vector == MANAGED_IRQ_SHUTDOWN_VECTOR ||
++	    cfg->dest_apicid == old_cfg.dest_apicid) {
++		irq_msi_update_msg(irqd, cfg);
++		return ret;
++	}
++
++	/*
++	 * Paranoia: Validate that the interrupt target is the local
++	 * CPU.
++	 */
++	if (WARN_ON_ONCE(cpu != smp_processor_id())) {
++		irq_msi_update_msg(irqd, cfg);
++		return ret;
++	}
++
++	/*
++	 * Redirect the interrupt to the new vector on the current CPU
++	 * first. This might cause a spurious interrupt on this vector if
++	 * the device raises an interrupt right between this update and the
++	 * update to the final destination CPU.
++	 *
++	 * If the vector is in use then the installed device handler will
++	 * denote it as spurious which is no harm as this is a rare event
++	 * and interrupt handlers have to cope with spurious interrupts
++	 * anyway. If the vector is unused, then it is marked so it won't
++	 * trigger the 'No irq handler for vector' warning in do_IRQ().
++	 *
++	 * This requires to hold vector lock to prevent concurrent updates to
++	 * the affected vector.
++	 */
++	lock_vector_lock();
++
++	/*
++	 * Mark the new target vector on the local CPU if it is currently
++	 * unused. Reuse the VECTOR_RETRIGGERED state which is also used in
++	 * the CPU hotplug path for a similar purpose. This cannot be
++	 * undone here as the current CPU has interrupts disabled and
++	 * cannot handle the interrupt before the whole set_affinity()
++	 * section is done. In the CPU unplug case, the current CPU is
++	 * about to vanish and will not handle any interrupts anymore. The
++	 * vector is cleaned up when the CPU comes online again.
++	 */
++	if (IS_ERR_OR_NULL(this_cpu_read(vector_irq[cfg->vector])))
++		this_cpu_write(vector_irq[cfg->vector], VECTOR_RETRIGGERED);
++
++	/* Redirect it to the new vector on the local CPU temporarily */
++	old_cfg.vector = cfg->vector;
++	irq_msi_update_msg(irqd, &old_cfg);
++
++	/* Now transition it to the target CPU */
++	irq_msi_update_msg(irqd, cfg);
++
++	/*
++	 * All interrupts after this point are now targeted at the new
++	 * vector/CPU.
++	 *
++	 * Drop vector lock before testing whether the temporary assignment
++	 * to the local CPU was hit by an interrupt raised in the device,
++	 * because the retrigger function acquires vector lock again.
++	 */
++	unlock_vector_lock();
++
++	/*
++	 * Check whether the transition raced with a device interrupt and
++	 * is pending in the local APICs IRR. It is safe to do this outside
++	 * of vector lock as the irq_desc::lock of this interrupt is still
++	 * held and interrupts are disabled: The check is not accessing the
++	 * underlying vector store. It's just checking the local APIC's
++	 * IRR.
++	 */
++	if (lapic_vector_set_in_irr(cfg->vector))
++		irq_data_get_irq_chip(irqd)->irq_retrigger(irqd);
++
++	return ret;
++}
++
+ /*
+  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
+  * which implement the MSI or MSI-X Capability Structure.
+@@ -61,6 +180,7 @@ static struct irq_chip pci_msi_controller = {
+ 	.irq_ack		= irq_chip_ack_parent,
+ 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
+ 	.irq_compose_msi_msg	= irq_msi_compose_msg,
++	.irq_set_affinity	= msi_set_affinity,
+ 	.flags			= IRQCHIP_SKIP_SET_WAKE,
+ };
+ 
+@@ -149,6 +269,8 @@ void __init arch_init_msi_domain(struct irq_domain *parent)
+ 	}
+ 	if (!msi_default_domain)
+ 		pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
++	else
++		msi_default_domain->flags |= IRQ_DOMAIN_MSI_NOMASK_QUIRK;
+ }
+ 
+ #ifdef CONFIG_IRQ_REMAP
+diff --git a/arch/x86/kernel/cpu/tsx.c b/arch/x86/kernel/cpu/tsx.c
+index 3e20d322bc98..032509adf9de 100644
+--- a/arch/x86/kernel/cpu/tsx.c
++++ b/arch/x86/kernel/cpu/tsx.c
+@@ -115,11 +115,12 @@ void __init tsx_init(void)
+ 		tsx_disable();
+ 
+ 		/*
+-		 * tsx_disable() will change the state of the
+-		 * RTM CPUID bit.  Clear it here since it is now
+-		 * expected to be not set.
++		 * tsx_disable() will change the state of the RTM and HLE CPUID
++		 * bits. Clear them here since they are now expected to be not
++		 * set.
+ 		 */
+ 		setup_clear_cpu_cap(X86_FEATURE_RTM);
++		setup_clear_cpu_cap(X86_FEATURE_HLE);
+ 	} else if (tsx_ctrl_state == TSX_CTRL_ENABLE) {
+ 
+ 		/*
+@@ -131,10 +132,10 @@ void __init tsx_init(void)
+ 		tsx_enable();
+ 
+ 		/*
+-		 * tsx_enable() will change the state of the
+-		 * RTM CPUID bit.  Force it here since it is now
+-		 * expected to be set.
++		 * tsx_enable() will change the state of the RTM and HLE CPUID
++		 * bits. Force them here since they are now expected to be set.
+ 		 */
+ 		setup_force_cpu_cap(X86_FEATURE_RTM);
++		setup_force_cpu_cap(X86_FEATURE_HLE);
+ 	}
+ }
+diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
+index e699f4d2a450..c91431bc476e 100644
+--- a/arch/x86/kvm/emulate.c
++++ b/arch/x86/kvm/emulate.c
+@@ -5164,16 +5164,28 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
+ 				ctxt->ad_bytes = def_ad_bytes ^ 6;
+ 			break;
+ 		case 0x26:	/* ES override */
++			has_seg_override = true;
++			ctxt->seg_override = VCPU_SREG_ES;
++			break;
+ 		case 0x2e:	/* CS override */
++			has_seg_override = true;
++			ctxt->seg_override = VCPU_SREG_CS;
++			break;
+ 		case 0x36:	/* SS override */
++			has_seg_override = true;
++			ctxt->seg_override = VCPU_SREG_SS;
++			break;
+ 		case 0x3e:	/* DS override */
+ 			has_seg_override = true;
+-			ctxt->seg_override = (ctxt->b >> 3) & 3;
++			ctxt->seg_override = VCPU_SREG_DS;
+ 			break;
+ 		case 0x64:	/* FS override */
++			has_seg_override = true;
++			ctxt->seg_override = VCPU_SREG_FS;
++			break;
+ 		case 0x65:	/* GS override */
+ 			has_seg_override = true;
+-			ctxt->seg_override = ctxt->b & 7;
++			ctxt->seg_override = VCPU_SREG_GS;
+ 			break;
+ 		case 0x40 ... 0x4f: /* REX */
+ 			if (mode != X86EMUL_MODE_PROT64)
+@@ -5257,10 +5269,15 @@ done_prefixes:
+ 			}
+ 			break;
+ 		case Escape:
+-			if (ctxt->modrm > 0xbf)
+-				opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
+-			else
++			if (ctxt->modrm > 0xbf) {
++				size_t size = ARRAY_SIZE(opcode.u.esc->high);
++				u32 index = array_index_nospec(
++					ctxt->modrm - 0xc0, size);
++
++				opcode = opcode.u.esc->high[index];
++			} else {
+ 				opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
++			}
+ 			break;
+ 		case InstrDual:
+ 			if ((ctxt->modrm >> 6) == 3)
+diff --git a/arch/x86/kvm/hyperv.c b/arch/x86/kvm/hyperv.c
+index 5842c5f587fe..3fd6c4b2c2b7 100644
+--- a/arch/x86/kvm/hyperv.c
++++ b/arch/x86/kvm/hyperv.c
+@@ -792,11 +792,12 @@ static int kvm_hv_msr_get_crash_data(struct kvm_vcpu *vcpu,
+ 				     u32 index, u64 *pdata)
+ {
+ 	struct kvm_hv *hv = &vcpu->kvm->arch.hyperv;
++	size_t size = ARRAY_SIZE(hv->hv_crash_param);
+ 
+-	if (WARN_ON_ONCE(index >= ARRAY_SIZE(hv->hv_crash_param)))
++	if (WARN_ON_ONCE(index >= size))
+ 		return -EINVAL;
+ 
+-	*pdata = hv->hv_crash_param[index];
++	*pdata = hv->hv_crash_param[array_index_nospec(index, size)];
+ 	return 0;
+ }
+ 
+@@ -835,11 +836,12 @@ static int kvm_hv_msr_set_crash_data(struct kvm_vcpu *vcpu,
+ 				     u32 index, u64 data)
+ {
+ 	struct kvm_hv *hv = &vcpu->kvm->arch.hyperv;
++	size_t size = ARRAY_SIZE(hv->hv_crash_param);
+ 
+-	if (WARN_ON_ONCE(index >= ARRAY_SIZE(hv->hv_crash_param)))
++	if (WARN_ON_ONCE(index >= size))
+ 		return -EINVAL;
+ 
+-	hv->hv_crash_param[index] = data;
++	hv->hv_crash_param[array_index_nospec(index, size)] = data;
+ 	return 0;
+ }
+ 
+diff --git a/arch/x86/kvm/i8259.c b/arch/x86/kvm/i8259.c
+index bdcd4139eca9..38a36a1cc87f 100644
+--- a/arch/x86/kvm/i8259.c
++++ b/arch/x86/kvm/i8259.c
+@@ -460,10 +460,14 @@ static int picdev_write(struct kvm_pic *s,
+ 	switch (addr) {
+ 	case 0x20:
+ 	case 0x21:
++		pic_lock(s);
++		pic_ioport_write(&s->pics[0], addr, data);
++		pic_unlock(s);
++		break;
+ 	case 0xa0:
+ 	case 0xa1:
+ 		pic_lock(s);
+-		pic_ioport_write(&s->pics[addr >> 7], addr, data);
++		pic_ioport_write(&s->pics[1], addr, data);
+ 		pic_unlock(s);
+ 		break;
+ 	case 0x4d0:
+diff --git a/arch/x86/kvm/ioapic.c b/arch/x86/kvm/ioapic.c
+index 4e822ad363f3..bac2ec9b4443 100644
+--- a/arch/x86/kvm/ioapic.c
++++ b/arch/x86/kvm/ioapic.c
+@@ -36,6 +36,7 @@
+ #include <linux/io.h>
+ #include <linux/slab.h>
+ #include <linux/export.h>
++#include <linux/nospec.h>
+ #include <asm/processor.h>
+ #include <asm/page.h>
+ #include <asm/current.h>
+@@ -73,13 +74,14 @@ static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
+ 	default:
+ 		{
+ 			u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
+-			u64 redir_content;
++			u64 redir_content = ~0ULL;
+ 
+-			if (redir_index < IOAPIC_NUM_PINS)
+-				redir_content =
+-					ioapic->redirtbl[redir_index].bits;
+-			else
+-				redir_content = ~0ULL;
++			if (redir_index < IOAPIC_NUM_PINS) {
++				u32 index = array_index_nospec(
++					redir_index, IOAPIC_NUM_PINS);
++
++				redir_content = ioapic->redirtbl[index].bits;
++			}
+ 
+ 			result = (ioapic->ioregsel & 0x1) ?
+ 			    (redir_content >> 32) & 0xffffffff :
+@@ -297,6 +299,7 @@ static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
+ 		ioapic_debug("change redir index %x val %x\n", index, val);
+ 		if (index >= IOAPIC_NUM_PINS)
+ 			return;
++		index = array_index_nospec(index, IOAPIC_NUM_PINS);
+ 		e = &ioapic->redirtbl[index];
+ 		mask_before = e->fields.mask;
+ 		/* Preserve read-only fields */
+diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
+index 262e49301cae..05905961ecca 100644
+--- a/arch/x86/kvm/lapic.c
++++ b/arch/x86/kvm/lapic.c
+@@ -1862,15 +1862,20 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
+ 	case APIC_LVTTHMR:
+ 	case APIC_LVTPC:
+ 	case APIC_LVT1:
+-	case APIC_LVTERR:
++	case APIC_LVTERR: {
+ 		/* TODO: Check vector */
++		size_t size;
++		u32 index;
++
+ 		if (!kvm_apic_sw_enabled(apic))
+ 			val |= APIC_LVT_MASKED;
+-
+-		val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
++		size = ARRAY_SIZE(apic_lvt_mask);
++		index = array_index_nospec(
++				(reg - APIC_LVTT) >> 4, size);
++		val &= apic_lvt_mask[index];
+ 		kvm_lapic_set_reg(apic, reg, val);
+-
+ 		break;
++	}
+ 
+ 	case APIC_LVTT:
+ 		if (!kvm_apic_sw_enabled(apic))
+diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
+index eddf91a0e363..62f1e4663bc3 100644
+--- a/arch/x86/kvm/mmu.c
++++ b/arch/x86/kvm/mmu.c
+@@ -1184,12 +1184,12 @@ static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn,
+ 	return __mmu_gfn_lpage_is_disallowed(gfn, level, slot);
+ }
+ 
+-static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
++static int host_mapping_level(struct kvm_vcpu *vcpu, gfn_t gfn)
+ {
+ 	unsigned long page_size;
+ 	int i, ret = 0;
+ 
+-	page_size = kvm_host_page_size(kvm, gfn);
++	page_size = kvm_host_page_size(vcpu, gfn);
+ 
+ 	for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
+ 		if (page_size >= KVM_HPAGE_SIZE(i))
+@@ -1239,7 +1239,7 @@ static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
+ 	if (unlikely(*force_pt_level))
+ 		return PT_PAGE_TABLE_LEVEL;
+ 
+-	host_level = host_mapping_level(vcpu->kvm, large_gfn);
++	host_level = host_mapping_level(vcpu, large_gfn);
+ 
+ 	if (host_level == PT_PAGE_TABLE_LEVEL)
+ 		return host_level;
+@@ -3390,7 +3390,7 @@ static bool is_access_allowed(u32 fault_err_code, u64 spte)
+  * - true: let the vcpu to access on the same address again.
+  * - false: let the real page fault path to fix it.
+  */
+-static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
++static bool fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, int level,
+ 			    u32 error_code)
+ {
+ 	struct kvm_shadow_walk_iterator iterator;
+@@ -3410,7 +3410,7 @@ static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
+ 	do {
+ 		u64 new_spte;
+ 
+-		for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
++		for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte)
+ 			if (!is_shadow_present_pte(spte) ||
+ 			    iterator.level < level)
+ 				break;
+@@ -3488,7 +3488,7 @@ static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
+ 
+ 	} while (true);
+ 
+-	trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
++	trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep,
+ 			      spte, fault_handled);
+ 	walk_shadow_page_lockless_end(vcpu);
+ 
+@@ -3496,10 +3496,11 @@ static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
+ }
+ 
+ static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
+-			 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable);
++			 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, bool write,
++			 bool *writable);
+ static int make_mmu_pages_available(struct kvm_vcpu *vcpu);
+ 
+-static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
++static int nonpaging_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
+ 			 gfn_t gfn, bool prefault)
+ {
+ 	int r;
+@@ -3525,16 +3526,16 @@ static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
+ 		gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
+ 	}
+ 
+-	if (fast_page_fault(vcpu, v, level, error_code))
++	if (fast_page_fault(vcpu, gpa, level, error_code))
+ 		return RET_PF_RETRY;
+ 
+ 	mmu_seq = vcpu->kvm->mmu_notifier_seq;
+ 	smp_rmb();
+ 
+-	if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
++	if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
+ 		return RET_PF_RETRY;
+ 
+-	if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
++	if (handle_abnormal_pfn(vcpu, gpa, gfn, pfn, ACC_ALL, &r))
+ 		return r;
+ 
+ 	r = RET_PF_RETRY;
+@@ -3545,7 +3546,7 @@ static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
+ 		goto out_unlock;
+ 	if (likely(!force_pt_level))
+ 		transparent_hugepage_adjust(vcpu, gfn, &pfn, &level);
+-	r = __direct_map(vcpu, v, write, map_writable, level, pfn,
++	r = __direct_map(vcpu, gpa, write, map_writable, level, pfn,
+ 			 prefault, false);
+ out_unlock:
+ 	spin_unlock(&vcpu->kvm->mmu_lock);
+@@ -3838,7 +3839,7 @@ void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
+ }
+ EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
+ 
+-static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
++static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
+ 				  u32 access, struct x86_exception *exception)
+ {
+ 	if (exception)
+@@ -3846,7 +3847,7 @@ static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
+ 	return vaddr;
+ }
+ 
+-static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
++static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
+ 					 u32 access,
+ 					 struct x86_exception *exception)
+ {
+@@ -4006,13 +4007,14 @@ static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
+ 	walk_shadow_page_lockless_end(vcpu);
+ }
+ 
+-static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
++static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
+ 				u32 error_code, bool prefault)
+ {
+-	gfn_t gfn = gva >> PAGE_SHIFT;
++	gfn_t gfn = gpa >> PAGE_SHIFT;
+ 	int r;
+ 
+-	pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
++	/* Note, paging is disabled, ergo gva == gpa. */
++	pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
+ 
+ 	if (page_fault_handle_page_track(vcpu, error_code, gfn))
+ 		return RET_PF_EMULATE;
+@@ -4024,11 +4026,12 @@ static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
+ 	MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
+ 
+ 
+-	return nonpaging_map(vcpu, gva & PAGE_MASK,
++	return nonpaging_map(vcpu, gpa & PAGE_MASK,
+ 			     error_code, gfn, prefault);
+ }
+ 
+-static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
++static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
++				   gfn_t gfn)
+ {
+ 	struct kvm_arch_async_pf arch;
+ 
+@@ -4037,7 +4040,8 @@ static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
+ 	arch.direct_map = vcpu->arch.mmu.direct_map;
+ 	arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
+ 
+-	return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
++	return kvm_setup_async_pf(vcpu, cr2_or_gpa,
++				  kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
+ }
+ 
+ bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
+@@ -4054,7 +4058,8 @@ bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
+ }
+ 
+ static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
+-			 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable)
++			 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, bool write,
++			 bool *writable)
+ {
+ 	struct kvm_memory_slot *slot;
+ 	bool async;
+@@ -4074,12 +4079,12 @@ static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
+ 		return false; /* *pfn has correct page already */
+ 
+ 	if (!prefault && kvm_can_do_async_pf(vcpu)) {
+-		trace_kvm_try_async_get_page(gva, gfn);
++		trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
+ 		if (kvm_find_async_pf_gfn(vcpu, gfn)) {
+-			trace_kvm_async_pf_doublefault(gva, gfn);
++			trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
+ 			kvm_make_request(KVM_REQ_APF_HALT, vcpu);
+ 			return true;
+-		} else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
++		} else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
+ 			return true;
+ 	}
+ 
+@@ -4092,6 +4097,12 @@ int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
+ {
+ 	int r = 1;
+ 
++#ifndef CONFIG_X86_64
++	/* A 64-bit CR2 should be impossible on 32-bit KVM. */
++	if (WARN_ON_ONCE(fault_address >> 32))
++		return -EFAULT;
++#endif
++
+ 	vcpu->arch.l1tf_flush_l1d = true;
+ 	switch (vcpu->arch.apf.host_apf_reason) {
+ 	default:
+@@ -4129,7 +4140,7 @@ check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level)
+ 	return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num);
+ }
+ 
+-static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
++static int tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
+ 			  bool prefault)
+ {
+ 	kvm_pfn_t pfn;
+@@ -5307,7 +5318,7 @@ static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
+ 	return 0;
+ }
+ 
+-int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code,
++int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
+ 		       void *insn, int insn_len)
+ {
+ 	int r, emulation_type = 0;
+@@ -5317,19 +5328,20 @@ int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code,
+ 	/* With shadow page tables, fault_address contains a GVA or nGPA.  */
+ 	if (vcpu->arch.mmu.direct_map) {
+ 		vcpu->arch.gpa_available = true;
+-		vcpu->arch.gpa_val = cr2;
++		vcpu->arch.gpa_val = cr2_or_gpa;
+ 	}
+ 
+ 	r = RET_PF_INVALID;
+ 	if (unlikely(error_code & PFERR_RSVD_MASK)) {
+-		r = handle_mmio_page_fault(vcpu, cr2, direct);
++		r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
+ 		if (r == RET_PF_EMULATE)
+ 			goto emulate;
+ 	}
+ 
+ 	if (r == RET_PF_INVALID) {
+-		r = vcpu->arch.mmu.page_fault(vcpu, cr2, lower_32_bits(error_code),
+-					      false);
++		r = vcpu->arch.mmu.page_fault(vcpu, cr2_or_gpa,
++					       lower_32_bits(error_code),
++					       false);
+ 		WARN_ON(r == RET_PF_INVALID);
+ 	}
+ 
+@@ -5347,7 +5359,7 @@ int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code,
+ 	 */
+ 	if (vcpu->arch.mmu.direct_map &&
+ 	    (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
+-		kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2));
++		kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
+ 		return 1;
+ 	}
+ 
+@@ -5362,7 +5374,7 @@ int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code,
+ 	 * explicitly shadowing L1's page tables, i.e. unprotecting something
+ 	 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
+ 	 */
+-	if (!mmio_info_in_cache(vcpu, cr2, direct) && !is_guest_mode(vcpu))
++	if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
+ 		emulation_type = EMULTYPE_ALLOW_RETRY;
+ emulate:
+ 	/*
+@@ -5375,7 +5387,7 @@ emulate:
+ 	if (unlikely(insn && !insn_len))
+ 		return 1;
+ 
+-	er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
++	er = x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn, insn_len);
+ 
+ 	switch (er) {
+ 	case EMULATE_DONE:
+diff --git a/arch/x86/kvm/mmutrace.h b/arch/x86/kvm/mmutrace.h
+index 918b0d5bf272..cb41b036eb26 100644
+--- a/arch/x86/kvm/mmutrace.h
++++ b/arch/x86/kvm/mmutrace.h
+@@ -249,13 +249,13 @@ TRACE_EVENT(
+ 
+ TRACE_EVENT(
+ 	fast_page_fault,
+-	TP_PROTO(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code,
++	TP_PROTO(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u32 error_code,
+ 		 u64 *sptep, u64 old_spte, bool retry),
+-	TP_ARGS(vcpu, gva, error_code, sptep, old_spte, retry),
++	TP_ARGS(vcpu, cr2_or_gpa, error_code, sptep, old_spte, retry),
+ 
+ 	TP_STRUCT__entry(
+ 		__field(int, vcpu_id)
+-		__field(gva_t, gva)
++		__field(gpa_t, cr2_or_gpa)
+ 		__field(u32, error_code)
+ 		__field(u64 *, sptep)
+ 		__field(u64, old_spte)
+@@ -265,7 +265,7 @@ TRACE_EVENT(
+ 
+ 	TP_fast_assign(
+ 		__entry->vcpu_id = vcpu->vcpu_id;
+-		__entry->gva = gva;
++		__entry->cr2_or_gpa = cr2_or_gpa;
+ 		__entry->error_code = error_code;
+ 		__entry->sptep = sptep;
+ 		__entry->old_spte = old_spte;
+@@ -273,9 +273,9 @@ TRACE_EVENT(
+ 		__entry->retry = retry;
+ 	),
+ 
+-	TP_printk("vcpu %d gva %lx error_code %s sptep %p old %#llx"
++	TP_printk("vcpu %d gva %llx error_code %s sptep %p old %#llx"
+ 		  " new %llx spurious %d fixed %d", __entry->vcpu_id,
+-		  __entry->gva, __print_flags(__entry->error_code, "|",
++		  __entry->cr2_or_gpa, __print_flags(__entry->error_code, "|",
+ 		  kvm_mmu_trace_pferr_flags), __entry->sptep,
+ 		  __entry->old_spte, __entry->new_spte,
+ 		  __spte_satisfied(old_spte), __spte_satisfied(new_spte)
+diff --git a/arch/x86/kvm/mtrr.c b/arch/x86/kvm/mtrr.c
+index 9f72cc427158..fabce87697e5 100644
+--- a/arch/x86/kvm/mtrr.c
++++ b/arch/x86/kvm/mtrr.c
+@@ -194,11 +194,15 @@ static bool fixed_msr_to_seg_unit(u32 msr, int *seg, int *unit)
+ 		break;
+ 	case MSR_MTRRfix16K_80000 ... MSR_MTRRfix16K_A0000:
+ 		*seg = 1;
+-		*unit = msr - MSR_MTRRfix16K_80000;
++		*unit = array_index_nospec(
++			msr - MSR_MTRRfix16K_80000,
++			MSR_MTRRfix16K_A0000 - MSR_MTRRfix16K_80000 + 1);
+ 		break;
+ 	case MSR_MTRRfix4K_C0000 ... MSR_MTRRfix4K_F8000:
+ 		*seg = 2;
+-		*unit = msr - MSR_MTRRfix4K_C0000;
++		*unit = array_index_nospec(
++			msr - MSR_MTRRfix4K_C0000,
++			MSR_MTRRfix4K_F8000 - MSR_MTRRfix4K_C0000 + 1);
+ 		break;
+ 	default:
+ 		return false;
+diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
+index adf42dc8d38b..100ae4fabf17 100644
+--- a/arch/x86/kvm/paging_tmpl.h
++++ b/arch/x86/kvm/paging_tmpl.h
+@@ -273,11 +273,11 @@ static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte)
+ }
+ 
+ /*
+- * Fetch a guest pte for a guest virtual address
++ * Fetch a guest pte for a guest virtual address, or for an L2's GPA.
+  */
+ static int FNAME(walk_addr_generic)(struct guest_walker *walker,
+ 				    struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
+-				    gva_t addr, u32 access)
++				    gpa_t addr, u32 access)
+ {
+ 	int ret;
+ 	pt_element_t pte;
+@@ -478,7 +478,7 @@ error:
+ }
+ 
+ static int FNAME(walk_addr)(struct guest_walker *walker,
+-			    struct kvm_vcpu *vcpu, gva_t addr, u32 access)
++			    struct kvm_vcpu *vcpu, gpa_t addr, u32 access)
+ {
+ 	return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
+ 					access);
+@@ -593,7 +593,7 @@ static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
+  * If the guest tries to write a write-protected page, we need to
+  * emulate this operation, return 1 to indicate this case.
+  */
+-static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
++static int FNAME(fetch)(struct kvm_vcpu *vcpu, gpa_t addr,
+ 			 struct guest_walker *gw,
+ 			 int write_fault, int hlevel,
+ 			 kvm_pfn_t pfn, bool map_writable, bool prefault,
+@@ -747,7 +747,7 @@ FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
+  *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
+  *           a negative value on error.
+  */
+-static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
++static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gpa_t addr, u32 error_code,
+ 			     bool prefault)
+ {
+ 	int write_fault = error_code & PFERR_WRITE_MASK;
+@@ -926,18 +926,19 @@ static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa)
+ 	spin_unlock(&vcpu->kvm->mmu_lock);
+ }
+ 
+-static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
++/* Note, @addr is a GPA when gva_to_gpa() translates an L2 GPA to an L1 GPA. */
++static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gpa_t addr, u32 access,
+ 			       struct x86_exception *exception)
+ {
+ 	struct guest_walker walker;
+ 	gpa_t gpa = UNMAPPED_GVA;
+ 	int r;
+ 
+-	r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
++	r = FNAME(walk_addr)(&walker, vcpu, addr, access);
+ 
+ 	if (r) {
+ 		gpa = gfn_to_gpa(walker.gfn);
+-		gpa |= vaddr & ~PAGE_MASK;
++		gpa |= addr & ~PAGE_MASK;
+ 	} else if (exception)
+ 		*exception = walker.fault;
+ 
+@@ -945,7 +946,8 @@ static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
+ }
+ 
+ #if PTTYPE != PTTYPE_EPT
+-static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
++/* Note, gva_to_gpa_nested() is only used to translate L2 GVAs. */
++static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gpa_t vaddr,
+ 				      u32 access,
+ 				      struct x86_exception *exception)
+ {
+@@ -953,6 +955,11 @@ static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
+ 	gpa_t gpa = UNMAPPED_GVA;
+ 	int r;
+ 
++#ifndef CONFIG_X86_64
++	/* A 64-bit GVA should be impossible on 32-bit KVM. */
++	WARN_ON_ONCE(vaddr >> 32);
++#endif
++
+ 	r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
+ 
+ 	if (r) {
+diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h
+index 22dff661145a..7b4828e50ab3 100644
+--- a/arch/x86/kvm/pmu.h
++++ b/arch/x86/kvm/pmu.h
+@@ -2,6 +2,8 @@
+ #ifndef __KVM_X86_PMU_H
+ #define __KVM_X86_PMU_H
+ 
++#include <linux/nospec.h>
++
+ #define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu)
+ #define pmu_to_vcpu(pmu)  (container_of((pmu), struct kvm_vcpu, arch.pmu))
+ #define pmc_to_pmu(pmc)   (&(pmc)->vcpu->arch.pmu)
+@@ -86,8 +88,12 @@ static inline bool pmc_is_enabled(struct kvm_pmc *pmc)
+ static inline struct kvm_pmc *get_gp_pmc(struct kvm_pmu *pmu, u32 msr,
+ 					 u32 base)
+ {
+-	if (msr >= base && msr < base + pmu->nr_arch_gp_counters)
+-		return &pmu->gp_counters[msr - base];
++	if (msr >= base && msr < base + pmu->nr_arch_gp_counters) {
++		u32 index = array_index_nospec(msr - base,
++					       pmu->nr_arch_gp_counters);
++
++		return &pmu->gp_counters[index];
++	}
+ 
+ 	return NULL;
+ }
+@@ -97,8 +103,12 @@ static inline struct kvm_pmc *get_fixed_pmc(struct kvm_pmu *pmu, u32 msr)
+ {
+ 	int base = MSR_CORE_PERF_FIXED_CTR0;
+ 
+-	if (msr >= base && msr < base + pmu->nr_arch_fixed_counters)
+-		return &pmu->fixed_counters[msr - base];
++	if (msr >= base && msr < base + pmu->nr_arch_fixed_counters) {
++		u32 index = array_index_nospec(msr - base,
++					       pmu->nr_arch_fixed_counters);
++
++		return &pmu->fixed_counters[index];
++	}
+ 
+ 	return NULL;
+ }
+diff --git a/arch/x86/kvm/pmu_intel.c b/arch/x86/kvm/pmu_intel.c
+index c3f103e2b08e..2ab8c20c8bfa 100644
+--- a/arch/x86/kvm/pmu_intel.c
++++ b/arch/x86/kvm/pmu_intel.c
+@@ -87,10 +87,14 @@ static unsigned intel_find_arch_event(struct kvm_pmu *pmu,
+ 
+ static unsigned intel_find_fixed_event(int idx)
+ {
+-	if (idx >= ARRAY_SIZE(fixed_pmc_events))
++	u32 event;
++	size_t size = ARRAY_SIZE(fixed_pmc_events);
++
++	if (idx >= size)
+ 		return PERF_COUNT_HW_MAX;
+ 
+-	return intel_arch_events[fixed_pmc_events[idx]].event_type;
++	event = fixed_pmc_events[array_index_nospec(idx, size)];
++	return intel_arch_events[event].event_type;
+ }
+ 
+ /* check if a PMC is enabled by comparing it with globl_ctrl bits. */
+@@ -131,16 +135,20 @@ static struct kvm_pmc *intel_msr_idx_to_pmc(struct kvm_vcpu *vcpu,
+ 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
+ 	bool fixed = idx & (1u << 30);
+ 	struct kvm_pmc *counters;
++	unsigned int num_counters;
+ 
+ 	idx &= ~(3u << 30);
+-	if (!fixed && idx >= pmu->nr_arch_gp_counters)
+-		return NULL;
+-	if (fixed && idx >= pmu->nr_arch_fixed_counters)
++	if (fixed) {
++		counters = pmu->fixed_counters;
++		num_counters = pmu->nr_arch_fixed_counters;
++	} else {
++		counters = pmu->gp_counters;
++		num_counters = pmu->nr_arch_gp_counters;
++	}
++	if (idx >= num_counters)
+ 		return NULL;
+-	counters = fixed ? pmu->fixed_counters : pmu->gp_counters;
+ 	*mask &= pmu->counter_bitmask[fixed ? KVM_PMC_FIXED : KVM_PMC_GP];
+-
+-	return &counters[idx];
++	return &counters[array_index_nospec(idx, num_counters)];
+ }
+ 
+ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
+diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
+index fa2abed1a14d..2660c01eadae 100644
+--- a/arch/x86/kvm/vmx.c
++++ b/arch/x86/kvm/vmx.c
+@@ -8793,8 +8793,10 @@ static int handle_vmread(struct kvm_vcpu *vcpu)
+ 		/* _system ok, nested_vmx_check_permission has verified cpl=0 */
+ 		if (kvm_write_guest_virt_system(vcpu, gva, &field_value,
+ 						(is_long_mode(vcpu) ? 8 : 4),
+-						&e))
++						&e)) {
+ 			kvm_inject_page_fault(vcpu, &e);
++			return 1;
++		}
+ 	}
+ 
+ 	nested_vmx_succeed(vcpu);
+diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
+new file mode 100644
+index 000000000000..3791ce8d269e
+--- /dev/null
++++ b/arch/x86/kvm/vmx/vmx.c
+@@ -0,0 +1,8033 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Kernel-based Virtual Machine driver for Linux
++ *
++ * This module enables machines with Intel VT-x extensions to run virtual
++ * machines without emulation or binary translation.
++ *
++ * Copyright (C) 2006 Qumranet, Inc.
++ * Copyright 2010 Red Hat, Inc. and/or its affiliates.
++ *
++ * Authors:
++ *   Avi Kivity   <avi@××××××××.com>
++ *   Yaniv Kamay  <yaniv@××××××××.com>
++ */
++
++#include <linux/frame.h>
++#include <linux/highmem.h>
++#include <linux/hrtimer.h>
++#include <linux/kernel.h>
++#include <linux/kvm_host.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/mod_devicetable.h>
++#include <linux/mm.h>
++#include <linux/sched.h>
++#include <linux/sched/smt.h>
++#include <linux/slab.h>
++#include <linux/tboot.h>
++#include <linux/trace_events.h>
++
++#include <asm/apic.h>
++#include <asm/asm.h>
++#include <asm/cpu.h>
++#include <asm/debugreg.h>
++#include <asm/desc.h>
++#include <asm/fpu/internal.h>
++#include <asm/io.h>
++#include <asm/irq_remapping.h>
++#include <asm/kexec.h>
++#include <asm/perf_event.h>
++#include <asm/mce.h>
++#include <asm/mmu_context.h>
++#include <asm/mshyperv.h>
++#include <asm/spec-ctrl.h>
++#include <asm/virtext.h>
++#include <asm/vmx.h>
++
++#include "capabilities.h"
++#include "cpuid.h"
++#include "evmcs.h"
++#include "irq.h"
++#include "kvm_cache_regs.h"
++#include "lapic.h"
++#include "mmu.h"
++#include "nested.h"
++#include "ops.h"
++#include "pmu.h"
++#include "trace.h"
++#include "vmcs.h"
++#include "vmcs12.h"
++#include "vmx.h"
++#include "x86.h"
++
++MODULE_AUTHOR("Qumranet");
++MODULE_LICENSE("GPL");
++
++static const struct x86_cpu_id vmx_cpu_id[] = {
++	X86_FEATURE_MATCH(X86_FEATURE_VMX),
++	{}
++};
++MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
++
++bool __read_mostly enable_vpid = 1;
++module_param_named(vpid, enable_vpid, bool, 0444);
++
++static bool __read_mostly enable_vnmi = 1;
++module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
++
++bool __read_mostly flexpriority_enabled = 1;
++module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
++
++bool __read_mostly enable_ept = 1;
++module_param_named(ept, enable_ept, bool, S_IRUGO);
++
++bool __read_mostly enable_unrestricted_guest = 1;
++module_param_named(unrestricted_guest,
++			enable_unrestricted_guest, bool, S_IRUGO);
++
++bool __read_mostly enable_ept_ad_bits = 1;
++module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
++
++static bool __read_mostly emulate_invalid_guest_state = true;
++module_param(emulate_invalid_guest_state, bool, S_IRUGO);
++
++static bool __read_mostly fasteoi = 1;
++module_param(fasteoi, bool, S_IRUGO);
++
++static bool __read_mostly enable_apicv = 1;
++module_param(enable_apicv, bool, S_IRUGO);
++
++/*
++ * If nested=1, nested virtualization is supported, i.e., guests may use
++ * VMX and be a hypervisor for its own guests. If nested=0, guests may not
++ * use VMX instructions.
++ */
++static bool __read_mostly nested = 1;
++module_param(nested, bool, S_IRUGO);
++
++bool __read_mostly enable_pml = 1;
++module_param_named(pml, enable_pml, bool, S_IRUGO);
++
++static bool __read_mostly dump_invalid_vmcs = 0;
++module_param(dump_invalid_vmcs, bool, 0644);
++
++#define MSR_BITMAP_MODE_X2APIC		1
++#define MSR_BITMAP_MODE_X2APIC_APICV	2
++
++#define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
++
++/* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
++static int __read_mostly cpu_preemption_timer_multi;
++static bool __read_mostly enable_preemption_timer = 1;
++#ifdef CONFIG_X86_64
++module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
++#endif
++
++#define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
++#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
++#define KVM_VM_CR0_ALWAYS_ON				\
++	(KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | 	\
++	 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
++#define KVM_CR4_GUEST_OWNED_BITS				      \
++	(X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
++	 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
++
++#define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
++#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
++#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
++
++#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
++
++#define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
++	RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
++	RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
++	RTIT_STATUS_BYTECNT))
++
++#define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
++	(~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
++
++/*
++ * These 2 parameters are used to config the controls for Pause-Loop Exiting:
++ * ple_gap:    upper bound on the amount of time between two successive
++ *             executions of PAUSE in a loop. Also indicate if ple enabled.
++ *             According to test, this time is usually smaller than 128 cycles.
++ * ple_window: upper bound on the amount of time a guest is allowed to execute
++ *             in a PAUSE loop. Tests indicate that most spinlocks are held for
++ *             less than 2^12 cycles
++ * Time is measured based on a counter that runs at the same rate as the TSC,
++ * refer SDM volume 3b section 21.6.13 & 22.1.3.
++ */
++static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
++module_param(ple_gap, uint, 0444);
++
++static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
++module_param(ple_window, uint, 0444);
++
++/* Default doubles per-vcpu window every exit. */
++static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
++module_param(ple_window_grow, uint, 0444);
++
++/* Default resets per-vcpu window every exit to ple_window. */
++static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
++module_param(ple_window_shrink, uint, 0444);
++
++/* Default is to compute the maximum so we can never overflow. */
++static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
++module_param(ple_window_max, uint, 0444);
++
++/* Default is SYSTEM mode, 1 for host-guest mode */
++int __read_mostly pt_mode = PT_MODE_SYSTEM;
++module_param(pt_mode, int, S_IRUGO);
++
++static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
++static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
++static DEFINE_MUTEX(vmx_l1d_flush_mutex);
++
++/* Storage for pre module init parameter parsing */
++static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
++
++static const struct {
++	const char *option;
++	bool for_parse;
++} vmentry_l1d_param[] = {
++	[VMENTER_L1D_FLUSH_AUTO]	 = {"auto", true},
++	[VMENTER_L1D_FLUSH_NEVER]	 = {"never", true},
++	[VMENTER_L1D_FLUSH_COND]	 = {"cond", true},
++	[VMENTER_L1D_FLUSH_ALWAYS]	 = {"always", true},
++	[VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
++	[VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
++};
++
++#define L1D_CACHE_ORDER 4
++static void *vmx_l1d_flush_pages;
++
++static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
++{
++	struct page *page;
++	unsigned int i;
++
++	if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
++		l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
++		return 0;
++	}
++
++	if (!enable_ept) {
++		l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
++		return 0;
++	}
++
++	if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
++		u64 msr;
++
++		rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
++		if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
++			l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
++			return 0;
++		}
++	}
++
++	/* If set to auto use the default l1tf mitigation method */
++	if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
++		switch (l1tf_mitigation) {
++		case L1TF_MITIGATION_OFF:
++			l1tf = VMENTER_L1D_FLUSH_NEVER;
++			break;
++		case L1TF_MITIGATION_FLUSH_NOWARN:
++		case L1TF_MITIGATION_FLUSH:
++		case L1TF_MITIGATION_FLUSH_NOSMT:
++			l1tf = VMENTER_L1D_FLUSH_COND;
++			break;
++		case L1TF_MITIGATION_FULL:
++		case L1TF_MITIGATION_FULL_FORCE:
++			l1tf = VMENTER_L1D_FLUSH_ALWAYS;
++			break;
++		}
++	} else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
++		l1tf = VMENTER_L1D_FLUSH_ALWAYS;
++	}
++
++	if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
++	    !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
++		/*
++		 * This allocation for vmx_l1d_flush_pages is not tied to a VM
++		 * lifetime and so should not be charged to a memcg.
++		 */
++		page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
++		if (!page)
++			return -ENOMEM;
++		vmx_l1d_flush_pages = page_address(page);
++
++		/*
++		 * Initialize each page with a different pattern in
++		 * order to protect against KSM in the nested
++		 * virtualization case.
++		 */
++		for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
++			memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
++			       PAGE_SIZE);
++		}
++	}
++
++	l1tf_vmx_mitigation = l1tf;
++
++	if (l1tf != VMENTER_L1D_FLUSH_NEVER)
++		static_branch_enable(&vmx_l1d_should_flush);
++	else
++		static_branch_disable(&vmx_l1d_should_flush);
++
++	if (l1tf == VMENTER_L1D_FLUSH_COND)
++		static_branch_enable(&vmx_l1d_flush_cond);
++	else
++		static_branch_disable(&vmx_l1d_flush_cond);
++	return 0;
++}
++
++static int vmentry_l1d_flush_parse(const char *s)
++{
++	unsigned int i;
++
++	if (s) {
++		for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
++			if (vmentry_l1d_param[i].for_parse &&
++			    sysfs_streq(s, vmentry_l1d_param[i].option))
++				return i;
++		}
++	}
++	return -EINVAL;
++}
++
++static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
++{
++	int l1tf, ret;
++
++	l1tf = vmentry_l1d_flush_parse(s);
++	if (l1tf < 0)
++		return l1tf;
++
++	if (!boot_cpu_has(X86_BUG_L1TF))
++		return 0;
++
++	/*
++	 * Has vmx_init() run already? If not then this is the pre init
++	 * parameter parsing. In that case just store the value and let
++	 * vmx_init() do the proper setup after enable_ept has been
++	 * established.
++	 */
++	if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
++		vmentry_l1d_flush_param = l1tf;
++		return 0;
++	}
++
++	mutex_lock(&vmx_l1d_flush_mutex);
++	ret = vmx_setup_l1d_flush(l1tf);
++	mutex_unlock(&vmx_l1d_flush_mutex);
++	return ret;
++}
++
++static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
++{
++	if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
++		return sprintf(s, "???\n");
++
++	return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
++}
++
++static const struct kernel_param_ops vmentry_l1d_flush_ops = {
++	.set = vmentry_l1d_flush_set,
++	.get = vmentry_l1d_flush_get,
++};
++module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
++
++static bool guest_state_valid(struct kvm_vcpu *vcpu);
++static u32 vmx_segment_access_rights(struct kvm_segment *var);
++static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
++							  u32 msr, int type);
++
++void vmx_vmexit(void);
++
++#define vmx_insn_failed(fmt...)		\
++do {					\
++	WARN_ONCE(1, fmt);		\
++	pr_warn_ratelimited(fmt);	\
++} while (0)
++
++asmlinkage void vmread_error(unsigned long field, bool fault)
++{
++	if (fault)
++		kvm_spurious_fault();
++	else
++		vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
++}
++
++noinline void vmwrite_error(unsigned long field, unsigned long value)
++{
++	vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
++			field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
++}
++
++noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
++{
++	vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
++}
++
++noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
++{
++	vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
++}
++
++noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
++{
++	vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
++			ext, vpid, gva);
++}
++
++noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
++{
++	vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
++			ext, eptp, gpa);
++}
++
++static DEFINE_PER_CPU(struct vmcs *, vmxarea);
++DEFINE_PER_CPU(struct vmcs *, current_vmcs);
++/*
++ * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
++ * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
++ */
++static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
++
++/*
++ * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
++ * can find which vCPU should be waken up.
++ */
++static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
++static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
++
++static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
++static DEFINE_SPINLOCK(vmx_vpid_lock);
++
++struct vmcs_config vmcs_config;
++struct vmx_capability vmx_capability;
++
++#define VMX_SEGMENT_FIELD(seg)					\
++	[VCPU_SREG_##seg] = {                                   \
++		.selector = GUEST_##seg##_SELECTOR,		\
++		.base = GUEST_##seg##_BASE,		   	\
++		.limit = GUEST_##seg##_LIMIT,		   	\
++		.ar_bytes = GUEST_##seg##_AR_BYTES,	   	\
++	}
++
++static const struct kvm_vmx_segment_field {
++	unsigned selector;
++	unsigned base;
++	unsigned limit;
++	unsigned ar_bytes;
++} kvm_vmx_segment_fields[] = {
++	VMX_SEGMENT_FIELD(CS),
++	VMX_SEGMENT_FIELD(DS),
++	VMX_SEGMENT_FIELD(ES),
++	VMX_SEGMENT_FIELD(FS),
++	VMX_SEGMENT_FIELD(GS),
++	VMX_SEGMENT_FIELD(SS),
++	VMX_SEGMENT_FIELD(TR),
++	VMX_SEGMENT_FIELD(LDTR),
++};
++
++u64 host_efer;
++static unsigned long host_idt_base;
++
++/*
++ * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
++ * will emulate SYSCALL in legacy mode if the vendor string in guest
++ * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
++ * support this emulation, IA32_STAR must always be included in
++ * vmx_msr_index[], even in i386 builds.
++ */
++const u32 vmx_msr_index[] = {
++#ifdef CONFIG_X86_64
++	MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
++#endif
++	MSR_EFER, MSR_TSC_AUX, MSR_STAR,
++	MSR_IA32_TSX_CTRL,
++};
++
++#if IS_ENABLED(CONFIG_HYPERV)
++static bool __read_mostly enlightened_vmcs = true;
++module_param(enlightened_vmcs, bool, 0444);
++
++/* check_ept_pointer() should be under protection of ept_pointer_lock. */
++static void check_ept_pointer_match(struct kvm *kvm)
++{
++	struct kvm_vcpu *vcpu;
++	u64 tmp_eptp = INVALID_PAGE;
++	int i;
++
++	kvm_for_each_vcpu(i, vcpu, kvm) {
++		if (!VALID_PAGE(tmp_eptp)) {
++			tmp_eptp = to_vmx(vcpu)->ept_pointer;
++		} else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
++			to_kvm_vmx(kvm)->ept_pointers_match
++				= EPT_POINTERS_MISMATCH;
++			return;
++		}
++	}
++
++	to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
++}
++
++static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
++		void *data)
++{
++	struct kvm_tlb_range *range = data;
++
++	return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
++			range->pages);
++}
++
++static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
++		struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
++{
++	u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
++
++	/*
++	 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
++	 * of the base of EPT PML4 table, strip off EPT configuration
++	 * information.
++	 */
++	if (range)
++		return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
++				kvm_fill_hv_flush_list_func, (void *)range);
++	else
++		return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
++}
++
++static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
++		struct kvm_tlb_range *range)
++{
++	struct kvm_vcpu *vcpu;
++	int ret = 0, i;
++
++	spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
++
++	if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
++		check_ept_pointer_match(kvm);
++
++	if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
++		kvm_for_each_vcpu(i, vcpu, kvm) {
++			/* If ept_pointer is invalid pointer, bypass flush request. */
++			if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
++				ret |= __hv_remote_flush_tlb_with_range(
++					kvm, vcpu, range);
++		}
++	} else {
++		ret = __hv_remote_flush_tlb_with_range(kvm,
++				kvm_get_vcpu(kvm, 0), range);
++	}
++
++	spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
++	return ret;
++}
++static int hv_remote_flush_tlb(struct kvm *kvm)
++{
++	return hv_remote_flush_tlb_with_range(kvm, NULL);
++}
++
++static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
++{
++	struct hv_enlightened_vmcs *evmcs;
++	struct hv_partition_assist_pg **p_hv_pa_pg =
++			&vcpu->kvm->arch.hyperv.hv_pa_pg;
++	/*
++	 * Synthetic VM-Exit is not enabled in current code and so All
++	 * evmcs in singe VM shares same assist page.
++	 */
++	if (!*p_hv_pa_pg)
++		*p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
++
++	if (!*p_hv_pa_pg)
++		return -ENOMEM;
++
++	evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
++
++	evmcs->partition_assist_page =
++		__pa(*p_hv_pa_pg);
++	evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
++	evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
++
++	return 0;
++}
++
++#endif /* IS_ENABLED(CONFIG_HYPERV) */
++
++/*
++ * Comment's format: document - errata name - stepping - processor name.
++ * Refer from
++ * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
++ */
++static u32 vmx_preemption_cpu_tfms[] = {
++/* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
++0x000206E6,
++/* 323056.pdf - AAX65  - C2 - Xeon L3406 */
++/* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
++/* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
++0x00020652,
++/* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
++0x00020655,
++/* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
++/* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
++/*
++ * 320767.pdf - AAP86  - B1 -
++ * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
++ */
++0x000106E5,
++/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
++0x000106A0,
++/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
++0x000106A1,
++/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
++0x000106A4,
++ /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
++ /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
++ /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
++0x000106A5,
++ /* Xeon E3-1220 V2 */
++0x000306A8,
++};
++
++static inline bool cpu_has_broken_vmx_preemption_timer(void)
++{
++	u32 eax = cpuid_eax(0x00000001), i;
++
++	/* Clear the reserved bits */
++	eax &= ~(0x3U << 14 | 0xfU << 28);
++	for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
++		if (eax == vmx_preemption_cpu_tfms[i])
++			return true;
++
++	return false;
++}
++
++static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
++{
++	return flexpriority_enabled && lapic_in_kernel(vcpu);
++}
++
++static inline bool report_flexpriority(void)
++{
++	return flexpriority_enabled;
++}
++
++static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
++{
++	int i;
++
++	for (i = 0; i < vmx->nmsrs; ++i)
++		if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
++			return i;
++	return -1;
++}
++
++struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
++{
++	int i;
++
++	i = __find_msr_index(vmx, msr);
++	if (i >= 0)
++		return &vmx->guest_msrs[i];
++	return NULL;
++}
++
++static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
++{
++	int ret = 0;
++
++	u64 old_msr_data = msr->data;
++	msr->data = data;
++	if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
++		preempt_disable();
++		ret = kvm_set_shared_msr(msr->index, msr->data,
++					 msr->mask);
++		preempt_enable();
++		if (ret)
++			msr->data = old_msr_data;
++	}
++	return ret;
++}
++
++void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
++{
++	vmcs_clear(loaded_vmcs->vmcs);
++	if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
++		vmcs_clear(loaded_vmcs->shadow_vmcs);
++	loaded_vmcs->cpu = -1;
++	loaded_vmcs->launched = 0;
++}
++
++#ifdef CONFIG_KEXEC_CORE
++/*
++ * This bitmap is used to indicate whether the vmclear
++ * operation is enabled on all cpus. All disabled by
++ * default.
++ */
++static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
++
++static inline void crash_enable_local_vmclear(int cpu)
++{
++	cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
++}
++
++static inline void crash_disable_local_vmclear(int cpu)
++{
++	cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
++}
++
++static inline int crash_local_vmclear_enabled(int cpu)
++{
++	return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
++}
++
++static void crash_vmclear_local_loaded_vmcss(void)
++{
++	int cpu = raw_smp_processor_id();
++	struct loaded_vmcs *v;
++
++	if (!crash_local_vmclear_enabled(cpu))
++		return;
++
++	list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
++			    loaded_vmcss_on_cpu_link)
++		vmcs_clear(v->vmcs);
++}
++#else
++static inline void crash_enable_local_vmclear(int cpu) { }
++static inline void crash_disable_local_vmclear(int cpu) { }
++#endif /* CONFIG_KEXEC_CORE */
++
++static void __loaded_vmcs_clear(void *arg)
++{
++	struct loaded_vmcs *loaded_vmcs = arg;
++	int cpu = raw_smp_processor_id();
++
++	if (loaded_vmcs->cpu != cpu)
++		return; /* vcpu migration can race with cpu offline */
++	if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
++		per_cpu(current_vmcs, cpu) = NULL;
++	crash_disable_local_vmclear(cpu);
++	list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
++
++	/*
++	 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
++	 * is before setting loaded_vmcs->vcpu to -1 which is done in
++	 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
++	 * then adds the vmcs into percpu list before it is deleted.
++	 */
++	smp_wmb();
++
++	loaded_vmcs_init(loaded_vmcs);
++	crash_enable_local_vmclear(cpu);
++}
++
++void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
++{
++	int cpu = loaded_vmcs->cpu;
++
++	if (cpu != -1)
++		smp_call_function_single(cpu,
++			 __loaded_vmcs_clear, loaded_vmcs, 1);
++}
++
++static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
++				       unsigned field)
++{
++	bool ret;
++	u32 mask = 1 << (seg * SEG_FIELD_NR + field);
++
++	if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
++		kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
++		vmx->segment_cache.bitmask = 0;
++	}
++	ret = vmx->segment_cache.bitmask & mask;
++	vmx->segment_cache.bitmask |= mask;
++	return ret;
++}
++
++static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
++{
++	u16 *p = &vmx->segment_cache.seg[seg].selector;
++
++	if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
++		*p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
++	return *p;
++}
++
++static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
++{
++	ulong *p = &vmx->segment_cache.seg[seg].base;
++
++	if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
++		*p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
++	return *p;
++}
++
++static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
++{
++	u32 *p = &vmx->segment_cache.seg[seg].limit;
++
++	if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
++		*p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
++	return *p;
++}
++
++static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
++{
++	u32 *p = &vmx->segment_cache.seg[seg].ar;
++
++	if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
++		*p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
++	return *p;
++}
++
++void update_exception_bitmap(struct kvm_vcpu *vcpu)
++{
++	u32 eb;
++
++	eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
++	     (1u << DB_VECTOR) | (1u << AC_VECTOR);
++	/*
++	 * Guest access to VMware backdoor ports could legitimately
++	 * trigger #GP because of TSS I/O permission bitmap.
++	 * We intercept those #GP and allow access to them anyway
++	 * as VMware does.
++	 */
++	if (enable_vmware_backdoor)
++		eb |= (1u << GP_VECTOR);
++	if ((vcpu->guest_debug &
++	     (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
++	    (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
++		eb |= 1u << BP_VECTOR;
++	if (to_vmx(vcpu)->rmode.vm86_active)
++		eb = ~0;
++	if (enable_ept)
++		eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
++
++	/* When we are running a nested L2 guest and L1 specified for it a
++	 * certain exception bitmap, we must trap the same exceptions and pass
++	 * them to L1. When running L2, we will only handle the exceptions
++	 * specified above if L1 did not want them.
++	 */
++	if (is_guest_mode(vcpu))
++		eb |= get_vmcs12(vcpu)->exception_bitmap;
++
++	vmcs_write32(EXCEPTION_BITMAP, eb);
++}
++
++/*
++ * Check if MSR is intercepted for currently loaded MSR bitmap.
++ */
++static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
++{
++	unsigned long *msr_bitmap;
++	int f = sizeof(unsigned long);
++
++	if (!cpu_has_vmx_msr_bitmap())
++		return true;
++
++	msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
++
++	if (msr <= 0x1fff) {
++		return !!test_bit(msr, msr_bitmap + 0x800 / f);
++	} else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
++		msr &= 0x1fff;
++		return !!test_bit(msr, msr_bitmap + 0xc00 / f);
++	}
++
++	return true;
++}
++
++static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
++		unsigned long entry, unsigned long exit)
++{
++	vm_entry_controls_clearbit(vmx, entry);
++	vm_exit_controls_clearbit(vmx, exit);
++}
++
++int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
++{
++	unsigned int i;
++
++	for (i = 0; i < m->nr; ++i) {
++		if (m->val[i].index == msr)
++			return i;
++	}
++	return -ENOENT;
++}
++
++static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
++{
++	int i;
++	struct msr_autoload *m = &vmx->msr_autoload;
++
++	switch (msr) {
++	case MSR_EFER:
++		if (cpu_has_load_ia32_efer()) {
++			clear_atomic_switch_msr_special(vmx,
++					VM_ENTRY_LOAD_IA32_EFER,
++					VM_EXIT_LOAD_IA32_EFER);
++			return;
++		}
++		break;
++	case MSR_CORE_PERF_GLOBAL_CTRL:
++		if (cpu_has_load_perf_global_ctrl()) {
++			clear_atomic_switch_msr_special(vmx,
++					VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
++					VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
++			return;
++		}
++		break;
++	}
++	i = vmx_find_msr_index(&m->guest, msr);
++	if (i < 0)
++		goto skip_guest;
++	--m->guest.nr;
++	m->guest.val[i] = m->guest.val[m->guest.nr];
++	vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
++
++skip_guest:
++	i = vmx_find_msr_index(&m->host, msr);
++	if (i < 0)
++		return;
++
++	--m->host.nr;
++	m->host.val[i] = m->host.val[m->host.nr];
++	vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
++}
++
++static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
++		unsigned long entry, unsigned long exit,
++		unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
++		u64 guest_val, u64 host_val)
++{
++	vmcs_write64(guest_val_vmcs, guest_val);
++	if (host_val_vmcs != HOST_IA32_EFER)
++		vmcs_write64(host_val_vmcs, host_val);
++	vm_entry_controls_setbit(vmx, entry);
++	vm_exit_controls_setbit(vmx, exit);
++}
++
++static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
++				  u64 guest_val, u64 host_val, bool entry_only)
++{
++	int i, j = 0;
++	struct msr_autoload *m = &vmx->msr_autoload;
++
++	switch (msr) {
++	case MSR_EFER:
++		if (cpu_has_load_ia32_efer()) {
++			add_atomic_switch_msr_special(vmx,
++					VM_ENTRY_LOAD_IA32_EFER,
++					VM_EXIT_LOAD_IA32_EFER,
++					GUEST_IA32_EFER,
++					HOST_IA32_EFER,
++					guest_val, host_val);
++			return;
++		}
++		break;
++	case MSR_CORE_PERF_GLOBAL_CTRL:
++		if (cpu_has_load_perf_global_ctrl()) {
++			add_atomic_switch_msr_special(vmx,
++					VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
++					VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
++					GUEST_IA32_PERF_GLOBAL_CTRL,
++					HOST_IA32_PERF_GLOBAL_CTRL,
++					guest_val, host_val);
++			return;
++		}
++		break;
++	case MSR_IA32_PEBS_ENABLE:
++		/* PEBS needs a quiescent period after being disabled (to write
++		 * a record).  Disabling PEBS through VMX MSR swapping doesn't
++		 * provide that period, so a CPU could write host's record into
++		 * guest's memory.
++		 */
++		wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
++	}
++
++	i = vmx_find_msr_index(&m->guest, msr);
++	if (!entry_only)
++		j = vmx_find_msr_index(&m->host, msr);
++
++	if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
++		(j < 0 &&  m->host.nr == NR_LOADSTORE_MSRS)) {
++		printk_once(KERN_WARNING "Not enough msr switch entries. "
++				"Can't add msr %x\n", msr);
++		return;
++	}
++	if (i < 0) {
++		i = m->guest.nr++;
++		vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
++	}
++	m->guest.val[i].index = msr;
++	m->guest.val[i].value = guest_val;
++
++	if (entry_only)
++		return;
++
++	if (j < 0) {
++		j = m->host.nr++;
++		vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
++	}
++	m->host.val[j].index = msr;
++	m->host.val[j].value = host_val;
++}
++
++static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
++{
++	u64 guest_efer = vmx->vcpu.arch.efer;
++	u64 ignore_bits = 0;
++
++	/* Shadow paging assumes NX to be available.  */
++	if (!enable_ept)
++		guest_efer |= EFER_NX;
++
++	/*
++	 * LMA and LME handled by hardware; SCE meaningless outside long mode.
++	 */
++	ignore_bits |= EFER_SCE;
++#ifdef CONFIG_X86_64
++	ignore_bits |= EFER_LMA | EFER_LME;
++	/* SCE is meaningful only in long mode on Intel */
++	if (guest_efer & EFER_LMA)
++		ignore_bits &= ~(u64)EFER_SCE;
++#endif
++
++	/*
++	 * On EPT, we can't emulate NX, so we must switch EFER atomically.
++	 * On CPUs that support "load IA32_EFER", always switch EFER
++	 * atomically, since it's faster than switching it manually.
++	 */
++	if (cpu_has_load_ia32_efer() ||
++	    (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
++		if (!(guest_efer & EFER_LMA))
++			guest_efer &= ~EFER_LME;
++		if (guest_efer != host_efer)
++			add_atomic_switch_msr(vmx, MSR_EFER,
++					      guest_efer, host_efer, false);
++		else
++			clear_atomic_switch_msr(vmx, MSR_EFER);
++		return false;
++	} else {
++		clear_atomic_switch_msr(vmx, MSR_EFER);
++
++		guest_efer &= ~ignore_bits;
++		guest_efer |= host_efer & ignore_bits;
++
++		vmx->guest_msrs[efer_offset].data = guest_efer;
++		vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
++
++		return true;
++	}
++}
++
++#ifdef CONFIG_X86_32
++/*
++ * On 32-bit kernels, VM exits still load the FS and GS bases from the
++ * VMCS rather than the segment table.  KVM uses this helper to figure
++ * out the current bases to poke them into the VMCS before entry.
++ */
++static unsigned long segment_base(u16 selector)
++{
++	struct desc_struct *table;
++	unsigned long v;
++
++	if (!(selector & ~SEGMENT_RPL_MASK))
++		return 0;
++
++	table = get_current_gdt_ro();
++
++	if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
++		u16 ldt_selector = kvm_read_ldt();
++
++		if (!(ldt_selector & ~SEGMENT_RPL_MASK))
++			return 0;
++
++		table = (struct desc_struct *)segment_base(ldt_selector);
++	}
++	v = get_desc_base(&table[selector >> 3]);
++	return v;
++}
++#endif
++
++static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
++{
++	u32 i;
++
++	wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
++	wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
++	wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
++	wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
++	for (i = 0; i < addr_range; i++) {
++		wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
++		wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
++	}
++}
++
++static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
++{
++	u32 i;
++
++	rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
++	rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
++	rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
++	rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
++	for (i = 0; i < addr_range; i++) {
++		rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
++		rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
++	}
++}
++
++static void pt_guest_enter(struct vcpu_vmx *vmx)
++{
++	if (pt_mode == PT_MODE_SYSTEM)
++		return;
++
++	/*
++	 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
++	 * Save host state before VM entry.
++	 */
++	rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
++	if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
++		wrmsrl(MSR_IA32_RTIT_CTL, 0);
++		pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
++		pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
++	}
++}
++
++static void pt_guest_exit(struct vcpu_vmx *vmx)
++{
++	if (pt_mode == PT_MODE_SYSTEM)
++		return;
++
++	if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
++		pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
++		pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
++	}
++
++	/* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
++	wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
++}
++
++void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
++			unsigned long fs_base, unsigned long gs_base)
++{
++	if (unlikely(fs_sel != host->fs_sel)) {
++		if (!(fs_sel & 7))
++			vmcs_write16(HOST_FS_SELECTOR, fs_sel);
++		else
++			vmcs_write16(HOST_FS_SELECTOR, 0);
++		host->fs_sel = fs_sel;
++	}
++	if (unlikely(gs_sel != host->gs_sel)) {
++		if (!(gs_sel & 7))
++			vmcs_write16(HOST_GS_SELECTOR, gs_sel);
++		else
++			vmcs_write16(HOST_GS_SELECTOR, 0);
++		host->gs_sel = gs_sel;
++	}
++	if (unlikely(fs_base != host->fs_base)) {
++		vmcs_writel(HOST_FS_BASE, fs_base);
++		host->fs_base = fs_base;
++	}
++	if (unlikely(gs_base != host->gs_base)) {
++		vmcs_writel(HOST_GS_BASE, gs_base);
++		host->gs_base = gs_base;
++	}
++}
++
++void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	struct vmcs_host_state *host_state;
++#ifdef CONFIG_X86_64
++	int cpu = raw_smp_processor_id();
++#endif
++	unsigned long fs_base, gs_base;
++	u16 fs_sel, gs_sel;
++	int i;
++
++	vmx->req_immediate_exit = false;
++
++	/*
++	 * Note that guest MSRs to be saved/restored can also be changed
++	 * when guest state is loaded. This happens when guest transitions
++	 * to/from long-mode by setting MSR_EFER.LMA.
++	 */
++	if (!vmx->guest_msrs_ready) {
++		vmx->guest_msrs_ready = true;
++		for (i = 0; i < vmx->save_nmsrs; ++i)
++			kvm_set_shared_msr(vmx->guest_msrs[i].index,
++					   vmx->guest_msrs[i].data,
++					   vmx->guest_msrs[i].mask);
++
++	}
++	if (vmx->guest_state_loaded)
++		return;
++
++	host_state = &vmx->loaded_vmcs->host_state;
++
++	/*
++	 * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
++	 * allow segment selectors with cpl > 0 or ti == 1.
++	 */
++	host_state->ldt_sel = kvm_read_ldt();
++
++#ifdef CONFIG_X86_64
++	savesegment(ds, host_state->ds_sel);
++	savesegment(es, host_state->es_sel);
++
++	gs_base = cpu_kernelmode_gs_base(cpu);
++	if (likely(is_64bit_mm(current->mm))) {
++		save_fsgs_for_kvm();
++		fs_sel = current->thread.fsindex;
++		gs_sel = current->thread.gsindex;
++		fs_base = current->thread.fsbase;
++		vmx->msr_host_kernel_gs_base = current->thread.gsbase;
++	} else {
++		savesegment(fs, fs_sel);
++		savesegment(gs, gs_sel);
++		fs_base = read_msr(MSR_FS_BASE);
++		vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
++	}
++
++	wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
++#else
++	savesegment(fs, fs_sel);
++	savesegment(gs, gs_sel);
++	fs_base = segment_base(fs_sel);
++	gs_base = segment_base(gs_sel);
++#endif
++
++	vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
++	vmx->guest_state_loaded = true;
++}
++
++static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
++{
++	struct vmcs_host_state *host_state;
++
++	if (!vmx->guest_state_loaded)
++		return;
++
++	host_state = &vmx->loaded_vmcs->host_state;
++
++	++vmx->vcpu.stat.host_state_reload;
++
++#ifdef CONFIG_X86_64
++	rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
++#endif
++	if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
++		kvm_load_ldt(host_state->ldt_sel);
++#ifdef CONFIG_X86_64
++		load_gs_index(host_state->gs_sel);
++#else
++		loadsegment(gs, host_state->gs_sel);
++#endif
++	}
++	if (host_state->fs_sel & 7)
++		loadsegment(fs, host_state->fs_sel);
++#ifdef CONFIG_X86_64
++	if (unlikely(host_state->ds_sel | host_state->es_sel)) {
++		loadsegment(ds, host_state->ds_sel);
++		loadsegment(es, host_state->es_sel);
++	}
++#endif
++	invalidate_tss_limit();
++#ifdef CONFIG_X86_64
++	wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
++#endif
++	load_fixmap_gdt(raw_smp_processor_id());
++	vmx->guest_state_loaded = false;
++	vmx->guest_msrs_ready = false;
++}
++
++#ifdef CONFIG_X86_64
++static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
++{
++	preempt_disable();
++	if (vmx->guest_state_loaded)
++		rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
++	preempt_enable();
++	return vmx->msr_guest_kernel_gs_base;
++}
++
++static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
++{
++	preempt_disable();
++	if (vmx->guest_state_loaded)
++		wrmsrl(MSR_KERNEL_GS_BASE, data);
++	preempt_enable();
++	vmx->msr_guest_kernel_gs_base = data;
++}
++#endif
++
++static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
++{
++	struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
++	struct pi_desc old, new;
++	unsigned int dest;
++
++	/*
++	 * In case of hot-plug or hot-unplug, we may have to undo
++	 * vmx_vcpu_pi_put even if there is no assigned device.  And we
++	 * always keep PI.NDST up to date for simplicity: it makes the
++	 * code easier, and CPU migration is not a fast path.
++	 */
++	if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
++		return;
++
++	/*
++	 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
++	 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
++	 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
++	 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
++	 * correctly.
++	 */
++	if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
++		pi_clear_sn(pi_desc);
++		goto after_clear_sn;
++	}
++
++	/* The full case.  */
++	do {
++		old.control = new.control = pi_desc->control;
++
++		dest = cpu_physical_id(cpu);
++
++		if (x2apic_enabled())
++			new.ndst = dest;
++		else
++			new.ndst = (dest << 8) & 0xFF00;
++
++		new.sn = 0;
++	} while (cmpxchg64(&pi_desc->control, old.control,
++			   new.control) != old.control);
++
++after_clear_sn:
++
++	/*
++	 * Clear SN before reading the bitmap.  The VT-d firmware
++	 * writes the bitmap and reads SN atomically (5.2.3 in the
++	 * spec), so it doesn't really have a memory barrier that
++	 * pairs with this, but we cannot do that and we need one.
++	 */
++	smp_mb__after_atomic();
++
++	if (!pi_is_pir_empty(pi_desc))
++		pi_set_on(pi_desc);
++}
++
++void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
++
++	if (!already_loaded) {
++		loaded_vmcs_clear(vmx->loaded_vmcs);
++		local_irq_disable();
++		crash_disable_local_vmclear(cpu);
++
++		/*
++		 * Read loaded_vmcs->cpu should be before fetching
++		 * loaded_vmcs->loaded_vmcss_on_cpu_link.
++		 * See the comments in __loaded_vmcs_clear().
++		 */
++		smp_rmb();
++
++		list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
++			 &per_cpu(loaded_vmcss_on_cpu, cpu));
++		crash_enable_local_vmclear(cpu);
++		local_irq_enable();
++	}
++
++	if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
++		per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
++		vmcs_load(vmx->loaded_vmcs->vmcs);
++		indirect_branch_prediction_barrier();
++	}
++
++	if (!already_loaded) {
++		void *gdt = get_current_gdt_ro();
++		unsigned long sysenter_esp;
++
++		kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
++
++		/*
++		 * Linux uses per-cpu TSS and GDT, so set these when switching
++		 * processors.  See 22.2.4.
++		 */
++		vmcs_writel(HOST_TR_BASE,
++			    (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
++		vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
++
++		rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
++		vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
++
++		vmx->loaded_vmcs->cpu = cpu;
++	}
++
++	/* Setup TSC multiplier */
++	if (kvm_has_tsc_control &&
++	    vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
++		decache_tsc_multiplier(vmx);
++}
++
++/*
++ * Switches to specified vcpu, until a matching vcpu_put(), but assumes
++ * vcpu mutex is already taken.
++ */
++void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++
++	vmx_vcpu_load_vmcs(vcpu, cpu);
++
++	vmx_vcpu_pi_load(vcpu, cpu);
++
++	vmx->host_pkru = read_pkru();
++	vmx->host_debugctlmsr = get_debugctlmsr();
++}
++
++static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
++{
++	struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
++
++	if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
++		!irq_remapping_cap(IRQ_POSTING_CAP)  ||
++		!kvm_vcpu_apicv_active(vcpu))
++		return;
++
++	/* Set SN when the vCPU is preempted */
++	if (vcpu->preempted)
++		pi_set_sn(pi_desc);
++}
++
++static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
++{
++	vmx_vcpu_pi_put(vcpu);
++
++	vmx_prepare_switch_to_host(to_vmx(vcpu));
++}
++
++static bool emulation_required(struct kvm_vcpu *vcpu)
++{
++	return emulate_invalid_guest_state && !guest_state_valid(vcpu);
++}
++
++static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
++
++unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	unsigned long rflags, save_rflags;
++
++	if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
++		kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
++		rflags = vmcs_readl(GUEST_RFLAGS);
++		if (vmx->rmode.vm86_active) {
++			rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
++			save_rflags = vmx->rmode.save_rflags;
++			rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
++		}
++		vmx->rflags = rflags;
++	}
++	return vmx->rflags;
++}
++
++void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	unsigned long old_rflags;
++
++	if (enable_unrestricted_guest) {
++		kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
++		vmx->rflags = rflags;
++		vmcs_writel(GUEST_RFLAGS, rflags);
++		return;
++	}
++
++	old_rflags = vmx_get_rflags(vcpu);
++	vmx->rflags = rflags;
++	if (vmx->rmode.vm86_active) {
++		vmx->rmode.save_rflags = rflags;
++		rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
++	}
++	vmcs_writel(GUEST_RFLAGS, rflags);
++
++	if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
++		vmx->emulation_required = emulation_required(vcpu);
++}
++
++u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
++{
++	u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
++	int ret = 0;
++
++	if (interruptibility & GUEST_INTR_STATE_STI)
++		ret |= KVM_X86_SHADOW_INT_STI;
++	if (interruptibility & GUEST_INTR_STATE_MOV_SS)
++		ret |= KVM_X86_SHADOW_INT_MOV_SS;
++
++	return ret;
++}
++
++void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
++{
++	u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
++	u32 interruptibility = interruptibility_old;
++
++	interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
++
++	if (mask & KVM_X86_SHADOW_INT_MOV_SS)
++		interruptibility |= GUEST_INTR_STATE_MOV_SS;
++	else if (mask & KVM_X86_SHADOW_INT_STI)
++		interruptibility |= GUEST_INTR_STATE_STI;
++
++	if ((interruptibility != interruptibility_old))
++		vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
++}
++
++static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	unsigned long value;
++
++	/*
++	 * Any MSR write that attempts to change bits marked reserved will
++	 * case a #GP fault.
++	 */
++	if (data & vmx->pt_desc.ctl_bitmask)
++		return 1;
++
++	/*
++	 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
++	 * result in a #GP unless the same write also clears TraceEn.
++	 */
++	if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
++		((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
++		return 1;
++
++	/*
++	 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
++	 * and FabricEn would cause #GP, if
++	 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
++	 */
++	if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
++		!(data & RTIT_CTL_FABRIC_EN) &&
++		!intel_pt_validate_cap(vmx->pt_desc.caps,
++					PT_CAP_single_range_output))
++		return 1;
++
++	/*
++	 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
++	 * utilize encodings marked reserved will casue a #GP fault.
++	 */
++	value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
++	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
++			!test_bit((data & RTIT_CTL_MTC_RANGE) >>
++			RTIT_CTL_MTC_RANGE_OFFSET, &value))
++		return 1;
++	value = intel_pt_validate_cap(vmx->pt_desc.caps,
++						PT_CAP_cycle_thresholds);
++	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
++			!test_bit((data & RTIT_CTL_CYC_THRESH) >>
++			RTIT_CTL_CYC_THRESH_OFFSET, &value))
++		return 1;
++	value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
++	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
++			!test_bit((data & RTIT_CTL_PSB_FREQ) >>
++			RTIT_CTL_PSB_FREQ_OFFSET, &value))
++		return 1;
++
++	/*
++	 * If ADDRx_CFG is reserved or the encodings is >2 will
++	 * cause a #GP fault.
++	 */
++	value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
++	if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
++		return 1;
++	value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
++	if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
++		return 1;
++	value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
++	if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
++		return 1;
++	value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
++	if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
++		return 1;
++
++	return 0;
++}
++
++static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
++{
++	unsigned long rip;
++
++	/*
++	 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
++	 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
++	 * set when EPT misconfig occurs.  In practice, real hardware updates
++	 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
++	 * (namely Hyper-V) don't set it due to it being undefined behavior,
++	 * i.e. we end up advancing IP with some random value.
++	 */
++	if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
++	    to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
++		rip = kvm_rip_read(vcpu);
++		rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
++		kvm_rip_write(vcpu, rip);
++	} else {
++		if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
++			return 0;
++	}
++
++	/* skipping an emulated instruction also counts */
++	vmx_set_interrupt_shadow(vcpu, 0);
++
++	return 1;
++}
++
++static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
++{
++	/*
++	 * Ensure that we clear the HLT state in the VMCS.  We don't need to
++	 * explicitly skip the instruction because if the HLT state is set,
++	 * then the instruction is already executing and RIP has already been
++	 * advanced.
++	 */
++	if (kvm_hlt_in_guest(vcpu->kvm) &&
++			vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
++		vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
++}
++
++static void vmx_queue_exception(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	unsigned nr = vcpu->arch.exception.nr;
++	bool has_error_code = vcpu->arch.exception.has_error_code;
++	u32 error_code = vcpu->arch.exception.error_code;
++	u32 intr_info = nr | INTR_INFO_VALID_MASK;
++
++	kvm_deliver_exception_payload(vcpu);
++
++	if (has_error_code) {
++		vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
++		intr_info |= INTR_INFO_DELIVER_CODE_MASK;
++	}
++
++	if (vmx->rmode.vm86_active) {
++		int inc_eip = 0;
++		if (kvm_exception_is_soft(nr))
++			inc_eip = vcpu->arch.event_exit_inst_len;
++		kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
++		return;
++	}
++
++	WARN_ON_ONCE(vmx->emulation_required);
++
++	if (kvm_exception_is_soft(nr)) {
++		vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
++			     vmx->vcpu.arch.event_exit_inst_len);
++		intr_info |= INTR_TYPE_SOFT_EXCEPTION;
++	} else
++		intr_info |= INTR_TYPE_HARD_EXCEPTION;
++
++	vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
++
++	vmx_clear_hlt(vcpu);
++}
++
++static bool vmx_rdtscp_supported(void)
++{
++	return cpu_has_vmx_rdtscp();
++}
++
++static bool vmx_invpcid_supported(void)
++{
++	return cpu_has_vmx_invpcid();
++}
++
++/*
++ * Swap MSR entry in host/guest MSR entry array.
++ */
++static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
++{
++	struct shared_msr_entry tmp;
++
++	tmp = vmx->guest_msrs[to];
++	vmx->guest_msrs[to] = vmx->guest_msrs[from];
++	vmx->guest_msrs[from] = tmp;
++}
++
++/*
++ * Set up the vmcs to automatically save and restore system
++ * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
++ * mode, as fiddling with msrs is very expensive.
++ */
++static void setup_msrs(struct vcpu_vmx *vmx)
++{
++	int save_nmsrs, index;
++
++	save_nmsrs = 0;
++#ifdef CONFIG_X86_64
++	/*
++	 * The SYSCALL MSRs are only needed on long mode guests, and only
++	 * when EFER.SCE is set.
++	 */
++	if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
++		index = __find_msr_index(vmx, MSR_STAR);
++		if (index >= 0)
++			move_msr_up(vmx, index, save_nmsrs++);
++		index = __find_msr_index(vmx, MSR_LSTAR);
++		if (index >= 0)
++			move_msr_up(vmx, index, save_nmsrs++);
++		index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
++		if (index >= 0)
++			move_msr_up(vmx, index, save_nmsrs++);
++	}
++#endif
++	index = __find_msr_index(vmx, MSR_EFER);
++	if (index >= 0 && update_transition_efer(vmx, index))
++		move_msr_up(vmx, index, save_nmsrs++);
++	index = __find_msr_index(vmx, MSR_TSC_AUX);
++	if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
++		move_msr_up(vmx, index, save_nmsrs++);
++	index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
++	if (index >= 0)
++		move_msr_up(vmx, index, save_nmsrs++);
++
++	vmx->save_nmsrs = save_nmsrs;
++	vmx->guest_msrs_ready = false;
++
++	if (cpu_has_vmx_msr_bitmap())
++		vmx_update_msr_bitmap(&vmx->vcpu);
++}
++
++static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
++{
++	struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
++
++	if (is_guest_mode(vcpu) &&
++	    (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
++		return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
++
++	return vcpu->arch.tsc_offset;
++}
++
++static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
++{
++	struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
++	u64 g_tsc_offset = 0;
++
++	/*
++	 * We're here if L1 chose not to trap WRMSR to TSC. According
++	 * to the spec, this should set L1's TSC; The offset that L1
++	 * set for L2 remains unchanged, and still needs to be added
++	 * to the newly set TSC to get L2's TSC.
++	 */
++	if (is_guest_mode(vcpu) &&
++	    (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
++		g_tsc_offset = vmcs12->tsc_offset;
++
++	trace_kvm_write_tsc_offset(vcpu->vcpu_id,
++				   vcpu->arch.tsc_offset - g_tsc_offset,
++				   offset);
++	vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
++	return offset + g_tsc_offset;
++}
++
++/*
++ * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
++ * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
++ * all guests if the "nested" module option is off, and can also be disabled
++ * for a single guest by disabling its VMX cpuid bit.
++ */
++bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
++{
++	return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
++}
++
++static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
++						 uint64_t val)
++{
++	uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
++
++	return !(val & ~valid_bits);
++}
++
++static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
++{
++	switch (msr->index) {
++	case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
++		if (!nested)
++			return 1;
++		return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
++	default:
++		return 1;
++	}
++}
++
++/*
++ * Reads an msr value (of 'msr_index') into 'pdata'.
++ * Returns 0 on success, non-0 otherwise.
++ * Assumes vcpu_load() was already called.
++ */
++static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	struct shared_msr_entry *msr;
++	u32 index;
++
++	switch (msr_info->index) {
++#ifdef CONFIG_X86_64
++	case MSR_FS_BASE:
++		msr_info->data = vmcs_readl(GUEST_FS_BASE);
++		break;
++	case MSR_GS_BASE:
++		msr_info->data = vmcs_readl(GUEST_GS_BASE);
++		break;
++	case MSR_KERNEL_GS_BASE:
++		msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
++		break;
++#endif
++	case MSR_EFER:
++		return kvm_get_msr_common(vcpu, msr_info);
++	case MSR_IA32_TSX_CTRL:
++		if (!msr_info->host_initiated &&
++		    !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
++			return 1;
++		goto find_shared_msr;
++	case MSR_IA32_UMWAIT_CONTROL:
++		if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
++			return 1;
++
++		msr_info->data = vmx->msr_ia32_umwait_control;
++		break;
++	case MSR_IA32_SPEC_CTRL:
++		if (!msr_info->host_initiated &&
++		    !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
++			return 1;
++
++		msr_info->data = to_vmx(vcpu)->spec_ctrl;
++		break;
++	case MSR_IA32_SYSENTER_CS:
++		msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
++		break;
++	case MSR_IA32_SYSENTER_EIP:
++		msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
++		break;
++	case MSR_IA32_SYSENTER_ESP:
++		msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
++		break;
++	case MSR_IA32_BNDCFGS:
++		if (!kvm_mpx_supported() ||
++		    (!msr_info->host_initiated &&
++		     !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
++			return 1;
++		msr_info->data = vmcs_read64(GUEST_BNDCFGS);
++		break;
++	case MSR_IA32_MCG_EXT_CTL:
++		if (!msr_info->host_initiated &&
++		    !(vmx->msr_ia32_feature_control &
++		      FEATURE_CONTROL_LMCE))
++			return 1;
++		msr_info->data = vcpu->arch.mcg_ext_ctl;
++		break;
++	case MSR_IA32_FEATURE_CONTROL:
++		msr_info->data = vmx->msr_ia32_feature_control;
++		break;
++	case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
++		if (!nested_vmx_allowed(vcpu))
++			return 1;
++		return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
++				       &msr_info->data);
++	case MSR_IA32_RTIT_CTL:
++		if (pt_mode != PT_MODE_HOST_GUEST)
++			return 1;
++		msr_info->data = vmx->pt_desc.guest.ctl;
++		break;
++	case MSR_IA32_RTIT_STATUS:
++		if (pt_mode != PT_MODE_HOST_GUEST)
++			return 1;
++		msr_info->data = vmx->pt_desc.guest.status;
++		break;
++	case MSR_IA32_RTIT_CR3_MATCH:
++		if ((pt_mode != PT_MODE_HOST_GUEST) ||
++			!intel_pt_validate_cap(vmx->pt_desc.caps,
++						PT_CAP_cr3_filtering))
++			return 1;
++		msr_info->data = vmx->pt_desc.guest.cr3_match;
++		break;
++	case MSR_IA32_RTIT_OUTPUT_BASE:
++		if ((pt_mode != PT_MODE_HOST_GUEST) ||
++			(!intel_pt_validate_cap(vmx->pt_desc.caps,
++					PT_CAP_topa_output) &&
++			 !intel_pt_validate_cap(vmx->pt_desc.caps,
++					PT_CAP_single_range_output)))
++			return 1;
++		msr_info->data = vmx->pt_desc.guest.output_base;
++		break;
++	case MSR_IA32_RTIT_OUTPUT_MASK:
++		if ((pt_mode != PT_MODE_HOST_GUEST) ||
++			(!intel_pt_validate_cap(vmx->pt_desc.caps,
++					PT_CAP_topa_output) &&
++			 !intel_pt_validate_cap(vmx->pt_desc.caps,
++					PT_CAP_single_range_output)))
++			return 1;
++		msr_info->data = vmx->pt_desc.guest.output_mask;
++		break;
++	case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
++		index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
++		if ((pt_mode != PT_MODE_HOST_GUEST) ||
++			(index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
++					PT_CAP_num_address_ranges)))
++			return 1;
++		if (is_noncanonical_address(data, vcpu))
++			return 1;
++		if (index % 2)
++			msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
++		else
++			msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
++		break;
++	case MSR_TSC_AUX:
++		if (!msr_info->host_initiated &&
++		    !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
++			return 1;
++		goto find_shared_msr;
++	default:
++	find_shared_msr:
++		msr = find_msr_entry(vmx, msr_info->index);
++		if (msr) {
++			msr_info->data = msr->data;
++			break;
++		}
++		return kvm_get_msr_common(vcpu, msr_info);
++	}
++
++	return 0;
++}
++
++/*
++ * Writes msr value into the appropriate "register".
++ * Returns 0 on success, non-0 otherwise.
++ * Assumes vcpu_load() was already called.
++ */
++static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	struct shared_msr_entry *msr;
++	int ret = 0;
++	u32 msr_index = msr_info->index;
++	u64 data = msr_info->data;
++	u32 index;
++
++	switch (msr_index) {
++	case MSR_EFER:
++		ret = kvm_set_msr_common(vcpu, msr_info);
++		break;
++#ifdef CONFIG_X86_64
++	case MSR_FS_BASE:
++		vmx_segment_cache_clear(vmx);
++		vmcs_writel(GUEST_FS_BASE, data);
++		break;
++	case MSR_GS_BASE:
++		vmx_segment_cache_clear(vmx);
++		vmcs_writel(GUEST_GS_BASE, data);
++		break;
++	case MSR_KERNEL_GS_BASE:
++		vmx_write_guest_kernel_gs_base(vmx, data);
++		break;
++#endif
++	case MSR_IA32_SYSENTER_CS:
++		if (is_guest_mode(vcpu))
++			get_vmcs12(vcpu)->guest_sysenter_cs = data;
++		vmcs_write32(GUEST_SYSENTER_CS, data);
++		break;
++	case MSR_IA32_SYSENTER_EIP:
++		if (is_guest_mode(vcpu))
++			get_vmcs12(vcpu)->guest_sysenter_eip = data;
++		vmcs_writel(GUEST_SYSENTER_EIP, data);
++		break;
++	case MSR_IA32_SYSENTER_ESP:
++		if (is_guest_mode(vcpu))
++			get_vmcs12(vcpu)->guest_sysenter_esp = data;
++		vmcs_writel(GUEST_SYSENTER_ESP, data);
++		break;
++	case MSR_IA32_DEBUGCTLMSR:
++		if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
++						VM_EXIT_SAVE_DEBUG_CONTROLS)
++			get_vmcs12(vcpu)->guest_ia32_debugctl = data;
++
++		ret = kvm_set_msr_common(vcpu, msr_info);
++		break;
++
++	case MSR_IA32_BNDCFGS:
++		if (!kvm_mpx_supported() ||
++		    (!msr_info->host_initiated &&
++		     !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
++			return 1;
++		if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
++		    (data & MSR_IA32_BNDCFGS_RSVD))
++			return 1;
++		vmcs_write64(GUEST_BNDCFGS, data);
++		break;
++	case MSR_IA32_UMWAIT_CONTROL:
++		if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
++			return 1;
++
++		/* The reserved bit 1 and non-32 bit [63:32] should be zero */
++		if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
++			return 1;
++
++		vmx->msr_ia32_umwait_control = data;
++		break;
++	case MSR_IA32_SPEC_CTRL:
++		if (!msr_info->host_initiated &&
++		    !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
++			return 1;
++
++		/* The STIBP bit doesn't fault even if it's not advertised */
++		if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
++			return 1;
++
++		vmx->spec_ctrl = data;
++
++		if (!data)
++			break;
++
++		/*
++		 * For non-nested:
++		 * When it's written (to non-zero) for the first time, pass
++		 * it through.
++		 *
++		 * For nested:
++		 * The handling of the MSR bitmap for L2 guests is done in
++		 * nested_vmx_prepare_msr_bitmap. We should not touch the
++		 * vmcs02.msr_bitmap here since it gets completely overwritten
++		 * in the merging. We update the vmcs01 here for L1 as well
++		 * since it will end up touching the MSR anyway now.
++		 */
++		vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
++					      MSR_IA32_SPEC_CTRL,
++					      MSR_TYPE_RW);
++		break;
++	case MSR_IA32_TSX_CTRL:
++		if (!msr_info->host_initiated &&
++		    !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
++			return 1;
++		if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
++			return 1;
++		goto find_shared_msr;
++	case MSR_IA32_PRED_CMD:
++		if (!msr_info->host_initiated &&
++		    !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
++			return 1;
++
++		if (data & ~PRED_CMD_IBPB)
++			return 1;
++
++		if (!data)
++			break;
++
++		wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
++
++		/*
++		 * For non-nested:
++		 * When it's written (to non-zero) for the first time, pass
++		 * it through.
++		 *
++		 * For nested:
++		 * The handling of the MSR bitmap for L2 guests is done in
++		 * nested_vmx_prepare_msr_bitmap. We should not touch the
++		 * vmcs02.msr_bitmap here since it gets completely overwritten
++		 * in the merging.
++		 */
++		vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
++					      MSR_TYPE_W);
++		break;
++	case MSR_IA32_CR_PAT:
++		if (!kvm_pat_valid(data))
++			return 1;
++
++		if (is_guest_mode(vcpu) &&
++		    get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
++			get_vmcs12(vcpu)->guest_ia32_pat = data;
++
++		if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
++			vmcs_write64(GUEST_IA32_PAT, data);
++			vcpu->arch.pat = data;
++			break;
++		}
++		ret = kvm_set_msr_common(vcpu, msr_info);
++		break;
++	case MSR_IA32_TSC_ADJUST:
++		ret = kvm_set_msr_common(vcpu, msr_info);
++		break;
++	case MSR_IA32_MCG_EXT_CTL:
++		if ((!msr_info->host_initiated &&
++		     !(to_vmx(vcpu)->msr_ia32_feature_control &
++		       FEATURE_CONTROL_LMCE)) ||
++		    (data & ~MCG_EXT_CTL_LMCE_EN))
++			return 1;
++		vcpu->arch.mcg_ext_ctl = data;
++		break;
++	case MSR_IA32_FEATURE_CONTROL:
++		if (!vmx_feature_control_msr_valid(vcpu, data) ||
++		    (to_vmx(vcpu)->msr_ia32_feature_control &
++		     FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
++			return 1;
++		vmx->msr_ia32_feature_control = data;
++		if (msr_info->host_initiated && data == 0)
++			vmx_leave_nested(vcpu);
++		break;
++	case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
++		if (!msr_info->host_initiated)
++			return 1; /* they are read-only */
++		if (!nested_vmx_allowed(vcpu))
++			return 1;
++		return vmx_set_vmx_msr(vcpu, msr_index, data);
++	case MSR_IA32_RTIT_CTL:
++		if ((pt_mode != PT_MODE_HOST_GUEST) ||
++			vmx_rtit_ctl_check(vcpu, data) ||
++			vmx->nested.vmxon)
++			return 1;
++		vmcs_write64(GUEST_IA32_RTIT_CTL, data);
++		vmx->pt_desc.guest.ctl = data;
++		pt_update_intercept_for_msr(vmx);
++		break;
++	case MSR_IA32_RTIT_STATUS:
++		if ((pt_mode != PT_MODE_HOST_GUEST) ||
++			(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
++			(data & MSR_IA32_RTIT_STATUS_MASK))
++			return 1;
++		vmx->pt_desc.guest.status = data;
++		break;
++	case MSR_IA32_RTIT_CR3_MATCH:
++		if ((pt_mode != PT_MODE_HOST_GUEST) ||
++			(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
++			!intel_pt_validate_cap(vmx->pt_desc.caps,
++						PT_CAP_cr3_filtering))
++			return 1;
++		vmx->pt_desc.guest.cr3_match = data;
++		break;
++	case MSR_IA32_RTIT_OUTPUT_BASE:
++		if ((pt_mode != PT_MODE_HOST_GUEST) ||
++			(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
++			(!intel_pt_validate_cap(vmx->pt_desc.caps,
++					PT_CAP_topa_output) &&
++			 !intel_pt_validate_cap(vmx->pt_desc.caps,
++					PT_CAP_single_range_output)) ||
++			(data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
++			return 1;
++		vmx->pt_desc.guest.output_base = data;
++		break;
++	case MSR_IA32_RTIT_OUTPUT_MASK:
++		if ((pt_mode != PT_MODE_HOST_GUEST) ||
++			(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
++			(!intel_pt_validate_cap(vmx->pt_desc.caps,
++					PT_CAP_topa_output) &&
++			 !intel_pt_validate_cap(vmx->pt_desc.caps,
++					PT_CAP_single_range_output)))
++			return 1;
++		vmx->pt_desc.guest.output_mask = data;
++		break;
++	case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
++		index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
++		if ((pt_mode != PT_MODE_HOST_GUEST) ||
++			(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
++			(index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
++					PT_CAP_num_address_ranges)))
++			return 1;
++		if (is_noncanonical_address(data, vcpu))
++			return 1;
++		if (index % 2)
++			vmx->pt_desc.guest.addr_b[index / 2] = data;
++		else
++			vmx->pt_desc.guest.addr_a[index / 2] = data;
++		break;
++	case MSR_TSC_AUX:
++		if (!msr_info->host_initiated &&
++		    !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
++			return 1;
++		/* Check reserved bit, higher 32 bits should be zero */
++		if ((data >> 32) != 0)
++			return 1;
++		goto find_shared_msr;
++
++	default:
++	find_shared_msr:
++		msr = find_msr_entry(vmx, msr_index);
++		if (msr)
++			ret = vmx_set_guest_msr(vmx, msr, data);
++		else
++			ret = kvm_set_msr_common(vcpu, msr_info);
++	}
++
++	return ret;
++}
++
++static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
++{
++	kvm_register_mark_available(vcpu, reg);
++
++	switch (reg) {
++	case VCPU_REGS_RSP:
++		vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
++		break;
++	case VCPU_REGS_RIP:
++		vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
++		break;
++	case VCPU_EXREG_PDPTR:
++		if (enable_ept)
++			ept_save_pdptrs(vcpu);
++		break;
++	case VCPU_EXREG_CR3:
++		if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
++			vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
++		break;
++	default:
++		WARN_ON_ONCE(1);
++		break;
++	}
++}
++
++static __init int cpu_has_kvm_support(void)
++{
++	return cpu_has_vmx();
++}
++
++static __init int vmx_disabled_by_bios(void)
++{
++	u64 msr;
++
++	rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
++	if (msr & FEATURE_CONTROL_LOCKED) {
++		/* launched w/ TXT and VMX disabled */
++		if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
++			&& tboot_enabled())
++			return 1;
++		/* launched w/o TXT and VMX only enabled w/ TXT */
++		if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
++			&& (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
++			&& !tboot_enabled()) {
++			printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
++				"activate TXT before enabling KVM\n");
++			return 1;
++		}
++		/* launched w/o TXT and VMX disabled */
++		if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
++			&& !tboot_enabled())
++			return 1;
++	}
++
++	return 0;
++}
++
++static void kvm_cpu_vmxon(u64 addr)
++{
++	cr4_set_bits(X86_CR4_VMXE);
++	intel_pt_handle_vmx(1);
++
++	asm volatile ("vmxon %0" : : "m"(addr));
++}
++
++static int hardware_enable(void)
++{
++	int cpu = raw_smp_processor_id();
++	u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
++	u64 old, test_bits;
++
++	if (cr4_read_shadow() & X86_CR4_VMXE)
++		return -EBUSY;
++
++	/*
++	 * This can happen if we hot-added a CPU but failed to allocate
++	 * VP assist page for it.
++	 */
++	if (static_branch_unlikely(&enable_evmcs) &&
++	    !hv_get_vp_assist_page(cpu))
++		return -EFAULT;
++
++	INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
++	INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
++	spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
++
++	/*
++	 * Now we can enable the vmclear operation in kdump
++	 * since the loaded_vmcss_on_cpu list on this cpu
++	 * has been initialized.
++	 *
++	 * Though the cpu is not in VMX operation now, there
++	 * is no problem to enable the vmclear operation
++	 * for the loaded_vmcss_on_cpu list is empty!
++	 */
++	crash_enable_local_vmclear(cpu);
++
++	rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
++
++	test_bits = FEATURE_CONTROL_LOCKED;
++	test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
++	if (tboot_enabled())
++		test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
++
++	if ((old & test_bits) != test_bits) {
++		/* enable and lock */
++		wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
++	}
++	kvm_cpu_vmxon(phys_addr);
++	if (enable_ept)
++		ept_sync_global();
++
++	return 0;
++}
++
++static void vmclear_local_loaded_vmcss(void)
++{
++	int cpu = raw_smp_processor_id();
++	struct loaded_vmcs *v, *n;
++
++	list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
++				 loaded_vmcss_on_cpu_link)
++		__loaded_vmcs_clear(v);
++}
++
++
++/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
++ * tricks.
++ */
++static void kvm_cpu_vmxoff(void)
++{
++	asm volatile (__ex("vmxoff"));
++
++	intel_pt_handle_vmx(0);
++	cr4_clear_bits(X86_CR4_VMXE);
++}
++
++static void hardware_disable(void)
++{
++	vmclear_local_loaded_vmcss();
++	kvm_cpu_vmxoff();
++}
++
++static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
++				      u32 msr, u32 *result)
++{
++	u32 vmx_msr_low, vmx_msr_high;
++	u32 ctl = ctl_min | ctl_opt;
++
++	rdmsr(msr, vmx_msr_low, vmx_msr_high);
++
++	ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
++	ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
++
++	/* Ensure minimum (required) set of control bits are supported. */
++	if (ctl_min & ~ctl)
++		return -EIO;
++
++	*result = ctl;
++	return 0;
++}
++
++static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
++				    struct vmx_capability *vmx_cap)
++{
++	u32 vmx_msr_low, vmx_msr_high;
++	u32 min, opt, min2, opt2;
++	u32 _pin_based_exec_control = 0;
++	u32 _cpu_based_exec_control = 0;
++	u32 _cpu_based_2nd_exec_control = 0;
++	u32 _vmexit_control = 0;
++	u32 _vmentry_control = 0;
++
++	memset(vmcs_conf, 0, sizeof(*vmcs_conf));
++	min = CPU_BASED_HLT_EXITING |
++#ifdef CONFIG_X86_64
++	      CPU_BASED_CR8_LOAD_EXITING |
++	      CPU_BASED_CR8_STORE_EXITING |
++#endif
++	      CPU_BASED_CR3_LOAD_EXITING |
++	      CPU_BASED_CR3_STORE_EXITING |
++	      CPU_BASED_UNCOND_IO_EXITING |
++	      CPU_BASED_MOV_DR_EXITING |
++	      CPU_BASED_USE_TSC_OFFSETTING |
++	      CPU_BASED_MWAIT_EXITING |
++	      CPU_BASED_MONITOR_EXITING |
++	      CPU_BASED_INVLPG_EXITING |
++	      CPU_BASED_RDPMC_EXITING;
++
++	opt = CPU_BASED_TPR_SHADOW |
++	      CPU_BASED_USE_MSR_BITMAPS |
++	      CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
++	if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
++				&_cpu_based_exec_control) < 0)
++		return -EIO;
++#ifdef CONFIG_X86_64
++	if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
++		_cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
++					   ~CPU_BASED_CR8_STORE_EXITING;
++#endif
++	if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
++		min2 = 0;
++		opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
++			SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
++			SECONDARY_EXEC_WBINVD_EXITING |
++			SECONDARY_EXEC_ENABLE_VPID |
++			SECONDARY_EXEC_ENABLE_EPT |
++			SECONDARY_EXEC_UNRESTRICTED_GUEST |
++			SECONDARY_EXEC_PAUSE_LOOP_EXITING |
++			SECONDARY_EXEC_DESC |
++			SECONDARY_EXEC_RDTSCP |
++			SECONDARY_EXEC_ENABLE_INVPCID |
++			SECONDARY_EXEC_APIC_REGISTER_VIRT |
++			SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
++			SECONDARY_EXEC_SHADOW_VMCS |
++			SECONDARY_EXEC_XSAVES |
++			SECONDARY_EXEC_RDSEED_EXITING |
++			SECONDARY_EXEC_RDRAND_EXITING |
++			SECONDARY_EXEC_ENABLE_PML |
++			SECONDARY_EXEC_TSC_SCALING |
++			SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
++			SECONDARY_EXEC_PT_USE_GPA |
++			SECONDARY_EXEC_PT_CONCEAL_VMX |
++			SECONDARY_EXEC_ENABLE_VMFUNC |
++			SECONDARY_EXEC_ENCLS_EXITING;
++		if (adjust_vmx_controls(min2, opt2,
++					MSR_IA32_VMX_PROCBASED_CTLS2,
++					&_cpu_based_2nd_exec_control) < 0)
++			return -EIO;
++	}
++#ifndef CONFIG_X86_64
++	if (!(_cpu_based_2nd_exec_control &
++				SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
++		_cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
++#endif
++
++	if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
++		_cpu_based_2nd_exec_control &= ~(
++				SECONDARY_EXEC_APIC_REGISTER_VIRT |
++				SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
++				SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
++
++	rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
++		&vmx_cap->ept, &vmx_cap->vpid);
++
++	if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
++		/* CR3 accesses and invlpg don't need to cause VM Exits when EPT
++		   enabled */
++		_cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
++					     CPU_BASED_CR3_STORE_EXITING |
++					     CPU_BASED_INVLPG_EXITING);
++	} else if (vmx_cap->ept) {
++		vmx_cap->ept = 0;
++		pr_warn_once("EPT CAP should not exist if not support "
++				"1-setting enable EPT VM-execution control\n");
++	}
++	if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
++		vmx_cap->vpid) {
++		vmx_cap->vpid = 0;
++		pr_warn_once("VPID CAP should not exist if not support "
++				"1-setting enable VPID VM-execution control\n");
++	}
++
++	min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
++#ifdef CONFIG_X86_64
++	min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
++#endif
++	opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
++	      VM_EXIT_LOAD_IA32_PAT |
++	      VM_EXIT_LOAD_IA32_EFER |
++	      VM_EXIT_CLEAR_BNDCFGS |
++	      VM_EXIT_PT_CONCEAL_PIP |
++	      VM_EXIT_CLEAR_IA32_RTIT_CTL;
++	if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
++				&_vmexit_control) < 0)
++		return -EIO;
++
++	min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
++	opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
++		 PIN_BASED_VMX_PREEMPTION_TIMER;
++	if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
++				&_pin_based_exec_control) < 0)
++		return -EIO;
++
++	if (cpu_has_broken_vmx_preemption_timer())
++		_pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
++	if (!(_cpu_based_2nd_exec_control &
++		SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
++		_pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
++
++	min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
++	opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
++	      VM_ENTRY_LOAD_IA32_PAT |
++	      VM_ENTRY_LOAD_IA32_EFER |
++	      VM_ENTRY_LOAD_BNDCFGS |
++	      VM_ENTRY_PT_CONCEAL_PIP |
++	      VM_ENTRY_LOAD_IA32_RTIT_CTL;
++	if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
++				&_vmentry_control) < 0)
++		return -EIO;
++
++	/*
++	 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
++	 * can't be used due to an errata where VM Exit may incorrectly clear
++	 * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
++	 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
++	 */
++	if (boot_cpu_data.x86 == 0x6) {
++		switch (boot_cpu_data.x86_model) {
++		case 26: /* AAK155 */
++		case 30: /* AAP115 */
++		case 37: /* AAT100 */
++		case 44: /* BC86,AAY89,BD102 */
++		case 46: /* BA97 */
++			_vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
++			_vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
++			pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
++					"does not work properly. Using workaround\n");
++			break;
++		default:
++			break;
++		}
++	}
++
++
++	rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
++
++	/* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
++	if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
++		return -EIO;
++
++#ifdef CONFIG_X86_64
++	/* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
++	if (vmx_msr_high & (1u<<16))
++		return -EIO;
++#endif
++
++	/* Require Write-Back (WB) memory type for VMCS accesses. */
++	if (((vmx_msr_high >> 18) & 15) != 6)
++		return -EIO;
++
++	vmcs_conf->size = vmx_msr_high & 0x1fff;
++	vmcs_conf->order = get_order(vmcs_conf->size);
++	vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
++
++	vmcs_conf->revision_id = vmx_msr_low;
++
++	vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
++	vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
++	vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
++	vmcs_conf->vmexit_ctrl         = _vmexit_control;
++	vmcs_conf->vmentry_ctrl        = _vmentry_control;
++
++	if (static_branch_unlikely(&enable_evmcs))
++		evmcs_sanitize_exec_ctrls(vmcs_conf);
++
++	return 0;
++}
++
++struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
++{
++	int node = cpu_to_node(cpu);
++	struct page *pages;
++	struct vmcs *vmcs;
++
++	pages = __alloc_pages_node(node, flags, vmcs_config.order);
++	if (!pages)
++		return NULL;
++	vmcs = page_address(pages);
++	memset(vmcs, 0, vmcs_config.size);
++
++	/* KVM supports Enlightened VMCS v1 only */
++	if (static_branch_unlikely(&enable_evmcs))
++		vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
++	else
++		vmcs->hdr.revision_id = vmcs_config.revision_id;
++
++	if (shadow)
++		vmcs->hdr.shadow_vmcs = 1;
++	return vmcs;
++}
++
++void free_vmcs(struct vmcs *vmcs)
++{
++	free_pages((unsigned long)vmcs, vmcs_config.order);
++}
++
++/*
++ * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
++ */
++void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
++{
++	if (!loaded_vmcs->vmcs)
++		return;
++	loaded_vmcs_clear(loaded_vmcs);
++	free_vmcs(loaded_vmcs->vmcs);
++	loaded_vmcs->vmcs = NULL;
++	if (loaded_vmcs->msr_bitmap)
++		free_page((unsigned long)loaded_vmcs->msr_bitmap);
++	WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
++}
++
++int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
++{
++	loaded_vmcs->vmcs = alloc_vmcs(false);
++	if (!loaded_vmcs->vmcs)
++		return -ENOMEM;
++
++	loaded_vmcs->shadow_vmcs = NULL;
++	loaded_vmcs->hv_timer_soft_disabled = false;
++	loaded_vmcs_init(loaded_vmcs);
++
++	if (cpu_has_vmx_msr_bitmap()) {
++		loaded_vmcs->msr_bitmap = (unsigned long *)
++				__get_free_page(GFP_KERNEL_ACCOUNT);
++		if (!loaded_vmcs->msr_bitmap)
++			goto out_vmcs;
++		memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
++
++		if (IS_ENABLED(CONFIG_HYPERV) &&
++		    static_branch_unlikely(&enable_evmcs) &&
++		    (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
++			struct hv_enlightened_vmcs *evmcs =
++				(struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
++
++			evmcs->hv_enlightenments_control.msr_bitmap = 1;
++		}
++	}
++
++	memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
++	memset(&loaded_vmcs->controls_shadow, 0,
++		sizeof(struct vmcs_controls_shadow));
++
++	return 0;
++
++out_vmcs:
++	free_loaded_vmcs(loaded_vmcs);
++	return -ENOMEM;
++}
++
++static void free_kvm_area(void)
++{
++	int cpu;
++
++	for_each_possible_cpu(cpu) {
++		free_vmcs(per_cpu(vmxarea, cpu));
++		per_cpu(vmxarea, cpu) = NULL;
++	}
++}
++
++static __init int alloc_kvm_area(void)
++{
++	int cpu;
++
++	for_each_possible_cpu(cpu) {
++		struct vmcs *vmcs;
++
++		vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
++		if (!vmcs) {
++			free_kvm_area();
++			return -ENOMEM;
++		}
++
++		/*
++		 * When eVMCS is enabled, alloc_vmcs_cpu() sets
++		 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
++		 * revision_id reported by MSR_IA32_VMX_BASIC.
++		 *
++		 * However, even though not explicitly documented by
++		 * TLFS, VMXArea passed as VMXON argument should
++		 * still be marked with revision_id reported by
++		 * physical CPU.
++		 */
++		if (static_branch_unlikely(&enable_evmcs))
++			vmcs->hdr.revision_id = vmcs_config.revision_id;
++
++		per_cpu(vmxarea, cpu) = vmcs;
++	}
++	return 0;
++}
++
++static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
++		struct kvm_segment *save)
++{
++	if (!emulate_invalid_guest_state) {
++		/*
++		 * CS and SS RPL should be equal during guest entry according
++		 * to VMX spec, but in reality it is not always so. Since vcpu
++		 * is in the middle of the transition from real mode to
++		 * protected mode it is safe to assume that RPL 0 is a good
++		 * default value.
++		 */
++		if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
++			save->selector &= ~SEGMENT_RPL_MASK;
++		save->dpl = save->selector & SEGMENT_RPL_MASK;
++		save->s = 1;
++	}
++	vmx_set_segment(vcpu, save, seg);
++}
++
++static void enter_pmode(struct kvm_vcpu *vcpu)
++{
++	unsigned long flags;
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++
++	/*
++	 * Update real mode segment cache. It may be not up-to-date if sement
++	 * register was written while vcpu was in a guest mode.
++	 */
++	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
++	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
++	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
++	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
++	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
++	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
++
++	vmx->rmode.vm86_active = 0;
++
++	vmx_segment_cache_clear(vmx);
++
++	vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
++
++	flags = vmcs_readl(GUEST_RFLAGS);
++	flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
++	flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
++	vmcs_writel(GUEST_RFLAGS, flags);
++
++	vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
++			(vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
++
++	update_exception_bitmap(vcpu);
++
++	fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
++	fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
++	fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
++	fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
++	fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
++	fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
++}
++
++static void fix_rmode_seg(int seg, struct kvm_segment *save)
++{
++	const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
++	struct kvm_segment var = *save;
++
++	var.dpl = 0x3;
++	if (seg == VCPU_SREG_CS)
++		var.type = 0x3;
++
++	if (!emulate_invalid_guest_state) {
++		var.selector = var.base >> 4;
++		var.base = var.base & 0xffff0;
++		var.limit = 0xffff;
++		var.g = 0;
++		var.db = 0;
++		var.present = 1;
++		var.s = 1;
++		var.l = 0;
++		var.unusable = 0;
++		var.type = 0x3;
++		var.avl = 0;
++		if (save->base & 0xf)
++			printk_once(KERN_WARNING "kvm: segment base is not "
++					"paragraph aligned when entering "
++					"protected mode (seg=%d)", seg);
++	}
++
++	vmcs_write16(sf->selector, var.selector);
++	vmcs_writel(sf->base, var.base);
++	vmcs_write32(sf->limit, var.limit);
++	vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
++}
++
++static void enter_rmode(struct kvm_vcpu *vcpu)
++{
++	unsigned long flags;
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
++
++	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
++	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
++	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
++	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
++	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
++	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
++	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
++
++	vmx->rmode.vm86_active = 1;
++
++	/*
++	 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
++	 * vcpu. Warn the user that an update is overdue.
++	 */
++	if (!kvm_vmx->tss_addr)
++		printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
++			     "called before entering vcpu\n");
++
++	vmx_segment_cache_clear(vmx);
++
++	vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
++	vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
++	vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
++
++	flags = vmcs_readl(GUEST_RFLAGS);
++	vmx->rmode.save_rflags = flags;
++
++	flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
++
++	vmcs_writel(GUEST_RFLAGS, flags);
++	vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
++	update_exception_bitmap(vcpu);
++
++	fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
++	fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
++	fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
++	fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
++	fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
++	fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
++
++	kvm_mmu_reset_context(vcpu);
++}
++
++void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
++
++	if (!msr)
++		return;
++
++	vcpu->arch.efer = efer;
++	if (efer & EFER_LMA) {
++		vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
++		msr->data = efer;
++	} else {
++		vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
++
++		msr->data = efer & ~EFER_LME;
++	}
++	setup_msrs(vmx);
++}
++
++#ifdef CONFIG_X86_64
++
++static void enter_lmode(struct kvm_vcpu *vcpu)
++{
++	u32 guest_tr_ar;
++
++	vmx_segment_cache_clear(to_vmx(vcpu));
++
++	guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
++	if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
++		pr_debug_ratelimited("%s: tss fixup for long mode. \n",
++				     __func__);
++		vmcs_write32(GUEST_TR_AR_BYTES,
++			     (guest_tr_ar & ~VMX_AR_TYPE_MASK)
++			     | VMX_AR_TYPE_BUSY_64_TSS);
++	}
++	vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
++}
++
++static void exit_lmode(struct kvm_vcpu *vcpu)
++{
++	vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
++	vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
++}
++
++#endif
++
++static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
++{
++	int vpid = to_vmx(vcpu)->vpid;
++
++	if (!vpid_sync_vcpu_addr(vpid, addr))
++		vpid_sync_context(vpid);
++
++	/*
++	 * If VPIDs are not supported or enabled, then the above is a no-op.
++	 * But we don't really need a TLB flush in that case anyway, because
++	 * each VM entry/exit includes an implicit flush when VPID is 0.
++	 */
++}
++
++static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
++{
++	ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
++
++	vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
++	vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
++}
++
++static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
++{
++	ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
++
++	vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
++	vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
++}
++
++static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
++{
++	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
++
++	if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
++		return;
++
++	if (is_pae_paging(vcpu)) {
++		vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
++		vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
++		vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
++		vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
++	}
++}
++
++void ept_save_pdptrs(struct kvm_vcpu *vcpu)
++{
++	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
++
++	if (is_pae_paging(vcpu)) {
++		mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
++		mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
++		mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
++		mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
++	}
++
++	kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
++}
++
++static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
++					unsigned long cr0,
++					struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++
++	if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
++		vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
++	if (!(cr0 & X86_CR0_PG)) {
++		/* From paging/starting to nonpaging */
++		exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
++					  CPU_BASED_CR3_STORE_EXITING);
++		vcpu->arch.cr0 = cr0;
++		vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
++	} else if (!is_paging(vcpu)) {
++		/* From nonpaging to paging */
++		exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
++					    CPU_BASED_CR3_STORE_EXITING);
++		vcpu->arch.cr0 = cr0;
++		vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
++	}
++
++	if (!(cr0 & X86_CR0_WP))
++		*hw_cr0 &= ~X86_CR0_WP;
++}
++
++void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	unsigned long hw_cr0;
++
++	hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
++	if (enable_unrestricted_guest)
++		hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
++	else {
++		hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
++
++		if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
++			enter_pmode(vcpu);
++
++		if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
++			enter_rmode(vcpu);
++	}
++
++#ifdef CONFIG_X86_64
++	if (vcpu->arch.efer & EFER_LME) {
++		if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
++			enter_lmode(vcpu);
++		if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
++			exit_lmode(vcpu);
++	}
++#endif
++
++	if (enable_ept && !enable_unrestricted_guest)
++		ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
++
++	vmcs_writel(CR0_READ_SHADOW, cr0);
++	vmcs_writel(GUEST_CR0, hw_cr0);
++	vcpu->arch.cr0 = cr0;
++
++	/* depends on vcpu->arch.cr0 to be set to a new value */
++	vmx->emulation_required = emulation_required(vcpu);
++}
++
++static int get_ept_level(struct kvm_vcpu *vcpu)
++{
++	if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
++		return 5;
++	return 4;
++}
++
++u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
++{
++	u64 eptp = VMX_EPTP_MT_WB;
++
++	eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
++
++	if (enable_ept_ad_bits &&
++	    (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
++		eptp |= VMX_EPTP_AD_ENABLE_BIT;
++	eptp |= (root_hpa & PAGE_MASK);
++
++	return eptp;
++}
++
++void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
++{
++	struct kvm *kvm = vcpu->kvm;
++	bool update_guest_cr3 = true;
++	unsigned long guest_cr3;
++	u64 eptp;
++
++	guest_cr3 = cr3;
++	if (enable_ept) {
++		eptp = construct_eptp(vcpu, cr3);
++		vmcs_write64(EPT_POINTER, eptp);
++
++		if (kvm_x86_ops->tlb_remote_flush) {
++			spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
++			to_vmx(vcpu)->ept_pointer = eptp;
++			to_kvm_vmx(kvm)->ept_pointers_match
++				= EPT_POINTERS_CHECK;
++			spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
++		}
++
++		/* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
++		if (is_guest_mode(vcpu))
++			update_guest_cr3 = false;
++		else if (!enable_unrestricted_guest && !is_paging(vcpu))
++			guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
++		else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
++			guest_cr3 = vcpu->arch.cr3;
++		else /* vmcs01.GUEST_CR3 is already up-to-date. */
++			update_guest_cr3 = false;
++		ept_load_pdptrs(vcpu);
++	}
++
++	if (update_guest_cr3)
++		vmcs_writel(GUEST_CR3, guest_cr3);
++}
++
++int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	/*
++	 * Pass through host's Machine Check Enable value to hw_cr4, which
++	 * is in force while we are in guest mode.  Do not let guests control
++	 * this bit, even if host CR4.MCE == 0.
++	 */
++	unsigned long hw_cr4;
++
++	hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
++	if (enable_unrestricted_guest)
++		hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
++	else if (vmx->rmode.vm86_active)
++		hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
++	else
++		hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
++
++	if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
++		if (cr4 & X86_CR4_UMIP) {
++			secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
++			hw_cr4 &= ~X86_CR4_UMIP;
++		} else if (!is_guest_mode(vcpu) ||
++			!nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
++			secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
++		}
++	}
++
++	if (cr4 & X86_CR4_VMXE) {
++		/*
++		 * To use VMXON (and later other VMX instructions), a guest
++		 * must first be able to turn on cr4.VMXE (see handle_vmon()).
++		 * So basically the check on whether to allow nested VMX
++		 * is here.  We operate under the default treatment of SMM,
++		 * so VMX cannot be enabled under SMM.
++		 */
++		if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
++			return 1;
++	}
++
++	if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
++		return 1;
++
++	vcpu->arch.cr4 = cr4;
++
++	if (!enable_unrestricted_guest) {
++		if (enable_ept) {
++			if (!is_paging(vcpu)) {
++				hw_cr4 &= ~X86_CR4_PAE;
++				hw_cr4 |= X86_CR4_PSE;
++			} else if (!(cr4 & X86_CR4_PAE)) {
++				hw_cr4 &= ~X86_CR4_PAE;
++			}
++		}
++
++		/*
++		 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
++		 * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
++		 * to be manually disabled when guest switches to non-paging
++		 * mode.
++		 *
++		 * If !enable_unrestricted_guest, the CPU is always running
++		 * with CR0.PG=1 and CR4 needs to be modified.
++		 * If enable_unrestricted_guest, the CPU automatically
++		 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
++		 */
++		if (!is_paging(vcpu))
++			hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
++	}
++
++	vmcs_writel(CR4_READ_SHADOW, cr4);
++	vmcs_writel(GUEST_CR4, hw_cr4);
++	return 0;
++}
++
++void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	u32 ar;
++
++	if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
++		*var = vmx->rmode.segs[seg];
++		if (seg == VCPU_SREG_TR
++		    || var->selector == vmx_read_guest_seg_selector(vmx, seg))
++			return;
++		var->base = vmx_read_guest_seg_base(vmx, seg);
++		var->selector = vmx_read_guest_seg_selector(vmx, seg);
++		return;
++	}
++	var->base = vmx_read_guest_seg_base(vmx, seg);
++	var->limit = vmx_read_guest_seg_limit(vmx, seg);
++	var->selector = vmx_read_guest_seg_selector(vmx, seg);
++	ar = vmx_read_guest_seg_ar(vmx, seg);
++	var->unusable = (ar >> 16) & 1;
++	var->type = ar & 15;
++	var->s = (ar >> 4) & 1;
++	var->dpl = (ar >> 5) & 3;
++	/*
++	 * Some userspaces do not preserve unusable property. Since usable
++	 * segment has to be present according to VMX spec we can use present
++	 * property to amend userspace bug by making unusable segment always
++	 * nonpresent. vmx_segment_access_rights() already marks nonpresent
++	 * segment as unusable.
++	 */
++	var->present = !var->unusable;
++	var->avl = (ar >> 12) & 1;
++	var->l = (ar >> 13) & 1;
++	var->db = (ar >> 14) & 1;
++	var->g = (ar >> 15) & 1;
++}
++
++static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
++{
++	struct kvm_segment s;
++
++	if (to_vmx(vcpu)->rmode.vm86_active) {
++		vmx_get_segment(vcpu, &s, seg);
++		return s.base;
++	}
++	return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
++}
++
++int vmx_get_cpl(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++
++	if (unlikely(vmx->rmode.vm86_active))
++		return 0;
++	else {
++		int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
++		return VMX_AR_DPL(ar);
++	}
++}
++
++static u32 vmx_segment_access_rights(struct kvm_segment *var)
++{
++	u32 ar;
++
++	if (var->unusable || !var->present)
++		ar = 1 << 16;
++	else {
++		ar = var->type & 15;
++		ar |= (var->s & 1) << 4;
++		ar |= (var->dpl & 3) << 5;
++		ar |= (var->present & 1) << 7;
++		ar |= (var->avl & 1) << 12;
++		ar |= (var->l & 1) << 13;
++		ar |= (var->db & 1) << 14;
++		ar |= (var->g & 1) << 15;
++	}
++
++	return ar;
++}
++
++void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
++
++	vmx_segment_cache_clear(vmx);
++
++	if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
++		vmx->rmode.segs[seg] = *var;
++		if (seg == VCPU_SREG_TR)
++			vmcs_write16(sf->selector, var->selector);
++		else if (var->s)
++			fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
++		goto out;
++	}
++
++	vmcs_writel(sf->base, var->base);
++	vmcs_write32(sf->limit, var->limit);
++	vmcs_write16(sf->selector, var->selector);
++
++	/*
++	 *   Fix the "Accessed" bit in AR field of segment registers for older
++	 * qemu binaries.
++	 *   IA32 arch specifies that at the time of processor reset the
++	 * "Accessed" bit in the AR field of segment registers is 1. And qemu
++	 * is setting it to 0 in the userland code. This causes invalid guest
++	 * state vmexit when "unrestricted guest" mode is turned on.
++	 *    Fix for this setup issue in cpu_reset is being pushed in the qemu
++	 * tree. Newer qemu binaries with that qemu fix would not need this
++	 * kvm hack.
++	 */
++	if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
++		var->type |= 0x1; /* Accessed */
++
++	vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
++
++out:
++	vmx->emulation_required = emulation_required(vcpu);
++}
++
++static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
++{
++	u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
++
++	*db = (ar >> 14) & 1;
++	*l = (ar >> 13) & 1;
++}
++
++static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
++{
++	dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
++	dt->address = vmcs_readl(GUEST_IDTR_BASE);
++}
++
++static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
++{
++	vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
++	vmcs_writel(GUEST_IDTR_BASE, dt->address);
++}
++
++static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
++{
++	dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
++	dt->address = vmcs_readl(GUEST_GDTR_BASE);
++}
++
++static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
++{
++	vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
++	vmcs_writel(GUEST_GDTR_BASE, dt->address);
++}
++
++static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
++{
++	struct kvm_segment var;
++	u32 ar;
++
++	vmx_get_segment(vcpu, &var, seg);
++	var.dpl = 0x3;
++	if (seg == VCPU_SREG_CS)
++		var.type = 0x3;
++	ar = vmx_segment_access_rights(&var);
++
++	if (var.base != (var.selector << 4))
++		return false;
++	if (var.limit != 0xffff)
++		return false;
++	if (ar != 0xf3)
++		return false;
++
++	return true;
++}
++
++static bool code_segment_valid(struct kvm_vcpu *vcpu)
++{
++	struct kvm_segment cs;
++	unsigned int cs_rpl;
++
++	vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
++	cs_rpl = cs.selector & SEGMENT_RPL_MASK;
++
++	if (cs.unusable)
++		return false;
++	if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
++		return false;
++	if (!cs.s)
++		return false;
++	if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
++		if (cs.dpl > cs_rpl)
++			return false;
++	} else {
++		if (cs.dpl != cs_rpl)
++			return false;
++	}
++	if (!cs.present)
++		return false;
++
++	/* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
++	return true;
++}
++
++static bool stack_segment_valid(struct kvm_vcpu *vcpu)
++{
++	struct kvm_segment ss;
++	unsigned int ss_rpl;
++
++	vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
++	ss_rpl = ss.selector & SEGMENT_RPL_MASK;
++
++	if (ss.unusable)
++		return true;
++	if (ss.type != 3 && ss.type != 7)
++		return false;
++	if (!ss.s)
++		return false;
++	if (ss.dpl != ss_rpl) /* DPL != RPL */
++		return false;
++	if (!ss.present)
++		return false;
++
++	return true;
++}
++
++static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
++{
++	struct kvm_segment var;
++	unsigned int rpl;
++
++	vmx_get_segment(vcpu, &var, seg);
++	rpl = var.selector & SEGMENT_RPL_MASK;
++
++	if (var.unusable)
++		return true;
++	if (!var.s)
++		return false;
++	if (!var.present)
++		return false;
++	if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
++		if (var.dpl < rpl) /* DPL < RPL */
++			return false;
++	}
++
++	/* TODO: Add other members to kvm_segment_field to allow checking for other access
++	 * rights flags
++	 */
++	return true;
++}
++
++static bool tr_valid(struct kvm_vcpu *vcpu)
++{
++	struct kvm_segment tr;
++
++	vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
++
++	if (tr.unusable)
++		return false;
++	if (tr.selector & SEGMENT_TI_MASK)	/* TI = 1 */
++		return false;
++	if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
++		return false;
++	if (!tr.present)
++		return false;
++
++	return true;
++}
++
++static bool ldtr_valid(struct kvm_vcpu *vcpu)
++{
++	struct kvm_segment ldtr;
++
++	vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
++
++	if (ldtr.unusable)
++		return true;
++	if (ldtr.selector & SEGMENT_TI_MASK)	/* TI = 1 */
++		return false;
++	if (ldtr.type != 2)
++		return false;
++	if (!ldtr.present)
++		return false;
++
++	return true;
++}
++
++static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
++{
++	struct kvm_segment cs, ss;
++
++	vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
++	vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
++
++	return ((cs.selector & SEGMENT_RPL_MASK) ==
++		 (ss.selector & SEGMENT_RPL_MASK));
++}
++
++/*
++ * Check if guest state is valid. Returns true if valid, false if
++ * not.
++ * We assume that registers are always usable
++ */
++static bool guest_state_valid(struct kvm_vcpu *vcpu)
++{
++	if (enable_unrestricted_guest)
++		return true;
++
++	/* real mode guest state checks */
++	if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
++		if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
++			return false;
++		if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
++			return false;
++		if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
++			return false;
++		if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
++			return false;
++		if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
++			return false;
++		if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
++			return false;
++	} else {
++	/* protected mode guest state checks */
++		if (!cs_ss_rpl_check(vcpu))
++			return false;
++		if (!code_segment_valid(vcpu))
++			return false;
++		if (!stack_segment_valid(vcpu))
++			return false;
++		if (!data_segment_valid(vcpu, VCPU_SREG_DS))
++			return false;
++		if (!data_segment_valid(vcpu, VCPU_SREG_ES))
++			return false;
++		if (!data_segment_valid(vcpu, VCPU_SREG_FS))
++			return false;
++		if (!data_segment_valid(vcpu, VCPU_SREG_GS))
++			return false;
++		if (!tr_valid(vcpu))
++			return false;
++		if (!ldtr_valid(vcpu))
++			return false;
++	}
++	/* TODO:
++	 * - Add checks on RIP
++	 * - Add checks on RFLAGS
++	 */
++
++	return true;
++}
++
++static int init_rmode_tss(struct kvm *kvm)
++{
++	gfn_t fn;
++	u16 data = 0;
++	int idx, r;
++
++	idx = srcu_read_lock(&kvm->srcu);
++	fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
++	r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
++	if (r < 0)
++		goto out;
++	data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
++	r = kvm_write_guest_page(kvm, fn++, &data,
++			TSS_IOPB_BASE_OFFSET, sizeof(u16));
++	if (r < 0)
++		goto out;
++	r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
++	if (r < 0)
++		goto out;
++	r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
++	if (r < 0)
++		goto out;
++	data = ~0;
++	r = kvm_write_guest_page(kvm, fn, &data,
++				 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
++				 sizeof(u8));
++out:
++	srcu_read_unlock(&kvm->srcu, idx);
++	return r;
++}
++
++static int init_rmode_identity_map(struct kvm *kvm)
++{
++	struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
++	int i, idx, r = 0;
++	kvm_pfn_t identity_map_pfn;
++	u32 tmp;
++
++	/* Protect kvm_vmx->ept_identity_pagetable_done. */
++	mutex_lock(&kvm->slots_lock);
++
++	if (likely(kvm_vmx->ept_identity_pagetable_done))
++		goto out2;
++
++	if (!kvm_vmx->ept_identity_map_addr)
++		kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
++	identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
++
++	r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
++				    kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
++	if (r < 0)
++		goto out2;
++
++	idx = srcu_read_lock(&kvm->srcu);
++	r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
++	if (r < 0)
++		goto out;
++	/* Set up identity-mapping pagetable for EPT in real mode */
++	for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
++		tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
++			_PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
++		r = kvm_write_guest_page(kvm, identity_map_pfn,
++				&tmp, i * sizeof(tmp), sizeof(tmp));
++		if (r < 0)
++			goto out;
++	}
++	kvm_vmx->ept_identity_pagetable_done = true;
++
++out:
++	srcu_read_unlock(&kvm->srcu, idx);
++
++out2:
++	mutex_unlock(&kvm->slots_lock);
++	return r;
++}
++
++static void seg_setup(int seg)
++{
++	const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
++	unsigned int ar;
++
++	vmcs_write16(sf->selector, 0);
++	vmcs_writel(sf->base, 0);
++	vmcs_write32(sf->limit, 0xffff);
++	ar = 0x93;
++	if (seg == VCPU_SREG_CS)
++		ar |= 0x08; /* code segment */
++
++	vmcs_write32(sf->ar_bytes, ar);
++}
++
++static int alloc_apic_access_page(struct kvm *kvm)
++{
++	struct page *page;
++	int r = 0;
++
++	mutex_lock(&kvm->slots_lock);
++	if (kvm->arch.apic_access_page_done)
++		goto out;
++	r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
++				    APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
++	if (r)
++		goto out;
++
++	page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
++	if (is_error_page(page)) {
++		r = -EFAULT;
++		goto out;
++	}
++
++	/*
++	 * Do not pin the page in memory, so that memory hot-unplug
++	 * is able to migrate it.
++	 */
++	put_page(page);
++	kvm->arch.apic_access_page_done = true;
++out:
++	mutex_unlock(&kvm->slots_lock);
++	return r;
++}
++
++int allocate_vpid(void)
++{
++	int vpid;
++
++	if (!enable_vpid)
++		return 0;
++	spin_lock(&vmx_vpid_lock);
++	vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
++	if (vpid < VMX_NR_VPIDS)
++		__set_bit(vpid, vmx_vpid_bitmap);
++	else
++		vpid = 0;
++	spin_unlock(&vmx_vpid_lock);
++	return vpid;
++}
++
++void free_vpid(int vpid)
++{
++	if (!enable_vpid || vpid == 0)
++		return;
++	spin_lock(&vmx_vpid_lock);
++	__clear_bit(vpid, vmx_vpid_bitmap);
++	spin_unlock(&vmx_vpid_lock);
++}
++
++static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
++							  u32 msr, int type)
++{
++	int f = sizeof(unsigned long);
++
++	if (!cpu_has_vmx_msr_bitmap())
++		return;
++
++	if (static_branch_unlikely(&enable_evmcs))
++		evmcs_touch_msr_bitmap();
++
++	/*
++	 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
++	 * have the write-low and read-high bitmap offsets the wrong way round.
++	 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
++	 */
++	if (msr <= 0x1fff) {
++		if (type & MSR_TYPE_R)
++			/* read-low */
++			__clear_bit(msr, msr_bitmap + 0x000 / f);
++
++		if (type & MSR_TYPE_W)
++			/* write-low */
++			__clear_bit(msr, msr_bitmap + 0x800 / f);
++
++	} else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
++		msr &= 0x1fff;
++		if (type & MSR_TYPE_R)
++			/* read-high */
++			__clear_bit(msr, msr_bitmap + 0x400 / f);
++
++		if (type & MSR_TYPE_W)
++			/* write-high */
++			__clear_bit(msr, msr_bitmap + 0xc00 / f);
++
++	}
++}
++
++static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
++							 u32 msr, int type)
++{
++	int f = sizeof(unsigned long);
++
++	if (!cpu_has_vmx_msr_bitmap())
++		return;
++
++	if (static_branch_unlikely(&enable_evmcs))
++		evmcs_touch_msr_bitmap();
++
++	/*
++	 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
++	 * have the write-low and read-high bitmap offsets the wrong way round.
++	 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
++	 */
++	if (msr <= 0x1fff) {
++		if (type & MSR_TYPE_R)
++			/* read-low */
++			__set_bit(msr, msr_bitmap + 0x000 / f);
++
++		if (type & MSR_TYPE_W)
++			/* write-low */
++			__set_bit(msr, msr_bitmap + 0x800 / f);
++
++	} else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
++		msr &= 0x1fff;
++		if (type & MSR_TYPE_R)
++			/* read-high */
++			__set_bit(msr, msr_bitmap + 0x400 / f);
++
++		if (type & MSR_TYPE_W)
++			/* write-high */
++			__set_bit(msr, msr_bitmap + 0xc00 / f);
++
++	}
++}
++
++static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
++			     			      u32 msr, int type, bool value)
++{
++	if (value)
++		vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
++	else
++		vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
++}
++
++static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
++{
++	u8 mode = 0;
++
++	if (cpu_has_secondary_exec_ctrls() &&
++	    (secondary_exec_controls_get(to_vmx(vcpu)) &
++	     SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
++		mode |= MSR_BITMAP_MODE_X2APIC;
++		if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
++			mode |= MSR_BITMAP_MODE_X2APIC_APICV;
++	}
++
++	return mode;
++}
++
++static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
++					 u8 mode)
++{
++	int msr;
++
++	for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
++		unsigned word = msr / BITS_PER_LONG;
++		msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
++		msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
++	}
++
++	if (mode & MSR_BITMAP_MODE_X2APIC) {
++		/*
++		 * TPR reads and writes can be virtualized even if virtual interrupt
++		 * delivery is not in use.
++		 */
++		vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
++		if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
++			vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
++			vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
++			vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
++		}
++	}
++}
++
++void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
++	u8 mode = vmx_msr_bitmap_mode(vcpu);
++	u8 changed = mode ^ vmx->msr_bitmap_mode;
++
++	if (!changed)
++		return;
++
++	if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
++		vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
++
++	vmx->msr_bitmap_mode = mode;
++}
++
++void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
++{
++	unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
++	bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
++	u32 i;
++
++	vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
++							MSR_TYPE_RW, flag);
++	vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
++							MSR_TYPE_RW, flag);
++	vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
++							MSR_TYPE_RW, flag);
++	vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
++							MSR_TYPE_RW, flag);
++	for (i = 0; i < vmx->pt_desc.addr_range; i++) {
++		vmx_set_intercept_for_msr(msr_bitmap,
++			MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
++		vmx_set_intercept_for_msr(msr_bitmap,
++			MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
++	}
++}
++
++static bool vmx_get_enable_apicv(struct kvm *kvm)
++{
++	return enable_apicv;
++}
++
++static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	void *vapic_page;
++	u32 vppr;
++	int rvi;
++
++	if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
++		!nested_cpu_has_vid(get_vmcs12(vcpu)) ||
++		WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
++		return false;
++
++	rvi = vmx_get_rvi();
++
++	vapic_page = vmx->nested.virtual_apic_map.hva;
++	vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
++
++	return ((rvi & 0xf0) > (vppr & 0xf0));
++}
++
++static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
++						     bool nested)
++{
++#ifdef CONFIG_SMP
++	int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
++
++	if (vcpu->mode == IN_GUEST_MODE) {
++		/*
++		 * The vector of interrupt to be delivered to vcpu had
++		 * been set in PIR before this function.
++		 *
++		 * Following cases will be reached in this block, and
++		 * we always send a notification event in all cases as
++		 * explained below.
++		 *
++		 * Case 1: vcpu keeps in non-root mode. Sending a
++		 * notification event posts the interrupt to vcpu.
++		 *
++		 * Case 2: vcpu exits to root mode and is still
++		 * runnable. PIR will be synced to vIRR before the
++		 * next vcpu entry. Sending a notification event in
++		 * this case has no effect, as vcpu is not in root
++		 * mode.
++		 *
++		 * Case 3: vcpu exits to root mode and is blocked.
++		 * vcpu_block() has already synced PIR to vIRR and
++		 * never blocks vcpu if vIRR is not cleared. Therefore,
++		 * a blocked vcpu here does not wait for any requested
++		 * interrupts in PIR, and sending a notification event
++		 * which has no effect is safe here.
++		 */
++
++		apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
++		return true;
++	}
++#endif
++	return false;
++}
++
++static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
++						int vector)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++
++	if (is_guest_mode(vcpu) &&
++	    vector == vmx->nested.posted_intr_nv) {
++		/*
++		 * If a posted intr is not recognized by hardware,
++		 * we will accomplish it in the next vmentry.
++		 */
++		vmx->nested.pi_pending = true;
++		kvm_make_request(KVM_REQ_EVENT, vcpu);
++		/* the PIR and ON have been set by L1. */
++		if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
++			kvm_vcpu_kick(vcpu);
++		return 0;
++	}
++	return -1;
++}
++/*
++ * Send interrupt to vcpu via posted interrupt way.
++ * 1. If target vcpu is running(non-root mode), send posted interrupt
++ * notification to vcpu and hardware will sync PIR to vIRR atomically.
++ * 2. If target vcpu isn't running(root mode), kick it to pick up the
++ * interrupt from PIR in next vmentry.
++ */
++static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	int r;
++
++	r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
++	if (!r)
++		return;
++
++	if (pi_test_and_set_pir(vector, &vmx->pi_desc))
++		return;
++
++	/* If a previous notification has sent the IPI, nothing to do.  */
++	if (pi_test_and_set_on(&vmx->pi_desc))
++		return;
++
++	if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
++		kvm_vcpu_kick(vcpu);
++}
++
++/*
++ * Set up the vmcs's constant host-state fields, i.e., host-state fields that
++ * will not change in the lifetime of the guest.
++ * Note that host-state that does change is set elsewhere. E.g., host-state
++ * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
++ */
++void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
++{
++	u32 low32, high32;
++	unsigned long tmpl;
++	unsigned long cr0, cr3, cr4;
++
++	cr0 = read_cr0();
++	WARN_ON(cr0 & X86_CR0_TS);
++	vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
++
++	/*
++	 * Save the most likely value for this task's CR3 in the VMCS.
++	 * We can't use __get_current_cr3_fast() because we're not atomic.
++	 */
++	cr3 = __read_cr3();
++	vmcs_writel(HOST_CR3, cr3);		/* 22.2.3  FIXME: shadow tables */
++	vmx->loaded_vmcs->host_state.cr3 = cr3;
++
++	/* Save the most likely value for this task's CR4 in the VMCS. */
++	cr4 = cr4_read_shadow();
++	vmcs_writel(HOST_CR4, cr4);			/* 22.2.3, 22.2.5 */
++	vmx->loaded_vmcs->host_state.cr4 = cr4;
++
++	vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
++#ifdef CONFIG_X86_64
++	/*
++	 * Load null selectors, so we can avoid reloading them in
++	 * vmx_prepare_switch_to_host(), in case userspace uses
++	 * the null selectors too (the expected case).
++	 */
++	vmcs_write16(HOST_DS_SELECTOR, 0);
++	vmcs_write16(HOST_ES_SELECTOR, 0);
++#else
++	vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
++	vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
++#endif
++	vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
++	vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
++
++	vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
++
++	vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
++
++	rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
++	vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
++	rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
++	vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
++
++	if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
++		rdmsr(MSR_IA32_CR_PAT, low32, high32);
++		vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
++	}
++
++	if (cpu_has_load_ia32_efer())
++		vmcs_write64(HOST_IA32_EFER, host_efer);
++}
++
++void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
++{
++	vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
++	if (enable_ept)
++		vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
++	if (is_guest_mode(&vmx->vcpu))
++		vmx->vcpu.arch.cr4_guest_owned_bits &=
++			~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
++	vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
++}
++
++u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
++{
++	u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
++
++	if (!kvm_vcpu_apicv_active(&vmx->vcpu))
++		pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
++
++	if (!enable_vnmi)
++		pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
++
++	if (!enable_preemption_timer)
++		pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
++
++	return pin_based_exec_ctrl;
++}
++
++static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++
++	pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
++	if (cpu_has_secondary_exec_ctrls()) {
++		if (kvm_vcpu_apicv_active(vcpu))
++			secondary_exec_controls_setbit(vmx,
++				      SECONDARY_EXEC_APIC_REGISTER_VIRT |
++				      SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
++		else
++			secondary_exec_controls_clearbit(vmx,
++					SECONDARY_EXEC_APIC_REGISTER_VIRT |
++					SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
++	}
++
++	if (cpu_has_vmx_msr_bitmap())
++		vmx_update_msr_bitmap(vcpu);
++}
++
++u32 vmx_exec_control(struct vcpu_vmx *vmx)
++{
++	u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
++
++	if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
++		exec_control &= ~CPU_BASED_MOV_DR_EXITING;
++
++	if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
++		exec_control &= ~CPU_BASED_TPR_SHADOW;
++#ifdef CONFIG_X86_64
++		exec_control |= CPU_BASED_CR8_STORE_EXITING |
++				CPU_BASED_CR8_LOAD_EXITING;
++#endif
++	}
++	if (!enable_ept)
++		exec_control |= CPU_BASED_CR3_STORE_EXITING |
++				CPU_BASED_CR3_LOAD_EXITING  |
++				CPU_BASED_INVLPG_EXITING;
++	if (kvm_mwait_in_guest(vmx->vcpu.kvm))
++		exec_control &= ~(CPU_BASED_MWAIT_EXITING |
++				CPU_BASED_MONITOR_EXITING);
++	if (kvm_hlt_in_guest(vmx->vcpu.kvm))
++		exec_control &= ~CPU_BASED_HLT_EXITING;
++	return exec_control;
++}
++
++
++static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
++{
++	struct kvm_vcpu *vcpu = &vmx->vcpu;
++
++	u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
++
++	if (pt_mode == PT_MODE_SYSTEM)
++		exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
++	if (!cpu_need_virtualize_apic_accesses(vcpu))
++		exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
++	if (vmx->vpid == 0)
++		exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
++	if (!enable_ept) {
++		exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
++		enable_unrestricted_guest = 0;
++	}
++	if (!enable_unrestricted_guest)
++		exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
++	if (kvm_pause_in_guest(vmx->vcpu.kvm))
++		exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
++	if (!kvm_vcpu_apicv_active(vcpu))
++		exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
++				  SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
++	exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
++
++	/* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
++	 * in vmx_set_cr4.  */
++	exec_control &= ~SECONDARY_EXEC_DESC;
++
++	/* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
++	   (handle_vmptrld).
++	   We can NOT enable shadow_vmcs here because we don't have yet
++	   a current VMCS12
++	*/
++	exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
++
++	if (!enable_pml)
++		exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
++
++	if (vmx_xsaves_supported()) {
++		/* Exposing XSAVES only when XSAVE is exposed */
++		bool xsaves_enabled =
++			guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
++			guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
++
++		vcpu->arch.xsaves_enabled = xsaves_enabled;
++
++		if (!xsaves_enabled)
++			exec_control &= ~SECONDARY_EXEC_XSAVES;
++
++		if (nested) {
++			if (xsaves_enabled)
++				vmx->nested.msrs.secondary_ctls_high |=
++					SECONDARY_EXEC_XSAVES;
++			else
++				vmx->nested.msrs.secondary_ctls_high &=
++					~SECONDARY_EXEC_XSAVES;
++		}
++	}
++
++	if (vmx_rdtscp_supported()) {
++		bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
++		if (!rdtscp_enabled)
++			exec_control &= ~SECONDARY_EXEC_RDTSCP;
++
++		if (nested) {
++			if (rdtscp_enabled)
++				vmx->nested.msrs.secondary_ctls_high |=
++					SECONDARY_EXEC_RDTSCP;
++			else
++				vmx->nested.msrs.secondary_ctls_high &=
++					~SECONDARY_EXEC_RDTSCP;
++		}
++	}
++
++	if (vmx_invpcid_supported()) {
++		/* Exposing INVPCID only when PCID is exposed */
++		bool invpcid_enabled =
++			guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
++			guest_cpuid_has(vcpu, X86_FEATURE_PCID);
++
++		if (!invpcid_enabled) {
++			exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
++			guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
++		}
++
++		if (nested) {
++			if (invpcid_enabled)
++				vmx->nested.msrs.secondary_ctls_high |=
++					SECONDARY_EXEC_ENABLE_INVPCID;
++			else
++				vmx->nested.msrs.secondary_ctls_high &=
++					~SECONDARY_EXEC_ENABLE_INVPCID;
++		}
++	}
++
++	if (vmx_rdrand_supported()) {
++		bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
++		if (rdrand_enabled)
++			exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
++
++		if (nested) {
++			if (rdrand_enabled)
++				vmx->nested.msrs.secondary_ctls_high |=
++					SECONDARY_EXEC_RDRAND_EXITING;
++			else
++				vmx->nested.msrs.secondary_ctls_high &=
++					~SECONDARY_EXEC_RDRAND_EXITING;
++		}
++	}
++
++	if (vmx_rdseed_supported()) {
++		bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
++		if (rdseed_enabled)
++			exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
++
++		if (nested) {
++			if (rdseed_enabled)
++				vmx->nested.msrs.secondary_ctls_high |=
++					SECONDARY_EXEC_RDSEED_EXITING;
++			else
++				vmx->nested.msrs.secondary_ctls_high &=
++					~SECONDARY_EXEC_RDSEED_EXITING;
++		}
++	}
++
++	if (vmx_waitpkg_supported()) {
++		bool waitpkg_enabled =
++			guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
++
++		if (!waitpkg_enabled)
++			exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
++
++		if (nested) {
++			if (waitpkg_enabled)
++				vmx->nested.msrs.secondary_ctls_high |=
++					SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
++			else
++				vmx->nested.msrs.secondary_ctls_high &=
++					~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
++		}
++	}
++
++	vmx->secondary_exec_control = exec_control;
++}
++
++static void ept_set_mmio_spte_mask(void)
++{
++	/*
++	 * EPT Misconfigurations can be generated if the value of bits 2:0
++	 * of an EPT paging-structure entry is 110b (write/execute).
++	 */
++	kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
++				   VMX_EPT_MISCONFIG_WX_VALUE, 0);
++}
++
++#define VMX_XSS_EXIT_BITMAP 0
++
++/*
++ * Noting that the initialization of Guest-state Area of VMCS is in
++ * vmx_vcpu_reset().
++ */
++static void init_vmcs(struct vcpu_vmx *vmx)
++{
++	if (nested)
++		nested_vmx_set_vmcs_shadowing_bitmap();
++
++	if (cpu_has_vmx_msr_bitmap())
++		vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
++
++	vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
++
++	/* Control */
++	pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
++
++	exec_controls_set(vmx, vmx_exec_control(vmx));
++
++	if (cpu_has_secondary_exec_ctrls()) {
++		vmx_compute_secondary_exec_control(vmx);
++		secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
++	}
++
++	if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
++		vmcs_write64(EOI_EXIT_BITMAP0, 0);
++		vmcs_write64(EOI_EXIT_BITMAP1, 0);
++		vmcs_write64(EOI_EXIT_BITMAP2, 0);
++		vmcs_write64(EOI_EXIT_BITMAP3, 0);
++
++		vmcs_write16(GUEST_INTR_STATUS, 0);
++
++		vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
++		vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
++	}
++
++	if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
++		vmcs_write32(PLE_GAP, ple_gap);
++		vmx->ple_window = ple_window;
++		vmx->ple_window_dirty = true;
++	}
++
++	vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
++	vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
++	vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
++
++	vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
++	vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
++	vmx_set_constant_host_state(vmx);
++	vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
++	vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
++
++	if (cpu_has_vmx_vmfunc())
++		vmcs_write64(VM_FUNCTION_CONTROL, 0);
++
++	vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
++	vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
++	vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
++	vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
++	vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
++
++	if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
++		vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
++
++	vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
++
++	/* 22.2.1, 20.8.1 */
++	vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
++
++	vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
++	vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
++
++	set_cr4_guest_host_mask(vmx);
++
++	if (vmx->vpid != 0)
++		vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
++
++	if (vmx_xsaves_supported())
++		vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
++
++	if (enable_pml) {
++		vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
++		vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
++	}
++
++	if (cpu_has_vmx_encls_vmexit())
++		vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
++
++	if (pt_mode == PT_MODE_HOST_GUEST) {
++		memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
++		/* Bit[6~0] are forced to 1, writes are ignored. */
++		vmx->pt_desc.guest.output_mask = 0x7F;
++		vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
++	}
++}
++
++static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	struct msr_data apic_base_msr;
++	u64 cr0;
++
++	vmx->rmode.vm86_active = 0;
++	vmx->spec_ctrl = 0;
++
++	vmx->msr_ia32_umwait_control = 0;
++
++	vcpu->arch.microcode_version = 0x100000000ULL;
++	vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
++	vmx->hv_deadline_tsc = -1;
++	kvm_set_cr8(vcpu, 0);
++
++	if (!init_event) {
++		apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
++				     MSR_IA32_APICBASE_ENABLE;
++		if (kvm_vcpu_is_reset_bsp(vcpu))
++			apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
++		apic_base_msr.host_initiated = true;
++		kvm_set_apic_base(vcpu, &apic_base_msr);
++	}
++
++	vmx_segment_cache_clear(vmx);
++
++	seg_setup(VCPU_SREG_CS);
++	vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
++	vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
++
++	seg_setup(VCPU_SREG_DS);
++	seg_setup(VCPU_SREG_ES);
++	seg_setup(VCPU_SREG_FS);
++	seg_setup(VCPU_SREG_GS);
++	seg_setup(VCPU_SREG_SS);
++
++	vmcs_write16(GUEST_TR_SELECTOR, 0);
++	vmcs_writel(GUEST_TR_BASE, 0);
++	vmcs_write32(GUEST_TR_LIMIT, 0xffff);
++	vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
++
++	vmcs_write16(GUEST_LDTR_SELECTOR, 0);
++	vmcs_writel(GUEST_LDTR_BASE, 0);
++	vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
++	vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
++
++	if (!init_event) {
++		vmcs_write32(GUEST_SYSENTER_CS, 0);
++		vmcs_writel(GUEST_SYSENTER_ESP, 0);
++		vmcs_writel(GUEST_SYSENTER_EIP, 0);
++		vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
++	}
++
++	kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
++	kvm_rip_write(vcpu, 0xfff0);
++
++	vmcs_writel(GUEST_GDTR_BASE, 0);
++	vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
++
++	vmcs_writel(GUEST_IDTR_BASE, 0);
++	vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
++
++	vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
++	vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
++	vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
++	if (kvm_mpx_supported())
++		vmcs_write64(GUEST_BNDCFGS, 0);
++
++	setup_msrs(vmx);
++
++	vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
++
++	if (cpu_has_vmx_tpr_shadow() && !init_event) {
++		vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
++		if (cpu_need_tpr_shadow(vcpu))
++			vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
++				     __pa(vcpu->arch.apic->regs));
++		vmcs_write32(TPR_THRESHOLD, 0);
++	}
++
++	kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
++
++	cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
++	vmx->vcpu.arch.cr0 = cr0;
++	vmx_set_cr0(vcpu, cr0); /* enter rmode */
++	vmx_set_cr4(vcpu, 0);
++	vmx_set_efer(vcpu, 0);
++
++	update_exception_bitmap(vcpu);
++
++	vpid_sync_context(vmx->vpid);
++	if (init_event)
++		vmx_clear_hlt(vcpu);
++}
++
++static void enable_irq_window(struct kvm_vcpu *vcpu)
++{
++	exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
++}
++
++static void enable_nmi_window(struct kvm_vcpu *vcpu)
++{
++	if (!enable_vnmi ||
++	    vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
++		enable_irq_window(vcpu);
++		return;
++	}
++
++	exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
++}
++
++static void vmx_inject_irq(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	uint32_t intr;
++	int irq = vcpu->arch.interrupt.nr;
++
++	trace_kvm_inj_virq(irq);
++
++	++vcpu->stat.irq_injections;
++	if (vmx->rmode.vm86_active) {
++		int inc_eip = 0;
++		if (vcpu->arch.interrupt.soft)
++			inc_eip = vcpu->arch.event_exit_inst_len;
++		kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
++		return;
++	}
++	intr = irq | INTR_INFO_VALID_MASK;
++	if (vcpu->arch.interrupt.soft) {
++		intr |= INTR_TYPE_SOFT_INTR;
++		vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
++			     vmx->vcpu.arch.event_exit_inst_len);
++	} else
++		intr |= INTR_TYPE_EXT_INTR;
++	vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
++
++	vmx_clear_hlt(vcpu);
++}
++
++static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++
++	if (!enable_vnmi) {
++		/*
++		 * Tracking the NMI-blocked state in software is built upon
++		 * finding the next open IRQ window. This, in turn, depends on
++		 * well-behaving guests: They have to keep IRQs disabled at
++		 * least as long as the NMI handler runs. Otherwise we may
++		 * cause NMI nesting, maybe breaking the guest. But as this is
++		 * highly unlikely, we can live with the residual risk.
++		 */
++		vmx->loaded_vmcs->soft_vnmi_blocked = 1;
++		vmx->loaded_vmcs->vnmi_blocked_time = 0;
++	}
++
++	++vcpu->stat.nmi_injections;
++	vmx->loaded_vmcs->nmi_known_unmasked = false;
++
++	if (vmx->rmode.vm86_active) {
++		kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
++		return;
++	}
++
++	vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
++			INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
++
++	vmx_clear_hlt(vcpu);
++}
++
++bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	bool masked;
++
++	if (!enable_vnmi)
++		return vmx->loaded_vmcs->soft_vnmi_blocked;
++	if (vmx->loaded_vmcs->nmi_known_unmasked)
++		return false;
++	masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
++	vmx->loaded_vmcs->nmi_known_unmasked = !masked;
++	return masked;
++}
++
++void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++
++	if (!enable_vnmi) {
++		if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
++			vmx->loaded_vmcs->soft_vnmi_blocked = masked;
++			vmx->loaded_vmcs->vnmi_blocked_time = 0;
++		}
++	} else {
++		vmx->loaded_vmcs->nmi_known_unmasked = !masked;
++		if (masked)
++			vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
++				      GUEST_INTR_STATE_NMI);
++		else
++			vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
++					GUEST_INTR_STATE_NMI);
++	}
++}
++
++static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
++{
++	if (to_vmx(vcpu)->nested.nested_run_pending)
++		return 0;
++
++	if (!enable_vnmi &&
++	    to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
++		return 0;
++
++	return	!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
++		  (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
++		   | GUEST_INTR_STATE_NMI));
++}
++
++static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
++{
++	return (!to_vmx(vcpu)->nested.nested_run_pending &&
++		vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
++		!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
++			(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
++}
++
++static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
++{
++	int ret;
++
++	if (enable_unrestricted_guest)
++		return 0;
++
++	ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
++				    PAGE_SIZE * 3);
++	if (ret)
++		return ret;
++	to_kvm_vmx(kvm)->tss_addr = addr;
++	return init_rmode_tss(kvm);
++}
++
++static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
++{
++	to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
++	return 0;
++}
++
++static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
++{
++	switch (vec) {
++	case BP_VECTOR:
++		/*
++		 * Update instruction length as we may reinject the exception
++		 * from user space while in guest debugging mode.
++		 */
++		to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
++			vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
++		if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
++			return false;
++		/* fall through */
++	case DB_VECTOR:
++		if (vcpu->guest_debug &
++			(KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
++			return false;
++		/* fall through */
++	case DE_VECTOR:
++	case OF_VECTOR:
++	case BR_VECTOR:
++	case UD_VECTOR:
++	case DF_VECTOR:
++	case SS_VECTOR:
++	case GP_VECTOR:
++	case MF_VECTOR:
++		return true;
++	break;
++	}
++	return false;
++}
++
++static int handle_rmode_exception(struct kvm_vcpu *vcpu,
++				  int vec, u32 err_code)
++{
++	/*
++	 * Instruction with address size override prefix opcode 0x67
++	 * Cause the #SS fault with 0 error code in VM86 mode.
++	 */
++	if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
++		if (kvm_emulate_instruction(vcpu, 0)) {
++			if (vcpu->arch.halt_request) {
++				vcpu->arch.halt_request = 0;
++				return kvm_vcpu_halt(vcpu);
++			}
++			return 1;
++		}
++		return 0;
++	}
++
++	/*
++	 * Forward all other exceptions that are valid in real mode.
++	 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
++	 *        the required debugging infrastructure rework.
++	 */
++	kvm_queue_exception(vcpu, vec);
++	return 1;
++}
++
++/*
++ * Trigger machine check on the host. We assume all the MSRs are already set up
++ * by the CPU and that we still run on the same CPU as the MCE occurred on.
++ * We pass a fake environment to the machine check handler because we want
++ * the guest to be always treated like user space, no matter what context
++ * it used internally.
++ */
++static void kvm_machine_check(void)
++{
++#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
++	struct pt_regs regs = {
++		.cs = 3, /* Fake ring 3 no matter what the guest ran on */
++		.flags = X86_EFLAGS_IF,
++	};
++
++	do_machine_check(&regs, 0);
++#endif
++}
++
++static int handle_machine_check(struct kvm_vcpu *vcpu)
++{
++	/* handled by vmx_vcpu_run() */
++	return 1;
++}
++
++static int handle_exception_nmi(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	struct kvm_run *kvm_run = vcpu->run;
++	u32 intr_info, ex_no, error_code;
++	unsigned long cr2, rip, dr6;
++	u32 vect_info;
++
++	vect_info = vmx->idt_vectoring_info;
++	intr_info = vmx->exit_intr_info;
++
++	if (is_machine_check(intr_info) || is_nmi(intr_info))
++		return 1; /* handled by handle_exception_nmi_irqoff() */
++
++	if (is_invalid_opcode(intr_info))
++		return handle_ud(vcpu);
++
++	error_code = 0;
++	if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
++		error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
++
++	if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
++		WARN_ON_ONCE(!enable_vmware_backdoor);
++
++		/*
++		 * VMware backdoor emulation on #GP interception only handles
++		 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
++		 * error code on #GP.
++		 */
++		if (error_code) {
++			kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
++			return 1;
++		}
++		return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
++	}
++
++	/*
++	 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
++	 * MMIO, it is better to report an internal error.
++	 * See the comments in vmx_handle_exit.
++	 */
++	if ((vect_info & VECTORING_INFO_VALID_MASK) &&
++	    !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
++		vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
++		vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
++		vcpu->run->internal.ndata = 3;
++		vcpu->run->internal.data[0] = vect_info;
++		vcpu->run->internal.data[1] = intr_info;
++		vcpu->run->internal.data[2] = error_code;
++		return 0;
++	}
++
++	if (is_page_fault(intr_info)) {
++		cr2 = vmcs_readl(EXIT_QUALIFICATION);
++		/* EPT won't cause page fault directly */
++		WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
++		return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
++	}
++
++	ex_no = intr_info & INTR_INFO_VECTOR_MASK;
++
++	if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
++		return handle_rmode_exception(vcpu, ex_no, error_code);
++
++	switch (ex_no) {
++	case AC_VECTOR:
++		kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
++		return 1;
++	case DB_VECTOR:
++		dr6 = vmcs_readl(EXIT_QUALIFICATION);
++		if (!(vcpu->guest_debug &
++		      (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
++			vcpu->arch.dr6 &= ~DR_TRAP_BITS;
++			vcpu->arch.dr6 |= dr6 | DR6_RTM;
++			if (is_icebp(intr_info))
++				WARN_ON(!skip_emulated_instruction(vcpu));
++
++			kvm_queue_exception(vcpu, DB_VECTOR);
++			return 1;
++		}
++		kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
++		kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
++		/* fall through */
++	case BP_VECTOR:
++		/*
++		 * Update instruction length as we may reinject #BP from
++		 * user space while in guest debugging mode. Reading it for
++		 * #DB as well causes no harm, it is not used in that case.
++		 */
++		vmx->vcpu.arch.event_exit_inst_len =
++			vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
++		kvm_run->exit_reason = KVM_EXIT_DEBUG;
++		rip = kvm_rip_read(vcpu);
++		kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
++		kvm_run->debug.arch.exception = ex_no;
++		break;
++	default:
++		kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
++		kvm_run->ex.exception = ex_no;
++		kvm_run->ex.error_code = error_code;
++		break;
++	}
++	return 0;
++}
++
++static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
++{
++	++vcpu->stat.irq_exits;
++	return 1;
++}
++
++static int handle_triple_fault(struct kvm_vcpu *vcpu)
++{
++	vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
++	vcpu->mmio_needed = 0;
++	return 0;
++}
++
++static int handle_io(struct kvm_vcpu *vcpu)
++{
++	unsigned long exit_qualification;
++	int size, in, string;
++	unsigned port;
++
++	exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
++	string = (exit_qualification & 16) != 0;
++
++	++vcpu->stat.io_exits;
++
++	if (string)
++		return kvm_emulate_instruction(vcpu, 0);
++
++	port = exit_qualification >> 16;
++	size = (exit_qualification & 7) + 1;
++	in = (exit_qualification & 8) != 0;
++
++	return kvm_fast_pio(vcpu, size, port, in);
++}
++
++static void
++vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
++{
++	/*
++	 * Patch in the VMCALL instruction:
++	 */
++	hypercall[0] = 0x0f;
++	hypercall[1] = 0x01;
++	hypercall[2] = 0xc1;
++}
++
++/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
++static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
++{
++	if (is_guest_mode(vcpu)) {
++		struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
++		unsigned long orig_val = val;
++
++		/*
++		 * We get here when L2 changed cr0 in a way that did not change
++		 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
++		 * but did change L0 shadowed bits. So we first calculate the
++		 * effective cr0 value that L1 would like to write into the
++		 * hardware. It consists of the L2-owned bits from the new
++		 * value combined with the L1-owned bits from L1's guest_cr0.
++		 */
++		val = (val & ~vmcs12->cr0_guest_host_mask) |
++			(vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
++
++		if (!nested_guest_cr0_valid(vcpu, val))
++			return 1;
++
++		if (kvm_set_cr0(vcpu, val))
++			return 1;
++		vmcs_writel(CR0_READ_SHADOW, orig_val);
++		return 0;
++	} else {
++		if (to_vmx(vcpu)->nested.vmxon &&
++		    !nested_host_cr0_valid(vcpu, val))
++			return 1;
++
++		return kvm_set_cr0(vcpu, val);
++	}
++}
++
++static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
++{
++	if (is_guest_mode(vcpu)) {
++		struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
++		unsigned long orig_val = val;
++
++		/* analogously to handle_set_cr0 */
++		val = (val & ~vmcs12->cr4_guest_host_mask) |
++			(vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
++		if (kvm_set_cr4(vcpu, val))
++			return 1;
++		vmcs_writel(CR4_READ_SHADOW, orig_val);
++		return 0;
++	} else
++		return kvm_set_cr4(vcpu, val);
++}
++
++static int handle_desc(struct kvm_vcpu *vcpu)
++{
++	WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
++	return kvm_emulate_instruction(vcpu, 0);
++}
++
++static int handle_cr(struct kvm_vcpu *vcpu)
++{
++	unsigned long exit_qualification, val;
++	int cr;
++	int reg;
++	int err;
++	int ret;
++
++	exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
++	cr = exit_qualification & 15;
++	reg = (exit_qualification >> 8) & 15;
++	switch ((exit_qualification >> 4) & 3) {
++	case 0: /* mov to cr */
++		val = kvm_register_readl(vcpu, reg);
++		trace_kvm_cr_write(cr, val);
++		switch (cr) {
++		case 0:
++			err = handle_set_cr0(vcpu, val);
++			return kvm_complete_insn_gp(vcpu, err);
++		case 3:
++			WARN_ON_ONCE(enable_unrestricted_guest);
++			err = kvm_set_cr3(vcpu, val);
++			return kvm_complete_insn_gp(vcpu, err);
++		case 4:
++			err = handle_set_cr4(vcpu, val);
++			return kvm_complete_insn_gp(vcpu, err);
++		case 8: {
++				u8 cr8_prev = kvm_get_cr8(vcpu);
++				u8 cr8 = (u8)val;
++				err = kvm_set_cr8(vcpu, cr8);
++				ret = kvm_complete_insn_gp(vcpu, err);
++				if (lapic_in_kernel(vcpu))
++					return ret;
++				if (cr8_prev <= cr8)
++					return ret;
++				/*
++				 * TODO: we might be squashing a
++				 * KVM_GUESTDBG_SINGLESTEP-triggered
++				 * KVM_EXIT_DEBUG here.
++				 */
++				vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
++				return 0;
++			}
++		}
++		break;
++	case 2: /* clts */
++		WARN_ONCE(1, "Guest should always own CR0.TS");
++		vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
++		trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
++		return kvm_skip_emulated_instruction(vcpu);
++	case 1: /*mov from cr*/
++		switch (cr) {
++		case 3:
++			WARN_ON_ONCE(enable_unrestricted_guest);
++			val = kvm_read_cr3(vcpu);
++			kvm_register_write(vcpu, reg, val);
++			trace_kvm_cr_read(cr, val);
++			return kvm_skip_emulated_instruction(vcpu);
++		case 8:
++			val = kvm_get_cr8(vcpu);
++			kvm_register_write(vcpu, reg, val);
++			trace_kvm_cr_read(cr, val);
++			return kvm_skip_emulated_instruction(vcpu);
++		}
++		break;
++	case 3: /* lmsw */
++		val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
++		trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
++		kvm_lmsw(vcpu, val);
++
++		return kvm_skip_emulated_instruction(vcpu);
++	default:
++		break;
++	}
++	vcpu->run->exit_reason = 0;
++	vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
++	       (int)(exit_qualification >> 4) & 3, cr);
++	return 0;
++}
++
++static int handle_dr(struct kvm_vcpu *vcpu)
++{
++	unsigned long exit_qualification;
++	int dr, dr7, reg;
++
++	exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
++	dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
++
++	/* First, if DR does not exist, trigger UD */
++	if (!kvm_require_dr(vcpu, dr))
++		return 1;
++
++	/* Do not handle if the CPL > 0, will trigger GP on re-entry */
++	if (!kvm_require_cpl(vcpu, 0))
++		return 1;
++	dr7 = vmcs_readl(GUEST_DR7);
++	if (dr7 & DR7_GD) {
++		/*
++		 * As the vm-exit takes precedence over the debug trap, we
++		 * need to emulate the latter, either for the host or the
++		 * guest debugging itself.
++		 */
++		if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
++			vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
++			vcpu->run->debug.arch.dr7 = dr7;
++			vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
++			vcpu->run->debug.arch.exception = DB_VECTOR;
++			vcpu->run->exit_reason = KVM_EXIT_DEBUG;
++			return 0;
++		} else {
++			vcpu->arch.dr6 &= ~DR_TRAP_BITS;
++			vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
++			kvm_queue_exception(vcpu, DB_VECTOR);
++			return 1;
++		}
++	}
++
++	if (vcpu->guest_debug == 0) {
++		exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
++
++		/*
++		 * No more DR vmexits; force a reload of the debug registers
++		 * and reenter on this instruction.  The next vmexit will
++		 * retrieve the full state of the debug registers.
++		 */
++		vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
++		return 1;
++	}
++
++	reg = DEBUG_REG_ACCESS_REG(exit_qualification);
++	if (exit_qualification & TYPE_MOV_FROM_DR) {
++		unsigned long val;
++
++		if (kvm_get_dr(vcpu, dr, &val))
++			return 1;
++		kvm_register_write(vcpu, reg, val);
++	} else
++		if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
++			return 1;
++
++	return kvm_skip_emulated_instruction(vcpu);
++}
++
++static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
++{
++	return vcpu->arch.dr6;
++}
++
++static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
++{
++}
++
++static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
++{
++	get_debugreg(vcpu->arch.db[0], 0);
++	get_debugreg(vcpu->arch.db[1], 1);
++	get_debugreg(vcpu->arch.db[2], 2);
++	get_debugreg(vcpu->arch.db[3], 3);
++	get_debugreg(vcpu->arch.dr6, 6);
++	vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
++
++	vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
++	exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
++}
++
++static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
++{
++	vmcs_writel(GUEST_DR7, val);
++}
++
++static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
++{
++	kvm_apic_update_ppr(vcpu);
++	return 1;
++}
++
++static int handle_interrupt_window(struct kvm_vcpu *vcpu)
++{
++	exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
++
++	kvm_make_request(KVM_REQ_EVENT, vcpu);
++
++	++vcpu->stat.irq_window_exits;
++	return 1;
++}
++
++static int handle_vmcall(struct kvm_vcpu *vcpu)
++{
++	return kvm_emulate_hypercall(vcpu);
++}
++
++static int handle_invd(struct kvm_vcpu *vcpu)
++{
++	return kvm_emulate_instruction(vcpu, 0);
++}
++
++static int handle_invlpg(struct kvm_vcpu *vcpu)
++{
++	unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
++
++	kvm_mmu_invlpg(vcpu, exit_qualification);
++	return kvm_skip_emulated_instruction(vcpu);
++}
++
++static int handle_rdpmc(struct kvm_vcpu *vcpu)
++{
++	int err;
++
++	err = kvm_rdpmc(vcpu);
++	return kvm_complete_insn_gp(vcpu, err);
++}
++
++static int handle_wbinvd(struct kvm_vcpu *vcpu)
++{
++	return kvm_emulate_wbinvd(vcpu);
++}
++
++static int handle_xsetbv(struct kvm_vcpu *vcpu)
++{
++	u64 new_bv = kvm_read_edx_eax(vcpu);
++	u32 index = kvm_rcx_read(vcpu);
++
++	if (kvm_set_xcr(vcpu, index, new_bv) == 0)
++		return kvm_skip_emulated_instruction(vcpu);
++	return 1;
++}
++
++static int handle_apic_access(struct kvm_vcpu *vcpu)
++{
++	if (likely(fasteoi)) {
++		unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
++		int access_type, offset;
++
++		access_type = exit_qualification & APIC_ACCESS_TYPE;
++		offset = exit_qualification & APIC_ACCESS_OFFSET;
++		/*
++		 * Sane guest uses MOV to write EOI, with written value
++		 * not cared. So make a short-circuit here by avoiding
++		 * heavy instruction emulation.
++		 */
++		if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
++		    (offset == APIC_EOI)) {
++			kvm_lapic_set_eoi(vcpu);
++			return kvm_skip_emulated_instruction(vcpu);
++		}
++	}
++	return kvm_emulate_instruction(vcpu, 0);
++}
++
++static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
++{
++	unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
++	int vector = exit_qualification & 0xff;
++
++	/* EOI-induced VM exit is trap-like and thus no need to adjust IP */
++	kvm_apic_set_eoi_accelerated(vcpu, vector);
++	return 1;
++}
++
++static int handle_apic_write(struct kvm_vcpu *vcpu)
++{
++	unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
++	u32 offset = exit_qualification & 0xfff;
++
++	/* APIC-write VM exit is trap-like and thus no need to adjust IP */
++	kvm_apic_write_nodecode(vcpu, offset);
++	return 1;
++}
++
++static int handle_task_switch(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	unsigned long exit_qualification;
++	bool has_error_code = false;
++	u32 error_code = 0;
++	u16 tss_selector;
++	int reason, type, idt_v, idt_index;
++
++	idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
++	idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
++	type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
++
++	exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
++
++	reason = (u32)exit_qualification >> 30;
++	if (reason == TASK_SWITCH_GATE && idt_v) {
++		switch (type) {
++		case INTR_TYPE_NMI_INTR:
++			vcpu->arch.nmi_injected = false;
++			vmx_set_nmi_mask(vcpu, true);
++			break;
++		case INTR_TYPE_EXT_INTR:
++		case INTR_TYPE_SOFT_INTR:
++			kvm_clear_interrupt_queue(vcpu);
++			break;
++		case INTR_TYPE_HARD_EXCEPTION:
++			if (vmx->idt_vectoring_info &
++			    VECTORING_INFO_DELIVER_CODE_MASK) {
++				has_error_code = true;
++				error_code =
++					vmcs_read32(IDT_VECTORING_ERROR_CODE);
++			}
++			/* fall through */
++		case INTR_TYPE_SOFT_EXCEPTION:
++			kvm_clear_exception_queue(vcpu);
++			break;
++		default:
++			break;
++		}
++	}
++	tss_selector = exit_qualification;
++
++	if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
++		       type != INTR_TYPE_EXT_INTR &&
++		       type != INTR_TYPE_NMI_INTR))
++		WARN_ON(!skip_emulated_instruction(vcpu));
++
++	/*
++	 * TODO: What about debug traps on tss switch?
++	 *       Are we supposed to inject them and update dr6?
++	 */
++	return kvm_task_switch(vcpu, tss_selector,
++			       type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
++			       reason, has_error_code, error_code);
++}
++
++static int handle_ept_violation(struct kvm_vcpu *vcpu)
++{
++	unsigned long exit_qualification;
++	gpa_t gpa;
++	u64 error_code;
++
++	exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
++
++	/*
++	 * EPT violation happened while executing iret from NMI,
++	 * "blocked by NMI" bit has to be set before next VM entry.
++	 * There are errata that may cause this bit to not be set:
++	 * AAK134, BY25.
++	 */
++	if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
++			enable_vnmi &&
++			(exit_qualification & INTR_INFO_UNBLOCK_NMI))
++		vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
++
++	gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
++	trace_kvm_page_fault(gpa, exit_qualification);
++
++	/* Is it a read fault? */
++	error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
++		     ? PFERR_USER_MASK : 0;
++	/* Is it a write fault? */
++	error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
++		      ? PFERR_WRITE_MASK : 0;
++	/* Is it a fetch fault? */
++	error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
++		      ? PFERR_FETCH_MASK : 0;
++	/* ept page table entry is present? */
++	error_code |= (exit_qualification &
++		       (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
++			EPT_VIOLATION_EXECUTABLE))
++		      ? PFERR_PRESENT_MASK : 0;
++
++	error_code |= (exit_qualification & 0x100) != 0 ?
++	       PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
++
++	vcpu->arch.exit_qualification = exit_qualification;
++	return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
++}
++
++static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
++{
++	gpa_t gpa;
++
++	/*
++	 * A nested guest cannot optimize MMIO vmexits, because we have an
++	 * nGPA here instead of the required GPA.
++	 */
++	gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
++	if (!is_guest_mode(vcpu) &&
++	    !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
++		trace_kvm_fast_mmio(gpa);
++		return kvm_skip_emulated_instruction(vcpu);
++	}
++
++	return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
++}
++
++static int handle_nmi_window(struct kvm_vcpu *vcpu)
++{
++	WARN_ON_ONCE(!enable_vnmi);
++	exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
++	++vcpu->stat.nmi_window_exits;
++	kvm_make_request(KVM_REQ_EVENT, vcpu);
++
++	return 1;
++}
++
++static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	bool intr_window_requested;
++	unsigned count = 130;
++
++	/*
++	 * We should never reach the point where we are emulating L2
++	 * due to invalid guest state as that means we incorrectly
++	 * allowed a nested VMEntry with an invalid vmcs12.
++	 */
++	WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
++
++	intr_window_requested = exec_controls_get(vmx) &
++				CPU_BASED_INTR_WINDOW_EXITING;
++
++	while (vmx->emulation_required && count-- != 0) {
++		if (intr_window_requested && vmx_interrupt_allowed(vcpu))
++			return handle_interrupt_window(&vmx->vcpu);
++
++		if (kvm_test_request(KVM_REQ_EVENT, vcpu))
++			return 1;
++
++		if (!kvm_emulate_instruction(vcpu, 0))
++			return 0;
++
++		if (vmx->emulation_required && !vmx->rmode.vm86_active &&
++		    vcpu->arch.exception.pending) {
++			vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
++			vcpu->run->internal.suberror =
++						KVM_INTERNAL_ERROR_EMULATION;
++			vcpu->run->internal.ndata = 0;
++			return 0;
++		}
++
++		if (vcpu->arch.halt_request) {
++			vcpu->arch.halt_request = 0;
++			return kvm_vcpu_halt(vcpu);
++		}
++
++		/*
++		 * Note, return 1 and not 0, vcpu_run() is responsible for
++		 * morphing the pending signal into the proper return code.
++		 */
++		if (signal_pending(current))
++			return 1;
++
++		if (need_resched())
++			schedule();
++	}
++
++	return 1;
++}
++
++static void grow_ple_window(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	unsigned int old = vmx->ple_window;
++
++	vmx->ple_window = __grow_ple_window(old, ple_window,
++					    ple_window_grow,
++					    ple_window_max);
++
++	if (vmx->ple_window != old) {
++		vmx->ple_window_dirty = true;
++		trace_kvm_ple_window_update(vcpu->vcpu_id,
++					    vmx->ple_window, old);
++	}
++}
++
++static void shrink_ple_window(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	unsigned int old = vmx->ple_window;
++
++	vmx->ple_window = __shrink_ple_window(old, ple_window,
++					      ple_window_shrink,
++					      ple_window);
++
++	if (vmx->ple_window != old) {
++		vmx->ple_window_dirty = true;
++		trace_kvm_ple_window_update(vcpu->vcpu_id,
++					    vmx->ple_window, old);
++	}
++}
++
++/*
++ * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
++ */
++static void wakeup_handler(void)
++{
++	struct kvm_vcpu *vcpu;
++	int cpu = smp_processor_id();
++
++	spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
++	list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
++			blocked_vcpu_list) {
++		struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
++
++		if (pi_test_on(pi_desc) == 1)
++			kvm_vcpu_kick(vcpu);
++	}
++	spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
++}
++
++static void vmx_enable_tdp(void)
++{
++	kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
++		enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
++		enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
++		0ull, VMX_EPT_EXECUTABLE_MASK,
++		cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
++		VMX_EPT_RWX_MASK, 0ull);
++
++	ept_set_mmio_spte_mask();
++	kvm_enable_tdp();
++}
++
++/*
++ * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
++ * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
++ */
++static int handle_pause(struct kvm_vcpu *vcpu)
++{
++	if (!kvm_pause_in_guest(vcpu->kvm))
++		grow_ple_window(vcpu);
++
++	/*
++	 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
++	 * VM-execution control is ignored if CPL > 0. OTOH, KVM
++	 * never set PAUSE_EXITING and just set PLE if supported,
++	 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
++	 */
++	kvm_vcpu_on_spin(vcpu, true);
++	return kvm_skip_emulated_instruction(vcpu);
++}
++
++static int handle_nop(struct kvm_vcpu *vcpu)
++{
++	return kvm_skip_emulated_instruction(vcpu);
++}
++
++static int handle_mwait(struct kvm_vcpu *vcpu)
++{
++	printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
++	return handle_nop(vcpu);
++}
++
++static int handle_invalid_op(struct kvm_vcpu *vcpu)
++{
++	kvm_queue_exception(vcpu, UD_VECTOR);
++	return 1;
++}
++
++static int handle_monitor_trap(struct kvm_vcpu *vcpu)
++{
++	return 1;
++}
++
++static int handle_monitor(struct kvm_vcpu *vcpu)
++{
++	printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
++	return handle_nop(vcpu);
++}
++
++static int handle_invpcid(struct kvm_vcpu *vcpu)
++{
++	u32 vmx_instruction_info;
++	unsigned long type;
++	bool pcid_enabled;
++	gva_t gva;
++	struct x86_exception e;
++	unsigned i;
++	unsigned long roots_to_free = 0;
++	struct {
++		u64 pcid;
++		u64 gla;
++	} operand;
++
++	if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
++		kvm_queue_exception(vcpu, UD_VECTOR);
++		return 1;
++	}
++
++	vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
++	type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
++
++	if (type > 3) {
++		kvm_inject_gp(vcpu, 0);
++		return 1;
++	}
++
++	/* According to the Intel instruction reference, the memory operand
++	 * is read even if it isn't needed (e.g., for type==all)
++	 */
++	if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
++				vmx_instruction_info, false,
++				sizeof(operand), &gva))
++		return 1;
++
++	if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
++		kvm_inject_page_fault(vcpu, &e);
++		return 1;
++	}
++
++	if (operand.pcid >> 12 != 0) {
++		kvm_inject_gp(vcpu, 0);
++		return 1;
++	}
++
++	pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
++
++	switch (type) {
++	case INVPCID_TYPE_INDIV_ADDR:
++		if ((!pcid_enabled && (operand.pcid != 0)) ||
++		    is_noncanonical_address(operand.gla, vcpu)) {
++			kvm_inject_gp(vcpu, 0);
++			return 1;
++		}
++		kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
++		return kvm_skip_emulated_instruction(vcpu);
++
++	case INVPCID_TYPE_SINGLE_CTXT:
++		if (!pcid_enabled && (operand.pcid != 0)) {
++			kvm_inject_gp(vcpu, 0);
++			return 1;
++		}
++
++		if (kvm_get_active_pcid(vcpu) == operand.pcid) {
++			kvm_mmu_sync_roots(vcpu);
++			kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
++		}
++
++		for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
++			if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
++			    == operand.pcid)
++				roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
++
++		kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
++		/*
++		 * If neither the current cr3 nor any of the prev_roots use the
++		 * given PCID, then nothing needs to be done here because a
++		 * resync will happen anyway before switching to any other CR3.
++		 */
++
++		return kvm_skip_emulated_instruction(vcpu);
++
++	case INVPCID_TYPE_ALL_NON_GLOBAL:
++		/*
++		 * Currently, KVM doesn't mark global entries in the shadow
++		 * page tables, so a non-global flush just degenerates to a
++		 * global flush. If needed, we could optimize this later by
++		 * keeping track of global entries in shadow page tables.
++		 */
++
++		/* fall-through */
++	case INVPCID_TYPE_ALL_INCL_GLOBAL:
++		kvm_mmu_unload(vcpu);
++		return kvm_skip_emulated_instruction(vcpu);
++
++	default:
++		BUG(); /* We have already checked above that type <= 3 */
++	}
++}
++
++static int handle_pml_full(struct kvm_vcpu *vcpu)
++{
++	unsigned long exit_qualification;
++
++	trace_kvm_pml_full(vcpu->vcpu_id);
++
++	exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
++
++	/*
++	 * PML buffer FULL happened while executing iret from NMI,
++	 * "blocked by NMI" bit has to be set before next VM entry.
++	 */
++	if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
++			enable_vnmi &&
++			(exit_qualification & INTR_INFO_UNBLOCK_NMI))
++		vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
++				GUEST_INTR_STATE_NMI);
++
++	/*
++	 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
++	 * here.., and there's no userspace involvement needed for PML.
++	 */
++	return 1;
++}
++
++static int handle_preemption_timer(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++
++	if (!vmx->req_immediate_exit &&
++	    !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
++		kvm_lapic_expired_hv_timer(vcpu);
++
++	return 1;
++}
++
++/*
++ * When nested=0, all VMX instruction VM Exits filter here.  The handlers
++ * are overwritten by nested_vmx_setup() when nested=1.
++ */
++static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
++{
++	kvm_queue_exception(vcpu, UD_VECTOR);
++	return 1;
++}
++
++static int handle_encls(struct kvm_vcpu *vcpu)
++{
++	/*
++	 * SGX virtualization is not yet supported.  There is no software
++	 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
++	 * to prevent the guest from executing ENCLS.
++	 */
++	kvm_queue_exception(vcpu, UD_VECTOR);
++	return 1;
++}
++
++/*
++ * The exit handlers return 1 if the exit was handled fully and guest execution
++ * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
++ * to be done to userspace and return 0.
++ */
++static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
++	[EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
++	[EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
++	[EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
++	[EXIT_REASON_NMI_WINDOW]	      = handle_nmi_window,
++	[EXIT_REASON_IO_INSTRUCTION]          = handle_io,
++	[EXIT_REASON_CR_ACCESS]               = handle_cr,
++	[EXIT_REASON_DR_ACCESS]               = handle_dr,
++	[EXIT_REASON_CPUID]                   = kvm_emulate_cpuid,
++	[EXIT_REASON_MSR_READ]                = kvm_emulate_rdmsr,
++	[EXIT_REASON_MSR_WRITE]               = kvm_emulate_wrmsr,
++	[EXIT_REASON_INTERRUPT_WINDOW]        = handle_interrupt_window,
++	[EXIT_REASON_HLT]                     = kvm_emulate_halt,
++	[EXIT_REASON_INVD]		      = handle_invd,
++	[EXIT_REASON_INVLPG]		      = handle_invlpg,
++	[EXIT_REASON_RDPMC]                   = handle_rdpmc,
++	[EXIT_REASON_VMCALL]                  = handle_vmcall,
++	[EXIT_REASON_VMCLEAR]		      = handle_vmx_instruction,
++	[EXIT_REASON_VMLAUNCH]		      = handle_vmx_instruction,
++	[EXIT_REASON_VMPTRLD]		      = handle_vmx_instruction,
++	[EXIT_REASON_VMPTRST]		      = handle_vmx_instruction,
++	[EXIT_REASON_VMREAD]		      = handle_vmx_instruction,
++	[EXIT_REASON_VMRESUME]		      = handle_vmx_instruction,
++	[EXIT_REASON_VMWRITE]		      = handle_vmx_instruction,
++	[EXIT_REASON_VMOFF]		      = handle_vmx_instruction,
++	[EXIT_REASON_VMON]		      = handle_vmx_instruction,
++	[EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
++	[EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
++	[EXIT_REASON_APIC_WRITE]              = handle_apic_write,
++	[EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
++	[EXIT_REASON_WBINVD]                  = handle_wbinvd,
++	[EXIT_REASON_XSETBV]                  = handle_xsetbv,
++	[EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
++	[EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
++	[EXIT_REASON_GDTR_IDTR]		      = handle_desc,
++	[EXIT_REASON_LDTR_TR]		      = handle_desc,
++	[EXIT_REASON_EPT_VIOLATION]	      = handle_ept_violation,
++	[EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
++	[EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
++	[EXIT_REASON_MWAIT_INSTRUCTION]	      = handle_mwait,
++	[EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
++	[EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
++	[EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
++	[EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
++	[EXIT_REASON_RDRAND]                  = handle_invalid_op,
++	[EXIT_REASON_RDSEED]                  = handle_invalid_op,
++	[EXIT_REASON_PML_FULL]		      = handle_pml_full,
++	[EXIT_REASON_INVPCID]                 = handle_invpcid,
++	[EXIT_REASON_VMFUNC]		      = handle_vmx_instruction,
++	[EXIT_REASON_PREEMPTION_TIMER]	      = handle_preemption_timer,
++	[EXIT_REASON_ENCLS]		      = handle_encls,
++};
++
++static const int kvm_vmx_max_exit_handlers =
++	ARRAY_SIZE(kvm_vmx_exit_handlers);
++
++static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
++{
++	*info1 = vmcs_readl(EXIT_QUALIFICATION);
++	*info2 = vmcs_read32(VM_EXIT_INTR_INFO);
++}
++
++static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
++{
++	if (vmx->pml_pg) {
++		__free_page(vmx->pml_pg);
++		vmx->pml_pg = NULL;
++	}
++}
++
++static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	u64 *pml_buf;
++	u16 pml_idx;
++
++	pml_idx = vmcs_read16(GUEST_PML_INDEX);
++
++	/* Do nothing if PML buffer is empty */
++	if (pml_idx == (PML_ENTITY_NUM - 1))
++		return;
++
++	/* PML index always points to next available PML buffer entity */
++	if (pml_idx >= PML_ENTITY_NUM)
++		pml_idx = 0;
++	else
++		pml_idx++;
++
++	pml_buf = page_address(vmx->pml_pg);
++	for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
++		u64 gpa;
++
++		gpa = pml_buf[pml_idx];
++		WARN_ON(gpa & (PAGE_SIZE - 1));
++		kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
++	}
++
++	/* reset PML index */
++	vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
++}
++
++/*
++ * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
++ * Called before reporting dirty_bitmap to userspace.
++ */
++static void kvm_flush_pml_buffers(struct kvm *kvm)
++{
++	int i;
++	struct kvm_vcpu *vcpu;
++	/*
++	 * We only need to kick vcpu out of guest mode here, as PML buffer
++	 * is flushed at beginning of all VMEXITs, and it's obvious that only
++	 * vcpus running in guest are possible to have unflushed GPAs in PML
++	 * buffer.
++	 */
++	kvm_for_each_vcpu(i, vcpu, kvm)
++		kvm_vcpu_kick(vcpu);
++}
++
++static void vmx_dump_sel(char *name, uint32_t sel)
++{
++	pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
++	       name, vmcs_read16(sel),
++	       vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
++	       vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
++	       vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
++}
++
++static void vmx_dump_dtsel(char *name, uint32_t limit)
++{
++	pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
++	       name, vmcs_read32(limit),
++	       vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
++}
++
++void dump_vmcs(void)
++{
++	u32 vmentry_ctl, vmexit_ctl;
++	u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
++	unsigned long cr4;
++	u64 efer;
++	int i, n;
++
++	if (!dump_invalid_vmcs) {
++		pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
++		return;
++	}
++
++	vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
++	vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
++	cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
++	pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
++	cr4 = vmcs_readl(GUEST_CR4);
++	efer = vmcs_read64(GUEST_IA32_EFER);
++	secondary_exec_control = 0;
++	if (cpu_has_secondary_exec_ctrls())
++		secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
++
++	pr_err("*** Guest State ***\n");
++	pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
++	       vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
++	       vmcs_readl(CR0_GUEST_HOST_MASK));
++	pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
++	       cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
++	pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
++	if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
++	    (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
++	{
++		pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
++		       vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
++		pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
++		       vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
++	}
++	pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
++	       vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
++	pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
++	       vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
++	pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
++	       vmcs_readl(GUEST_SYSENTER_ESP),
++	       vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
++	vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
++	vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
++	vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
++	vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
++	vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
++	vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
++	vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
++	vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
++	vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
++	vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
++	if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
++	    (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
++		pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
++		       efer, vmcs_read64(GUEST_IA32_PAT));
++	pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
++	       vmcs_read64(GUEST_IA32_DEBUGCTL),
++	       vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
++	if (cpu_has_load_perf_global_ctrl() &&
++	    vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
++		pr_err("PerfGlobCtl = 0x%016llx\n",
++		       vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
++	if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
++		pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
++	pr_err("Interruptibility = %08x  ActivityState = %08x\n",
++	       vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
++	       vmcs_read32(GUEST_ACTIVITY_STATE));
++	if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
++		pr_err("InterruptStatus = %04x\n",
++		       vmcs_read16(GUEST_INTR_STATUS));
++
++	pr_err("*** Host State ***\n");
++	pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
++	       vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
++	pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
++	       vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
++	       vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
++	       vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
++	       vmcs_read16(HOST_TR_SELECTOR));
++	pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
++	       vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
++	       vmcs_readl(HOST_TR_BASE));
++	pr_err("GDTBase=%016lx IDTBase=%016lx\n",
++	       vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
++	pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
++	       vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
++	       vmcs_readl(HOST_CR4));
++	pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
++	       vmcs_readl(HOST_IA32_SYSENTER_ESP),
++	       vmcs_read32(HOST_IA32_SYSENTER_CS),
++	       vmcs_readl(HOST_IA32_SYSENTER_EIP));
++	if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
++		pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
++		       vmcs_read64(HOST_IA32_EFER),
++		       vmcs_read64(HOST_IA32_PAT));
++	if (cpu_has_load_perf_global_ctrl() &&
++	    vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
++		pr_err("PerfGlobCtl = 0x%016llx\n",
++		       vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
++
++	pr_err("*** Control State ***\n");
++	pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
++	       pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
++	pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
++	pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
++	       vmcs_read32(EXCEPTION_BITMAP),
++	       vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
++	       vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
++	pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
++	       vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
++	       vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
++	       vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
++	pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
++	       vmcs_read32(VM_EXIT_INTR_INFO),
++	       vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
++	       vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
++	pr_err("        reason=%08x qualification=%016lx\n",
++	       vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
++	pr_err("IDTVectoring: info=%08x errcode=%08x\n",
++	       vmcs_read32(IDT_VECTORING_INFO_FIELD),
++	       vmcs_read32(IDT_VECTORING_ERROR_CODE));
++	pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
++	if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
++		pr_err("TSC Multiplier = 0x%016llx\n",
++		       vmcs_read64(TSC_MULTIPLIER));
++	if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
++		if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
++			u16 status = vmcs_read16(GUEST_INTR_STATUS);
++			pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
++		}
++		pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
++		if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
++			pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
++		pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
++	}
++	if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
++		pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
++	if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
++		pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
++	n = vmcs_read32(CR3_TARGET_COUNT);
++	for (i = 0; i + 1 < n; i += 4)
++		pr_err("CR3 target%u=%016lx target%u=%016lx\n",
++		       i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
++		       i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
++	if (i < n)
++		pr_err("CR3 target%u=%016lx\n",
++		       i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
++	if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
++		pr_err("PLE Gap=%08x Window=%08x\n",
++		       vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
++	if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
++		pr_err("Virtual processor ID = 0x%04x\n",
++		       vmcs_read16(VIRTUAL_PROCESSOR_ID));
++}
++
++/*
++ * The guest has exited.  See if we can fix it or if we need userspace
++ * assistance.
++ */
++static int vmx_handle_exit(struct kvm_vcpu *vcpu,
++	enum exit_fastpath_completion exit_fastpath)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	u32 exit_reason = vmx->exit_reason;
++	u32 vectoring_info = vmx->idt_vectoring_info;
++
++	trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
++
++	/*
++	 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
++	 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
++	 * querying dirty_bitmap, we only need to kick all vcpus out of guest
++	 * mode as if vcpus is in root mode, the PML buffer must has been
++	 * flushed already.
++	 */
++	if (enable_pml)
++		vmx_flush_pml_buffer(vcpu);
++
++	/* If guest state is invalid, start emulating */
++	if (vmx->emulation_required)
++		return handle_invalid_guest_state(vcpu);
++
++	if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
++		return nested_vmx_reflect_vmexit(vcpu, exit_reason);
++
++	if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
++		dump_vmcs();
++		vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
++		vcpu->run->fail_entry.hardware_entry_failure_reason
++			= exit_reason;
++		return 0;
++	}
++
++	if (unlikely(vmx->fail)) {
++		dump_vmcs();
++		vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
++		vcpu->run->fail_entry.hardware_entry_failure_reason
++			= vmcs_read32(VM_INSTRUCTION_ERROR);
++		return 0;
++	}
++
++	/*
++	 * Note:
++	 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
++	 * delivery event since it indicates guest is accessing MMIO.
++	 * The vm-exit can be triggered again after return to guest that
++	 * will cause infinite loop.
++	 */
++	if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
++			(exit_reason != EXIT_REASON_EXCEPTION_NMI &&
++			exit_reason != EXIT_REASON_EPT_VIOLATION &&
++			exit_reason != EXIT_REASON_PML_FULL &&
++			exit_reason != EXIT_REASON_TASK_SWITCH)) {
++		vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
++		vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
++		vcpu->run->internal.ndata = 3;
++		vcpu->run->internal.data[0] = vectoring_info;
++		vcpu->run->internal.data[1] = exit_reason;
++		vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
++		if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
++			vcpu->run->internal.ndata++;
++			vcpu->run->internal.data[3] =
++				vmcs_read64(GUEST_PHYSICAL_ADDRESS);
++		}
++		return 0;
++	}
++
++	if (unlikely(!enable_vnmi &&
++		     vmx->loaded_vmcs->soft_vnmi_blocked)) {
++		if (vmx_interrupt_allowed(vcpu)) {
++			vmx->loaded_vmcs->soft_vnmi_blocked = 0;
++		} else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
++			   vcpu->arch.nmi_pending) {
++			/*
++			 * This CPU don't support us in finding the end of an
++			 * NMI-blocked window if the guest runs with IRQs
++			 * disabled. So we pull the trigger after 1 s of
++			 * futile waiting, but inform the user about this.
++			 */
++			printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
++			       "state on VCPU %d after 1 s timeout\n",
++			       __func__, vcpu->vcpu_id);
++			vmx->loaded_vmcs->soft_vnmi_blocked = 0;
++		}
++	}
++
++	if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
++		kvm_skip_emulated_instruction(vcpu);
++		return 1;
++	} else if (exit_reason < kvm_vmx_max_exit_handlers
++	    && kvm_vmx_exit_handlers[exit_reason]) {
++#ifdef CONFIG_RETPOLINE
++		if (exit_reason == EXIT_REASON_MSR_WRITE)
++			return kvm_emulate_wrmsr(vcpu);
++		else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
++			return handle_preemption_timer(vcpu);
++		else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
++			return handle_interrupt_window(vcpu);
++		else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
++			return handle_external_interrupt(vcpu);
++		else if (exit_reason == EXIT_REASON_HLT)
++			return kvm_emulate_halt(vcpu);
++		else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
++			return handle_ept_misconfig(vcpu);
++#endif
++		return kvm_vmx_exit_handlers[exit_reason](vcpu);
++	} else {
++		vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
++				exit_reason);
++		dump_vmcs();
++		vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
++		vcpu->run->internal.suberror =
++			KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
++		vcpu->run->internal.ndata = 1;
++		vcpu->run->internal.data[0] = exit_reason;
++		return 0;
++	}
++}
++
++/*
++ * Software based L1D cache flush which is used when microcode providing
++ * the cache control MSR is not loaded.
++ *
++ * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
++ * flush it is required to read in 64 KiB because the replacement algorithm
++ * is not exactly LRU. This could be sized at runtime via topology
++ * information but as all relevant affected CPUs have 32KiB L1D cache size
++ * there is no point in doing so.
++ */
++static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
++{
++	int size = PAGE_SIZE << L1D_CACHE_ORDER;
++
++	/*
++	 * This code is only executed when the the flush mode is 'cond' or
++	 * 'always'
++	 */
++	if (static_branch_likely(&vmx_l1d_flush_cond)) {
++		bool flush_l1d;
++
++		/*
++		 * Clear the per-vcpu flush bit, it gets set again
++		 * either from vcpu_run() or from one of the unsafe
++		 * VMEXIT handlers.
++		 */
++		flush_l1d = vcpu->arch.l1tf_flush_l1d;
++		vcpu->arch.l1tf_flush_l1d = false;
++
++		/*
++		 * Clear the per-cpu flush bit, it gets set again from
++		 * the interrupt handlers.
++		 */
++		flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
++		kvm_clear_cpu_l1tf_flush_l1d();
++
++		if (!flush_l1d)
++			return;
++	}
++
++	vcpu->stat.l1d_flush++;
++
++	if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
++		wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
++		return;
++	}
++
++	asm volatile(
++		/* First ensure the pages are in the TLB */
++		"xorl	%%eax, %%eax\n"
++		".Lpopulate_tlb:\n\t"
++		"movzbl	(%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
++		"addl	$4096, %%eax\n\t"
++		"cmpl	%%eax, %[size]\n\t"
++		"jne	.Lpopulate_tlb\n\t"
++		"xorl	%%eax, %%eax\n\t"
++		"cpuid\n\t"
++		/* Now fill the cache */
++		"xorl	%%eax, %%eax\n"
++		".Lfill_cache:\n"
++		"movzbl	(%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
++		"addl	$64, %%eax\n\t"
++		"cmpl	%%eax, %[size]\n\t"
++		"jne	.Lfill_cache\n\t"
++		"lfence\n"
++		:: [flush_pages] "r" (vmx_l1d_flush_pages),
++		    [size] "r" (size)
++		: "eax", "ebx", "ecx", "edx");
++}
++
++static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
++{
++	struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
++	int tpr_threshold;
++
++	if (is_guest_mode(vcpu) &&
++		nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
++		return;
++
++	tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
++	if (is_guest_mode(vcpu))
++		to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
++	else
++		vmcs_write32(TPR_THRESHOLD, tpr_threshold);
++}
++
++void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	u32 sec_exec_control;
++
++	if (!lapic_in_kernel(vcpu))
++		return;
++
++	if (!flexpriority_enabled &&
++	    !cpu_has_vmx_virtualize_x2apic_mode())
++		return;
++
++	/* Postpone execution until vmcs01 is the current VMCS. */
++	if (is_guest_mode(vcpu)) {
++		vmx->nested.change_vmcs01_virtual_apic_mode = true;
++		return;
++	}
++
++	sec_exec_control = secondary_exec_controls_get(vmx);
++	sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
++			      SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
++
++	switch (kvm_get_apic_mode(vcpu)) {
++	case LAPIC_MODE_INVALID:
++		WARN_ONCE(true, "Invalid local APIC state");
++	case LAPIC_MODE_DISABLED:
++		break;
++	case LAPIC_MODE_XAPIC:
++		if (flexpriority_enabled) {
++			sec_exec_control |=
++				SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
++			vmx_flush_tlb(vcpu, true);
++		}
++		break;
++	case LAPIC_MODE_X2APIC:
++		if (cpu_has_vmx_virtualize_x2apic_mode())
++			sec_exec_control |=
++				SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
++		break;
++	}
++	secondary_exec_controls_set(vmx, sec_exec_control);
++
++	vmx_update_msr_bitmap(vcpu);
++}
++
++static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
++{
++	if (!is_guest_mode(vcpu)) {
++		vmcs_write64(APIC_ACCESS_ADDR, hpa);
++		vmx_flush_tlb(vcpu, true);
++	}
++}
++
++static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
++{
++	u16 status;
++	u8 old;
++
++	if (max_isr == -1)
++		max_isr = 0;
++
++	status = vmcs_read16(GUEST_INTR_STATUS);
++	old = status >> 8;
++	if (max_isr != old) {
++		status &= 0xff;
++		status |= max_isr << 8;
++		vmcs_write16(GUEST_INTR_STATUS, status);
++	}
++}
++
++static void vmx_set_rvi(int vector)
++{
++	u16 status;
++	u8 old;
++
++	if (vector == -1)
++		vector = 0;
++
++	status = vmcs_read16(GUEST_INTR_STATUS);
++	old = (u8)status & 0xff;
++	if ((u8)vector != old) {
++		status &= ~0xff;
++		status |= (u8)vector;
++		vmcs_write16(GUEST_INTR_STATUS, status);
++	}
++}
++
++static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
++{
++	/*
++	 * When running L2, updating RVI is only relevant when
++	 * vmcs12 virtual-interrupt-delivery enabled.
++	 * However, it can be enabled only when L1 also
++	 * intercepts external-interrupts and in that case
++	 * we should not update vmcs02 RVI but instead intercept
++	 * interrupt. Therefore, do nothing when running L2.
++	 */
++	if (!is_guest_mode(vcpu))
++		vmx_set_rvi(max_irr);
++}
++
++static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	int max_irr;
++	bool max_irr_updated;
++
++	WARN_ON(!vcpu->arch.apicv_active);
++	if (pi_test_on(&vmx->pi_desc)) {
++		pi_clear_on(&vmx->pi_desc);
++		/*
++		 * IOMMU can write to PID.ON, so the barrier matters even on UP.
++		 * But on x86 this is just a compiler barrier anyway.
++		 */
++		smp_mb__after_atomic();
++		max_irr_updated =
++			kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
++
++		/*
++		 * If we are running L2 and L1 has a new pending interrupt
++		 * which can be injected, we should re-evaluate
++		 * what should be done with this new L1 interrupt.
++		 * If L1 intercepts external-interrupts, we should
++		 * exit from L2 to L1. Otherwise, interrupt should be
++		 * delivered directly to L2.
++		 */
++		if (is_guest_mode(vcpu) && max_irr_updated) {
++			if (nested_exit_on_intr(vcpu))
++				kvm_vcpu_exiting_guest_mode(vcpu);
++			else
++				kvm_make_request(KVM_REQ_EVENT, vcpu);
++		}
++	} else {
++		max_irr = kvm_lapic_find_highest_irr(vcpu);
++	}
++	vmx_hwapic_irr_update(vcpu, max_irr);
++	return max_irr;
++}
++
++static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
++{
++	struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
++
++	return pi_test_on(pi_desc) ||
++		(pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
++}
++
++static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
++{
++	if (!kvm_vcpu_apicv_active(vcpu))
++		return;
++
++	vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
++	vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
++	vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
++	vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
++}
++
++static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++
++	pi_clear_on(&vmx->pi_desc);
++	memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
++}
++
++static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
++{
++	vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
++
++	/* if exit due to PF check for async PF */
++	if (is_page_fault(vmx->exit_intr_info))
++		vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
++
++	/* Handle machine checks before interrupts are enabled */
++	if (is_machine_check(vmx->exit_intr_info))
++		kvm_machine_check();
++
++	/* We need to handle NMIs before interrupts are enabled */
++	if (is_nmi(vmx->exit_intr_info)) {
++		kvm_before_interrupt(&vmx->vcpu);
++		asm("int $2");
++		kvm_after_interrupt(&vmx->vcpu);
++	}
++}
++
++static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
++{
++	unsigned int vector;
++	unsigned long entry;
++#ifdef CONFIG_X86_64
++	unsigned long tmp;
++#endif
++	gate_desc *desc;
++	u32 intr_info;
++
++	intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
++	if (WARN_ONCE(!is_external_intr(intr_info),
++	    "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
++		return;
++
++	vector = intr_info & INTR_INFO_VECTOR_MASK;
++	desc = (gate_desc *)host_idt_base + vector;
++	entry = gate_offset(desc);
++
++	kvm_before_interrupt(vcpu);
++
++	asm volatile(
++#ifdef CONFIG_X86_64
++		"mov %%" _ASM_SP ", %[sp]\n\t"
++		"and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
++		"push $%c[ss]\n\t"
++		"push %[sp]\n\t"
++#endif
++		"pushf\n\t"
++		__ASM_SIZE(push) " $%c[cs]\n\t"
++		CALL_NOSPEC
++		:
++#ifdef CONFIG_X86_64
++		[sp]"=&r"(tmp),
++#endif
++		ASM_CALL_CONSTRAINT
++		:
++		THUNK_TARGET(entry),
++		[ss]"i"(__KERNEL_DS),
++		[cs]"i"(__KERNEL_CS)
++	);
++
++	kvm_after_interrupt(vcpu);
++}
++STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
++
++static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu,
++	enum exit_fastpath_completion *exit_fastpath)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++
++	if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
++		handle_external_interrupt_irqoff(vcpu);
++	else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
++		handle_exception_nmi_irqoff(vmx);
++	else if (!is_guest_mode(vcpu) &&
++		vmx->exit_reason == EXIT_REASON_MSR_WRITE)
++		*exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
++}
++
++static bool vmx_has_emulated_msr(int index)
++{
++	switch (index) {
++	case MSR_IA32_SMBASE:
++		/*
++		 * We cannot do SMM unless we can run the guest in big
++		 * real mode.
++		 */
++		return enable_unrestricted_guest || emulate_invalid_guest_state;
++	case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
++		return nested;
++	case MSR_AMD64_VIRT_SPEC_CTRL:
++		/* This is AMD only.  */
++		return false;
++	default:
++		return true;
++	}
++}
++
++static bool vmx_pt_supported(void)
++{
++	return pt_mode == PT_MODE_HOST_GUEST;
++}
++
++static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
++{
++	u32 exit_intr_info;
++	bool unblock_nmi;
++	u8 vector;
++	bool idtv_info_valid;
++
++	idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
++
++	if (enable_vnmi) {
++		if (vmx->loaded_vmcs->nmi_known_unmasked)
++			return;
++		/*
++		 * Can't use vmx->exit_intr_info since we're not sure what
++		 * the exit reason is.
++		 */
++		exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
++		unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
++		vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
++		/*
++		 * SDM 3: 27.7.1.2 (September 2008)
++		 * Re-set bit "block by NMI" before VM entry if vmexit caused by
++		 * a guest IRET fault.
++		 * SDM 3: 23.2.2 (September 2008)
++		 * Bit 12 is undefined in any of the following cases:
++		 *  If the VM exit sets the valid bit in the IDT-vectoring
++		 *   information field.
++		 *  If the VM exit is due to a double fault.
++		 */
++		if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
++		    vector != DF_VECTOR && !idtv_info_valid)
++			vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
++				      GUEST_INTR_STATE_NMI);
++		else
++			vmx->loaded_vmcs->nmi_known_unmasked =
++				!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
++				  & GUEST_INTR_STATE_NMI);
++	} else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
++		vmx->loaded_vmcs->vnmi_blocked_time +=
++			ktime_to_ns(ktime_sub(ktime_get(),
++					      vmx->loaded_vmcs->entry_time));
++}
++
++static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
++				      u32 idt_vectoring_info,
++				      int instr_len_field,
++				      int error_code_field)
++{
++	u8 vector;
++	int type;
++	bool idtv_info_valid;
++
++	idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
++
++	vcpu->arch.nmi_injected = false;
++	kvm_clear_exception_queue(vcpu);
++	kvm_clear_interrupt_queue(vcpu);
++
++	if (!idtv_info_valid)
++		return;
++
++	kvm_make_request(KVM_REQ_EVENT, vcpu);
++
++	vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
++	type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
++
++	switch (type) {
++	case INTR_TYPE_NMI_INTR:
++		vcpu->arch.nmi_injected = true;
++		/*
++		 * SDM 3: 27.7.1.2 (September 2008)
++		 * Clear bit "block by NMI" before VM entry if a NMI
++		 * delivery faulted.
++		 */
++		vmx_set_nmi_mask(vcpu, false);
++		break;
++	case INTR_TYPE_SOFT_EXCEPTION:
++		vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
++		/* fall through */
++	case INTR_TYPE_HARD_EXCEPTION:
++		if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
++			u32 err = vmcs_read32(error_code_field);
++			kvm_requeue_exception_e(vcpu, vector, err);
++		} else
++			kvm_requeue_exception(vcpu, vector);
++		break;
++	case INTR_TYPE_SOFT_INTR:
++		vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
++		/* fall through */
++	case INTR_TYPE_EXT_INTR:
++		kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
++		break;
++	default:
++		break;
++	}
++}
++
++static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
++{
++	__vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
++				  VM_EXIT_INSTRUCTION_LEN,
++				  IDT_VECTORING_ERROR_CODE);
++}
++
++static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
++{
++	__vmx_complete_interrupts(vcpu,
++				  vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
++				  VM_ENTRY_INSTRUCTION_LEN,
++				  VM_ENTRY_EXCEPTION_ERROR_CODE);
++
++	vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
++}
++
++static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
++{
++	int i, nr_msrs;
++	struct perf_guest_switch_msr *msrs;
++
++	msrs = perf_guest_get_msrs(&nr_msrs);
++
++	if (!msrs)
++		return;
++
++	for (i = 0; i < nr_msrs; i++)
++		if (msrs[i].host == msrs[i].guest)
++			clear_atomic_switch_msr(vmx, msrs[i].msr);
++		else
++			add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
++					msrs[i].host, false);
++}
++
++static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
++{
++	u32 host_umwait_control;
++
++	if (!vmx_has_waitpkg(vmx))
++		return;
++
++	host_umwait_control = get_umwait_control_msr();
++
++	if (vmx->msr_ia32_umwait_control != host_umwait_control)
++		add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
++			vmx->msr_ia32_umwait_control,
++			host_umwait_control, false);
++	else
++		clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
++}
++
++static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	u64 tscl;
++	u32 delta_tsc;
++
++	if (vmx->req_immediate_exit) {
++		vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
++		vmx->loaded_vmcs->hv_timer_soft_disabled = false;
++	} else if (vmx->hv_deadline_tsc != -1) {
++		tscl = rdtsc();
++		if (vmx->hv_deadline_tsc > tscl)
++			/* set_hv_timer ensures the delta fits in 32-bits */
++			delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
++				cpu_preemption_timer_multi);
++		else
++			delta_tsc = 0;
++
++		vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
++		vmx->loaded_vmcs->hv_timer_soft_disabled = false;
++	} else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
++		vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
++		vmx->loaded_vmcs->hv_timer_soft_disabled = true;
++	}
++}
++
++void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
++{
++	if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
++		vmx->loaded_vmcs->host_state.rsp = host_rsp;
++		vmcs_writel(HOST_RSP, host_rsp);
++	}
++}
++
++bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
++
++static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	unsigned long cr3, cr4;
++
++	/* Record the guest's net vcpu time for enforced NMI injections. */
++	if (unlikely(!enable_vnmi &&
++		     vmx->loaded_vmcs->soft_vnmi_blocked))
++		vmx->loaded_vmcs->entry_time = ktime_get();
++
++	/* Don't enter VMX if guest state is invalid, let the exit handler
++	   start emulation until we arrive back to a valid state */
++	if (vmx->emulation_required)
++		return;
++
++	if (vmx->ple_window_dirty) {
++		vmx->ple_window_dirty = false;
++		vmcs_write32(PLE_WINDOW, vmx->ple_window);
++	}
++
++	if (vmx->nested.need_vmcs12_to_shadow_sync)
++		nested_sync_vmcs12_to_shadow(vcpu);
++
++	if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
++		vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
++	if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
++		vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
++
++	cr3 = __get_current_cr3_fast();
++	if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
++		vmcs_writel(HOST_CR3, cr3);
++		vmx->loaded_vmcs->host_state.cr3 = cr3;
++	}
++
++	cr4 = cr4_read_shadow();
++	if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
++		vmcs_writel(HOST_CR4, cr4);
++		vmx->loaded_vmcs->host_state.cr4 = cr4;
++	}
++
++	/* When single-stepping over STI and MOV SS, we must clear the
++	 * corresponding interruptibility bits in the guest state. Otherwise
++	 * vmentry fails as it then expects bit 14 (BS) in pending debug
++	 * exceptions being set, but that's not correct for the guest debugging
++	 * case. */
++	if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
++		vmx_set_interrupt_shadow(vcpu, 0);
++
++	kvm_load_guest_xsave_state(vcpu);
++
++	if (static_cpu_has(X86_FEATURE_PKU) &&
++	    kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
++	    vcpu->arch.pkru != vmx->host_pkru)
++		__write_pkru(vcpu->arch.pkru);
++
++	pt_guest_enter(vmx);
++
++	atomic_switch_perf_msrs(vmx);
++	atomic_switch_umwait_control_msr(vmx);
++
++	if (enable_preemption_timer)
++		vmx_update_hv_timer(vcpu);
++
++	if (lapic_in_kernel(vcpu) &&
++		vcpu->arch.apic->lapic_timer.timer_advance_ns)
++		kvm_wait_lapic_expire(vcpu);
++
++	/*
++	 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
++	 * it's non-zero. Since vmentry is serialising on affected CPUs, there
++	 * is no need to worry about the conditional branch over the wrmsr
++	 * being speculatively taken.
++	 */
++	x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
++
++	/* L1D Flush includes CPU buffer clear to mitigate MDS */
++	if (static_branch_unlikely(&vmx_l1d_should_flush))
++		vmx_l1d_flush(vcpu);
++	else if (static_branch_unlikely(&mds_user_clear))
++		mds_clear_cpu_buffers();
++
++	if (vcpu->arch.cr2 != read_cr2())
++		write_cr2(vcpu->arch.cr2);
++
++	vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
++				   vmx->loaded_vmcs->launched);
++
++	vcpu->arch.cr2 = read_cr2();
++
++	/*
++	 * We do not use IBRS in the kernel. If this vCPU has used the
++	 * SPEC_CTRL MSR it may have left it on; save the value and
++	 * turn it off. This is much more efficient than blindly adding
++	 * it to the atomic save/restore list. Especially as the former
++	 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
++	 *
++	 * For non-nested case:
++	 * If the L01 MSR bitmap does not intercept the MSR, then we need to
++	 * save it.
++	 *
++	 * For nested case:
++	 * If the L02 MSR bitmap does not intercept the MSR, then we need to
++	 * save it.
++	 */
++	if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
++		vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
++
++	x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
++
++	/* All fields are clean at this point */
++	if (static_branch_unlikely(&enable_evmcs))
++		current_evmcs->hv_clean_fields |=
++			HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
++
++	if (static_branch_unlikely(&enable_evmcs))
++		current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
++
++	/* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
++	if (vmx->host_debugctlmsr)
++		update_debugctlmsr(vmx->host_debugctlmsr);
++
++#ifndef CONFIG_X86_64
++	/*
++	 * The sysexit path does not restore ds/es, so we must set them to
++	 * a reasonable value ourselves.
++	 *
++	 * We can't defer this to vmx_prepare_switch_to_host() since that
++	 * function may be executed in interrupt context, which saves and
++	 * restore segments around it, nullifying its effect.
++	 */
++	loadsegment(ds, __USER_DS);
++	loadsegment(es, __USER_DS);
++#endif
++
++	vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
++				  | (1 << VCPU_EXREG_RFLAGS)
++				  | (1 << VCPU_EXREG_PDPTR)
++				  | (1 << VCPU_EXREG_SEGMENTS)
++				  | (1 << VCPU_EXREG_CR3));
++	vcpu->arch.regs_dirty = 0;
++
++	pt_guest_exit(vmx);
++
++	/*
++	 * eager fpu is enabled if PKEY is supported and CR4 is switched
++	 * back on host, so it is safe to read guest PKRU from current
++	 * XSAVE.
++	 */
++	if (static_cpu_has(X86_FEATURE_PKU) &&
++	    kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
++		vcpu->arch.pkru = rdpkru();
++		if (vcpu->arch.pkru != vmx->host_pkru)
++			__write_pkru(vmx->host_pkru);
++	}
++
++	kvm_load_host_xsave_state(vcpu);
++
++	vmx->nested.nested_run_pending = 0;
++	vmx->idt_vectoring_info = 0;
++
++	vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
++	if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
++		kvm_machine_check();
++
++	if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
++		return;
++
++	vmx->loaded_vmcs->launched = 1;
++	vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
++
++	vmx_recover_nmi_blocking(vmx);
++	vmx_complete_interrupts(vmx);
++}
++
++static struct kvm *vmx_vm_alloc(void)
++{
++	struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
++					    GFP_KERNEL_ACCOUNT | __GFP_ZERO,
++					    PAGE_KERNEL);
++	return &kvm_vmx->kvm;
++}
++
++static void vmx_vm_free(struct kvm *kvm)
++{
++	kfree(kvm->arch.hyperv.hv_pa_pg);
++	vfree(to_kvm_vmx(kvm));
++}
++
++static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++
++	if (enable_pml)
++		vmx_destroy_pml_buffer(vmx);
++	free_vpid(vmx->vpid);
++	nested_vmx_free_vcpu(vcpu);
++	free_loaded_vmcs(vmx->loaded_vmcs);
++	kvm_vcpu_uninit(vcpu);
++	kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
++	kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
++	kmem_cache_free(kvm_vcpu_cache, vmx);
++}
++
++static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
++{
++	int err;
++	struct vcpu_vmx *vmx;
++	unsigned long *msr_bitmap;
++	int i, cpu;
++
++	BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0,
++		"struct kvm_vcpu must be at offset 0 for arch usercopy region");
++
++	vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
++	if (!vmx)
++		return ERR_PTR(-ENOMEM);
++
++	vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
++			GFP_KERNEL_ACCOUNT);
++	if (!vmx->vcpu.arch.user_fpu) {
++		printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
++		err = -ENOMEM;
++		goto free_partial_vcpu;
++	}
++
++	vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
++			GFP_KERNEL_ACCOUNT);
++	if (!vmx->vcpu.arch.guest_fpu) {
++		printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
++		err = -ENOMEM;
++		goto free_user_fpu;
++	}
++
++	vmx->vpid = allocate_vpid();
++
++	err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
++	if (err)
++		goto free_vcpu;
++
++	err = -ENOMEM;
++
++	/*
++	 * If PML is turned on, failure on enabling PML just results in failure
++	 * of creating the vcpu, therefore we can simplify PML logic (by
++	 * avoiding dealing with cases, such as enabling PML partially on vcpus
++	 * for the guest), etc.
++	 */
++	if (enable_pml) {
++		vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
++		if (!vmx->pml_pg)
++			goto uninit_vcpu;
++	}
++
++	BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS);
++
++	for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
++		u32 index = vmx_msr_index[i];
++		u32 data_low, data_high;
++		int j = vmx->nmsrs;
++
++		if (rdmsr_safe(index, &data_low, &data_high) < 0)
++			continue;
++		if (wrmsr_safe(index, data_low, data_high) < 0)
++			continue;
++
++		vmx->guest_msrs[j].index = i;
++		vmx->guest_msrs[j].data = 0;
++		switch (index) {
++		case MSR_IA32_TSX_CTRL:
++			/*
++			 * No need to pass TSX_CTRL_CPUID_CLEAR through, so
++			 * let's avoid changing CPUID bits under the host
++			 * kernel's feet.
++			 */
++			vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
++			break;
++		default:
++			vmx->guest_msrs[j].mask = -1ull;
++			break;
++		}
++		++vmx->nmsrs;
++	}
++
++	err = alloc_loaded_vmcs(&vmx->vmcs01);
++	if (err < 0)
++		goto free_pml;
++
++	msr_bitmap = vmx->vmcs01.msr_bitmap;
++	vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
++	vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
++	vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
++	vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
++	vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
++	vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
++	vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
++	if (kvm_cstate_in_guest(kvm)) {
++		vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
++		vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
++		vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
++		vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
++	}
++	vmx->msr_bitmap_mode = 0;
++
++	vmx->loaded_vmcs = &vmx->vmcs01;
++	cpu = get_cpu();
++	vmx_vcpu_load(&vmx->vcpu, cpu);
++	vmx->vcpu.cpu = cpu;
++	init_vmcs(vmx);
++	vmx_vcpu_put(&vmx->vcpu);
++	put_cpu();
++	if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
++		err = alloc_apic_access_page(kvm);
++		if (err)
++			goto free_vmcs;
++	}
++
++	if (enable_ept && !enable_unrestricted_guest) {
++		err = init_rmode_identity_map(kvm);
++		if (err)
++			goto free_vmcs;
++	}
++
++	if (nested)
++		nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
++					   vmx_capability.ept,
++					   kvm_vcpu_apicv_active(&vmx->vcpu));
++	else
++		memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
++
++	vmx->nested.posted_intr_nv = -1;
++	vmx->nested.current_vmptr = -1ull;
++
++	vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
++
++	/*
++	 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
++	 * or POSTED_INTR_WAKEUP_VECTOR.
++	 */
++	vmx->pi_desc.nv = POSTED_INTR_VECTOR;
++	vmx->pi_desc.sn = 1;
++
++	vmx->ept_pointer = INVALID_PAGE;
++
++	return &vmx->vcpu;
++
++free_vmcs:
++	free_loaded_vmcs(vmx->loaded_vmcs);
++free_pml:
++	vmx_destroy_pml_buffer(vmx);
++uninit_vcpu:
++	kvm_vcpu_uninit(&vmx->vcpu);
++free_vcpu:
++	free_vpid(vmx->vpid);
++	kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
++free_user_fpu:
++	kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
++free_partial_vcpu:
++	kmem_cache_free(kvm_vcpu_cache, vmx);
++	return ERR_PTR(err);
++}
++
++#define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
++#define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
++
++static int vmx_vm_init(struct kvm *kvm)
++{
++	spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
++
++	if (!ple_gap)
++		kvm->arch.pause_in_guest = true;
++
++	if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
++		switch (l1tf_mitigation) {
++		case L1TF_MITIGATION_OFF:
++		case L1TF_MITIGATION_FLUSH_NOWARN:
++			/* 'I explicitly don't care' is set */
++			break;
++		case L1TF_MITIGATION_FLUSH:
++		case L1TF_MITIGATION_FLUSH_NOSMT:
++		case L1TF_MITIGATION_FULL:
++			/*
++			 * Warn upon starting the first VM in a potentially
++			 * insecure environment.
++			 */
++			if (sched_smt_active())
++				pr_warn_once(L1TF_MSG_SMT);
++			if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
++				pr_warn_once(L1TF_MSG_L1D);
++			break;
++		case L1TF_MITIGATION_FULL_FORCE:
++			/* Flush is enforced */
++			break;
++		}
++	}
++	return 0;
++}
++
++static int __init vmx_check_processor_compat(void)
++{
++	struct vmcs_config vmcs_conf;
++	struct vmx_capability vmx_cap;
++
++	if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
++		return -EIO;
++	if (nested)
++		nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
++					   enable_apicv);
++	if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
++		printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
++				smp_processor_id());
++		return -EIO;
++	}
++	return 0;
++}
++
++static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
++{
++	u8 cache;
++	u64 ipat = 0;
++
++	/* For VT-d and EPT combination
++	 * 1. MMIO: always map as UC
++	 * 2. EPT with VT-d:
++	 *   a. VT-d without snooping control feature: can't guarantee the
++	 *	result, try to trust guest.
++	 *   b. VT-d with snooping control feature: snooping control feature of
++	 *	VT-d engine can guarantee the cache correctness. Just set it
++	 *	to WB to keep consistent with host. So the same as item 3.
++	 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
++	 *    consistent with host MTRR
++	 */
++	if (is_mmio) {
++		cache = MTRR_TYPE_UNCACHABLE;
++		goto exit;
++	}
++
++	if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
++		ipat = VMX_EPT_IPAT_BIT;
++		cache = MTRR_TYPE_WRBACK;
++		goto exit;
++	}
++
++	if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
++		ipat = VMX_EPT_IPAT_BIT;
++		if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
++			cache = MTRR_TYPE_WRBACK;
++		else
++			cache = MTRR_TYPE_UNCACHABLE;
++		goto exit;
++	}
++
++	cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
++
++exit:
++	return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
++}
++
++static int vmx_get_lpage_level(void)
++{
++	if (enable_ept && !cpu_has_vmx_ept_1g_page())
++		return PT_DIRECTORY_LEVEL;
++	else
++		/* For shadow and EPT supported 1GB page */
++		return PT_PDPE_LEVEL;
++}
++
++static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
++{
++	/*
++	 * These bits in the secondary execution controls field
++	 * are dynamic, the others are mostly based on the hypervisor
++	 * architecture and the guest's CPUID.  Do not touch the
++	 * dynamic bits.
++	 */
++	u32 mask =
++		SECONDARY_EXEC_SHADOW_VMCS |
++		SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
++		SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
++		SECONDARY_EXEC_DESC;
++
++	u32 new_ctl = vmx->secondary_exec_control;
++	u32 cur_ctl = secondary_exec_controls_get(vmx);
++
++	secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
++}
++
++/*
++ * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
++ * (indicating "allowed-1") if they are supported in the guest's CPUID.
++ */
++static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	struct kvm_cpuid_entry2 *entry;
++
++	vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
++	vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
++
++#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {		\
++	if (entry && (entry->_reg & (_cpuid_mask)))			\
++		vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);	\
++} while (0)
++
++	entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
++	cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
++	cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
++	cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
++	cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
++	cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
++	cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
++	cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
++	cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
++	cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
++	cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
++	cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
++	cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
++	cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
++	cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
++
++	entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
++	cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
++	cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
++	cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
++	cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
++	cr4_fixed1_update(X86_CR4_UMIP,       ecx, bit(X86_FEATURE_UMIP));
++	cr4_fixed1_update(X86_CR4_LA57,       ecx, bit(X86_FEATURE_LA57));
++
++#undef cr4_fixed1_update
++}
++
++static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++
++	if (kvm_mpx_supported()) {
++		bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
++
++		if (mpx_enabled) {
++			vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
++			vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
++		} else {
++			vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
++			vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
++		}
++	}
++}
++
++static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	struct kvm_cpuid_entry2 *best = NULL;
++	int i;
++
++	for (i = 0; i < PT_CPUID_LEAVES; i++) {
++		best = kvm_find_cpuid_entry(vcpu, 0x14, i);
++		if (!best)
++			return;
++		vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
++		vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
++		vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
++		vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
++	}
++
++	/* Get the number of configurable Address Ranges for filtering */
++	vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
++						PT_CAP_num_address_ranges);
++
++	/* Initialize and clear the no dependency bits */
++	vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
++			RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
++
++	/*
++	 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
++	 * will inject an #GP
++	 */
++	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
++		vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
++
++	/*
++	 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
++	 * PSBFreq can be set
++	 */
++	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
++		vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
++				RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
++
++	/*
++	 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
++	 * MTCFreq can be set
++	 */
++	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
++		vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
++				RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
++
++	/* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
++	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
++		vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
++							RTIT_CTL_PTW_EN);
++
++	/* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
++	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
++		vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
++
++	/* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
++	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
++		vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
++
++	/* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
++	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
++		vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
++
++	/* unmask address range configure area */
++	for (i = 0; i < vmx->pt_desc.addr_range; i++)
++		vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
++}
++
++static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++
++	/* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
++	vcpu->arch.xsaves_enabled = false;
++
++	if (cpu_has_secondary_exec_ctrls()) {
++		vmx_compute_secondary_exec_control(vmx);
++		vmcs_set_secondary_exec_control(vmx);
++	}
++
++	if (nested_vmx_allowed(vcpu))
++		to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
++			FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX |
++			FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
++	else
++		to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
++			~(FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX |
++			  FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX);
++
++	if (nested_vmx_allowed(vcpu)) {
++		nested_vmx_cr_fixed1_bits_update(vcpu);
++		nested_vmx_entry_exit_ctls_update(vcpu);
++	}
++
++	if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
++			guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
++		update_intel_pt_cfg(vcpu);
++
++	if (boot_cpu_has(X86_FEATURE_RTM)) {
++		struct shared_msr_entry *msr;
++		msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
++		if (msr) {
++			bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
++			vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
++		}
++	}
++}
++
++static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
++{
++	if (func == 1 && nested)
++		entry->ecx |= bit(X86_FEATURE_VMX);
++}
++
++static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
++{
++	to_vmx(vcpu)->req_immediate_exit = true;
++}
++
++static int vmx_check_intercept(struct kvm_vcpu *vcpu,
++			       struct x86_instruction_info *info,
++			       enum x86_intercept_stage stage)
++{
++	struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
++	struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
++
++	/*
++	 * RDPID causes #UD if disabled through secondary execution controls.
++	 * Because it is marked as EmulateOnUD, we need to intercept it here.
++	 */
++	if (info->intercept == x86_intercept_rdtscp &&
++	    !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
++		ctxt->exception.vector = UD_VECTOR;
++		ctxt->exception.error_code_valid = false;
++		return X86EMUL_PROPAGATE_FAULT;
++	}
++
++	/* TODO: check more intercepts... */
++	return X86EMUL_CONTINUE;
++}
++
++#ifdef CONFIG_X86_64
++/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
++static inline int u64_shl_div_u64(u64 a, unsigned int shift,
++				  u64 divisor, u64 *result)
++{
++	u64 low = a << shift, high = a >> (64 - shift);
++
++	/* To avoid the overflow on divq */
++	if (high >= divisor)
++		return 1;
++
++	/* Low hold the result, high hold rem which is discarded */
++	asm("divq %2\n\t" : "=a" (low), "=d" (high) :
++	    "rm" (divisor), "0" (low), "1" (high));
++	*result = low;
++
++	return 0;
++}
++
++static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
++			    bool *expired)
++{
++	struct vcpu_vmx *vmx;
++	u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
++	struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
++
++	if (kvm_mwait_in_guest(vcpu->kvm) ||
++		kvm_can_post_timer_interrupt(vcpu))
++		return -EOPNOTSUPP;
++
++	vmx = to_vmx(vcpu);
++	tscl = rdtsc();
++	guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
++	delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
++	lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
++						    ktimer->timer_advance_ns);
++
++	if (delta_tsc > lapic_timer_advance_cycles)
++		delta_tsc -= lapic_timer_advance_cycles;
++	else
++		delta_tsc = 0;
++
++	/* Convert to host delta tsc if tsc scaling is enabled */
++	if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
++	    delta_tsc && u64_shl_div_u64(delta_tsc,
++				kvm_tsc_scaling_ratio_frac_bits,
++				vcpu->arch.tsc_scaling_ratio, &delta_tsc))
++		return -ERANGE;
++
++	/*
++	 * If the delta tsc can't fit in the 32 bit after the multi shift,
++	 * we can't use the preemption timer.
++	 * It's possible that it fits on later vmentries, but checking
++	 * on every vmentry is costly so we just use an hrtimer.
++	 */
++	if (delta_tsc >> (cpu_preemption_timer_multi + 32))
++		return -ERANGE;
++
++	vmx->hv_deadline_tsc = tscl + delta_tsc;
++	*expired = !delta_tsc;
++	return 0;
++}
++
++static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
++{
++	to_vmx(vcpu)->hv_deadline_tsc = -1;
++}
++#endif
++
++static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
++{
++	if (!kvm_pause_in_guest(vcpu->kvm))
++		shrink_ple_window(vcpu);
++}
++
++static void vmx_slot_enable_log_dirty(struct kvm *kvm,
++				     struct kvm_memory_slot *slot)
++{
++	kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
++	kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
++}
++
++static void vmx_slot_disable_log_dirty(struct kvm *kvm,
++				       struct kvm_memory_slot *slot)
++{
++	kvm_mmu_slot_set_dirty(kvm, slot);
++}
++
++static void vmx_flush_log_dirty(struct kvm *kvm)
++{
++	kvm_flush_pml_buffers(kvm);
++}
++
++static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
++{
++	struct vmcs12 *vmcs12;
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	gpa_t gpa, dst;
++
++	if (is_guest_mode(vcpu)) {
++		WARN_ON_ONCE(vmx->nested.pml_full);
++
++		/*
++		 * Check if PML is enabled for the nested guest.
++		 * Whether eptp bit 6 is set is already checked
++		 * as part of A/D emulation.
++		 */
++		vmcs12 = get_vmcs12(vcpu);
++		if (!nested_cpu_has_pml(vmcs12))
++			return 0;
++
++		if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
++			vmx->nested.pml_full = true;
++			return 1;
++		}
++
++		gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
++		dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
++
++		if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
++					 offset_in_page(dst), sizeof(gpa)))
++			return 0;
++
++		vmcs12->guest_pml_index--;
++	}
++
++	return 0;
++}
++
++static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
++					   struct kvm_memory_slot *memslot,
++					   gfn_t offset, unsigned long mask)
++{
++	kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
++}
++
++static void __pi_post_block(struct kvm_vcpu *vcpu)
++{
++	struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
++	struct pi_desc old, new;
++	unsigned int dest;
++
++	do {
++		old.control = new.control = pi_desc->control;
++		WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
++		     "Wakeup handler not enabled while the VCPU is blocked\n");
++
++		dest = cpu_physical_id(vcpu->cpu);
++
++		if (x2apic_enabled())
++			new.ndst = dest;
++		else
++			new.ndst = (dest << 8) & 0xFF00;
++
++		/* set 'NV' to 'notification vector' */
++		new.nv = POSTED_INTR_VECTOR;
++	} while (cmpxchg64(&pi_desc->control, old.control,
++			   new.control) != old.control);
++
++	if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
++		spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
++		list_del(&vcpu->blocked_vcpu_list);
++		spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
++		vcpu->pre_pcpu = -1;
++	}
++}
++
++/*
++ * This routine does the following things for vCPU which is going
++ * to be blocked if VT-d PI is enabled.
++ * - Store the vCPU to the wakeup list, so when interrupts happen
++ *   we can find the right vCPU to wake up.
++ * - Change the Posted-interrupt descriptor as below:
++ *      'NDST' <-- vcpu->pre_pcpu
++ *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
++ * - If 'ON' is set during this process, which means at least one
++ *   interrupt is posted for this vCPU, we cannot block it, in
++ *   this case, return 1, otherwise, return 0.
++ *
++ */
++static int pi_pre_block(struct kvm_vcpu *vcpu)
++{
++	unsigned int dest;
++	struct pi_desc old, new;
++	struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
++
++	if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
++		!irq_remapping_cap(IRQ_POSTING_CAP)  ||
++		!kvm_vcpu_apicv_active(vcpu))
++		return 0;
++
++	WARN_ON(irqs_disabled());
++	local_irq_disable();
++	if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
++		vcpu->pre_pcpu = vcpu->cpu;
++		spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
++		list_add_tail(&vcpu->blocked_vcpu_list,
++			      &per_cpu(blocked_vcpu_on_cpu,
++				       vcpu->pre_pcpu));
++		spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
++	}
++
++	do {
++		old.control = new.control = pi_desc->control;
++
++		WARN((pi_desc->sn == 1),
++		     "Warning: SN field of posted-interrupts "
++		     "is set before blocking\n");
++
++		/*
++		 * Since vCPU can be preempted during this process,
++		 * vcpu->cpu could be different with pre_pcpu, we
++		 * need to set pre_pcpu as the destination of wakeup
++		 * notification event, then we can find the right vCPU
++		 * to wakeup in wakeup handler if interrupts happen
++		 * when the vCPU is in blocked state.
++		 */
++		dest = cpu_physical_id(vcpu->pre_pcpu);
++
++		if (x2apic_enabled())
++			new.ndst = dest;
++		else
++			new.ndst = (dest << 8) & 0xFF00;
++
++		/* set 'NV' to 'wakeup vector' */
++		new.nv = POSTED_INTR_WAKEUP_VECTOR;
++	} while (cmpxchg64(&pi_desc->control, old.control,
++			   new.control) != old.control);
++
++	/* We should not block the vCPU if an interrupt is posted for it.  */
++	if (pi_test_on(pi_desc) == 1)
++		__pi_post_block(vcpu);
++
++	local_irq_enable();
++	return (vcpu->pre_pcpu == -1);
++}
++
++static int vmx_pre_block(struct kvm_vcpu *vcpu)
++{
++	if (pi_pre_block(vcpu))
++		return 1;
++
++	if (kvm_lapic_hv_timer_in_use(vcpu))
++		kvm_lapic_switch_to_sw_timer(vcpu);
++
++	return 0;
++}
++
++static void pi_post_block(struct kvm_vcpu *vcpu)
++{
++	if (vcpu->pre_pcpu == -1)
++		return;
++
++	WARN_ON(irqs_disabled());
++	local_irq_disable();
++	__pi_post_block(vcpu);
++	local_irq_enable();
++}
++
++static void vmx_post_block(struct kvm_vcpu *vcpu)
++{
++	if (kvm_x86_ops->set_hv_timer)
++		kvm_lapic_switch_to_hv_timer(vcpu);
++
++	pi_post_block(vcpu);
++}
++
++/*
++ * vmx_update_pi_irte - set IRTE for Posted-Interrupts
++ *
++ * @kvm: kvm
++ * @host_irq: host irq of the interrupt
++ * @guest_irq: gsi of the interrupt
++ * @set: set or unset PI
++ * returns 0 on success, < 0 on failure
++ */
++static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
++			      uint32_t guest_irq, bool set)
++{
++	struct kvm_kernel_irq_routing_entry *e;
++	struct kvm_irq_routing_table *irq_rt;
++	struct kvm_lapic_irq irq;
++	struct kvm_vcpu *vcpu;
++	struct vcpu_data vcpu_info;
++	int idx, ret = 0;
++
++	if (!kvm_arch_has_assigned_device(kvm) ||
++		!irq_remapping_cap(IRQ_POSTING_CAP) ||
++		!kvm_vcpu_apicv_active(kvm->vcpus[0]))
++		return 0;
++
++	idx = srcu_read_lock(&kvm->irq_srcu);
++	irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
++	if (guest_irq >= irq_rt->nr_rt_entries ||
++	    hlist_empty(&irq_rt->map[guest_irq])) {
++		pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
++			     guest_irq, irq_rt->nr_rt_entries);
++		goto out;
++	}
++
++	hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
++		if (e->type != KVM_IRQ_ROUTING_MSI)
++			continue;
++		/*
++		 * VT-d PI cannot support posting multicast/broadcast
++		 * interrupts to a vCPU, we still use interrupt remapping
++		 * for these kind of interrupts.
++		 *
++		 * For lowest-priority interrupts, we only support
++		 * those with single CPU as the destination, e.g. user
++		 * configures the interrupts via /proc/irq or uses
++		 * irqbalance to make the interrupts single-CPU.
++		 *
++		 * We will support full lowest-priority interrupt later.
++		 *
++		 * In addition, we can only inject generic interrupts using
++		 * the PI mechanism, refuse to route others through it.
++		 */
++
++		kvm_set_msi_irq(kvm, e, &irq);
++		if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
++		    !kvm_irq_is_postable(&irq)) {
++			/*
++			 * Make sure the IRTE is in remapped mode if
++			 * we don't handle it in posted mode.
++			 */
++			ret = irq_set_vcpu_affinity(host_irq, NULL);
++			if (ret < 0) {
++				printk(KERN_INFO
++				   "failed to back to remapped mode, irq: %u\n",
++				   host_irq);
++				goto out;
++			}
++
++			continue;
++		}
++
++		vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
++		vcpu_info.vector = irq.vector;
++
++		trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
++				vcpu_info.vector, vcpu_info.pi_desc_addr, set);
++
++		if (set)
++			ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
++		else
++			ret = irq_set_vcpu_affinity(host_irq, NULL);
++
++		if (ret < 0) {
++			printk(KERN_INFO "%s: failed to update PI IRTE\n",
++					__func__);
++			goto out;
++		}
++	}
++
++	ret = 0;
++out:
++	srcu_read_unlock(&kvm->irq_srcu, idx);
++	return ret;
++}
++
++static void vmx_setup_mce(struct kvm_vcpu *vcpu)
++{
++	if (vcpu->arch.mcg_cap & MCG_LMCE_P)
++		to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
++			FEATURE_CONTROL_LMCE;
++	else
++		to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
++			~FEATURE_CONTROL_LMCE;
++}
++
++static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
++{
++	/* we need a nested vmexit to enter SMM, postpone if run is pending */
++	if (to_vmx(vcpu)->nested.nested_run_pending)
++		return 0;
++	return 1;
++}
++
++static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++
++	vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
++	if (vmx->nested.smm.guest_mode)
++		nested_vmx_vmexit(vcpu, -1, 0, 0);
++
++	vmx->nested.smm.vmxon = vmx->nested.vmxon;
++	vmx->nested.vmxon = false;
++	vmx_clear_hlt(vcpu);
++	return 0;
++}
++
++static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
++{
++	struct vcpu_vmx *vmx = to_vmx(vcpu);
++	int ret;
++
++	if (vmx->nested.smm.vmxon) {
++		vmx->nested.vmxon = true;
++		vmx->nested.smm.vmxon = false;
++	}
++
++	if (vmx->nested.smm.guest_mode) {
++		ret = nested_vmx_enter_non_root_mode(vcpu, false);
++		if (ret)
++			return ret;
++
++		vmx->nested.smm.guest_mode = false;
++	}
++	return 0;
++}
++
++static int enable_smi_window(struct kvm_vcpu *vcpu)
++{
++	return 0;
++}
++
++static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
++{
++	return false;
++}
++
++static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
++{
++	return to_vmx(vcpu)->nested.vmxon;
++}
++
++static __init int hardware_setup(void)
++{
++	unsigned long host_bndcfgs;
++	struct desc_ptr dt;
++	int r, i;
++
++	rdmsrl_safe(MSR_EFER, &host_efer);
++
++	store_idt(&dt);
++	host_idt_base = dt.address;
++
++	for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
++		kvm_define_shared_msr(i, vmx_msr_index[i]);
++
++	if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
++		return -EIO;
++
++	if (boot_cpu_has(X86_FEATURE_NX))
++		kvm_enable_efer_bits(EFER_NX);
++
++	if (boot_cpu_has(X86_FEATURE_MPX)) {
++		rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
++		WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
++	}
++
++	if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
++	    !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
++		enable_vpid = 0;
++
++	if (!cpu_has_vmx_ept() ||
++	    !cpu_has_vmx_ept_4levels() ||
++	    !cpu_has_vmx_ept_mt_wb() ||
++	    !cpu_has_vmx_invept_global())
++		enable_ept = 0;
++
++	if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
++		enable_ept_ad_bits = 0;
++
++	if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
++		enable_unrestricted_guest = 0;
++
++	if (!cpu_has_vmx_flexpriority())
++		flexpriority_enabled = 0;
++
++	if (!cpu_has_virtual_nmis())
++		enable_vnmi = 0;
++
++	/*
++	 * set_apic_access_page_addr() is used to reload apic access
++	 * page upon invalidation.  No need to do anything if not
++	 * using the APIC_ACCESS_ADDR VMCS field.
++	 */
++	if (!flexpriority_enabled)
++		kvm_x86_ops->set_apic_access_page_addr = NULL;
++
++	if (!cpu_has_vmx_tpr_shadow())
++		kvm_x86_ops->update_cr8_intercept = NULL;
++
++	if (enable_ept && !cpu_has_vmx_ept_2m_page())
++		kvm_disable_largepages();
++
++#if IS_ENABLED(CONFIG_HYPERV)
++	if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
++	    && enable_ept) {
++		kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
++		kvm_x86_ops->tlb_remote_flush_with_range =
++				hv_remote_flush_tlb_with_range;
++	}
++#endif
++
++	if (!cpu_has_vmx_ple()) {
++		ple_gap = 0;
++		ple_window = 0;
++		ple_window_grow = 0;
++		ple_window_max = 0;
++		ple_window_shrink = 0;
++	}
++
++	if (!cpu_has_vmx_apicv()) {
++		enable_apicv = 0;
++		kvm_x86_ops->sync_pir_to_irr = NULL;
++	}
++
++	if (cpu_has_vmx_tsc_scaling()) {
++		kvm_has_tsc_control = true;
++		kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
++		kvm_tsc_scaling_ratio_frac_bits = 48;
++	}
++
++	set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
++
++	if (enable_ept)
++		vmx_enable_tdp();
++	else
++		kvm_disable_tdp();
++
++	/*
++	 * Only enable PML when hardware supports PML feature, and both EPT
++	 * and EPT A/D bit features are enabled -- PML depends on them to work.
++	 */
++	if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
++		enable_pml = 0;
++
++	if (!enable_pml) {
++		kvm_x86_ops->slot_enable_log_dirty = NULL;
++		kvm_x86_ops->slot_disable_log_dirty = NULL;
++		kvm_x86_ops->flush_log_dirty = NULL;
++		kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
++	}
++
++	if (!cpu_has_vmx_preemption_timer())
++		enable_preemption_timer = false;
++
++	if (enable_preemption_timer) {
++		u64 use_timer_freq = 5000ULL * 1000 * 1000;
++		u64 vmx_msr;
++
++		rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
++		cpu_preemption_timer_multi =
++			vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
++
++		if (tsc_khz)
++			use_timer_freq = (u64)tsc_khz * 1000;
++		use_timer_freq >>= cpu_preemption_timer_multi;
++
++		/*
++		 * KVM "disables" the preemption timer by setting it to its max
++		 * value.  Don't use the timer if it might cause spurious exits
++		 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
++		 */
++		if (use_timer_freq > 0xffffffffu / 10)
++			enable_preemption_timer = false;
++	}
++
++	if (!enable_preemption_timer) {
++		kvm_x86_ops->set_hv_timer = NULL;
++		kvm_x86_ops->cancel_hv_timer = NULL;
++		kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
++	}
++
++	kvm_set_posted_intr_wakeup_handler(wakeup_handler);
++
++	kvm_mce_cap_supported |= MCG_LMCE_P;
++
++	if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
++		return -EINVAL;
++	if (!enable_ept || !cpu_has_vmx_intel_pt())
++		pt_mode = PT_MODE_SYSTEM;
++
++	if (nested) {
++		nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
++					   vmx_capability.ept, enable_apicv);
++
++		r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
++		if (r)
++			return r;
++	}
++
++	r = alloc_kvm_area();
++	if (r)
++		nested_vmx_hardware_unsetup();
++	return r;
++}
++
++static __exit void hardware_unsetup(void)
++{
++	if (nested)
++		nested_vmx_hardware_unsetup();
++
++	free_kvm_area();
++}
++
++static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
++	.cpu_has_kvm_support = cpu_has_kvm_support,
++	.disabled_by_bios = vmx_disabled_by_bios,
++	.hardware_setup = hardware_setup,
++	.hardware_unsetup = hardware_unsetup,
++	.check_processor_compatibility = vmx_check_processor_compat,
++	.hardware_enable = hardware_enable,
++	.hardware_disable = hardware_disable,
++	.cpu_has_accelerated_tpr = report_flexpriority,
++	.has_emulated_msr = vmx_has_emulated_msr,
++
++	.vm_init = vmx_vm_init,
++	.vm_alloc = vmx_vm_alloc,
++	.vm_free = vmx_vm_free,
++
++	.vcpu_create = vmx_create_vcpu,
++	.vcpu_free = vmx_free_vcpu,
++	.vcpu_reset = vmx_vcpu_reset,
++
++	.prepare_guest_switch = vmx_prepare_switch_to_guest,
++	.vcpu_load = vmx_vcpu_load,
++	.vcpu_put = vmx_vcpu_put,
++
++	.update_bp_intercept = update_exception_bitmap,
++	.get_msr_feature = vmx_get_msr_feature,
++	.get_msr = vmx_get_msr,
++	.set_msr = vmx_set_msr,
++	.get_segment_base = vmx_get_segment_base,
++	.get_segment = vmx_get_segment,
++	.set_segment = vmx_set_segment,
++	.get_cpl = vmx_get_cpl,
++	.get_cs_db_l_bits = vmx_get_cs_db_l_bits,
++	.decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
++	.decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
++	.set_cr0 = vmx_set_cr0,
++	.set_cr3 = vmx_set_cr3,
++	.set_cr4 = vmx_set_cr4,
++	.set_efer = vmx_set_efer,
++	.get_idt = vmx_get_idt,
++	.set_idt = vmx_set_idt,
++	.get_gdt = vmx_get_gdt,
++	.set_gdt = vmx_set_gdt,
++	.get_dr6 = vmx_get_dr6,
++	.set_dr6 = vmx_set_dr6,
++	.set_dr7 = vmx_set_dr7,
++	.sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
++	.cache_reg = vmx_cache_reg,
++	.get_rflags = vmx_get_rflags,
++	.set_rflags = vmx_set_rflags,
++
++	.tlb_flush = vmx_flush_tlb,
++	.tlb_flush_gva = vmx_flush_tlb_gva,
++
++	.run = vmx_vcpu_run,
++	.handle_exit = vmx_handle_exit,
++	.skip_emulated_instruction = skip_emulated_instruction,
++	.set_interrupt_shadow = vmx_set_interrupt_shadow,
++	.get_interrupt_shadow = vmx_get_interrupt_shadow,
++	.patch_hypercall = vmx_patch_hypercall,
++	.set_irq = vmx_inject_irq,
++	.set_nmi = vmx_inject_nmi,
++	.queue_exception = vmx_queue_exception,
++	.cancel_injection = vmx_cancel_injection,
++	.interrupt_allowed = vmx_interrupt_allowed,
++	.nmi_allowed = vmx_nmi_allowed,
++	.get_nmi_mask = vmx_get_nmi_mask,
++	.set_nmi_mask = vmx_set_nmi_mask,
++	.enable_nmi_window = enable_nmi_window,
++	.enable_irq_window = enable_irq_window,
++	.update_cr8_intercept = update_cr8_intercept,
++	.set_virtual_apic_mode = vmx_set_virtual_apic_mode,
++	.set_apic_access_page_addr = vmx_set_apic_access_page_addr,
++	.get_enable_apicv = vmx_get_enable_apicv,
++	.refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
++	.load_eoi_exitmap = vmx_load_eoi_exitmap,
++	.apicv_post_state_restore = vmx_apicv_post_state_restore,
++	.hwapic_irr_update = vmx_hwapic_irr_update,
++	.hwapic_isr_update = vmx_hwapic_isr_update,
++	.guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
++	.sync_pir_to_irr = vmx_sync_pir_to_irr,
++	.deliver_posted_interrupt = vmx_deliver_posted_interrupt,
++	.dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
++
++	.set_tss_addr = vmx_set_tss_addr,
++	.set_identity_map_addr = vmx_set_identity_map_addr,
++	.get_tdp_level = get_ept_level,
++	.get_mt_mask = vmx_get_mt_mask,
++
++	.get_exit_info = vmx_get_exit_info,
++
++	.get_lpage_level = vmx_get_lpage_level,
++
++	.cpuid_update = vmx_cpuid_update,
++
++	.rdtscp_supported = vmx_rdtscp_supported,
++	.invpcid_supported = vmx_invpcid_supported,
++
++	.set_supported_cpuid = vmx_set_supported_cpuid,
++
++	.has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
++
++	.read_l1_tsc_offset = vmx_read_l1_tsc_offset,
++	.write_l1_tsc_offset = vmx_write_l1_tsc_offset,
++
++	.set_tdp_cr3 = vmx_set_cr3,
++
++	.check_intercept = vmx_check_intercept,
++	.handle_exit_irqoff = vmx_handle_exit_irqoff,
++	.mpx_supported = vmx_mpx_supported,
++	.xsaves_supported = vmx_xsaves_supported,
++	.umip_emulated = vmx_umip_emulated,
++	.pt_supported = vmx_pt_supported,
++
++	.request_immediate_exit = vmx_request_immediate_exit,
++
++	.sched_in = vmx_sched_in,
++
++	.slot_enable_log_dirty = vmx_slot_enable_log_dirty,
++	.slot_disable_log_dirty = vmx_slot_disable_log_dirty,
++	.flush_log_dirty = vmx_flush_log_dirty,
++	.enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
++	.write_log_dirty = vmx_write_pml_buffer,
++
++	.pre_block = vmx_pre_block,
++	.post_block = vmx_post_block,
++
++	.pmu_ops = &intel_pmu_ops,
++
++	.update_pi_irte = vmx_update_pi_irte,
++
++#ifdef CONFIG_X86_64
++	.set_hv_timer = vmx_set_hv_timer,
++	.cancel_hv_timer = vmx_cancel_hv_timer,
++#endif
++
++	.setup_mce = vmx_setup_mce,
++
++	.smi_allowed = vmx_smi_allowed,
++	.pre_enter_smm = vmx_pre_enter_smm,
++	.pre_leave_smm = vmx_pre_leave_smm,
++	.enable_smi_window = enable_smi_window,
++
++	.check_nested_events = NULL,
++	.get_nested_state = NULL,
++	.set_nested_state = NULL,
++	.get_vmcs12_pages = NULL,
++	.nested_enable_evmcs = NULL,
++	.nested_get_evmcs_version = NULL,
++	.need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
++	.apic_init_signal_blocked = vmx_apic_init_signal_blocked,
++};
++
++static void vmx_cleanup_l1d_flush(void)
++{
++	if (vmx_l1d_flush_pages) {
++		free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
++		vmx_l1d_flush_pages = NULL;
++	}
++	/* Restore state so sysfs ignores VMX */
++	l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
++}
++
++static void vmx_exit(void)
++{
++#ifdef CONFIG_KEXEC_CORE
++	RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
++	synchronize_rcu();
++#endif
++
++	kvm_exit();
++
++#if IS_ENABLED(CONFIG_HYPERV)
++	if (static_branch_unlikely(&enable_evmcs)) {
++		int cpu;
++		struct hv_vp_assist_page *vp_ap;
++		/*
++		 * Reset everything to support using non-enlightened VMCS
++		 * access later (e.g. when we reload the module with
++		 * enlightened_vmcs=0)
++		 */
++		for_each_online_cpu(cpu) {
++			vp_ap =	hv_get_vp_assist_page(cpu);
++
++			if (!vp_ap)
++				continue;
++
++			vp_ap->nested_control.features.directhypercall = 0;
++			vp_ap->current_nested_vmcs = 0;
++			vp_ap->enlighten_vmentry = 0;
++		}
++
++		static_branch_disable(&enable_evmcs);
++	}
++#endif
++	vmx_cleanup_l1d_flush();
++}
++module_exit(vmx_exit);
++
++static int __init vmx_init(void)
++{
++	int r;
++
++#if IS_ENABLED(CONFIG_HYPERV)
++	/*
++	 * Enlightened VMCS usage should be recommended and the host needs
++	 * to support eVMCS v1 or above. We can also disable eVMCS support
++	 * with module parameter.
++	 */
++	if (enlightened_vmcs &&
++	    ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
++	    (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
++	    KVM_EVMCS_VERSION) {
++		int cpu;
++
++		/* Check that we have assist pages on all online CPUs */
++		for_each_online_cpu(cpu) {
++			if (!hv_get_vp_assist_page(cpu)) {
++				enlightened_vmcs = false;
++				break;
++			}
++		}
++
++		if (enlightened_vmcs) {
++			pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
++			static_branch_enable(&enable_evmcs);
++		}
++
++		if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
++			vmx_x86_ops.enable_direct_tlbflush
++				= hv_enable_direct_tlbflush;
++
++	} else {
++		enlightened_vmcs = false;
++	}
++#endif
++
++	r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
++		     __alignof__(struct vcpu_vmx), THIS_MODULE);
++	if (r)
++		return r;
++
++	/*
++	 * Must be called after kvm_init() so enable_ept is properly set
++	 * up. Hand the parameter mitigation value in which was stored in
++	 * the pre module init parser. If no parameter was given, it will
++	 * contain 'auto' which will be turned into the default 'cond'
++	 * mitigation mode.
++	 */
++	r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
++	if (r) {
++		vmx_exit();
++		return r;
++	}
++
++#ifdef CONFIG_KEXEC_CORE
++	rcu_assign_pointer(crash_vmclear_loaded_vmcss,
++			   crash_vmclear_local_loaded_vmcss);
++#endif
++	vmx_check_vmcs12_offsets();
++
++	return 0;
++}
++module_init(vmx_init);
+diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
+index 353f63f3b262..ade694f94a49 100644
+--- a/arch/x86/kvm/x86.c
++++ b/arch/x86/kvm/x86.c
+@@ -92,6 +92,8 @@ u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
+ static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
+ #endif
+ 
++static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
++
+ #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__
+ #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__
+ 
+@@ -793,9 +795,38 @@ int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
+ }
+ EXPORT_SYMBOL_GPL(kvm_set_xcr);
+ 
++static u64 kvm_host_cr4_reserved_bits(struct cpuinfo_x86 *c)
++{
++	u64 reserved_bits = CR4_RESERVED_BITS;
++
++	if (!cpu_has(c, X86_FEATURE_XSAVE))
++		reserved_bits |= X86_CR4_OSXSAVE;
++
++	if (!cpu_has(c, X86_FEATURE_SMEP))
++		reserved_bits |= X86_CR4_SMEP;
++
++	if (!cpu_has(c, X86_FEATURE_SMAP))
++		reserved_bits |= X86_CR4_SMAP;
++
++	if (!cpu_has(c, X86_FEATURE_FSGSBASE))
++		reserved_bits |= X86_CR4_FSGSBASE;
++
++	if (!cpu_has(c, X86_FEATURE_PKU))
++		reserved_bits |= X86_CR4_PKE;
++
++	if (!cpu_has(c, X86_FEATURE_LA57) &&
++	    !(cpuid_ecx(0x7) & bit(X86_FEATURE_LA57)))
++		reserved_bits |= X86_CR4_LA57;
++
++	if (!cpu_has(c, X86_FEATURE_UMIP) && !kvm_x86_ops->umip_emulated())
++		reserved_bits |= X86_CR4_UMIP;
++
++	return reserved_bits;
++}
++
+ static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
+ {
+-	if (cr4 & CR4_RESERVED_BITS)
++	if (cr4 & cr4_reserved_bits)
+ 		return -EINVAL;
+ 
+ 	if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
+@@ -961,9 +992,11 @@ static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
+ 
+ static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
+ {
++	size_t size = ARRAY_SIZE(vcpu->arch.db);
++
+ 	switch (dr) {
+ 	case 0 ... 3:
+-		vcpu->arch.db[dr] = val;
++		vcpu->arch.db[array_index_nospec(dr, size)] = val;
+ 		if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
+ 			vcpu->arch.eff_db[dr] = val;
+ 		break;
+@@ -1000,9 +1033,11 @@ EXPORT_SYMBOL_GPL(kvm_set_dr);
+ 
+ int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
+ {
++	size_t size = ARRAY_SIZE(vcpu->arch.db);
++
+ 	switch (dr) {
+ 	case 0 ... 3:
+-		*val = vcpu->arch.db[dr];
++		*val = vcpu->arch.db[array_index_nospec(dr, size)];
+ 		break;
+ 	case 4:
+ 		/* fall through */
+@@ -2269,7 +2304,10 @@ static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
+ 	default:
+ 		if (msr >= MSR_IA32_MC0_CTL &&
+ 		    msr < MSR_IA32_MCx_CTL(bank_num)) {
+-			u32 offset = msr - MSR_IA32_MC0_CTL;
++			u32 offset = array_index_nospec(
++				msr - MSR_IA32_MC0_CTL,
++				MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
++
+ 			/* only 0 or all 1s can be written to IA32_MCi_CTL
+ 			 * some Linux kernels though clear bit 10 in bank 4 to
+ 			 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
+@@ -2681,7 +2719,10 @@ static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
+ 	default:
+ 		if (msr >= MSR_IA32_MC0_CTL &&
+ 		    msr < MSR_IA32_MCx_CTL(bank_num)) {
+-			u32 offset = msr - MSR_IA32_MC0_CTL;
++			u32 offset = array_index_nospec(
++				msr - MSR_IA32_MC0_CTL,
++				MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
++
+ 			data = vcpu->arch.mce_banks[offset];
+ 			break;
+ 		}
+@@ -3234,6 +3275,9 @@ static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
+ 	if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
+ 		return;
+ 
++	if (vcpu->arch.st.steal.preempted)
++		return;
++
+ 	vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
+ 
+ 	kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
+@@ -5977,11 +6021,11 @@ static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
+ 	return r;
+ }
+ 
+-static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
++static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
+ 				  bool write_fault_to_shadow_pgtable,
+ 				  int emulation_type)
+ {
+-	gpa_t gpa = cr2;
++	gpa_t gpa = cr2_or_gpa;
+ 	kvm_pfn_t pfn;
+ 
+ 	if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
+@@ -5995,7 +6039,7 @@ static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
+ 		 * Write permission should be allowed since only
+ 		 * write access need to be emulated.
+ 		 */
+-		gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
++		gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
+ 
+ 		/*
+ 		 * If the mapping is invalid in guest, let cpu retry
+@@ -6052,10 +6096,10 @@ static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
+ }
+ 
+ static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
+-			      unsigned long cr2,  int emulation_type)
++			      gpa_t cr2_or_gpa,  int emulation_type)
+ {
+ 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
+-	unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
++	unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
+ 
+ 	last_retry_eip = vcpu->arch.last_retry_eip;
+ 	last_retry_addr = vcpu->arch.last_retry_addr;
+@@ -6084,14 +6128,14 @@ static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
+ 	if (x86_page_table_writing_insn(ctxt))
+ 		return false;
+ 
+-	if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
++	if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
+ 		return false;
+ 
+ 	vcpu->arch.last_retry_eip = ctxt->eip;
+-	vcpu->arch.last_retry_addr = cr2;
++	vcpu->arch.last_retry_addr = cr2_or_gpa;
+ 
+ 	if (!vcpu->arch.mmu.direct_map)
+-		gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
++		gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
+ 
+ 	kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
+ 
+@@ -6252,11 +6296,8 @@ static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
+ 	return false;
+ }
+ 
+-int x86_emulate_instruction(struct kvm_vcpu *vcpu,
+-			    unsigned long cr2,
+-			    int emulation_type,
+-			    void *insn,
+-			    int insn_len)
++int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
++			    int emulation_type, void *insn, int insn_len)
+ {
+ 	int r;
+ 	struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
+@@ -6299,7 +6340,7 @@ int x86_emulate_instruction(struct kvm_vcpu *vcpu,
+ 		if (r != EMULATION_OK)  {
+ 			if (emulation_type & EMULTYPE_TRAP_UD)
+ 				return EMULATE_FAIL;
+-			if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
++			if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
+ 						emulation_type))
+ 				return EMULATE_DONE;
+ 			if (ctxt->have_exception) {
+@@ -6329,7 +6370,7 @@ int x86_emulate_instruction(struct kvm_vcpu *vcpu,
+ 		return EMULATE_DONE;
+ 	}
+ 
+-	if (retry_instruction(ctxt, cr2, emulation_type))
++	if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
+ 		return EMULATE_DONE;
+ 
+ 	/* this is needed for vmware backdoor interface to work since it
+@@ -6341,7 +6382,7 @@ int x86_emulate_instruction(struct kvm_vcpu *vcpu,
+ 
+ restart:
+ 	/* Save the faulting GPA (cr2) in the address field */
+-	ctxt->exception.address = cr2;
++	ctxt->exception.address = cr2_or_gpa;
+ 
+ 	r = x86_emulate_insn(ctxt);
+ 
+@@ -6349,7 +6390,7 @@ restart:
+ 		return EMULATE_DONE;
+ 
+ 	if (r == EMULATION_FAILED) {
+-		if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
++		if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
+ 					emulation_type))
+ 			return EMULATE_DONE;
+ 
+@@ -6753,7 +6794,7 @@ static void kvm_set_mmio_spte_mask(void)
+ 	 * If reserved bit is not supported, clear the present bit to disable
+ 	 * mmio page fault.
+ 	 */
+-	if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
++	if (maxphyaddr == 52)
+ 		mask &= ~1ull;
+ 
+ 	kvm_mmu_set_mmio_spte_mask(mask, mask);
+@@ -8225,6 +8266,8 @@ int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
+ 				    struct kvm_mp_state *mp_state)
+ {
+ 	vcpu_load(vcpu);
++	if (kvm_mpx_supported())
++		kvm_load_guest_fpu(vcpu);
+ 
+ 	kvm_apic_accept_events(vcpu);
+ 	if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
+@@ -8233,6 +8276,8 @@ int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
+ 	else
+ 		mp_state->mp_state = vcpu->arch.mp_state;
+ 
++	if (kvm_mpx_supported())
++		kvm_put_guest_fpu(vcpu);
+ 	vcpu_put(vcpu);
+ 	return 0;
+ }
+@@ -8654,7 +8699,7 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
+ 	kvm_mmu_unload(vcpu);
+ 	vcpu_put(vcpu);
+ 
+-	kvm_x86_ops->vcpu_free(vcpu);
++	kvm_arch_vcpu_free(vcpu);
+ }
+ 
+ void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
+@@ -8847,6 +8892,8 @@ int kvm_arch_hardware_setup(void)
+ 	if (r != 0)
+ 		return r;
+ 
++	cr4_reserved_bits = kvm_host_cr4_reserved_bits(&boot_cpu_data);
++
+ 	if (kvm_has_tsc_control) {
+ 		/*
+ 		 * Make sure the user can only configure tsc_khz values that
+@@ -9505,7 +9552,7 @@ void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
+ 	      work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
+ 		return;
+ 
+-	vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
++	vcpu->arch.mmu.page_fault(vcpu, work->cr2_or_gpa, 0, true);
+ }
+ 
+ static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
+@@ -9588,7 +9635,7 @@ void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
+ {
+ 	struct x86_exception fault;
+ 
+-	trace_kvm_async_pf_not_present(work->arch.token, work->gva);
++	trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
+ 	kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
+ 
+ 	if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
+@@ -9616,7 +9663,7 @@ void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
+ 		work->arch.token = ~0; /* broadcast wakeup */
+ 	else
+ 		kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
+-	trace_kvm_async_pf_ready(work->arch.token, work->gva);
++	trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
+ 
+ 	if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
+ 	    !apf_get_user(vcpu, &val)) {
+diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h
+index 608e5f8c5d0a..422331b257d3 100644
+--- a/arch/x86/kvm/x86.h
++++ b/arch/x86/kvm/x86.h
+@@ -284,7 +284,7 @@ int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
+ bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn,
+ 					  int page_num);
+ bool kvm_vector_hashing_enabled(void);
+-int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2,
++int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
+ 			    int emulation_type, void *insn, int insn_len);
+ 
+ #define KVM_SUPPORTED_XCR0     (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
+diff --git a/crypto/algapi.c b/crypto/algapi.c
+index c0755cf4f53f..346557a3fc0b 100644
+--- a/crypto/algapi.c
++++ b/crypto/algapi.c
+@@ -649,11 +649,9 @@ EXPORT_SYMBOL_GPL(crypto_grab_spawn);
+ 
+ void crypto_drop_spawn(struct crypto_spawn *spawn)
+ {
+-	if (!spawn->alg)
+-		return;
+-
+ 	down_write(&crypto_alg_sem);
+-	list_del(&spawn->list);
++	if (spawn->alg)
++		list_del(&spawn->list);
+ 	up_write(&crypto_alg_sem);
+ }
+ EXPORT_SYMBOL_GPL(crypto_drop_spawn);
+@@ -661,22 +659,16 @@ EXPORT_SYMBOL_GPL(crypto_drop_spawn);
+ static struct crypto_alg *crypto_spawn_alg(struct crypto_spawn *spawn)
+ {
+ 	struct crypto_alg *alg;
+-	struct crypto_alg *alg2;
+ 
+ 	down_read(&crypto_alg_sem);
+ 	alg = spawn->alg;
+-	alg2 = alg;
+-	if (alg2)
+-		alg2 = crypto_mod_get(alg2);
+-	up_read(&crypto_alg_sem);
+-
+-	if (!alg2) {
+-		if (alg)
+-			crypto_shoot_alg(alg);
+-		return ERR_PTR(-EAGAIN);
++	if (alg && !crypto_mod_get(alg)) {
++		alg->cra_flags |= CRYPTO_ALG_DYING;
++		alg = NULL;
+ 	}
++	up_read(&crypto_alg_sem);
+ 
+-	return alg;
++	return alg ?: ERR_PTR(-EAGAIN);
+ }
+ 
+ struct crypto_tfm *crypto_spawn_tfm(struct crypto_spawn *spawn, u32 type,
+diff --git a/crypto/api.c b/crypto/api.c
+index 7aca9f86c5f3..1909195b2c70 100644
+--- a/crypto/api.c
++++ b/crypto/api.c
+@@ -349,13 +349,12 @@ static unsigned int crypto_ctxsize(struct crypto_alg *alg, u32 type, u32 mask)
+ 	return len;
+ }
+ 
+-void crypto_shoot_alg(struct crypto_alg *alg)
++static void crypto_shoot_alg(struct crypto_alg *alg)
+ {
+ 	down_write(&crypto_alg_sem);
+ 	alg->cra_flags |= CRYPTO_ALG_DYING;
+ 	up_write(&crypto_alg_sem);
+ }
+-EXPORT_SYMBOL_GPL(crypto_shoot_alg);
+ 
+ struct crypto_tfm *__crypto_alloc_tfm(struct crypto_alg *alg, u32 type,
+ 				      u32 mask)
+diff --git a/crypto/internal.h b/crypto/internal.h
+index 9a3f39939fba..f8d6efaffef9 100644
+--- a/crypto/internal.h
++++ b/crypto/internal.h
+@@ -79,7 +79,6 @@ void crypto_alg_tested(const char *name, int err);
+ void crypto_remove_spawns(struct crypto_alg *alg, struct list_head *list,
+ 			  struct crypto_alg *nalg);
+ void crypto_remove_final(struct list_head *list);
+-void crypto_shoot_alg(struct crypto_alg *alg);
+ struct crypto_tfm *__crypto_alloc_tfm(struct crypto_alg *alg, u32 type,
+ 				      u32 mask);
+ void *crypto_create_tfm(struct crypto_alg *alg,
+diff --git a/crypto/pcrypt.c b/crypto/pcrypt.c
+index 1348541da463..85082574c515 100644
+--- a/crypto/pcrypt.c
++++ b/crypto/pcrypt.c
+@@ -130,7 +130,6 @@ static void pcrypt_aead_done(struct crypto_async_request *areq, int err)
+ 	struct padata_priv *padata = pcrypt_request_padata(preq);
+ 
+ 	padata->info = err;
+-	req->base.flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+ 
+ 	padata_do_serial(padata);
+ }
+diff --git a/drivers/acpi/battery.c b/drivers/acpi/battery.c
+index cb97b6105f52..674a0e92b798 100644
+--- a/drivers/acpi/battery.c
++++ b/drivers/acpi/battery.c
+@@ -51,6 +51,8 @@
+ #define PREFIX "ACPI: "
+ 
+ #define ACPI_BATTERY_VALUE_UNKNOWN 0xFFFFFFFF
++#define ACPI_BATTERY_CAPACITY_VALID(capacity) \
++	((capacity) != 0 && (capacity) != ACPI_BATTERY_VALUE_UNKNOWN)
+ 
+ #define ACPI_BATTERY_DEVICE_NAME	"Battery"
+ 
+@@ -205,7 +207,8 @@ static int acpi_battery_is_charged(struct acpi_battery *battery)
+ 
+ static bool acpi_battery_is_degraded(struct acpi_battery *battery)
+ {
+-	return battery->full_charge_capacity && battery->design_capacity &&
++	return ACPI_BATTERY_CAPACITY_VALID(battery->full_charge_capacity) &&
++		ACPI_BATTERY_CAPACITY_VALID(battery->design_capacity) &&
+ 		battery->full_charge_capacity < battery->design_capacity;
+ }
+ 
+@@ -227,7 +230,7 @@ static int acpi_battery_get_property(struct power_supply *psy,
+ 				     enum power_supply_property psp,
+ 				     union power_supply_propval *val)
+ {
+-	int ret = 0;
++	int full_capacity = ACPI_BATTERY_VALUE_UNKNOWN, ret = 0;
+ 	struct acpi_battery *battery = to_acpi_battery(psy);
+ 
+ 	if (acpi_battery_present(battery)) {
+@@ -276,14 +279,14 @@ static int acpi_battery_get_property(struct power_supply *psy,
+ 		break;
+ 	case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
+ 	case POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN:
+-		if (battery->design_capacity == ACPI_BATTERY_VALUE_UNKNOWN)
++		if (!ACPI_BATTERY_CAPACITY_VALID(battery->design_capacity))
+ 			ret = -ENODEV;
+ 		else
+ 			val->intval = battery->design_capacity * 1000;
+ 		break;
+ 	case POWER_SUPPLY_PROP_CHARGE_FULL:
+ 	case POWER_SUPPLY_PROP_ENERGY_FULL:
+-		if (battery->full_charge_capacity == ACPI_BATTERY_VALUE_UNKNOWN)
++		if (!ACPI_BATTERY_CAPACITY_VALID(battery->full_charge_capacity))
+ 			ret = -ENODEV;
+ 		else
+ 			val->intval = battery->full_charge_capacity * 1000;
+@@ -296,11 +299,17 @@ static int acpi_battery_get_property(struct power_supply *psy,
+ 			val->intval = battery->capacity_now * 1000;
+ 		break;
+ 	case POWER_SUPPLY_PROP_CAPACITY:
+-		if (battery->capacity_now && battery->full_charge_capacity)
+-			val->intval = battery->capacity_now * 100/
+-					battery->full_charge_capacity;
++		if (ACPI_BATTERY_CAPACITY_VALID(battery->full_charge_capacity))
++			full_capacity = battery->full_charge_capacity;
++		else if (ACPI_BATTERY_CAPACITY_VALID(battery->design_capacity))
++			full_capacity = battery->design_capacity;
++
++		if (battery->capacity_now == ACPI_BATTERY_VALUE_UNKNOWN ||
++		    full_capacity == ACPI_BATTERY_VALUE_UNKNOWN)
++			ret = -ENODEV;
+ 		else
+-			val->intval = 0;
++			val->intval = battery->capacity_now * 100/
++					full_capacity;
+ 		break;
+ 	case POWER_SUPPLY_PROP_CAPACITY_LEVEL:
+ 		if (battery->state & ACPI_BATTERY_STATE_CRITICAL)
+@@ -346,6 +355,20 @@ static enum power_supply_property charge_battery_props[] = {
+ 	POWER_SUPPLY_PROP_SERIAL_NUMBER,
+ };
+ 
++static enum power_supply_property charge_battery_full_cap_broken_props[] = {
++	POWER_SUPPLY_PROP_STATUS,
++	POWER_SUPPLY_PROP_PRESENT,
++	POWER_SUPPLY_PROP_TECHNOLOGY,
++	POWER_SUPPLY_PROP_CYCLE_COUNT,
++	POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
++	POWER_SUPPLY_PROP_VOLTAGE_NOW,
++	POWER_SUPPLY_PROP_CURRENT_NOW,
++	POWER_SUPPLY_PROP_CHARGE_NOW,
++	POWER_SUPPLY_PROP_MODEL_NAME,
++	POWER_SUPPLY_PROP_MANUFACTURER,
++	POWER_SUPPLY_PROP_SERIAL_NUMBER,
++};
++
+ static enum power_supply_property energy_battery_props[] = {
+ 	POWER_SUPPLY_PROP_STATUS,
+ 	POWER_SUPPLY_PROP_PRESENT,
+@@ -807,20 +830,34 @@ static void __exit battery_hook_exit(void)
+ static int sysfs_add_battery(struct acpi_battery *battery)
+ {
+ 	struct power_supply_config psy_cfg = { .drv_data = battery, };
++	bool full_cap_broken = false;
++
++	if (!ACPI_BATTERY_CAPACITY_VALID(battery->full_charge_capacity) &&
++	    !ACPI_BATTERY_CAPACITY_VALID(battery->design_capacity))
++		full_cap_broken = true;
+ 
+ 	if (battery->power_unit == ACPI_BATTERY_POWER_UNIT_MA) {
+-		battery->bat_desc.properties = charge_battery_props;
+-		battery->bat_desc.num_properties =
+-			ARRAY_SIZE(charge_battery_props);
+-	} else if (battery->full_charge_capacity == 0) {
+-		battery->bat_desc.properties =
+-			energy_battery_full_cap_broken_props;
+-		battery->bat_desc.num_properties =
+-			ARRAY_SIZE(energy_battery_full_cap_broken_props);
++		if (full_cap_broken) {
++			battery->bat_desc.properties =
++			    charge_battery_full_cap_broken_props;
++			battery->bat_desc.num_properties =
++			    ARRAY_SIZE(charge_battery_full_cap_broken_props);
++		} else {
++			battery->bat_desc.properties = charge_battery_props;
++			battery->bat_desc.num_properties =
++			    ARRAY_SIZE(charge_battery_props);
++		}
+ 	} else {
+-		battery->bat_desc.properties = energy_battery_props;
+-		battery->bat_desc.num_properties =
+-			ARRAY_SIZE(energy_battery_props);
++		if (full_cap_broken) {
++			battery->bat_desc.properties =
++			    energy_battery_full_cap_broken_props;
++			battery->bat_desc.num_properties =
++			    ARRAY_SIZE(energy_battery_full_cap_broken_props);
++		} else {
++			battery->bat_desc.properties = energy_battery_props;
++			battery->bat_desc.num_properties =
++			    ARRAY_SIZE(energy_battery_props);
++		}
+ 	}
+ 
+ 	battery->bat_desc.name = acpi_device_bid(battery->device);
+diff --git a/drivers/acpi/video_detect.c b/drivers/acpi/video_detect.c
+index 43587ac680e4..214c4e2e8ade 100644
+--- a/drivers/acpi/video_detect.c
++++ b/drivers/acpi/video_detect.c
+@@ -328,6 +328,11 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
+ 		DMI_MATCH(DMI_PRODUCT_NAME, "Precision 7510"),
+ 		},
+ 	},
++
++	/*
++	 * Desktops which falsely report a backlight and which our heuristics
++	 * for this do not catch.
++	 */
+ 	{
+ 	 .callback = video_detect_force_none,
+ 	 .ident = "Dell OptiPlex 9020M",
+@@ -336,6 +341,14 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
+ 		DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 9020M"),
+ 		},
+ 	},
++	{
++	 .callback = video_detect_force_none,
++	 .ident = "MSI MS-7721",
++	 .matches = {
++		DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
++		DMI_MATCH(DMI_PRODUCT_NAME, "MS-7721"),
++		},
++	},
+ 	{ },
+ };
+ 
+diff --git a/drivers/base/power/main.c b/drivers/base/power/main.c
+index 4abd7c6531d9..3b382a7e07b2 100644
+--- a/drivers/base/power/main.c
++++ b/drivers/base/power/main.c
+@@ -265,10 +265,38 @@ static void dpm_wait_for_suppliers(struct device *dev, bool async)
+ 	device_links_read_unlock(idx);
+ }
+ 
+-static void dpm_wait_for_superior(struct device *dev, bool async)
++static bool dpm_wait_for_superior(struct device *dev, bool async)
+ {
+-	dpm_wait(dev->parent, async);
++	struct device *parent;
++
++	/*
++	 * If the device is resumed asynchronously and the parent's callback
++	 * deletes both the device and the parent itself, the parent object may
++	 * be freed while this function is running, so avoid that by reference
++	 * counting the parent once more unless the device has been deleted
++	 * already (in which case return right away).
++	 */
++	mutex_lock(&dpm_list_mtx);
++
++	if (!device_pm_initialized(dev)) {
++		mutex_unlock(&dpm_list_mtx);
++		return false;
++	}
++
++	parent = get_device(dev->parent);
++
++	mutex_unlock(&dpm_list_mtx);
++
++	dpm_wait(parent, async);
++	put_device(parent);
++
+ 	dpm_wait_for_suppliers(dev, async);
++
++	/*
++	 * If the parent's callback has deleted the device, attempting to resume
++	 * it would be invalid, so avoid doing that then.
++	 */
++	return device_pm_initialized(dev);
+ }
+ 
+ static void dpm_wait_for_consumers(struct device *dev, bool async)
+@@ -628,7 +656,8 @@ static int device_resume_noirq(struct device *dev, pm_message_t state, bool asyn
+ 	if (!dev->power.is_noirq_suspended)
+ 		goto Out;
+ 
+-	dpm_wait_for_superior(dev, async);
++	if (!dpm_wait_for_superior(dev, async))
++		goto Out;
+ 
+ 	skip_resume = dev_pm_may_skip_resume(dev);
+ 
+@@ -829,7 +858,8 @@ static int device_resume_early(struct device *dev, pm_message_t state, bool asyn
+ 	if (!dev->power.is_late_suspended)
+ 		goto Out;
+ 
+-	dpm_wait_for_superior(dev, async);
++	if (!dpm_wait_for_superior(dev, async))
++		goto Out;
+ 
+ 	callback = dpm_subsys_resume_early_cb(dev, state, &info);
+ 
+@@ -949,7 +979,9 @@ static int device_resume(struct device *dev, pm_message_t state, bool async)
+ 		goto Complete;
+ 	}
+ 
+-	dpm_wait_for_superior(dev, async);
++	if (!dpm_wait_for_superior(dev, async))
++		goto Complete;
++
+ 	dpm_watchdog_set(&wd, dev);
+ 	device_lock(dev);
+ 
+diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
+index 38c4eb28c8bf..b137c5d34eec 100644
+--- a/drivers/clk/tegra/clk-tegra-periph.c
++++ b/drivers/clk/tegra/clk-tegra-periph.c
+@@ -799,7 +799,11 @@ static struct tegra_periph_init_data gate_clks[] = {
+ 	GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),
+ 	GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0),
+ 	GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
+-	GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
++	/*
++	 * Critical for RAM re-repair operation, which must occur on resume
++	 * from LP1 system suspend and as part of CCPLEX cluster switching.
++	 */
++	GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, CLK_IS_CRITICAL),
+ 	GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
+ 	GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
+ 	GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
+diff --git a/drivers/crypto/atmel-aes.c b/drivers/crypto/atmel-aes.c
+index 53a78035381d..92060864e356 100644
+--- a/drivers/crypto/atmel-aes.c
++++ b/drivers/crypto/atmel-aes.c
+@@ -91,7 +91,6 @@
+ struct atmel_aes_caps {
+ 	bool			has_dualbuff;
+ 	bool			has_cfb64;
+-	bool			has_ctr32;
+ 	bool			has_gcm;
+ 	bool			has_xts;
+ 	bool			has_authenc;
+@@ -1016,8 +1015,9 @@ static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd)
+ 	struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
+ 	struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
+ 	struct scatterlist *src, *dst;
+-	u32 ctr, blocks;
+ 	size_t datalen;
++	u32 ctr;
++	u16 blocks, start, end;
+ 	bool use_dma, fragmented = false;
+ 
+ 	/* Check for transfer completion. */
+@@ -1029,27 +1029,17 @@ static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd)
+ 	datalen = req->nbytes - ctx->offset;
+ 	blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE);
+ 	ctr = be32_to_cpu(ctx->iv[3]);
+-	if (dd->caps.has_ctr32) {
+-		/* Check 32bit counter overflow. */
+-		u32 start = ctr;
+-		u32 end = start + blocks - 1;
+-
+-		if (end < start) {
+-			ctr |= 0xffffffff;
+-			datalen = AES_BLOCK_SIZE * -start;
+-			fragmented = true;
+-		}
+-	} else {
+-		/* Check 16bit counter overflow. */
+-		u16 start = ctr & 0xffff;
+-		u16 end = start + (u16)blocks - 1;
+-
+-		if (blocks >> 16 || end < start) {
+-			ctr |= 0xffff;
+-			datalen = AES_BLOCK_SIZE * (0x10000-start);
+-			fragmented = true;
+-		}
++
++	/* Check 16bit counter overflow. */
++	start = ctr & 0xffff;
++	end = start + blocks - 1;
++
++	if (blocks >> 16 || end < start) {
++		ctr |= 0xffff;
++		datalen = AES_BLOCK_SIZE * (0x10000 - start);
++		fragmented = true;
+ 	}
++
+ 	use_dma = (datalen >= ATMEL_AES_DMA_THRESHOLD);
+ 
+ 	/* Jump to offset. */
+@@ -2553,7 +2543,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
+ {
+ 	dd->caps.has_dualbuff = 0;
+ 	dd->caps.has_cfb64 = 0;
+-	dd->caps.has_ctr32 = 0;
+ 	dd->caps.has_gcm = 0;
+ 	dd->caps.has_xts = 0;
+ 	dd->caps.has_authenc = 0;
+@@ -2564,7 +2553,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
+ 	case 0x500:
+ 		dd->caps.has_dualbuff = 1;
+ 		dd->caps.has_cfb64 = 1;
+-		dd->caps.has_ctr32 = 1;
+ 		dd->caps.has_gcm = 1;
+ 		dd->caps.has_xts = 1;
+ 		dd->caps.has_authenc = 1;
+@@ -2573,7 +2561,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
+ 	case 0x200:
+ 		dd->caps.has_dualbuff = 1;
+ 		dd->caps.has_cfb64 = 1;
+-		dd->caps.has_ctr32 = 1;
+ 		dd->caps.has_gcm = 1;
+ 		dd->caps.max_burst_size = 4;
+ 		break;
+diff --git a/drivers/crypto/ccp/ccp-dev-v3.c b/drivers/crypto/ccp/ccp-dev-v3.c
+index 240bebbcb8ac..ae0cc0a4dc5c 100644
+--- a/drivers/crypto/ccp/ccp-dev-v3.c
++++ b/drivers/crypto/ccp/ccp-dev-v3.c
+@@ -590,6 +590,7 @@ const struct ccp_vdata ccpv3_platform = {
+ 	.setup = NULL,
+ 	.perform = &ccp3_actions,
+ 	.offset = 0,
++	.rsamax = CCP_RSA_MAX_WIDTH,
+ };
+ 
+ const struct ccp_vdata ccpv3 = {
+diff --git a/drivers/crypto/ccree/cc_driver.h b/drivers/crypto/ccree/cc_driver.h
+index be7f9bd5c559..d41193932207 100644
+--- a/drivers/crypto/ccree/cc_driver.h
++++ b/drivers/crypto/ccree/cc_driver.h
+@@ -131,6 +131,7 @@ struct cc_drvdata {
+ 	u32 axim_mon_offset;
+ 	u32 sig_offset;
+ 	u32 ver_offset;
++	bool pm_on;
+ };
+ 
+ struct cc_crypto_alg {
+diff --git a/drivers/crypto/ccree/cc_pm.c b/drivers/crypto/ccree/cc_pm.c
+index 638082dff183..2df2c2ca8aae 100644
+--- a/drivers/crypto/ccree/cc_pm.c
++++ b/drivers/crypto/ccree/cc_pm.c
+@@ -23,14 +23,8 @@ const struct dev_pm_ops ccree_pm = {
+ int cc_pm_suspend(struct device *dev)
+ {
+ 	struct cc_drvdata *drvdata = dev_get_drvdata(dev);
+-	int rc;
+ 
+ 	dev_dbg(dev, "set HOST_POWER_DOWN_EN\n");
+-	rc = cc_suspend_req_queue(drvdata);
+-	if (rc) {
+-		dev_err(dev, "cc_suspend_req_queue (%x)\n", rc);
+-		return rc;
+-	}
+ 	fini_cc_regs(drvdata);
+ 	cc_iowrite(drvdata, CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_ENABLE);
+ 	cc_clk_off(drvdata);
+@@ -59,13 +53,6 @@ int cc_pm_resume(struct device *dev)
+ 	/* check if tee fips error occurred during power down */
+ 	cc_tee_handle_fips_error(drvdata);
+ 
+-	rc = cc_resume_req_queue(drvdata);
+-	if (rc) {
+-		dev_err(dev, "cc_resume_req_queue (%x)\n", rc);
+-		return rc;
+-	}
+-
+-	/* must be after the queue resuming as it uses the HW queue*/
+ 	cc_init_hash_sram(drvdata);
+ 
+ 	cc_init_iv_sram(drvdata);
+@@ -77,12 +64,10 @@ int cc_pm_get(struct device *dev)
+ 	int rc = 0;
+ 	struct cc_drvdata *drvdata = dev_get_drvdata(dev);
+ 
+-	if (cc_req_queue_suspended(drvdata))
++	if (drvdata->pm_on)
+ 		rc = pm_runtime_get_sync(dev);
+-	else
+-		pm_runtime_get_noresume(dev);
+ 
+-	return rc;
++	return (rc == 1 ? 0 : rc);
+ }
+ 
+ int cc_pm_put_suspend(struct device *dev)
+@@ -90,14 +75,11 @@ int cc_pm_put_suspend(struct device *dev)
+ 	int rc = 0;
+ 	struct cc_drvdata *drvdata = dev_get_drvdata(dev);
+ 
+-	if (!cc_req_queue_suspended(drvdata)) {
++	if (drvdata->pm_on) {
+ 		pm_runtime_mark_last_busy(dev);
+ 		rc = pm_runtime_put_autosuspend(dev);
+-	} else {
+-		/* Something wrong happens*/
+-		dev_err(dev, "request to suspend already suspended queue");
+-		rc = -EBUSY;
+ 	}
++
+ 	return rc;
+ }
+ 
+@@ -108,7 +90,7 @@ int cc_pm_init(struct cc_drvdata *drvdata)
+ 	/* must be before the enabling to avoid resdundent suspending */
+ 	pm_runtime_set_autosuspend_delay(dev, CC_SUSPEND_TIMEOUT);
+ 	pm_runtime_use_autosuspend(dev);
+-	/* activate the PM module */
++	/* set us as active - note we won't do PM ops until cc_pm_go()! */
+ 	return pm_runtime_set_active(dev);
+ }
+ 
+@@ -116,9 +98,11 @@ int cc_pm_init(struct cc_drvdata *drvdata)
+ void cc_pm_go(struct cc_drvdata *drvdata)
+ {
+ 	pm_runtime_enable(drvdata_to_dev(drvdata));
++	drvdata->pm_on = true;
+ }
+ 
+ void cc_pm_fini(struct cc_drvdata *drvdata)
+ {
+ 	pm_runtime_disable(drvdata_to_dev(drvdata));
++	drvdata->pm_on = false;
+ }
+diff --git a/drivers/crypto/ccree/cc_request_mgr.c b/drivers/crypto/ccree/cc_request_mgr.c
+index 83a8aaae61c7..1d88abc6d230 100644
+--- a/drivers/crypto/ccree/cc_request_mgr.c
++++ b/drivers/crypto/ccree/cc_request_mgr.c
+@@ -41,7 +41,6 @@ struct cc_req_mgr_handle {
+ #else
+ 	struct tasklet_struct comptask;
+ #endif
+-	bool is_runtime_suspended;
+ };
+ 
+ struct cc_bl_item {
+@@ -403,6 +402,7 @@ static void cc_proc_backlog(struct cc_drvdata *drvdata)
+ 		spin_lock(&mgr->bl_lock);
+ 		list_del(&bli->list);
+ 		--mgr->bl_len;
++		kfree(bli);
+ 	}
+ 
+ 	spin_unlock(&mgr->bl_lock);
+@@ -660,52 +660,3 @@ static void comp_handler(unsigned long devarg)
+ 
+ 	cc_proc_backlog(drvdata);
+ }
+-
+-/*
+- * resume the queue configuration - no need to take the lock as this happens
+- * inside the spin lock protection
+- */
+-#if defined(CONFIG_PM)
+-int cc_resume_req_queue(struct cc_drvdata *drvdata)
+-{
+-	struct cc_req_mgr_handle *request_mgr_handle =
+-		drvdata->request_mgr_handle;
+-
+-	spin_lock_bh(&request_mgr_handle->hw_lock);
+-	request_mgr_handle->is_runtime_suspended = false;
+-	spin_unlock_bh(&request_mgr_handle->hw_lock);
+-
+-	return 0;
+-}
+-
+-/*
+- * suspend the queue configuration. Since it is used for the runtime suspend
+- * only verify that the queue can be suspended.
+- */
+-int cc_suspend_req_queue(struct cc_drvdata *drvdata)
+-{
+-	struct cc_req_mgr_handle *request_mgr_handle =
+-						drvdata->request_mgr_handle;
+-
+-	/* lock the send_request */
+-	spin_lock_bh(&request_mgr_handle->hw_lock);
+-	if (request_mgr_handle->req_queue_head !=
+-	    request_mgr_handle->req_queue_tail) {
+-		spin_unlock_bh(&request_mgr_handle->hw_lock);
+-		return -EBUSY;
+-	}
+-	request_mgr_handle->is_runtime_suspended = true;
+-	spin_unlock_bh(&request_mgr_handle->hw_lock);
+-
+-	return 0;
+-}
+-
+-bool cc_req_queue_suspended(struct cc_drvdata *drvdata)
+-{
+-	struct cc_req_mgr_handle *request_mgr_handle =
+-						drvdata->request_mgr_handle;
+-
+-	return	request_mgr_handle->is_runtime_suspended;
+-}
+-
+-#endif
+diff --git a/drivers/crypto/ccree/cc_request_mgr.h b/drivers/crypto/ccree/cc_request_mgr.h
+index 573cb97af085..ae96abce25c9 100644
+--- a/drivers/crypto/ccree/cc_request_mgr.h
++++ b/drivers/crypto/ccree/cc_request_mgr.h
+@@ -40,12 +40,4 @@ void complete_request(struct cc_drvdata *drvdata);
+ 
+ void cc_req_mgr_fini(struct cc_drvdata *drvdata);
+ 
+-#if defined(CONFIG_PM)
+-int cc_resume_req_queue(struct cc_drvdata *drvdata);
+-
+-int cc_suspend_req_queue(struct cc_drvdata *drvdata);
+-
+-bool cc_req_queue_suspended(struct cc_drvdata *drvdata);
+-#endif
+-
+ #endif /*__REQUEST_MGR_H__*/
+diff --git a/drivers/crypto/geode-aes.c b/drivers/crypto/geode-aes.c
+index d670f7000cbb..0bd99c0decf5 100644
+--- a/drivers/crypto/geode-aes.c
++++ b/drivers/crypto/geode-aes.c
+@@ -14,7 +14,7 @@
+ #include <linux/spinlock.h>
+ #include <crypto/algapi.h>
+ #include <crypto/aes.h>
+-#include <crypto/skcipher.h>
++#include <crypto/internal/skcipher.h>
+ 
+ #include <linux/io.h>
+ #include <linux/delay.h>
+@@ -28,12 +28,12 @@ static spinlock_t lock;
+ 
+ /* Write a 128 bit field (either a writable key or IV) */
+ static inline void
+-_writefield(u32 offset, void *value)
++_writefield(u32 offset, const void *value)
+ {
+ 	int i;
+ 
+ 	for (i = 0; i < 4; i++)
+-		iowrite32(((u32 *) value)[i], _iobase + offset + (i * 4));
++		iowrite32(((const u32 *) value)[i], _iobase + offset + (i * 4));
+ }
+ 
+ /* Read a 128 bit field (either a writable key or IV) */
+@@ -47,12 +47,12 @@ _readfield(u32 offset, void *value)
+ }
+ 
+ static int
+-do_crypt(void *src, void *dst, int len, u32 flags)
++do_crypt(const void *src, void *dst, u32 len, u32 flags)
+ {
+ 	u32 status;
+ 	u32 counter = AES_OP_TIMEOUT;
+ 
+-	iowrite32(virt_to_phys(src), _iobase + AES_SOURCEA_REG);
++	iowrite32(virt_to_phys((void *)src), _iobase + AES_SOURCEA_REG);
+ 	iowrite32(virt_to_phys(dst), _iobase + AES_DSTA_REG);
+ 	iowrite32(len,  _iobase + AES_LENA_REG);
+ 
+@@ -69,16 +69,14 @@ do_crypt(void *src, void *dst, int len, u32 flags)
+ 	return counter ? 0 : 1;
+ }
+ 
+-static unsigned int
+-geode_aes_crypt(struct geode_aes_op *op)
++static void
++geode_aes_crypt(const struct geode_aes_tfm_ctx *tctx, const void *src,
++		void *dst, u32 len, u8 *iv, int mode, int dir)
+ {
+ 	u32 flags = 0;
+ 	unsigned long iflags;
+ 	int ret;
+ 
+-	if (op->len == 0)
+-		return 0;
+-
+ 	/* If the source and destination is the same, then
+ 	 * we need to turn on the coherent flags, otherwise
+ 	 * we don't need to worry
+@@ -86,32 +84,28 @@ geode_aes_crypt(struct geode_aes_op *op)
+ 
+ 	flags |= (AES_CTRL_DCA | AES_CTRL_SCA);
+ 
+-	if (op->dir == AES_DIR_ENCRYPT)
++	if (dir == AES_DIR_ENCRYPT)
+ 		flags |= AES_CTRL_ENCRYPT;
+ 
+ 	/* Start the critical section */
+ 
+ 	spin_lock_irqsave(&lock, iflags);
+ 
+-	if (op->mode == AES_MODE_CBC) {
++	if (mode == AES_MODE_CBC) {
+ 		flags |= AES_CTRL_CBC;
+-		_writefield(AES_WRITEIV0_REG, op->iv);
++		_writefield(AES_WRITEIV0_REG, iv);
+ 	}
+ 
+-	if (!(op->flags & AES_FLAGS_HIDDENKEY)) {
+-		flags |= AES_CTRL_WRKEY;
+-		_writefield(AES_WRITEKEY0_REG, op->key);
+-	}
++	flags |= AES_CTRL_WRKEY;
++	_writefield(AES_WRITEKEY0_REG, tctx->key);
+ 
+-	ret = do_crypt(op->src, op->dst, op->len, flags);
++	ret = do_crypt(src, dst, len, flags);
+ 	BUG_ON(ret);
+ 
+-	if (op->mode == AES_MODE_CBC)
+-		_readfield(AES_WRITEIV0_REG, op->iv);
++	if (mode == AES_MODE_CBC)
++		_readfield(AES_WRITEIV0_REG, iv);
+ 
+ 	spin_unlock_irqrestore(&lock, iflags);
+-
+-	return op->len;
+ }
+ 
+ /* CRYPTO-API Functions */
+@@ -119,13 +113,13 @@ geode_aes_crypt(struct geode_aes_op *op)
+ static int geode_setkey_cip(struct crypto_tfm *tfm, const u8 *key,
+ 		unsigned int len)
+ {
+-	struct geode_aes_op *op = crypto_tfm_ctx(tfm);
++	struct geode_aes_tfm_ctx *tctx = crypto_tfm_ctx(tfm);
+ 	unsigned int ret;
+ 
+-	op->keylen = len;
++	tctx->keylen = len;
+ 
+ 	if (len == AES_KEYSIZE_128) {
+-		memcpy(op->key, key, len);
++		memcpy(tctx->key, key, len);
+ 		return 0;
+ 	}
+ 
+@@ -138,132 +132,93 @@ static int geode_setkey_cip(struct crypto_tfm *tfm, const u8 *key,
+ 	/*
+ 	 * The requested key size is not supported by HW, do a fallback
+ 	 */
+-	op->fallback.cip->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
+-	op->fallback.cip->base.crt_flags |= (tfm->crt_flags & CRYPTO_TFM_REQ_MASK);
++	tctx->fallback.cip->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
++	tctx->fallback.cip->base.crt_flags |=
++		(tfm->crt_flags & CRYPTO_TFM_REQ_MASK);
+ 
+-	ret = crypto_cipher_setkey(op->fallback.cip, key, len);
++	ret = crypto_cipher_setkey(tctx->fallback.cip, key, len);
+ 	if (ret) {
+ 		tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK;
+-		tfm->crt_flags |= (op->fallback.cip->base.crt_flags & CRYPTO_TFM_RES_MASK);
++		tfm->crt_flags |= (tctx->fallback.cip->base.crt_flags &
++				   CRYPTO_TFM_RES_MASK);
+ 	}
+ 	return ret;
+ }
+ 
+-static int geode_setkey_blk(struct crypto_tfm *tfm, const u8 *key,
+-		unsigned int len)
++static int geode_setkey_skcipher(struct crypto_skcipher *tfm, const u8 *key,
++				 unsigned int len)
+ {
+-	struct geode_aes_op *op = crypto_tfm_ctx(tfm);
++	struct geode_aes_tfm_ctx *tctx = crypto_skcipher_ctx(tfm);
+ 	unsigned int ret;
+ 
+-	op->keylen = len;
++	tctx->keylen = len;
+ 
+ 	if (len == AES_KEYSIZE_128) {
+-		memcpy(op->key, key, len);
++		memcpy(tctx->key, key, len);
+ 		return 0;
+ 	}
+ 
+ 	if (len != AES_KEYSIZE_192 && len != AES_KEYSIZE_256) {
+ 		/* not supported at all */
+-		tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
++		crypto_skcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
+ 		return -EINVAL;
+ 	}
+ 
+ 	/*
+ 	 * The requested key size is not supported by HW, do a fallback
+ 	 */
+-	crypto_skcipher_clear_flags(op->fallback.blk, CRYPTO_TFM_REQ_MASK);
+-	crypto_skcipher_set_flags(op->fallback.blk,
+-				  tfm->crt_flags & CRYPTO_TFM_REQ_MASK);
+-
+-	ret = crypto_skcipher_setkey(op->fallback.blk, key, len);
+-	if (ret) {
+-		tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK;
+-		tfm->crt_flags |= crypto_skcipher_get_flags(op->fallback.blk) &
+-				  CRYPTO_TFM_RES_MASK;
+-	}
++	crypto_skcipher_clear_flags(tctx->fallback.skcipher,
++				    CRYPTO_TFM_REQ_MASK);
++	crypto_skcipher_set_flags(tctx->fallback.skcipher,
++				  crypto_skcipher_get_flags(tfm) &
++				  CRYPTO_TFM_REQ_MASK);
++	ret = crypto_skcipher_setkey(tctx->fallback.skcipher, key, len);
++	crypto_skcipher_set_flags(tfm,
++				  crypto_skcipher_get_flags(tctx->fallback.skcipher) &
++				  CRYPTO_TFM_RES_MASK);
+ 	return ret;
+ }
+ 
+-static int fallback_blk_dec(struct blkcipher_desc *desc,
+-		struct scatterlist *dst, struct scatterlist *src,
+-		unsigned int nbytes)
+-{
+-	struct geode_aes_op *op = crypto_blkcipher_ctx(desc->tfm);
+-	SKCIPHER_REQUEST_ON_STACK(req, op->fallback.blk);
+-
+-	skcipher_request_set_tfm(req, op->fallback.blk);
+-	skcipher_request_set_callback(req, 0, NULL, NULL);
+-	skcipher_request_set_crypt(req, src, dst, nbytes, desc->info);
+-
+-	return crypto_skcipher_decrypt(req);
+-}
+-
+-static int fallback_blk_enc(struct blkcipher_desc *desc,
+-		struct scatterlist *dst, struct scatterlist *src,
+-		unsigned int nbytes)
+-{
+-	struct geode_aes_op *op = crypto_blkcipher_ctx(desc->tfm);
+-	SKCIPHER_REQUEST_ON_STACK(req, op->fallback.blk);
+-
+-	skcipher_request_set_tfm(req, op->fallback.blk);
+-	skcipher_request_set_callback(req, 0, NULL, NULL);
+-	skcipher_request_set_crypt(req, src, dst, nbytes, desc->info);
+-
+-	return crypto_skcipher_encrypt(req);
+-}
+-
+ static void
+ geode_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
+ {
+-	struct geode_aes_op *op = crypto_tfm_ctx(tfm);
++	const struct geode_aes_tfm_ctx *tctx = crypto_tfm_ctx(tfm);
+ 
+-	if (unlikely(op->keylen != AES_KEYSIZE_128)) {
+-		crypto_cipher_encrypt_one(op->fallback.cip, out, in);
++	if (unlikely(tctx->keylen != AES_KEYSIZE_128)) {
++		crypto_cipher_encrypt_one(tctx->fallback.cip, out, in);
+ 		return;
+ 	}
+ 
+-	op->src = (void *) in;
+-	op->dst = (void *) out;
+-	op->mode = AES_MODE_ECB;
+-	op->flags = 0;
+-	op->len = AES_BLOCK_SIZE;
+-	op->dir = AES_DIR_ENCRYPT;
+-
+-	geode_aes_crypt(op);
++	geode_aes_crypt(tctx, in, out, AES_BLOCK_SIZE, NULL,
++			AES_MODE_ECB, AES_DIR_ENCRYPT);
+ }
+ 
+ 
+ static void
+ geode_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
+ {
+-	struct geode_aes_op *op = crypto_tfm_ctx(tfm);
++	const struct geode_aes_tfm_ctx *tctx = crypto_tfm_ctx(tfm);
+ 
+-	if (unlikely(op->keylen != AES_KEYSIZE_128)) {
+-		crypto_cipher_decrypt_one(op->fallback.cip, out, in);
++	if (unlikely(tctx->keylen != AES_KEYSIZE_128)) {
++		crypto_cipher_decrypt_one(tctx->fallback.cip, out, in);
+ 		return;
+ 	}
+ 
+-	op->src = (void *) in;
+-	op->dst = (void *) out;
+-	op->mode = AES_MODE_ECB;
+-	op->flags = 0;
+-	op->len = AES_BLOCK_SIZE;
+-	op->dir = AES_DIR_DECRYPT;
+-
+-	geode_aes_crypt(op);
++	geode_aes_crypt(tctx, in, out, AES_BLOCK_SIZE, NULL,
++			AES_MODE_ECB, AES_DIR_DECRYPT);
+ }
+ 
+ static int fallback_init_cip(struct crypto_tfm *tfm)
+ {
+ 	const char *name = crypto_tfm_alg_name(tfm);
+-	struct geode_aes_op *op = crypto_tfm_ctx(tfm);
++	struct geode_aes_tfm_ctx *tctx = crypto_tfm_ctx(tfm);
+ 
+-	op->fallback.cip = crypto_alloc_cipher(name, 0,
+-				CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK);
++	tctx->fallback.cip = crypto_alloc_cipher(name, 0,
++						 CRYPTO_ALG_NEED_FALLBACK);
+ 
+-	if (IS_ERR(op->fallback.cip)) {
++	if (IS_ERR(tctx->fallback.cip)) {
+ 		printk(KERN_ERR "Error allocating fallback algo %s\n", name);
+-		return PTR_ERR(op->fallback.cip);
++		return PTR_ERR(tctx->fallback.cip);
+ 	}
+ 
+ 	return 0;
+@@ -271,10 +226,9 @@ static int fallback_init_cip(struct crypto_tfm *tfm)
+ 
+ static void fallback_exit_cip(struct crypto_tfm *tfm)
+ {
+-	struct geode_aes_op *op = crypto_tfm_ctx(tfm);
++	struct geode_aes_tfm_ctx *tctx = crypto_tfm_ctx(tfm);
+ 
+-	crypto_free_cipher(op->fallback.cip);
+-	op->fallback.cip = NULL;
++	crypto_free_cipher(tctx->fallback.cip);
+ }
+ 
+ static struct crypto_alg geode_alg = {
+@@ -287,7 +241,7 @@ static struct crypto_alg geode_alg = {
+ 	.cra_init			=	fallback_init_cip,
+ 	.cra_exit			=	fallback_exit_cip,
+ 	.cra_blocksize		=	AES_BLOCK_SIZE,
+-	.cra_ctxsize		=	sizeof(struct geode_aes_op),
++	.cra_ctxsize		=	sizeof(struct geode_aes_tfm_ctx),
+ 	.cra_module			=	THIS_MODULE,
+ 	.cra_u				=	{
+ 		.cipher	=	{
+@@ -300,222 +254,126 @@ static struct crypto_alg geode_alg = {
+ 	}
+ };
+ 
+-static int
+-geode_cbc_decrypt(struct blkcipher_desc *desc,
+-		  struct scatterlist *dst, struct scatterlist *src,
+-		  unsigned int nbytes)
++static int geode_init_skcipher(struct crypto_skcipher *tfm)
+ {
+-	struct geode_aes_op *op = crypto_blkcipher_ctx(desc->tfm);
+-	struct blkcipher_walk walk;
+-	int err, ret;
+-
+-	if (nbytes % AES_BLOCK_SIZE)
+-		return -EINVAL;
+-
+-	if (unlikely(op->keylen != AES_KEYSIZE_128))
+-		return fallback_blk_dec(desc, dst, src, nbytes);
++	const char *name = crypto_tfm_alg_name(&tfm->base);
++	struct geode_aes_tfm_ctx *tctx = crypto_skcipher_ctx(tfm);
+ 
+-	blkcipher_walk_init(&walk, dst, src, nbytes);
+-	err = blkcipher_walk_virt(desc, &walk);
+-	op->iv = walk.iv;
+-
+-	while ((nbytes = walk.nbytes)) {
+-		op->src = walk.src.virt.addr,
+-		op->dst = walk.dst.virt.addr;
+-		op->mode = AES_MODE_CBC;
+-		op->len = nbytes - (nbytes % AES_BLOCK_SIZE);
+-		op->dir = AES_DIR_DECRYPT;
+-
+-		ret = geode_aes_crypt(op);
+-
+-		nbytes -= ret;
+-		err = blkcipher_walk_done(desc, &walk, nbytes);
++	tctx->fallback.skcipher =
++		crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK |
++				      CRYPTO_ALG_ASYNC);
++	if (IS_ERR(tctx->fallback.skcipher)) {
++		printk(KERN_ERR "Error allocating fallback algo %s\n", name);
++		return PTR_ERR(tctx->fallback.skcipher);
+ 	}
+ 
+-	return err;
++	crypto_skcipher_set_reqsize(tfm, sizeof(struct skcipher_request) +
++				    crypto_skcipher_reqsize(tctx->fallback.skcipher));
++	return 0;
+ }
+ 
+-static int
+-geode_cbc_encrypt(struct blkcipher_desc *desc,
+-		  struct scatterlist *dst, struct scatterlist *src,
+-		  unsigned int nbytes)
++static void geode_exit_skcipher(struct crypto_skcipher *tfm)
+ {
+-	struct geode_aes_op *op = crypto_blkcipher_ctx(desc->tfm);
+-	struct blkcipher_walk walk;
+-	int err, ret;
++	struct geode_aes_tfm_ctx *tctx = crypto_skcipher_ctx(tfm);
+ 
+-	if (nbytes % AES_BLOCK_SIZE)
+-		return -EINVAL;
+-
+-	if (unlikely(op->keylen != AES_KEYSIZE_128))
+-		return fallback_blk_enc(desc, dst, src, nbytes);
++	crypto_free_skcipher(tctx->fallback.skcipher);
++}
+ 
+-	blkcipher_walk_init(&walk, dst, src, nbytes);
+-	err = blkcipher_walk_virt(desc, &walk);
+-	op->iv = walk.iv;
++static int geode_skcipher_crypt(struct skcipher_request *req, int mode, int dir)
++{
++	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
++	const struct geode_aes_tfm_ctx *tctx = crypto_skcipher_ctx(tfm);
++	struct skcipher_walk walk;
++	unsigned int nbytes;
++	int err;
++
++	if (unlikely(tctx->keylen != AES_KEYSIZE_128)) {
++		struct skcipher_request *subreq = skcipher_request_ctx(req);
++
++		*subreq = *req;
++		skcipher_request_set_tfm(subreq, tctx->fallback.skcipher);
++		if (dir == AES_DIR_DECRYPT)
++			return crypto_skcipher_decrypt(subreq);
++		else
++			return crypto_skcipher_encrypt(subreq);
++	}
+ 
+-	while ((nbytes = walk.nbytes)) {
+-		op->src = walk.src.virt.addr,
+-		op->dst = walk.dst.virt.addr;
+-		op->mode = AES_MODE_CBC;
+-		op->len = nbytes - (nbytes % AES_BLOCK_SIZE);
+-		op->dir = AES_DIR_ENCRYPT;
++	err = skcipher_walk_virt(&walk, req, false);
+ 
+-		ret = geode_aes_crypt(op);
+-		nbytes -= ret;
+-		err = blkcipher_walk_done(desc, &walk, nbytes);
++	while ((nbytes = walk.nbytes) != 0) {
++		geode_aes_crypt(tctx, walk.src.virt.addr, walk.dst.virt.addr,
++				round_down(nbytes, AES_BLOCK_SIZE),
++				walk.iv, mode, dir);
++		err = skcipher_walk_done(&walk, nbytes % AES_BLOCK_SIZE);
+ 	}
+ 
+ 	return err;
+ }
+ 
+-static int fallback_init_blk(struct crypto_tfm *tfm)
++static int geode_cbc_encrypt(struct skcipher_request *req)
+ {
+-	const char *name = crypto_tfm_alg_name(tfm);
+-	struct geode_aes_op *op = crypto_tfm_ctx(tfm);
+-
+-	op->fallback.blk = crypto_alloc_skcipher(name, 0,
+-						 CRYPTO_ALG_ASYNC |
+-						 CRYPTO_ALG_NEED_FALLBACK);
+-
+-	if (IS_ERR(op->fallback.blk)) {
+-		printk(KERN_ERR "Error allocating fallback algo %s\n", name);
+-		return PTR_ERR(op->fallback.blk);
+-	}
+-
+-	return 0;
++	return geode_skcipher_crypt(req, AES_MODE_CBC, AES_DIR_ENCRYPT);
+ }
+ 
+-static void fallback_exit_blk(struct crypto_tfm *tfm)
++static int geode_cbc_decrypt(struct skcipher_request *req)
+ {
+-	struct geode_aes_op *op = crypto_tfm_ctx(tfm);
+-
+-	crypto_free_skcipher(op->fallback.blk);
+-	op->fallback.blk = NULL;
++	return geode_skcipher_crypt(req, AES_MODE_CBC, AES_DIR_DECRYPT);
+ }
+ 
+-static struct crypto_alg geode_cbc_alg = {
+-	.cra_name		=	"cbc(aes)",
+-	.cra_driver_name	=	"cbc-aes-geode",
+-	.cra_priority		=	400,
+-	.cra_flags			=	CRYPTO_ALG_TYPE_BLKCIPHER |
+-						CRYPTO_ALG_KERN_DRIVER_ONLY |
+-						CRYPTO_ALG_NEED_FALLBACK,
+-	.cra_init			=	fallback_init_blk,
+-	.cra_exit			=	fallback_exit_blk,
+-	.cra_blocksize		=	AES_BLOCK_SIZE,
+-	.cra_ctxsize		=	sizeof(struct geode_aes_op),
+-	.cra_alignmask		=	15,
+-	.cra_type			=	&crypto_blkcipher_type,
+-	.cra_module			=	THIS_MODULE,
+-	.cra_u				=	{
+-		.blkcipher	=	{
+-			.min_keysize	=	AES_MIN_KEY_SIZE,
+-			.max_keysize	=	AES_MAX_KEY_SIZE,
+-			.setkey			=	geode_setkey_blk,
+-			.encrypt		=	geode_cbc_encrypt,
+-			.decrypt		=	geode_cbc_decrypt,
+-			.ivsize			=	AES_BLOCK_SIZE,
+-		}
+-	}
+-};
+-
+-static int
+-geode_ecb_decrypt(struct blkcipher_desc *desc,
+-		  struct scatterlist *dst, struct scatterlist *src,
+-		  unsigned int nbytes)
++static int geode_ecb_encrypt(struct skcipher_request *req)
+ {
+-	struct geode_aes_op *op = crypto_blkcipher_ctx(desc->tfm);
+-	struct blkcipher_walk walk;
+-	int err, ret;
+-
+-	if (nbytes % AES_BLOCK_SIZE)
+-		return -EINVAL;
+-
+-	if (unlikely(op->keylen != AES_KEYSIZE_128))
+-		return fallback_blk_dec(desc, dst, src, nbytes);
+-
+-	blkcipher_walk_init(&walk, dst, src, nbytes);
+-	err = blkcipher_walk_virt(desc, &walk);
+-
+-	while ((nbytes = walk.nbytes)) {
+-		op->src = walk.src.virt.addr,
+-		op->dst = walk.dst.virt.addr;
+-		op->mode = AES_MODE_ECB;
+-		op->len = nbytes - (nbytes % AES_BLOCK_SIZE);
+-		op->dir = AES_DIR_DECRYPT;
+-
+-		ret = geode_aes_crypt(op);
+-		nbytes -= ret;
+-		err = blkcipher_walk_done(desc, &walk, nbytes);
+-	}
+-
+-	return err;
++	return geode_skcipher_crypt(req, AES_MODE_ECB, AES_DIR_ENCRYPT);
+ }
+ 
+-static int
+-geode_ecb_encrypt(struct blkcipher_desc *desc,
+-		  struct scatterlist *dst, struct scatterlist *src,
+-		  unsigned int nbytes)
++static int geode_ecb_decrypt(struct skcipher_request *req)
+ {
+-	struct geode_aes_op *op = crypto_blkcipher_ctx(desc->tfm);
+-	struct blkcipher_walk walk;
+-	int err, ret;
+-
+-	if (nbytes % AES_BLOCK_SIZE)
+-		return -EINVAL;
+-
+-	if (unlikely(op->keylen != AES_KEYSIZE_128))
+-		return fallback_blk_enc(desc, dst, src, nbytes);
+-
+-	blkcipher_walk_init(&walk, dst, src, nbytes);
+-	err = blkcipher_walk_virt(desc, &walk);
+-
+-	while ((nbytes = walk.nbytes)) {
+-		op->src = walk.src.virt.addr,
+-		op->dst = walk.dst.virt.addr;
+-		op->mode = AES_MODE_ECB;
+-		op->len = nbytes - (nbytes % AES_BLOCK_SIZE);
+-		op->dir = AES_DIR_ENCRYPT;
+-
+-		ret = geode_aes_crypt(op);
+-		nbytes -= ret;
+-		ret =  blkcipher_walk_done(desc, &walk, nbytes);
+-	}
+-
+-	return err;
++	return geode_skcipher_crypt(req, AES_MODE_ECB, AES_DIR_DECRYPT);
+ }
+ 
+-static struct crypto_alg geode_ecb_alg = {
+-	.cra_name			=	"ecb(aes)",
+-	.cra_driver_name	=	"ecb-aes-geode",
+-	.cra_priority		=	400,
+-	.cra_flags			=	CRYPTO_ALG_TYPE_BLKCIPHER |
+-						CRYPTO_ALG_KERN_DRIVER_ONLY |
+-						CRYPTO_ALG_NEED_FALLBACK,
+-	.cra_init			=	fallback_init_blk,
+-	.cra_exit			=	fallback_exit_blk,
+-	.cra_blocksize		=	AES_BLOCK_SIZE,
+-	.cra_ctxsize		=	sizeof(struct geode_aes_op),
+-	.cra_alignmask		=	15,
+-	.cra_type			=	&crypto_blkcipher_type,
+-	.cra_module			=	THIS_MODULE,
+-	.cra_u				=	{
+-		.blkcipher	=	{
+-			.min_keysize	=	AES_MIN_KEY_SIZE,
+-			.max_keysize	=	AES_MAX_KEY_SIZE,
+-			.setkey			=	geode_setkey_blk,
+-			.encrypt		=	geode_ecb_encrypt,
+-			.decrypt		=	geode_ecb_decrypt,
+-		}
+-	}
++static struct skcipher_alg geode_skcipher_algs[] = {
++	{
++		.base.cra_name		= "cbc(aes)",
++		.base.cra_driver_name	= "cbc-aes-geode",
++		.base.cra_priority	= 400,
++		.base.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |
++					  CRYPTO_ALG_NEED_FALLBACK,
++		.base.cra_blocksize	= AES_BLOCK_SIZE,
++		.base.cra_ctxsize	= sizeof(struct geode_aes_tfm_ctx),
++		.base.cra_alignmask	= 15,
++		.base.cra_module	= THIS_MODULE,
++		.init			= geode_init_skcipher,
++		.exit			= geode_exit_skcipher,
++		.setkey			= geode_setkey_skcipher,
++		.encrypt		= geode_cbc_encrypt,
++		.decrypt		= geode_cbc_decrypt,
++		.min_keysize		= AES_MIN_KEY_SIZE,
++		.max_keysize		= AES_MAX_KEY_SIZE,
++		.ivsize			= AES_BLOCK_SIZE,
++	}, {
++		.base.cra_name		= "ecb(aes)",
++		.base.cra_driver_name	= "ecb-aes-geode",
++		.base.cra_priority	= 400,
++		.base.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |
++					  CRYPTO_ALG_NEED_FALLBACK,
++		.base.cra_blocksize	= AES_BLOCK_SIZE,
++		.base.cra_ctxsize	= sizeof(struct geode_aes_tfm_ctx),
++		.base.cra_alignmask	= 15,
++		.base.cra_module	= THIS_MODULE,
++		.init			= geode_init_skcipher,
++		.exit			= geode_exit_skcipher,
++		.setkey			= geode_setkey_skcipher,
++		.encrypt		= geode_ecb_encrypt,
++		.decrypt		= geode_ecb_decrypt,
++		.min_keysize		= AES_MIN_KEY_SIZE,
++		.max_keysize		= AES_MAX_KEY_SIZE,
++	},
+ };
+ 
+ static void geode_aes_remove(struct pci_dev *dev)
+ {
+ 	crypto_unregister_alg(&geode_alg);
+-	crypto_unregister_alg(&geode_ecb_alg);
+-	crypto_unregister_alg(&geode_cbc_alg);
++	crypto_unregister_skciphers(geode_skcipher_algs,
++				    ARRAY_SIZE(geode_skcipher_algs));
+ 
+ 	pci_iounmap(dev, _iobase);
+ 	_iobase = NULL;
+@@ -553,20 +411,14 @@ static int geode_aes_probe(struct pci_dev *dev, const struct pci_device_id *id)
+ 	if (ret)
+ 		goto eiomap;
+ 
+-	ret = crypto_register_alg(&geode_ecb_alg);
++	ret = crypto_register_skciphers(geode_skcipher_algs,
++					ARRAY_SIZE(geode_skcipher_algs));
+ 	if (ret)
+ 		goto ealg;
+ 
+-	ret = crypto_register_alg(&geode_cbc_alg);
+-	if (ret)
+-		goto eecb;
+-
+ 	dev_notice(&dev->dev, "GEODE AES engine enabled.\n");
+ 	return 0;
+ 
+- eecb:
+-	crypto_unregister_alg(&geode_ecb_alg);
+-
+  ealg:
+ 	crypto_unregister_alg(&geode_alg);
+ 
+diff --git a/drivers/crypto/geode-aes.h b/drivers/crypto/geode-aes.h
+index c5763a041bb8..157443dc6d8a 100644
+--- a/drivers/crypto/geode-aes.h
++++ b/drivers/crypto/geode-aes.h
+@@ -50,21 +50,10 @@
+ 
+ #define AES_OP_TIMEOUT    0x50000
+ 
+-struct geode_aes_op {
+-
+-	void *src;
+-	void *dst;
+-
+-	u32 mode;
+-	u32 dir;
+-	u32 flags;
+-	int len;
+-
++struct geode_aes_tfm_ctx {
+ 	u8 key[AES_KEYSIZE_128];
+-	u8 *iv;
+-
+ 	union {
+-		struct crypto_skcipher *blk;
++		struct crypto_skcipher *skcipher;
+ 		struct crypto_cipher *cip;
+ 	} fallback;
+ 	u32 keylen;
+diff --git a/drivers/crypto/picoxcell_crypto.c b/drivers/crypto/picoxcell_crypto.c
+index 321d5e2ac833..e2491754c468 100644
+--- a/drivers/crypto/picoxcell_crypto.c
++++ b/drivers/crypto/picoxcell_crypto.c
+@@ -1616,6 +1616,11 @@ static const struct of_device_id spacc_of_id_table[] = {
+ MODULE_DEVICE_TABLE(of, spacc_of_id_table);
+ #endif /* CONFIG_OF */
+ 
++static void spacc_tasklet_kill(void *data)
++{
++	tasklet_kill(data);
++}
++
+ static int spacc_probe(struct platform_device *pdev)
+ {
+ 	int i, err, ret;
+@@ -1659,6 +1664,14 @@ static int spacc_probe(struct platform_device *pdev)
+ 		return -ENXIO;
+ 	}
+ 
++	tasklet_init(&engine->complete, spacc_spacc_complete,
++		     (unsigned long)engine);
++
++	ret = devm_add_action(&pdev->dev, spacc_tasklet_kill,
++			      &engine->complete);
++	if (ret)
++		return ret;
++
+ 	if (devm_request_irq(&pdev->dev, irq->start, spacc_spacc_irq, 0,
+ 			     engine->name, engine)) {
+ 		dev_err(engine->dev, "failed to request IRQ\n");
+@@ -1716,8 +1729,6 @@ static int spacc_probe(struct platform_device *pdev)
+ 	INIT_LIST_HEAD(&engine->completed);
+ 	INIT_LIST_HEAD(&engine->in_progress);
+ 	engine->in_flight = 0;
+-	tasklet_init(&engine->complete, spacc_spacc_complete,
+-		     (unsigned long)engine);
+ 
+ 	platform_set_drvdata(pdev, engine);
+ 
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+index 8403b6a9a77b..d8c53ddc23b4 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+@@ -248,7 +248,8 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
+ 		drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port);
+ 	}
+ 
+-	ret = drm_dp_update_payload_part1(mst_mgr);
++	/* It's OK for this to fail */
++	drm_dp_update_payload_part1(mst_mgr);
+ 
+ 	/* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
+ 	 * AUX message. The sequence is slot 1-63 allocated sequence for each
+@@ -257,9 +258,6 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
+ 
+ 	get_payload_table(aconnector, proposed_table);
+ 
+-	if (ret)
+-		return false;
+-
+ 	return true;
+ }
+ 
+@@ -310,7 +308,6 @@ bool dm_helpers_dp_mst_send_payload_allocation(
+ 	struct amdgpu_dm_connector *aconnector;
+ 	struct drm_dp_mst_topology_mgr *mst_mgr;
+ 	struct drm_dp_mst_port *mst_port;
+-	int ret;
+ 
+ 	aconnector = stream->sink->priv;
+ 
+@@ -324,10 +321,8 @@ bool dm_helpers_dp_mst_send_payload_allocation(
+ 	if (!mst_mgr->mst_state)
+ 		return false;
+ 
+-	ret = drm_dp_update_payload_part2(mst_mgr);
+-
+-	if (ret)
+-		return false;
++	/* It's OK for this to fail */
++	drm_dp_update_payload_part2(mst_mgr);
+ 
+ 	if (!enable)
+ 		drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port);
+diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
+index d73281095fac..976109c20d49 100644
+--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
++++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
+@@ -79,7 +79,11 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c)
+ 	struct videomode vm;
+ 	unsigned long prate;
+ 	unsigned int cfg;
+-	int div;
++	int div, ret;
++
++	ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
++	if (ret)
++		return;
+ 
+ 	vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay;
+ 	vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end;
+@@ -138,6 +142,8 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c)
+ 			   ATMEL_HLCDC_VSPSU | ATMEL_HLCDC_VSPHO |
+ 			   ATMEL_HLCDC_GUARDTIME_MASK | ATMEL_HLCDC_MODE_MASK,
+ 			   cfg);
++
++	clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
+ }
+ 
+ static enum drm_mode_status
+diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
+index 58fe3945494c..bf4eed5f6a7e 100644
+--- a/drivers/gpu/drm/drm_dp_mst_topology.c
++++ b/drivers/gpu/drm/drm_dp_mst_topology.c
+@@ -2125,6 +2125,7 @@ static bool drm_dp_get_vc_payload_bw(int dp_link_bw,
+ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool mst_state)
+ {
+ 	int ret = 0;
++	int i = 0;
+ 	struct drm_dp_mst_branch *mstb = NULL;
+ 
+ 	mutex_lock(&mgr->lock);
+@@ -2185,10 +2186,21 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms
+ 		/* this can fail if the device is gone */
+ 		drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 0);
+ 		ret = 0;
++		mutex_lock(&mgr->payload_lock);
+ 		memset(mgr->payloads, 0, mgr->max_payloads * sizeof(struct drm_dp_payload));
+ 		mgr->payload_mask = 0;
+ 		set_bit(0, &mgr->payload_mask);
++		for (i = 0; i < mgr->max_payloads; i++) {
++			struct drm_dp_vcpi *vcpi = mgr->proposed_vcpis[i];
++
++			if (vcpi) {
++				vcpi->vcpi = 0;
++				vcpi->num_slots = 0;
++			}
++			mgr->proposed_vcpis[i] = NULL;
++		}
+ 		mgr->vcpi_mask = 0;
++		mutex_unlock(&mgr->payload_lock);
+ 	}
+ 
+ out_unlock:
+diff --git a/drivers/gpu/drm/drm_rect.c b/drivers/gpu/drm/drm_rect.c
+index 8c057829b804..0f5a0c64c4c4 100644
+--- a/drivers/gpu/drm/drm_rect.c
++++ b/drivers/gpu/drm/drm_rect.c
+@@ -52,7 +52,12 @@ EXPORT_SYMBOL(drm_rect_intersect);
+ 
+ static u32 clip_scaled(u32 src, u32 dst, u32 clip)
+ {
+-	u64 tmp = mul_u32_u32(src, dst - clip);
++	u64 tmp;
++
++	if (dst == 0)
++		return 0;
++
++	tmp = mul_u32_u32(src, dst - clip);
+ 
+ 	/*
+ 	 * Round toward 1.0 when clipping so that we don't accidentally
+diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c
+index 6a1ebdace391..6253717d2e0c 100644
+--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c
++++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c
+@@ -139,7 +139,7 @@ static void mdp4_dsi_encoder_enable(struct drm_encoder *encoder)
+ 	if (mdp4_dsi_encoder->enabled)
+ 		return;
+ 
+-	 mdp4_crtc_set_config(encoder->crtc,
++	mdp4_crtc_set_config(encoder->crtc,
+ 			MDP4_DMA_CONFIG_PACK_ALIGN_MSB |
+ 			MDP4_DMA_CONFIG_DEFLKR_EN |
+ 			MDP4_DMA_CONFIG_DITHER_EN |
+diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+index 97a0573cc514..79eb11cd185d 100644
+--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
++++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+@@ -357,8 +357,7 @@ static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi,
+ static u16 sun6i_dsi_get_video_start_delay(struct sun6i_dsi *dsi,
+ 					   struct drm_display_mode *mode)
+ {
+-	u16 start = clamp(mode->vtotal - mode->vdisplay - 10, 8, 100);
+-	u16 delay = mode->vtotal - (mode->vsync_end - mode->vdisplay) + start;
++	u16 delay = mode->vtotal - (mode->vsync_end - mode->vdisplay) + 1;
+ 
+ 	if (delay > mode->vtotal)
+ 		delay = delay % mode->vtotal;
+diff --git a/drivers/hv/hv_balloon.c b/drivers/hv/hv_balloon.c
+index d2a735ac9ba1..9ca0706a9d40 100644
+--- a/drivers/hv/hv_balloon.c
++++ b/drivers/hv/hv_balloon.c
+@@ -1215,10 +1215,7 @@ static unsigned int alloc_balloon_pages(struct hv_dynmem_device *dm,
+ 	unsigned int i = 0;
+ 	struct page *pg;
+ 
+-	if (num_pages < alloc_unit)
+-		return 0;
+-
+-	for (i = 0; (i * alloc_unit) < num_pages; i++) {
++	for (i = 0; i < num_pages / alloc_unit; i++) {
+ 		if (bl_resp->hdr.size + sizeof(union dm_mem_page_range) >
+ 			PAGE_SIZE)
+ 			return i * alloc_unit;
+@@ -1252,7 +1249,7 @@ static unsigned int alloc_balloon_pages(struct hv_dynmem_device *dm,
+ 
+ 	}
+ 
+-	return num_pages;
++	return i * alloc_unit;
+ }
+ 
+ static void balloon_up(struct work_struct *dummy)
+@@ -1267,9 +1264,6 @@ static void balloon_up(struct work_struct *dummy)
+ 	long avail_pages;
+ 	unsigned long floor;
+ 
+-	/* The host balloons pages in 2M granularity. */
+-	WARN_ON_ONCE(num_pages % PAGES_IN_2M != 0);
+-
+ 	/*
+ 	 * We will attempt 2M allocations. However, if we fail to
+ 	 * allocate 2M chunks, we will go back to 4k allocations.
+@@ -1279,14 +1273,13 @@ static void balloon_up(struct work_struct *dummy)
+ 	avail_pages = si_mem_available();
+ 	floor = compute_balloon_floor();
+ 
+-	/* Refuse to balloon below the floor, keep the 2M granularity. */
++	/* Refuse to balloon below the floor. */
+ 	if (avail_pages < num_pages || avail_pages - num_pages < floor) {
+ 		pr_warn("Balloon request will be partially fulfilled. %s\n",
+ 			avail_pages < num_pages ? "Not enough memory." :
+ 			"Balloon floor reached.");
+ 
+ 		num_pages = avail_pages > floor ? (avail_pages - floor) : 0;
+-		num_pages -= num_pages % PAGES_IN_2M;
+ 	}
+ 
+ 	while (!done) {
+diff --git a/drivers/infiniband/core/umem_odp.c b/drivers/infiniband/core/umem_odp.c
+index 6ec748eccff7..4bda1242df87 100644
+--- a/drivers/infiniband/core/umem_odp.c
++++ b/drivers/infiniband/core/umem_odp.c
+@@ -689,7 +689,7 @@ int ib_umem_odp_map_dma_pages(struct ib_umem *umem, u64 user_virt, u64 bcnt,
+ 
+ 	while (bcnt > 0) {
+ 		const size_t gup_num_pages = min_t(size_t,
+-				(bcnt + BIT(page_shift) - 1) >> page_shift,
++				ALIGN(bcnt, PAGE_SIZE) / PAGE_SIZE,
+ 				PAGE_SIZE / sizeof(struct page *));
+ 
+ 		down_read(&owning_mm->mmap_sem);
+diff --git a/drivers/infiniband/hw/mlx5/gsi.c b/drivers/infiniband/hw/mlx5/gsi.c
+index 4950df3f71b6..5c73c0a790fa 100644
+--- a/drivers/infiniband/hw/mlx5/gsi.c
++++ b/drivers/infiniband/hw/mlx5/gsi.c
+@@ -507,8 +507,7 @@ int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr,
+ 		ret = ib_post_send(tx_qp, &cur_wr.wr, bad_wr);
+ 		if (ret) {
+ 			/* Undo the effect of adding the outstanding wr */
+-			gsi->outstanding_pi = (gsi->outstanding_pi - 1) %
+-					      gsi->cap.max_send_wr;
++			gsi->outstanding_pi--;
+ 			goto err;
+ 		}
+ 		spin_unlock_irqrestore(&gsi->lock, flags);
+diff --git a/drivers/md/bcache/bcache.h b/drivers/md/bcache/bcache.h
+index 4677b18ac281..2a2f189dd37c 100644
+--- a/drivers/md/bcache/bcache.h
++++ b/drivers/md/bcache/bcache.h
+@@ -329,6 +329,9 @@ struct cached_dev {
+ 	 */
+ 	atomic_t		has_dirty;
+ 
++#define BCH_CACHE_READA_ALL		0
++#define BCH_CACHE_READA_META_ONLY	1
++	unsigned int		cache_readahead_policy;
+ 	struct bch_ratelimit	writeback_rate;
+ 	struct delayed_work	writeback_rate_update;
+ 
+diff --git a/drivers/md/bcache/request.c b/drivers/md/bcache/request.c
+index 4ca3e3d3f9c7..c1e487d1261c 100644
+--- a/drivers/md/bcache/request.c
++++ b/drivers/md/bcache/request.c
+@@ -391,13 +391,20 @@ static bool check_should_bypass(struct cached_dev *dc, struct bio *bio)
+ 		goto skip;
+ 
+ 	/*
+-	 * Flag for bypass if the IO is for read-ahead or background,
+-	 * unless the read-ahead request is for metadata
++	 * If the bio is for read-ahead or background IO, bypass it or
++	 * not depends on the following situations,
++	 * - If the IO is for meta data, always cache it and no bypass
++	 * - If the IO is not meta data, check dc->cache_reada_policy,
++	 *      BCH_CACHE_READA_ALL: cache it and not bypass
++	 *      BCH_CACHE_READA_META_ONLY: not cache it and bypass
++	 * That is, read-ahead request for metadata always get cached
+ 	 * (eg, for gfs2 or xfs).
+ 	 */
+-	if (bio->bi_opf & (REQ_RAHEAD|REQ_BACKGROUND) &&
+-	    !(bio->bi_opf & (REQ_META|REQ_PRIO)))
+-		goto skip;
++	if ((bio->bi_opf & (REQ_RAHEAD|REQ_BACKGROUND))) {
++		if (!(bio->bi_opf & (REQ_META|REQ_PRIO)) &&
++		    (dc->cache_readahead_policy != BCH_CACHE_READA_ALL))
++			goto skip;
++	}
+ 
+ 	if (bio->bi_iter.bi_sector & (c->sb.block_size - 1) ||
+ 	    bio_sectors(bio) & (c->sb.block_size - 1)) {
+diff --git a/drivers/md/bcache/sysfs.c b/drivers/md/bcache/sysfs.c
+index 3e8d1f1b562f..591d9c8107dd 100644
+--- a/drivers/md/bcache/sysfs.c
++++ b/drivers/md/bcache/sysfs.c
+@@ -25,6 +25,12 @@ static const char * const bch_cache_modes[] = {
+ 	NULL
+ };
+ 
++static const char * const bch_reada_cache_policies[] = {
++	"all",
++	"meta-only",
++	NULL
++};
++
+ /* Default is -1; we skip past it for stop_when_cache_set_failed */
+ static const char * const bch_stop_on_failure_modes[] = {
+ 	"auto",
+@@ -94,6 +100,7 @@ rw_attribute(congested_write_threshold_us);
+ rw_attribute(sequential_cutoff);
+ rw_attribute(data_csum);
+ rw_attribute(cache_mode);
++rw_attribute(readahead_cache_policy);
+ rw_attribute(stop_when_cache_set_failed);
+ rw_attribute(writeback_metadata);
+ rw_attribute(writeback_running);
+@@ -160,6 +167,11 @@ SHOW(__bch_cached_dev)
+ 					       bch_cache_modes,
+ 					       BDEV_CACHE_MODE(&dc->sb));
+ 
++	if (attr == &sysfs_readahead_cache_policy)
++		return bch_snprint_string_list(buf, PAGE_SIZE,
++					      bch_reada_cache_policies,
++					      dc->cache_readahead_policy);
++
+ 	if (attr == &sysfs_stop_when_cache_set_failed)
+ 		return bch_snprint_string_list(buf, PAGE_SIZE,
+ 					       bch_stop_on_failure_modes,
+@@ -324,6 +336,15 @@ STORE(__cached_dev)
+ 		}
+ 	}
+ 
++	if (attr == &sysfs_readahead_cache_policy) {
++		v = __sysfs_match_string(bch_reada_cache_policies, -1, buf);
++		if (v < 0)
++			return v;
++
++		if ((unsigned int) v != dc->cache_readahead_policy)
++			dc->cache_readahead_policy = v;
++	}
++
+ 	if (attr == &sysfs_stop_when_cache_set_failed) {
+ 		v = __sysfs_match_string(bch_stop_on_failure_modes, -1, buf);
+ 		if (v < 0)
+@@ -417,6 +438,7 @@ static struct attribute *bch_cached_dev_files[] = {
+ 	&sysfs_data_csum,
+ #endif
+ 	&sysfs_cache_mode,
++	&sysfs_readahead_cache_policy,
+ 	&sysfs_stop_when_cache_set_failed,
+ 	&sysfs_writeback_metadata,
+ 	&sysfs_writeback_running,
+diff --git a/drivers/md/dm-crypt.c b/drivers/md/dm-crypt.c
+index 34f5de13a93d..750f8b34e693 100644
+--- a/drivers/md/dm-crypt.c
++++ b/drivers/md/dm-crypt.c
+@@ -482,8 +482,14 @@ static int crypt_iv_essiv_gen(struct crypt_config *cc, u8 *iv,
+ static int crypt_iv_benbi_ctr(struct crypt_config *cc, struct dm_target *ti,
+ 			      const char *opts)
+ {
+-	unsigned bs = crypto_skcipher_blocksize(any_tfm(cc));
+-	int log = ilog2(bs);
++	unsigned bs;
++	int log;
++
++	if (test_bit(CRYPT_MODE_INTEGRITY_AEAD, &cc->cipher_flags))
++		bs = crypto_aead_blocksize(any_tfm_aead(cc));
++	else
++		bs = crypto_skcipher_blocksize(any_tfm(cc));
++	log = ilog2(bs);
+ 
+ 	/* we need to calculate how far we must shift the sector count
+ 	 * to get the cipher block count, we use this shift in _gen */
+diff --git a/drivers/md/dm-writecache.c b/drivers/md/dm-writecache.c
+index 503c4265ecbe..820c2e07dadf 100644
+--- a/drivers/md/dm-writecache.c
++++ b/drivers/md/dm-writecache.c
+@@ -447,7 +447,13 @@ static void writecache_notify_io(unsigned long error, void *context)
+ 		complete(&endio->c);
+ }
+ 
+-static void ssd_commit_flushed(struct dm_writecache *wc)
++static void writecache_wait_for_ios(struct dm_writecache *wc, int direction)
++{
++	wait_event(wc->bio_in_progress_wait[direction],
++		   !atomic_read(&wc->bio_in_progress[direction]));
++}
++
++static void ssd_commit_flushed(struct dm_writecache *wc, bool wait_for_ios)
+ {
+ 	struct dm_io_region region;
+ 	struct dm_io_request req;
+@@ -493,17 +499,20 @@ static void ssd_commit_flushed(struct dm_writecache *wc)
+ 	writecache_notify_io(0, &endio);
+ 	wait_for_completion_io(&endio.c);
+ 
++	if (wait_for_ios)
++		writecache_wait_for_ios(wc, WRITE);
++
+ 	writecache_disk_flush(wc, wc->ssd_dev);
+ 
+ 	memset(wc->dirty_bitmap, 0, wc->dirty_bitmap_size);
+ }
+ 
+-static void writecache_commit_flushed(struct dm_writecache *wc)
++static void writecache_commit_flushed(struct dm_writecache *wc, bool wait_for_ios)
+ {
+ 	if (WC_MODE_PMEM(wc))
+ 		wmb();
+ 	else
+-		ssd_commit_flushed(wc);
++		ssd_commit_flushed(wc, wait_for_ios);
+ }
+ 
+ static void writecache_disk_flush(struct dm_writecache *wc, struct dm_dev *dev)
+@@ -527,12 +536,6 @@ static void writecache_disk_flush(struct dm_writecache *wc, struct dm_dev *dev)
+ 		writecache_error(wc, r, "error flushing metadata: %d", r);
+ }
+ 
+-static void writecache_wait_for_ios(struct dm_writecache *wc, int direction)
+-{
+-	wait_event(wc->bio_in_progress_wait[direction],
+-		   !atomic_read(&wc->bio_in_progress[direction]));
+-}
+-
+ #define WFE_RETURN_FOLLOWING	1
+ #define WFE_LOWEST_SEQ		2
+ 
+@@ -730,14 +733,12 @@ static void writecache_flush(struct dm_writecache *wc)
+ 		e = e2;
+ 		cond_resched();
+ 	}
+-	writecache_commit_flushed(wc);
+-
+-	writecache_wait_for_ios(wc, WRITE);
++	writecache_commit_flushed(wc, true);
+ 
+ 	wc->seq_count++;
+ 	pmem_assign(sb(wc)->seq_count, cpu_to_le64(wc->seq_count));
+ 	writecache_flush_region(wc, &sb(wc)->seq_count, sizeof sb(wc)->seq_count);
+-	writecache_commit_flushed(wc);
++	writecache_commit_flushed(wc, false);
+ 
+ 	wc->overwrote_committed = false;
+ 
+@@ -761,7 +762,7 @@ static void writecache_flush(struct dm_writecache *wc)
+ 	}
+ 
+ 	if (need_flush_after_free)
+-		writecache_commit_flushed(wc);
++		writecache_commit_flushed(wc, false);
+ }
+ 
+ static void writecache_flush_work(struct work_struct *work)
+@@ -814,7 +815,7 @@ static void writecache_discard(struct dm_writecache *wc, sector_t start, sector_
+ 	}
+ 
+ 	if (discarded_something)
+-		writecache_commit_flushed(wc);
++		writecache_commit_flushed(wc, false);
+ }
+ 
+ static bool writecache_wait_for_writeback(struct dm_writecache *wc)
+@@ -963,7 +964,7 @@ erase_this:
+ 
+ 	if (need_flush) {
+ 		writecache_flush_all_metadata(wc);
+-		writecache_commit_flushed(wc);
++		writecache_commit_flushed(wc, false);
+ 	}
+ 
+ 	wc_unlock(wc);
+@@ -1347,7 +1348,7 @@ static void __writecache_endio_pmem(struct dm_writecache *wc, struct list_head *
+ 			wc->writeback_size--;
+ 			n_walked++;
+ 			if (unlikely(n_walked >= ENDIO_LATENCY)) {
+-				writecache_commit_flushed(wc);
++				writecache_commit_flushed(wc, false);
+ 				wc_unlock(wc);
+ 				wc_lock(wc);
+ 				n_walked = 0;
+@@ -1428,7 +1429,7 @@ pop_from_list:
+ 			writecache_wait_for_ios(wc, READ);
+ 		}
+ 
+-		writecache_commit_flushed(wc);
++		writecache_commit_flushed(wc, false);
+ 
+ 		wc_unlock(wc);
+ 	}
+@@ -1759,10 +1760,10 @@ static int init_memory(struct dm_writecache *wc)
+ 		write_original_sector_seq_count(wc, &wc->entries[b], -1, -1);
+ 
+ 	writecache_flush_all_metadata(wc);
+-	writecache_commit_flushed(wc);
++	writecache_commit_flushed(wc, false);
+ 	pmem_assign(sb(wc)->magic, cpu_to_le32(MEMORY_SUPERBLOCK_MAGIC));
+ 	writecache_flush_region(wc, &sb(wc)->magic, sizeof sb(wc)->magic);
+-	writecache_commit_flushed(wc);
++	writecache_commit_flushed(wc, false);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/md/dm-zoned-metadata.c b/drivers/md/dm-zoned-metadata.c
+index c2c17149d968..086a870087cf 100644
+--- a/drivers/md/dm-zoned-metadata.c
++++ b/drivers/md/dm-zoned-metadata.c
+@@ -132,6 +132,7 @@ struct dmz_metadata {
+ 
+ 	sector_t		zone_bitmap_size;
+ 	unsigned int		zone_nr_bitmap_blocks;
++	unsigned int		zone_bits_per_mblk;
+ 
+ 	unsigned int		nr_bitmap_blocks;
+ 	unsigned int		nr_map_blocks;
+@@ -1165,7 +1166,10 @@ static int dmz_init_zones(struct dmz_metadata *zmd)
+ 
+ 	/* Init */
+ 	zmd->zone_bitmap_size = dev->zone_nr_blocks >> 3;
+-	zmd->zone_nr_bitmap_blocks = zmd->zone_bitmap_size >> DMZ_BLOCK_SHIFT;
++	zmd->zone_nr_bitmap_blocks =
++		max_t(sector_t, 1, zmd->zone_bitmap_size >> DMZ_BLOCK_SHIFT);
++	zmd->zone_bits_per_mblk = min_t(sector_t, dev->zone_nr_blocks,
++					DMZ_BLOCK_SIZE_BITS);
+ 
+ 	/* Allocate zone array */
+ 	zmd->zones = kcalloc(dev->nr_zones, sizeof(struct dm_zone), GFP_KERNEL);
+@@ -1982,7 +1986,7 @@ int dmz_copy_valid_blocks(struct dmz_metadata *zmd, struct dm_zone *from_zone,
+ 		dmz_release_mblock(zmd, to_mblk);
+ 		dmz_release_mblock(zmd, from_mblk);
+ 
+-		chunk_block += DMZ_BLOCK_SIZE_BITS;
++		chunk_block += zmd->zone_bits_per_mblk;
+ 	}
+ 
+ 	to_zone->weight = from_zone->weight;
+@@ -2043,7 +2047,7 @@ int dmz_validate_blocks(struct dmz_metadata *zmd, struct dm_zone *zone,
+ 
+ 		/* Set bits */
+ 		bit = chunk_block & DMZ_BLOCK_MASK_BITS;
+-		nr_bits = min(nr_blocks, DMZ_BLOCK_SIZE_BITS - bit);
++		nr_bits = min(nr_blocks, zmd->zone_bits_per_mblk - bit);
+ 
+ 		count = dmz_set_bits((unsigned long *)mblk->data, bit, nr_bits);
+ 		if (count) {
+@@ -2122,7 +2126,7 @@ int dmz_invalidate_blocks(struct dmz_metadata *zmd, struct dm_zone *zone,
+ 
+ 		/* Clear bits */
+ 		bit = chunk_block & DMZ_BLOCK_MASK_BITS;
+-		nr_bits = min(nr_blocks, DMZ_BLOCK_SIZE_BITS - bit);
++		nr_bits = min(nr_blocks, zmd->zone_bits_per_mblk - bit);
+ 
+ 		count = dmz_clear_bits((unsigned long *)mblk->data,
+ 				       bit, nr_bits);
+@@ -2182,6 +2186,7 @@ static int dmz_to_next_set_block(struct dmz_metadata *zmd, struct dm_zone *zone,
+ {
+ 	struct dmz_mblock *mblk;
+ 	unsigned int bit, set_bit, nr_bits;
++	unsigned int zone_bits = zmd->zone_bits_per_mblk;
+ 	unsigned long *bitmap;
+ 	int n = 0;
+ 
+@@ -2196,15 +2201,15 @@ static int dmz_to_next_set_block(struct dmz_metadata *zmd, struct dm_zone *zone,
+ 		/* Get offset */
+ 		bitmap = (unsigned long *) mblk->data;
+ 		bit = chunk_block & DMZ_BLOCK_MASK_BITS;
+-		nr_bits = min(nr_blocks, DMZ_BLOCK_SIZE_BITS - bit);
++		nr_bits = min(nr_blocks, zone_bits - bit);
+ 		if (set)
+-			set_bit = find_next_bit(bitmap, DMZ_BLOCK_SIZE_BITS, bit);
++			set_bit = find_next_bit(bitmap, zone_bits, bit);
+ 		else
+-			set_bit = find_next_zero_bit(bitmap, DMZ_BLOCK_SIZE_BITS, bit);
++			set_bit = find_next_zero_bit(bitmap, zone_bits, bit);
+ 		dmz_release_mblock(zmd, mblk);
+ 
+ 		n += set_bit - bit;
+-		if (set_bit < DMZ_BLOCK_SIZE_BITS)
++		if (set_bit < zone_bits)
+ 			break;
+ 
+ 		nr_blocks -= nr_bits;
+@@ -2307,7 +2312,7 @@ static void dmz_get_zone_weight(struct dmz_metadata *zmd, struct dm_zone *zone)
+ 		/* Count bits in this block */
+ 		bitmap = mblk->data;
+ 		bit = chunk_block & DMZ_BLOCK_MASK_BITS;
+-		nr_bits = min(nr_blocks, DMZ_BLOCK_SIZE_BITS - bit);
++		nr_bits = min(nr_blocks, zmd->zone_bits_per_mblk - bit);
+ 		n += dmz_count_bits(bitmap, bit, nr_bits);
+ 
+ 		dmz_release_mblock(zmd, mblk);
+diff --git a/drivers/md/dm.c b/drivers/md/dm.c
+index c9860e3b04dd..3965f3cf8ea1 100644
+--- a/drivers/md/dm.c
++++ b/drivers/md/dm.c
+@@ -1819,6 +1819,7 @@ static void dm_init_normal_md_queue(struct mapped_device *md)
+ 	/*
+ 	 * Initialize aspects of queue that aren't relevant for blk-mq
+ 	 */
++	md->queue->backing_dev_info->congested_data = md;
+ 	md->queue->backing_dev_info->congested_fn = dm_any_congested;
+ }
+ 
+@@ -1913,7 +1914,12 @@ static struct mapped_device *alloc_dev(int minor)
+ 	if (!md->queue)
+ 		goto bad;
+ 	md->queue->queuedata = md;
+-	md->queue->backing_dev_info->congested_data = md;
++	/*
++	 * default to bio-based required ->make_request_fn until DM
++	 * table is loaded and md->type established. If request-based
++	 * table is loaded: blk-mq will override accordingly.
++	 */
++	blk_queue_make_request(md->queue, dm_make_request);
+ 
+ 	md->disk = alloc_disk_node(1, md->numa_node_id);
+ 	if (!md->disk)
+@@ -2242,7 +2248,6 @@ int dm_setup_md_queue(struct mapped_device *md, struct dm_table *t)
+ 	case DM_TYPE_BIO_BASED:
+ 	case DM_TYPE_DAX_BIO_BASED:
+ 		dm_init_normal_md_queue(md);
+-		blk_queue_make_request(md->queue, dm_make_request);
+ 		break;
+ 	case DM_TYPE_NVME_BIO_BASED:
+ 		dm_init_normal_md_queue(md);
+diff --git a/drivers/md/persistent-data/dm-space-map-common.c b/drivers/md/persistent-data/dm-space-map-common.c
+index 0a3b8ae4a29c..17aef55ed708 100644
+--- a/drivers/md/persistent-data/dm-space-map-common.c
++++ b/drivers/md/persistent-data/dm-space-map-common.c
+@@ -382,6 +382,33 @@ int sm_ll_find_free_block(struct ll_disk *ll, dm_block_t begin,
+ 	return -ENOSPC;
+ }
+ 
++int sm_ll_find_common_free_block(struct ll_disk *old_ll, struct ll_disk *new_ll,
++	                         dm_block_t begin, dm_block_t end, dm_block_t *b)
++{
++	int r;
++	uint32_t count;
++
++	do {
++		r = sm_ll_find_free_block(new_ll, begin, new_ll->nr_blocks, b);
++		if (r)
++			break;
++
++		/* double check this block wasn't used in the old transaction */
++		if (*b >= old_ll->nr_blocks)
++			count = 0;
++		else {
++			r = sm_ll_lookup(old_ll, *b, &count);
++			if (r)
++				break;
++
++			if (count)
++				begin = *b + 1;
++		}
++	} while (count);
++
++	return r;
++}
++
+ static int sm_ll_mutate(struct ll_disk *ll, dm_block_t b,
+ 			int (*mutator)(void *context, uint32_t old, uint32_t *new),
+ 			void *context, enum allocation_event *ev)
+diff --git a/drivers/md/persistent-data/dm-space-map-common.h b/drivers/md/persistent-data/dm-space-map-common.h
+index b3078d5eda0c..8de63ce39bdd 100644
+--- a/drivers/md/persistent-data/dm-space-map-common.h
++++ b/drivers/md/persistent-data/dm-space-map-common.h
+@@ -109,6 +109,8 @@ int sm_ll_lookup_bitmap(struct ll_disk *ll, dm_block_t b, uint32_t *result);
+ int sm_ll_lookup(struct ll_disk *ll, dm_block_t b, uint32_t *result);
+ int sm_ll_find_free_block(struct ll_disk *ll, dm_block_t begin,
+ 			  dm_block_t end, dm_block_t *result);
++int sm_ll_find_common_free_block(struct ll_disk *old_ll, struct ll_disk *new_ll,
++	                         dm_block_t begin, dm_block_t end, dm_block_t *result);
+ int sm_ll_insert(struct ll_disk *ll, dm_block_t b, uint32_t ref_count, enum allocation_event *ev);
+ int sm_ll_inc(struct ll_disk *ll, dm_block_t b, enum allocation_event *ev);
+ int sm_ll_dec(struct ll_disk *ll, dm_block_t b, enum allocation_event *ev);
+diff --git a/drivers/md/persistent-data/dm-space-map-disk.c b/drivers/md/persistent-data/dm-space-map-disk.c
+index 32adf6b4a9c7..bf4c5e2ccb6f 100644
+--- a/drivers/md/persistent-data/dm-space-map-disk.c
++++ b/drivers/md/persistent-data/dm-space-map-disk.c
+@@ -167,8 +167,10 @@ static int sm_disk_new_block(struct dm_space_map *sm, dm_block_t *b)
+ 	enum allocation_event ev;
+ 	struct sm_disk *smd = container_of(sm, struct sm_disk, sm);
+ 
+-	/* FIXME: we should loop round a couple of times */
+-	r = sm_ll_find_free_block(&smd->old_ll, smd->begin, smd->old_ll.nr_blocks, b);
++	/*
++	 * Any block we allocate has to be free in both the old and current ll.
++	 */
++	r = sm_ll_find_common_free_block(&smd->old_ll, &smd->ll, smd->begin, smd->ll.nr_blocks, b);
+ 	if (r)
+ 		return r;
+ 
+diff --git a/drivers/md/persistent-data/dm-space-map-metadata.c b/drivers/md/persistent-data/dm-space-map-metadata.c
+index 25328582cc48..9e3c64ec2026 100644
+--- a/drivers/md/persistent-data/dm-space-map-metadata.c
++++ b/drivers/md/persistent-data/dm-space-map-metadata.c
+@@ -448,7 +448,10 @@ static int sm_metadata_new_block_(struct dm_space_map *sm, dm_block_t *b)
+ 	enum allocation_event ev;
+ 	struct sm_metadata *smm = container_of(sm, struct sm_metadata, sm);
+ 
+-	r = sm_ll_find_free_block(&smm->old_ll, smm->begin, smm->old_ll.nr_blocks, b);
++	/*
++	 * Any block we allocate has to be free in both the old and current ll.
++	 */
++	r = sm_ll_find_common_free_block(&smm->old_ll, &smm->ll, smm->begin, smm->ll.nr_blocks, b);
+ 	if (r)
+ 		return r;
+ 
+diff --git a/drivers/media/rc/iguanair.c b/drivers/media/rc/iguanair.c
+index 6f3030b2054d..1df9522c30fa 100644
+--- a/drivers/media/rc/iguanair.c
++++ b/drivers/media/rc/iguanair.c
+@@ -424,7 +424,7 @@ static int iguanair_probe(struct usb_interface *intf,
+ 	int ret, pipein, pipeout;
+ 	struct usb_host_interface *idesc;
+ 
+-	idesc = intf->altsetting;
++	idesc = intf->cur_altsetting;
+ 	if (idesc->desc.bNumEndpoints < 2)
+ 		return -ENODEV;
+ 
+diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c
+index 0f218afdadaa..c30affbd43a9 100644
+--- a/drivers/media/rc/rc-main.c
++++ b/drivers/media/rc/rc-main.c
+@@ -1874,23 +1874,28 @@ int rc_register_device(struct rc_dev *dev)
+ 
+ 	dev->registered = true;
+ 
+-	if (dev->driver_type != RC_DRIVER_IR_RAW_TX) {
+-		rc = rc_setup_rx_device(dev);
+-		if (rc)
+-			goto out_dev;
+-	}
+-
+-	/* Ensure that the lirc kfifo is setup before we start the thread */
++	/*
++	 * once the the input device is registered in rc_setup_rx_device,
++	 * userspace can open the input device and rc_open() will be called
++	 * as a result. This results in driver code being allowed to submit
++	 * keycodes with rc_keydown, so lirc must be registered first.
++	 */
+ 	if (dev->allowed_protocols != RC_PROTO_BIT_CEC) {
+ 		rc = ir_lirc_register(dev);
+ 		if (rc < 0)
+-			goto out_rx;
++			goto out_dev;
++	}
++
++	if (dev->driver_type != RC_DRIVER_IR_RAW_TX) {
++		rc = rc_setup_rx_device(dev);
++		if (rc)
++			goto out_lirc;
+ 	}
+ 
+ 	if (dev->driver_type == RC_DRIVER_IR_RAW) {
+ 		rc = ir_raw_event_register(dev);
+ 		if (rc < 0)
+-			goto out_lirc;
++			goto out_rx;
+ 	}
+ 
+ 	dev_dbg(&dev->dev, "Registered rc%u (driver: %s)\n", dev->minor,
+@@ -1898,11 +1903,11 @@ int rc_register_device(struct rc_dev *dev)
+ 
+ 	return 0;
+ 
++out_rx:
++	rc_free_rx_device(dev);
+ out_lirc:
+ 	if (dev->allowed_protocols != RC_PROTO_BIT_CEC)
+ 		ir_lirc_unregister(dev);
+-out_rx:
+-	rc_free_rx_device(dev);
+ out_dev:
+ 	device_del(&dev->dev);
+ out_rx_free:
+diff --git a/drivers/media/usb/uvc/uvc_driver.c b/drivers/media/usb/uvc/uvc_driver.c
+index 063e229ead5e..38c73cdbef70 100644
+--- a/drivers/media/usb/uvc/uvc_driver.c
++++ b/drivers/media/usb/uvc/uvc_driver.c
+@@ -1482,6 +1482,11 @@ static int uvc_scan_chain_forward(struct uvc_video_chain *chain,
+ 			break;
+ 		if (forward == prev)
+ 			continue;
++		if (forward->chain.next || forward->chain.prev) {
++			uvc_trace(UVC_TRACE_DESCR, "Found reference to "
++				"entity %d already in chain.\n", forward->id);
++			return -EINVAL;
++		}
+ 
+ 		switch (UVC_ENTITY_TYPE(forward)) {
+ 		case UVC_VC_EXTENSION_UNIT:
+@@ -1563,6 +1568,13 @@ static int uvc_scan_chain_backward(struct uvc_video_chain *chain,
+ 				return -1;
+ 			}
+ 
++			if (term->chain.next || term->chain.prev) {
++				uvc_trace(UVC_TRACE_DESCR, "Found reference to "
++					"entity %d already in chain.\n",
++					term->id);
++				return -EINVAL;
++			}
++
+ 			if (uvc_trace_param & UVC_TRACE_PROBE)
+ 				printk(KERN_CONT " %d", term->id);
+ 
+diff --git a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c
+index 6481212fda77..3efe4e0a80a4 100644
+--- a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c
++++ b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c
+@@ -1171,36 +1171,38 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar
+ 	u32 aux_space;
+ 	int compatible_arg = 1;
+ 	long err = 0;
++	unsigned int ncmd;
+ 
+ 	/*
+ 	 * 1. When struct size is different, converts the command.
+ 	 */
+ 	switch (cmd) {
+-	case VIDIOC_G_FMT32: cmd = VIDIOC_G_FMT; break;
+-	case VIDIOC_S_FMT32: cmd = VIDIOC_S_FMT; break;
+-	case VIDIOC_QUERYBUF32: cmd = VIDIOC_QUERYBUF; break;
+-	case VIDIOC_G_FBUF32: cmd = VIDIOC_G_FBUF; break;
+-	case VIDIOC_S_FBUF32: cmd = VIDIOC_S_FBUF; break;
+-	case VIDIOC_QBUF32: cmd = VIDIOC_QBUF; break;
+-	case VIDIOC_DQBUF32: cmd = VIDIOC_DQBUF; break;
+-	case VIDIOC_ENUMSTD32: cmd = VIDIOC_ENUMSTD; break;
+-	case VIDIOC_ENUMINPUT32: cmd = VIDIOC_ENUMINPUT; break;
+-	case VIDIOC_TRY_FMT32: cmd = VIDIOC_TRY_FMT; break;
+-	case VIDIOC_G_EXT_CTRLS32: cmd = VIDIOC_G_EXT_CTRLS; break;
+-	case VIDIOC_S_EXT_CTRLS32: cmd = VIDIOC_S_EXT_CTRLS; break;
+-	case VIDIOC_TRY_EXT_CTRLS32: cmd = VIDIOC_TRY_EXT_CTRLS; break;
+-	case VIDIOC_DQEVENT32: cmd = VIDIOC_DQEVENT; break;
+-	case VIDIOC_OVERLAY32: cmd = VIDIOC_OVERLAY; break;
+-	case VIDIOC_STREAMON32: cmd = VIDIOC_STREAMON; break;
+-	case VIDIOC_STREAMOFF32: cmd = VIDIOC_STREAMOFF; break;
+-	case VIDIOC_G_INPUT32: cmd = VIDIOC_G_INPUT; break;
+-	case VIDIOC_S_INPUT32: cmd = VIDIOC_S_INPUT; break;
+-	case VIDIOC_G_OUTPUT32: cmd = VIDIOC_G_OUTPUT; break;
+-	case VIDIOC_S_OUTPUT32: cmd = VIDIOC_S_OUTPUT; break;
+-	case VIDIOC_CREATE_BUFS32: cmd = VIDIOC_CREATE_BUFS; break;
+-	case VIDIOC_PREPARE_BUF32: cmd = VIDIOC_PREPARE_BUF; break;
+-	case VIDIOC_G_EDID32: cmd = VIDIOC_G_EDID; break;
+-	case VIDIOC_S_EDID32: cmd = VIDIOC_S_EDID; break;
++	case VIDIOC_G_FMT32: ncmd = VIDIOC_G_FMT; break;
++	case VIDIOC_S_FMT32: ncmd = VIDIOC_S_FMT; break;
++	case VIDIOC_QUERYBUF32: ncmd = VIDIOC_QUERYBUF; break;
++	case VIDIOC_G_FBUF32: ncmd = VIDIOC_G_FBUF; break;
++	case VIDIOC_S_FBUF32: ncmd = VIDIOC_S_FBUF; break;
++	case VIDIOC_QBUF32: ncmd = VIDIOC_QBUF; break;
++	case VIDIOC_DQBUF32: ncmd = VIDIOC_DQBUF; break;
++	case VIDIOC_ENUMSTD32: ncmd = VIDIOC_ENUMSTD; break;
++	case VIDIOC_ENUMINPUT32: ncmd = VIDIOC_ENUMINPUT; break;
++	case VIDIOC_TRY_FMT32: ncmd = VIDIOC_TRY_FMT; break;
++	case VIDIOC_G_EXT_CTRLS32: ncmd = VIDIOC_G_EXT_CTRLS; break;
++	case VIDIOC_S_EXT_CTRLS32: ncmd = VIDIOC_S_EXT_CTRLS; break;
++	case VIDIOC_TRY_EXT_CTRLS32: ncmd = VIDIOC_TRY_EXT_CTRLS; break;
++	case VIDIOC_DQEVENT32: ncmd = VIDIOC_DQEVENT; break;
++	case VIDIOC_OVERLAY32: ncmd = VIDIOC_OVERLAY; break;
++	case VIDIOC_STREAMON32: ncmd = VIDIOC_STREAMON; break;
++	case VIDIOC_STREAMOFF32: ncmd = VIDIOC_STREAMOFF; break;
++	case VIDIOC_G_INPUT32: ncmd = VIDIOC_G_INPUT; break;
++	case VIDIOC_S_INPUT32: ncmd = VIDIOC_S_INPUT; break;
++	case VIDIOC_G_OUTPUT32: ncmd = VIDIOC_G_OUTPUT; break;
++	case VIDIOC_S_OUTPUT32: ncmd = VIDIOC_S_OUTPUT; break;
++	case VIDIOC_CREATE_BUFS32: ncmd = VIDIOC_CREATE_BUFS; break;
++	case VIDIOC_PREPARE_BUF32: ncmd = VIDIOC_PREPARE_BUF; break;
++	case VIDIOC_G_EDID32: ncmd = VIDIOC_G_EDID; break;
++	case VIDIOC_S_EDID32: ncmd = VIDIOC_S_EDID; break;
++	default: ncmd = cmd; break;
+ 	}
+ 
+ 	/*
+@@ -1209,11 +1211,11 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar
+ 	 * argument into it.
+ 	 */
+ 	switch (cmd) {
+-	case VIDIOC_OVERLAY:
+-	case VIDIOC_STREAMON:
+-	case VIDIOC_STREAMOFF:
+-	case VIDIOC_S_INPUT:
+-	case VIDIOC_S_OUTPUT:
++	case VIDIOC_OVERLAY32:
++	case VIDIOC_STREAMON32:
++	case VIDIOC_STREAMOFF32:
++	case VIDIOC_S_INPUT32:
++	case VIDIOC_S_OUTPUT32:
+ 		err = alloc_userspace(sizeof(unsigned int), 0, &new_p64);
+ 		if (!err && assign_in_user((unsigned int __user *)new_p64,
+ 					   (compat_uint_t __user *)p32))
+@@ -1221,23 +1223,23 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar
+ 		compatible_arg = 0;
+ 		break;
+ 
+-	case VIDIOC_G_INPUT:
+-	case VIDIOC_G_OUTPUT:
++	case VIDIOC_G_INPUT32:
++	case VIDIOC_G_OUTPUT32:
+ 		err = alloc_userspace(sizeof(unsigned int), 0, &new_p64);
+ 		compatible_arg = 0;
+ 		break;
+ 
+-	case VIDIOC_G_EDID:
+-	case VIDIOC_S_EDID:
++	case VIDIOC_G_EDID32:
++	case VIDIOC_S_EDID32:
+ 		err = alloc_userspace(sizeof(struct v4l2_edid), 0, &new_p64);
+ 		if (!err)
+ 			err = get_v4l2_edid32(new_p64, p32);
+ 		compatible_arg = 0;
+ 		break;
+ 
+-	case VIDIOC_G_FMT:
+-	case VIDIOC_S_FMT:
+-	case VIDIOC_TRY_FMT:
++	case VIDIOC_G_FMT32:
++	case VIDIOC_S_FMT32:
++	case VIDIOC_TRY_FMT32:
+ 		err = bufsize_v4l2_format(p32, &aux_space);
+ 		if (!err)
+ 			err = alloc_userspace(sizeof(struct v4l2_format),
+@@ -1250,7 +1252,7 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar
+ 		compatible_arg = 0;
+ 		break;
+ 
+-	case VIDIOC_CREATE_BUFS:
++	case VIDIOC_CREATE_BUFS32:
+ 		err = bufsize_v4l2_create(p32, &aux_space);
+ 		if (!err)
+ 			err = alloc_userspace(sizeof(struct v4l2_create_buffers),
+@@ -1263,10 +1265,10 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar
+ 		compatible_arg = 0;
+ 		break;
+ 
+-	case VIDIOC_PREPARE_BUF:
+-	case VIDIOC_QUERYBUF:
+-	case VIDIOC_QBUF:
+-	case VIDIOC_DQBUF:
++	case VIDIOC_PREPARE_BUF32:
++	case VIDIOC_QUERYBUF32:
++	case VIDIOC_QBUF32:
++	case VIDIOC_DQBUF32:
+ 		err = bufsize_v4l2_buffer(p32, &aux_space);
+ 		if (!err)
+ 			err = alloc_userspace(sizeof(struct v4l2_buffer),
+@@ -1279,7 +1281,7 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar
+ 		compatible_arg = 0;
+ 		break;
+ 
+-	case VIDIOC_S_FBUF:
++	case VIDIOC_S_FBUF32:
+ 		err = alloc_userspace(sizeof(struct v4l2_framebuffer), 0,
+ 				      &new_p64);
+ 		if (!err)
+@@ -1287,13 +1289,13 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar
+ 		compatible_arg = 0;
+ 		break;
+ 
+-	case VIDIOC_G_FBUF:
++	case VIDIOC_G_FBUF32:
+ 		err = alloc_userspace(sizeof(struct v4l2_framebuffer), 0,
+ 				      &new_p64);
+ 		compatible_arg = 0;
+ 		break;
+ 
+-	case VIDIOC_ENUMSTD:
++	case VIDIOC_ENUMSTD32:
+ 		err = alloc_userspace(sizeof(struct v4l2_standard), 0,
+ 				      &new_p64);
+ 		if (!err)
+@@ -1301,16 +1303,16 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar
+ 		compatible_arg = 0;
+ 		break;
+ 
+-	case VIDIOC_ENUMINPUT:
++	case VIDIOC_ENUMINPUT32:
+ 		err = alloc_userspace(sizeof(struct v4l2_input), 0, &new_p64);
+ 		if (!err)
+ 			err = get_v4l2_input32(new_p64, p32);
+ 		compatible_arg = 0;
+ 		break;
+ 
+-	case VIDIOC_G_EXT_CTRLS:
+-	case VIDIOC_S_EXT_CTRLS:
+-	case VIDIOC_TRY_EXT_CTRLS:
++	case VIDIOC_G_EXT_CTRLS32:
++	case VIDIOC_S_EXT_CTRLS32:
++	case VIDIOC_TRY_EXT_CTRLS32:
+ 		err = bufsize_v4l2_ext_controls(p32, &aux_space);
+ 		if (!err)
+ 			err = alloc_userspace(sizeof(struct v4l2_ext_controls),
+@@ -1322,7 +1324,7 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar
+ 		}
+ 		compatible_arg = 0;
+ 		break;
+-	case VIDIOC_DQEVENT:
++	case VIDIOC_DQEVENT32:
+ 		err = alloc_userspace(sizeof(struct v4l2_event), 0, &new_p64);
+ 		compatible_arg = 0;
+ 		break;
+@@ -1340,9 +1342,9 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar
+ 	 * Otherwise, it will pass the newly allocated @new_p64 argument.
+ 	 */
+ 	if (compatible_arg)
+-		err = native_ioctl(file, cmd, (unsigned long)p32);
++		err = native_ioctl(file, ncmd, (unsigned long)p32);
+ 	else
+-		err = native_ioctl(file, cmd, (unsigned long)new_p64);
++		err = native_ioctl(file, ncmd, (unsigned long)new_p64);
+ 
+ 	if (err == -ENOTTY)
+ 		return err;
+@@ -1358,13 +1360,13 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar
+ 	 * the blocks to maximum allowed value.
+ 	 */
+ 	switch (cmd) {
+-	case VIDIOC_G_EXT_CTRLS:
+-	case VIDIOC_S_EXT_CTRLS:
+-	case VIDIOC_TRY_EXT_CTRLS:
++	case VIDIOC_G_EXT_CTRLS32:
++	case VIDIOC_S_EXT_CTRLS32:
++	case VIDIOC_TRY_EXT_CTRLS32:
+ 		if (put_v4l2_ext_controls32(file, new_p64, p32))
+ 			err = -EFAULT;
+ 		break;
+-	case VIDIOC_S_EDID:
++	case VIDIOC_S_EDID32:
+ 		if (put_v4l2_edid32(new_p64, p32))
+ 			err = -EFAULT;
+ 		break;
+@@ -1377,49 +1379,49 @@ static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long ar
+ 	 * the original 32 bits structure.
+ 	 */
+ 	switch (cmd) {
+-	case VIDIOC_S_INPUT:
+-	case VIDIOC_S_OUTPUT:
+-	case VIDIOC_G_INPUT:
+-	case VIDIOC_G_OUTPUT:
++	case VIDIOC_S_INPUT32:
++	case VIDIOC_S_OUTPUT32:
++	case VIDIOC_G_INPUT32:
++	case VIDIOC_G_OUTPUT32:
+ 		if (assign_in_user((compat_uint_t __user *)p32,
+ 				   ((unsigned int __user *)new_p64)))
+ 			err = -EFAULT;
+ 		break;
+ 
+-	case VIDIOC_G_FBUF:
++	case VIDIOC_G_FBUF32:
+ 		err = put_v4l2_framebuffer32(new_p64, p32);
+ 		break;
+ 
+-	case VIDIOC_DQEVENT:
++	case VIDIOC_DQEVENT32:
+ 		err = put_v4l2_event32(new_p64, p32);
+ 		break;
+ 
+-	case VIDIOC_G_EDID:
++	case VIDIOC_G_EDID32:
+ 		err = put_v4l2_edid32(new_p64, p32);
+ 		break;
+ 
+-	case VIDIOC_G_FMT:
+-	case VIDIOC_S_FMT:
+-	case VIDIOC_TRY_FMT:
++	case VIDIOC_G_FMT32:
++	case VIDIOC_S_FMT32:
++	case VIDIOC_TRY_FMT32:
+ 		err = put_v4l2_format32(new_p64, p32);
+ 		break;
+ 
+-	case VIDIOC_CREATE_BUFS:
++	case VIDIOC_CREATE_BUFS32:
+ 		err = put_v4l2_create32(new_p64, p32);
+ 		break;
+ 
+-	case VIDIOC_PREPARE_BUF:
+-	case VIDIOC_QUERYBUF:
+-	case VIDIOC_QBUF:
+-	case VIDIOC_DQBUF:
++	case VIDIOC_PREPARE_BUF32:
++	case VIDIOC_QUERYBUF32:
++	case VIDIOC_QBUF32:
++	case VIDIOC_DQBUF32:
+ 		err = put_v4l2_buffer32(new_p64, p32);
+ 		break;
+ 
+-	case VIDIOC_ENUMSTD:
++	case VIDIOC_ENUMSTD32:
+ 		err = put_v4l2_standard32(new_p64, p32);
+ 		break;
+ 
+-	case VIDIOC_ENUMINPUT:
++	case VIDIOC_ENUMINPUT32:
+ 		err = put_v4l2_input32(new_p64, p32);
+ 		break;
+ 	}
+diff --git a/drivers/media/v4l2-core/videobuf-dma-sg.c b/drivers/media/v4l2-core/videobuf-dma-sg.c
+index 08929c087e27..4c396e0defa4 100644
+--- a/drivers/media/v4l2-core/videobuf-dma-sg.c
++++ b/drivers/media/v4l2-core/videobuf-dma-sg.c
+@@ -352,8 +352,11 @@ int videobuf_dma_free(struct videobuf_dmabuf *dma)
+ 	BUG_ON(dma->sglen);
+ 
+ 	if (dma->pages) {
+-		for (i = 0; i < dma->nr_pages; i++)
++		for (i = 0; i < dma->nr_pages; i++) {
++			if (dma->direction == DMA_FROM_DEVICE)
++				set_page_dirty_lock(dma->pages[i]);
+ 			put_page(dma->pages[i]);
++		}
+ 		kfree(dma->pages);
+ 		dma->pages = NULL;
+ 	}
+diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
+index f8e0fa97bb31..aa65931142ba 100644
+--- a/drivers/mfd/axp20x.c
++++ b/drivers/mfd/axp20x.c
+@@ -128,7 +128,7 @@ static const struct regmap_range axp288_writeable_ranges[] = {
+ static const struct regmap_range axp288_volatile_ranges[] = {
+ 	regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP288_POWER_REASON),
+ 	regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL),
+-	regmap_reg_range(AXP288_BC_DET_STAT, AXP288_BC_DET_STAT),
++	regmap_reg_range(AXP288_BC_DET_STAT, AXP20X_VBUS_IPSOUT_MGMT),
+ 	regmap_reg_range(AXP20X_CHRG_BAK_CTRL, AXP20X_CHRG_BAK_CTRL),
+ 	regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
+ 	regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
+diff --git a/drivers/mfd/da9062-core.c b/drivers/mfd/da9062-core.c
+index 9f6105906c09..83c624f6033c 100644
+--- a/drivers/mfd/da9062-core.c
++++ b/drivers/mfd/da9062-core.c
+@@ -257,7 +257,7 @@ static const struct mfd_cell da9062_devs[] = {
+ 		.name		= "da9062-watchdog",
+ 		.num_resources	= ARRAY_SIZE(da9062_wdt_resources),
+ 		.resources	= da9062_wdt_resources,
+-		.of_compatible  = "dlg,da9062-wdt",
++		.of_compatible  = "dlg,da9062-watchdog",
+ 	},
+ 	{
+ 		.name		= "da9062-thermal",
+diff --git a/drivers/mfd/dln2.c b/drivers/mfd/dln2.c
+index 90e789943466..1476465ce803 100644
+--- a/drivers/mfd/dln2.c
++++ b/drivers/mfd/dln2.c
+@@ -725,6 +725,8 @@ static int dln2_probe(struct usb_interface *interface,
+ 		      const struct usb_device_id *usb_id)
+ {
+ 	struct usb_host_interface *hostif = interface->cur_altsetting;
++	struct usb_endpoint_descriptor *epin;
++	struct usb_endpoint_descriptor *epout;
+ 	struct device *dev = &interface->dev;
+ 	struct dln2_dev *dln2;
+ 	int ret;
+@@ -734,12 +736,19 @@ static int dln2_probe(struct usb_interface *interface,
+ 	    hostif->desc.bNumEndpoints < 2)
+ 		return -ENODEV;
+ 
++	epin = &hostif->endpoint[0].desc;
++	epout = &hostif->endpoint[1].desc;
++	if (!usb_endpoint_is_bulk_out(epout))
++		return -ENODEV;
++	if (!usb_endpoint_is_bulk_in(epin))
++		return -ENODEV;
++
+ 	dln2 = kzalloc(sizeof(*dln2), GFP_KERNEL);
+ 	if (!dln2)
+ 		return -ENOMEM;
+ 
+-	dln2->ep_out = hostif->endpoint[0].desc.bEndpointAddress;
+-	dln2->ep_in = hostif->endpoint[1].desc.bEndpointAddress;
++	dln2->ep_out = epout->bEndpointAddress;
++	dln2->ep_in = epin->bEndpointAddress;
+ 	dln2->usb_dev = usb_get_dev(interface_to_usbdev(interface));
+ 	dln2->interface = interface;
+ 	usb_set_intfdata(interface, dln2);
+diff --git a/drivers/mfd/rn5t618.c b/drivers/mfd/rn5t618.c
+index f4037d42a60f..dd4251f105e0 100644
+--- a/drivers/mfd/rn5t618.c
++++ b/drivers/mfd/rn5t618.c
+@@ -32,6 +32,7 @@ static bool rn5t618_volatile_reg(struct device *dev, unsigned int reg)
+ 	case RN5T618_WATCHDOGCNT:
+ 	case RN5T618_DCIRQ:
+ 	case RN5T618_ILIMDATAH ... RN5T618_AIN0DATAL:
++	case RN5T618_ADCCNT3:
+ 	case RN5T618_IR_ADC1 ... RN5T618_IR_ADC3:
+ 	case RN5T618_IR_GPR:
+ 	case RN5T618_IR_GPF:
+diff --git a/drivers/mmc/host/mmc_spi.c b/drivers/mmc/host/mmc_spi.c
+index ea254d00541f..24795454d106 100644
+--- a/drivers/mmc/host/mmc_spi.c
++++ b/drivers/mmc/host/mmc_spi.c
+@@ -1154,17 +1154,22 @@ static void mmc_spi_initsequence(struct mmc_spi_host *host)
+ 	 * SPI protocol.  Another is that when chipselect is released while
+ 	 * the card returns BUSY status, the clock must issue several cycles
+ 	 * with chipselect high before the card will stop driving its output.
++	 *
++	 * SPI_CS_HIGH means "asserted" here. In some cases like when using
++	 * GPIOs for chip select, SPI_CS_HIGH is set but this will be logically
++	 * inverted by gpiolib, so if we want to ascertain to drive it high
++	 * we should toggle the default with an XOR as we do here.
+ 	 */
+-	host->spi->mode |= SPI_CS_HIGH;
++	host->spi->mode ^= SPI_CS_HIGH;
+ 	if (spi_setup(host->spi) != 0) {
+ 		/* Just warn; most cards work without it. */
+ 		dev_warn(&host->spi->dev,
+ 				"can't change chip-select polarity\n");
+-		host->spi->mode &= ~SPI_CS_HIGH;
++		host->spi->mode ^= SPI_CS_HIGH;
+ 	} else {
+ 		mmc_spi_readbytes(host, 18);
+ 
+-		host->spi->mode &= ~SPI_CS_HIGH;
++		host->spi->mode ^= SPI_CS_HIGH;
+ 		if (spi_setup(host->spi) != 0) {
+ 			/* Wot, we can't get the same setup we had before? */
+ 			dev_err(&host->spi->dev,
+diff --git a/drivers/mmc/host/sdhci-of-at91.c b/drivers/mmc/host/sdhci-of-at91.c
+index 1ebcf0eb781e..04e88d4796fa 100644
+--- a/drivers/mmc/host/sdhci-of-at91.c
++++ b/drivers/mmc/host/sdhci-of-at91.c
+@@ -332,19 +332,22 @@ static int sdhci_at91_probe(struct platform_device *pdev)
+ 	priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
+ 	if (IS_ERR(priv->mainck)) {
+ 		dev_err(&pdev->dev, "failed to get baseclk\n");
+-		return PTR_ERR(priv->mainck);
++		ret = PTR_ERR(priv->mainck);
++		goto sdhci_pltfm_free;
+ 	}
+ 
+ 	priv->hclock = devm_clk_get(&pdev->dev, "hclock");
+ 	if (IS_ERR(priv->hclock)) {
+ 		dev_err(&pdev->dev, "failed to get hclock\n");
+-		return PTR_ERR(priv->hclock);
++		ret = PTR_ERR(priv->hclock);
++		goto sdhci_pltfm_free;
+ 	}
+ 
+ 	priv->gck = devm_clk_get(&pdev->dev, "multclk");
+ 	if (IS_ERR(priv->gck)) {
+ 		dev_err(&pdev->dev, "failed to get multclk\n");
+-		return PTR_ERR(priv->gck);
++		ret = PTR_ERR(priv->gck);
++		goto sdhci_pltfm_free;
+ 	}
+ 
+ 	ret = sdhci_at91_set_clks_presets(&pdev->dev);
+diff --git a/drivers/mtd/ubi/fastmap.c b/drivers/mtd/ubi/fastmap.c
+index 462526a10537..8e292992f84c 100644
+--- a/drivers/mtd/ubi/fastmap.c
++++ b/drivers/mtd/ubi/fastmap.c
+@@ -73,7 +73,7 @@ static int self_check_seen(struct ubi_device *ubi, unsigned long *seen)
+ 		return 0;
+ 
+ 	for (pnum = 0; pnum < ubi->peb_count; pnum++) {
+-		if (test_bit(pnum, seen) && ubi->lookuptbl[pnum]) {
++		if (!test_bit(pnum, seen) && ubi->lookuptbl[pnum]) {
+ 			ubi_err(ubi, "self-check failed for PEB %d, fastmap didn't see it", pnum);
+ 			ret = -EINVAL;
+ 		}
+@@ -1146,7 +1146,7 @@ static int ubi_write_fastmap(struct ubi_device *ubi,
+ 	struct rb_node *tmp_rb;
+ 	int ret, i, j, free_peb_count, used_peb_count, vol_count;
+ 	int scrub_peb_count, erase_peb_count;
+-	unsigned long *seen_pebs = NULL;
++	unsigned long *seen_pebs;
+ 
+ 	fm_raw = ubi->fm_buf;
+ 	memset(ubi->fm_buf, 0, ubi->fm_size);
+@@ -1160,7 +1160,7 @@ static int ubi_write_fastmap(struct ubi_device *ubi,
+ 	dvbuf = new_fm_vbuf(ubi, UBI_FM_DATA_VOLUME_ID);
+ 	if (!dvbuf) {
+ 		ret = -ENOMEM;
+-		goto out_kfree;
++		goto out_free_avbuf;
+ 	}
+ 
+ 	avhdr = ubi_get_vid_hdr(avbuf);
+@@ -1169,7 +1169,7 @@ static int ubi_write_fastmap(struct ubi_device *ubi,
+ 	seen_pebs = init_seen(ubi);
+ 	if (IS_ERR(seen_pebs)) {
+ 		ret = PTR_ERR(seen_pebs);
+-		goto out_kfree;
++		goto out_free_dvbuf;
+ 	}
+ 
+ 	spin_lock(&ubi->volumes_lock);
+@@ -1337,7 +1337,7 @@ static int ubi_write_fastmap(struct ubi_device *ubi,
+ 	ret = ubi_io_write_vid_hdr(ubi, new_fm->e[0]->pnum, avbuf);
+ 	if (ret) {
+ 		ubi_err(ubi, "unable to write vid_hdr to fastmap SB!");
+-		goto out_kfree;
++		goto out_free_seen;
+ 	}
+ 
+ 	for (i = 0; i < new_fm->used_blocks; i++) {
+@@ -1359,7 +1359,7 @@ static int ubi_write_fastmap(struct ubi_device *ubi,
+ 		if (ret) {
+ 			ubi_err(ubi, "unable to write vid_hdr to PEB %i!",
+ 				new_fm->e[i]->pnum);
+-			goto out_kfree;
++			goto out_free_seen;
+ 		}
+ 	}
+ 
+@@ -1369,7 +1369,7 @@ static int ubi_write_fastmap(struct ubi_device *ubi,
+ 		if (ret) {
+ 			ubi_err(ubi, "unable to write fastmap to PEB %i!",
+ 				new_fm->e[i]->pnum);
+-			goto out_kfree;
++			goto out_free_seen;
+ 		}
+ 	}
+ 
+@@ -1379,10 +1379,13 @@ static int ubi_write_fastmap(struct ubi_device *ubi,
+ 	ret = self_check_seen(ubi, seen_pebs);
+ 	dbg_bld("fastmap written!");
+ 
+-out_kfree:
+-	ubi_free_vid_buf(avbuf);
+-	ubi_free_vid_buf(dvbuf);
++out_free_seen:
+ 	free_seen(seen_pebs);
++out_free_dvbuf:
++	ubi_free_vid_buf(dvbuf);
++out_free_avbuf:
++	ubi_free_vid_buf(avbuf);
++
+ out:
+ 	return ret;
+ }
+diff --git a/drivers/net/bonding/bond_alb.c b/drivers/net/bonding/bond_alb.c
+index e82108c917a6..334e3f22d4f1 100644
+--- a/drivers/net/bonding/bond_alb.c
++++ b/drivers/net/bonding/bond_alb.c
+@@ -1399,26 +1399,31 @@ netdev_tx_t bond_alb_xmit(struct sk_buff *skb, struct net_device *bond_dev)
+ 	bool do_tx_balance = true;
+ 	u32 hash_index = 0;
+ 	const u8 *hash_start = NULL;
+-	struct ipv6hdr *ip6hdr;
+ 
+ 	skb_reset_mac_header(skb);
+ 	eth_data = eth_hdr(skb);
+ 
+ 	switch (ntohs(skb->protocol)) {
+ 	case ETH_P_IP: {
+-		const struct iphdr *iph = ip_hdr(skb);
++		const struct iphdr *iph;
+ 
+ 		if (is_broadcast_ether_addr(eth_data->h_dest) ||
+-		    iph->daddr == ip_bcast ||
+-		    iph->protocol == IPPROTO_IGMP) {
++		    !pskb_network_may_pull(skb, sizeof(*iph))) {
++			do_tx_balance = false;
++			break;
++		}
++		iph = ip_hdr(skb);
++		if (iph->daddr == ip_bcast || iph->protocol == IPPROTO_IGMP) {
+ 			do_tx_balance = false;
+ 			break;
+ 		}
+ 		hash_start = (char *)&(iph->daddr);
+ 		hash_size = sizeof(iph->daddr);
+-	}
+ 		break;
+-	case ETH_P_IPV6:
++	}
++	case ETH_P_IPV6: {
++		const struct ipv6hdr *ip6hdr;
++
+ 		/* IPv6 doesn't really use broadcast mac address, but leave
+ 		 * that here just in case.
+ 		 */
+@@ -1435,7 +1440,11 @@ netdev_tx_t bond_alb_xmit(struct sk_buff *skb, struct net_device *bond_dev)
+ 			break;
+ 		}
+ 
+-		/* Additianally, DAD probes should not be tx-balanced as that
++		if (!pskb_network_may_pull(skb, sizeof(*ip6hdr))) {
++			do_tx_balance = false;
++			break;
++		}
++		/* Additionally, DAD probes should not be tx-balanced as that
+ 		 * will lead to false positives for duplicate addresses and
+ 		 * prevent address configuration from working.
+ 		 */
+@@ -1445,17 +1454,26 @@ netdev_tx_t bond_alb_xmit(struct sk_buff *skb, struct net_device *bond_dev)
+ 			break;
+ 		}
+ 
+-		hash_start = (char *)&(ipv6_hdr(skb)->daddr);
+-		hash_size = sizeof(ipv6_hdr(skb)->daddr);
++		hash_start = (char *)&ip6hdr->daddr;
++		hash_size = sizeof(ip6hdr->daddr);
+ 		break;
+-	case ETH_P_IPX:
+-		if (ipx_hdr(skb)->ipx_checksum != IPX_NO_CHECKSUM) {
++	}
++	case ETH_P_IPX: {
++		const struct ipxhdr *ipxhdr;
++
++		if (pskb_network_may_pull(skb, sizeof(*ipxhdr))) {
++			do_tx_balance = false;
++			break;
++		}
++		ipxhdr = (struct ipxhdr *)skb_network_header(skb);
++
++		if (ipxhdr->ipx_checksum != IPX_NO_CHECKSUM) {
+ 			/* something is wrong with this packet */
+ 			do_tx_balance = false;
+ 			break;
+ 		}
+ 
+-		if (ipx_hdr(skb)->ipx_type != IPX_TYPE_NCP) {
++		if (ipxhdr->ipx_type != IPX_TYPE_NCP) {
+ 			/* The only protocol worth balancing in
+ 			 * this family since it has an "ARP" like
+ 			 * mechanism
+@@ -1464,9 +1482,11 @@ netdev_tx_t bond_alb_xmit(struct sk_buff *skb, struct net_device *bond_dev)
+ 			break;
+ 		}
+ 
++		eth_data = eth_hdr(skb);
+ 		hash_start = (char *)eth_data->h_dest;
+ 		hash_size = ETH_ALEN;
+ 		break;
++	}
+ 	case ETH_P_ARP:
+ 		do_tx_balance = false;
+ 		if (bond_info->rlb_enabled)
+diff --git a/drivers/net/dsa/b53/b53_common.c b/drivers/net/dsa/b53/b53_common.c
+index 9f21e710fc38..51436e7eae10 100644
+--- a/drivers/net/dsa/b53/b53_common.c
++++ b/drivers/net/dsa/b53/b53_common.c
+@@ -655,7 +655,7 @@ int b53_configure_vlan(struct dsa_switch *ds)
+ 		b53_do_vlan_op(dev, VTA_CMD_CLEAR);
+ 	}
+ 
+-	b53_enable_vlan(dev, false, dev->vlan_filtering_enabled);
++	b53_enable_vlan(dev, dev->vlan_enabled, dev->vlan_filtering_enabled);
+ 
+ 	b53_for_each_port(dev, i)
+ 		b53_write16(dev, B53_VLAN_PAGE,
+diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c
+index c93609007670..f181a28cb452 100644
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -72,7 +72,9 @@ static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
+ 
+ 		/* Force link status for IMP port */
+ 		reg = core_readl(priv, offset);
+-		reg |= (MII_SW_OR | LINK_STS | GMII_SPEED_UP_2G);
++		reg |= (MII_SW_OR | LINK_STS);
++		if (priv->type == BCM7278_DEVICE_ID)
++			reg |= GMII_SPEED_UP_2G;
+ 		core_writel(priv, reg, offset);
+ 
+ 		/* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
+diff --git a/drivers/net/ethernet/broadcom/bcmsysport.c b/drivers/net/ethernet/broadcom/bcmsysport.c
+index 49aa3b5ea57c..6f8649376ff0 100644
+--- a/drivers/net/ethernet/broadcom/bcmsysport.c
++++ b/drivers/net/ethernet/broadcom/bcmsysport.c
+@@ -2716,6 +2716,9 @@ static int __maybe_unused bcm_sysport_resume(struct device *d)
+ 
+ 	umac_reset(priv);
+ 
++	/* Disable the UniMAC RX/TX */
++	umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0);
++
+ 	/* We may have been suspended and never received a WOL event that
+ 	 * would turn off MPD detection, take care of that now
+ 	 */
+diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
+index 5cf85a89016e..c19d0eabeb52 100644
+--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c
++++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
+@@ -5861,7 +5861,7 @@ static void bnxt_setup_msix(struct bnxt *bp)
+ 	int tcs, i;
+ 
+ 	tcs = netdev_get_num_tc(dev);
+-	if (tcs > 1) {
++	if (tcs) {
+ 		int i, off, count;
+ 
+ 		for (i = 0; i < tcs; i++) {
+diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
+index c2eb18854794..d1ff317f3b18 100644
+--- a/drivers/net/ethernet/cadence/macb_main.c
++++ b/drivers/net/ethernet/cadence/macb_main.c
+@@ -66,7 +66,11 @@
+ /* Max length of transmit frame must be a multiple of 8 bytes */
+ #define MACB_TX_LEN_ALIGN	8
+ #define MACB_MAX_TX_LEN		((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
+-#define GEM_MAX_TX_LEN		((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
++/* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
++ * false amba_error in TX path from the DMA assuming there is not enough
++ * space in the SRAM (16KB) even when there is.
++ */
++#define GEM_MAX_TX_LEN		(unsigned int)(0x3FC0)
+ 
+ #define GEM_MTU_MIN_SIZE	ETH_MIN_MTU
+ #define MACB_NETIF_LSO		NETIF_F_TSO
+@@ -1654,16 +1658,14 @@ static netdev_features_t macb_features_check(struct sk_buff *skb,
+ 
+ 	/* Validate LSO compatibility */
+ 
+-	/* there is only one buffer */
+-	if (!skb_is_nonlinear(skb))
++	/* there is only one buffer or protocol is not UDP */
++	if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
+ 		return features;
+ 
+ 	/* length of header */
+ 	hdrlen = skb_transport_offset(skb);
+-	if (ip_hdr(skb)->protocol == IPPROTO_TCP)
+-		hdrlen += tcp_hdrlen(skb);
+ 
+-	/* For LSO:
++	/* For UFO only:
+ 	 * When software supplies two or more payload buffers all payload buffers
+ 	 * apart from the last must be a multiple of 8 bytes in size.
+ 	 */
+diff --git a/drivers/net/ethernet/dec/tulip/dmfe.c b/drivers/net/ethernet/dec/tulip/dmfe.c
+index 17ef7a28873d..0defd5b1212a 100644
+--- a/drivers/net/ethernet/dec/tulip/dmfe.c
++++ b/drivers/net/ethernet/dec/tulip/dmfe.c
+@@ -2222,15 +2222,16 @@ static int __init dmfe_init_module(void)
+ 	if (cr6set)
+ 		dmfe_cr6_user_set = cr6set;
+ 
+- 	switch(mode) {
+-   	case DMFE_10MHF:
++	switch (mode) {
++	case DMFE_10MHF:
+ 	case DMFE_100MHF:
+ 	case DMFE_10MFD:
+ 	case DMFE_100MFD:
+ 	case DMFE_1M_HPNA:
+ 		dmfe_media_mode = mode;
+ 		break;
+-	default:dmfe_media_mode = DMFE_AUTO;
++	default:
++		dmfe_media_mode = DMFE_AUTO;
+ 		break;
+ 	}
+ 
+diff --git a/drivers/net/ethernet/dec/tulip/uli526x.c b/drivers/net/ethernet/dec/tulip/uli526x.c
+index 488a744084c9..f4751a8de629 100644
+--- a/drivers/net/ethernet/dec/tulip/uli526x.c
++++ b/drivers/net/ethernet/dec/tulip/uli526x.c
+@@ -1817,8 +1817,8 @@ static int __init uli526x_init_module(void)
+ 	if (cr6set)
+ 		uli526x_cr6_user_set = cr6set;
+ 
+- 	switch (mode) {
+-   	case ULI526X_10MHF:
++	switch (mode) {
++	case ULI526X_10MHF:
+ 	case ULI526X_100MHF:
+ 	case ULI526X_10MFD:
+ 	case ULI526X_100MFD:
+diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
+index 4313bbb2396f..51885e6dec50 100644
+--- a/drivers/net/ethernet/marvell/mvneta.c
++++ b/drivers/net/ethernet/marvell/mvneta.c
+@@ -385,6 +385,8 @@ struct mvneta_pcpu_stats {
+ 	struct	u64_stats_sync syncp;
+ 	u64	rx_packets;
+ 	u64	rx_bytes;
++	u64	rx_dropped;
++	u64	rx_errors;
+ 	u64	tx_packets;
+ 	u64	tx_bytes;
+ };
+@@ -701,6 +703,8 @@ mvneta_get_stats64(struct net_device *dev,
+ 		struct mvneta_pcpu_stats *cpu_stats;
+ 		u64 rx_packets;
+ 		u64 rx_bytes;
++		u64 rx_dropped;
++		u64 rx_errors;
+ 		u64 tx_packets;
+ 		u64 tx_bytes;
+ 
+@@ -709,19 +713,20 @@ mvneta_get_stats64(struct net_device *dev,
+ 			start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
+ 			rx_packets = cpu_stats->rx_packets;
+ 			rx_bytes   = cpu_stats->rx_bytes;
++			rx_dropped = cpu_stats->rx_dropped;
++			rx_errors  = cpu_stats->rx_errors;
+ 			tx_packets = cpu_stats->tx_packets;
+ 			tx_bytes   = cpu_stats->tx_bytes;
+ 		} while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
+ 
+ 		stats->rx_packets += rx_packets;
+ 		stats->rx_bytes   += rx_bytes;
++		stats->rx_dropped += rx_dropped;
++		stats->rx_errors  += rx_errors;
+ 		stats->tx_packets += tx_packets;
+ 		stats->tx_bytes   += tx_bytes;
+ 	}
+ 
+-	stats->rx_errors	= dev->stats.rx_errors;
+-	stats->rx_dropped	= dev->stats.rx_dropped;
+-
+ 	stats->tx_dropped	= dev->stats.tx_dropped;
+ }
+ 
+@@ -1698,8 +1703,14 @@ static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
+ static void mvneta_rx_error(struct mvneta_port *pp,
+ 			    struct mvneta_rx_desc *rx_desc)
+ {
++	struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
+ 	u32 status = rx_desc->status;
+ 
++	/* update per-cpu counter */
++	u64_stats_update_begin(&stats->syncp);
++	stats->rx_errors++;
++	u64_stats_update_end(&stats->syncp);
++
+ 	switch (status & MVNETA_RXD_ERR_CODE_MASK) {
+ 	case MVNETA_RXD_ERR_CRC:
+ 		netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
+@@ -1960,7 +1971,6 @@ static int mvneta_rx_swbm(struct napi_struct *napi,
+ 			/* Check errors only for FIRST descriptor */
+ 			if (rx_status & MVNETA_RXD_ERR_SUMMARY) {
+ 				mvneta_rx_error(pp, rx_desc);
+-				dev->stats.rx_errors++;
+ 				/* leave the descriptor untouched */
+ 				continue;
+ 			}
+@@ -1971,11 +1981,17 @@ static int mvneta_rx_swbm(struct napi_struct *napi,
+ 			skb_size = max(rx_copybreak, rx_header_size);
+ 			rxq->skb = netdev_alloc_skb_ip_align(dev, skb_size);
+ 			if (unlikely(!rxq->skb)) {
++				struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
++
+ 				netdev_err(dev,
+ 					   "Can't allocate skb on queue %d\n",
+ 					   rxq->id);
+-				dev->stats.rx_dropped++;
++
+ 				rxq->skb_alloc_err++;
++
++				u64_stats_update_begin(&stats->syncp);
++				stats->rx_dropped++;
++				u64_stats_update_end(&stats->syncp);
+ 				continue;
+ 			}
+ 			copy_size = min(skb_size, rx_bytes);
+@@ -2135,7 +2151,6 @@ err_drop_frame_ret_pool:
+ 			mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
+ 					      rx_desc->buf_phys_addr);
+ err_drop_frame:
+-			dev->stats.rx_errors++;
+ 			mvneta_rx_error(pp, rx_desc);
+ 			/* leave the descriptor untouched */
+ 			continue;
+diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c
+index b5a8769a5bfd..715ccafc92cd 100644
+--- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c
++++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c
+@@ -848,6 +848,7 @@ void mlx5_fpga_ipsec_delete_sa_ctx(void *context)
+ 	mutex_lock(&fpga_xfrm->lock);
+ 	if (!--fpga_xfrm->num_rules) {
+ 		mlx5_fpga_ipsec_release_sa_ctx(fpga_xfrm->sa_ctx);
++		kfree(fpga_xfrm->sa_ctx);
+ 		fpga_xfrm->sa_ctx = NULL;
+ 	}
+ 	mutex_unlock(&fpga_xfrm->lock);
+@@ -1472,7 +1473,7 @@ int mlx5_fpga_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
+ 	if (!memcmp(&xfrm->attrs, attrs, sizeof(xfrm->attrs)))
+ 		return 0;
+ 
+-	if (!mlx5_fpga_esp_validate_xfrm_attrs(mdev, attrs)) {
++	if (mlx5_fpga_esp_validate_xfrm_attrs(mdev, attrs)) {
+ 		mlx5_core_warn(mdev, "Tried to create an esp with unsupported attrs\n");
+ 		return -EOPNOTSUPP;
+ 	}
+diff --git a/drivers/net/ethernet/smsc/smc911x.c b/drivers/net/ethernet/smsc/smc911x.c
+index 8355dfbb8ec3..f97b35430c84 100644
+--- a/drivers/net/ethernet/smsc/smc911x.c
++++ b/drivers/net/ethernet/smsc/smc911x.c
+@@ -947,7 +947,7 @@ static void smc911x_phy_configure(struct work_struct *work)
+ 	if (lp->ctl_rspeed != 100)
+ 		my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF);
+ 
+-	 if (!lp->ctl_rfduplx)
++	if (!lp->ctl_rfduplx)
+ 		my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
+ 
+ 	/* Update our Auto-Neg Advertisement Register */
+diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+index f069adfc2b35..9c7b1d8e8220 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+@@ -4513,6 +4513,7 @@ int stmmac_suspend(struct device *dev)
+ {
+ 	struct net_device *ndev = dev_get_drvdata(dev);
+ 	struct stmmac_priv *priv = netdev_priv(ndev);
++	u32 chan;
+ 
+ 	if (!ndev || !netif_running(ndev))
+ 		return 0;
+@@ -4527,6 +4528,9 @@ int stmmac_suspend(struct device *dev)
+ 
+ 	stmmac_disable_all_queues(priv);
+ 
++	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
++		del_timer_sync(&priv->tx_queue[chan].txtimer);
++
+ 	/* Stop TX/RX DMA */
+ 	stmmac_stop_all_dma(priv);
+ 
+diff --git a/drivers/net/gtp.c b/drivers/net/gtp.c
+index ee086441dcbe..eab9984f73a8 100644
+--- a/drivers/net/gtp.c
++++ b/drivers/net/gtp.c
+@@ -772,12 +772,12 @@ static int gtp_hashtable_new(struct gtp_dev *gtp, int hsize)
+ 	int i;
+ 
+ 	gtp->addr_hash = kmalloc_array(hsize, sizeof(struct hlist_head),
+-				       GFP_KERNEL);
++				       GFP_KERNEL | __GFP_NOWARN);
+ 	if (gtp->addr_hash == NULL)
+ 		return -ENOMEM;
+ 
+ 	gtp->tid_hash = kmalloc_array(hsize, sizeof(struct hlist_head),
+-				      GFP_KERNEL);
++				      GFP_KERNEL | __GFP_NOWARN);
+ 	if (gtp->tid_hash == NULL)
+ 		goto err1;
+ 
+diff --git a/drivers/net/ppp/ppp_async.c b/drivers/net/ppp/ppp_async.c
+index bdc4d23627c5..bf03db40d4f0 100644
+--- a/drivers/net/ppp/ppp_async.c
++++ b/drivers/net/ppp/ppp_async.c
+@@ -878,15 +878,15 @@ ppp_async_input(struct asyncppp *ap, const unsigned char *buf,
+ 				skb = dev_alloc_skb(ap->mru + PPP_HDRLEN + 2);
+ 				if (!skb)
+ 					goto nomem;
+- 				ap->rpkt = skb;
+- 			}
+- 			if (skb->len == 0) {
+- 				/* Try to get the payload 4-byte aligned.
+- 				 * This should match the
+- 				 * PPP_ALLSTATIONS/PPP_UI/compressed tests in
+- 				 * process_input_packet, but we do not have
+- 				 * enough chars here to test buf[1] and buf[2].
+- 				 */
++				ap->rpkt = skb;
++			}
++			if (skb->len == 0) {
++				/* Try to get the payload 4-byte aligned.
++				 * This should match the
++				 * PPP_ALLSTATIONS/PPP_UI/compressed tests in
++				 * process_input_packet, but we do not have
++				 * enough chars here to test buf[1] and buf[2].
++				 */
+ 				if (buf[0] != PPP_ALLSTATIONS)
+ 					skb_reserve(skb, 2 + (buf[0] & 1));
+ 			}
+diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/usb.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/usb.c
+index 6a213fe760ff..41254f04ab15 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/usb.c
++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/usb.c
+@@ -441,6 +441,7 @@ fail:
+ 			usb_free_urb(req->urb);
+ 		list_del(q->next);
+ 	}
++	kfree(reqs);
+ 	return NULL;
+ 
+ }
+diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/nvm.c b/drivers/net/wireless/intel/iwlwifi/mvm/nvm.c
+index f2579c94ffdb..3270faafe0bc 100644
+--- a/drivers/net/wireless/intel/iwlwifi/mvm/nvm.c
++++ b/drivers/net/wireless/intel/iwlwifi/mvm/nvm.c
+@@ -286,7 +286,7 @@ iwl_parse_nvm_sections(struct iwl_mvm *mvm)
+ 	int regulatory_type;
+ 
+ 	/* Checking for required sections */
+-	if (mvm->trans->cfg->nvm_type != IWL_NVM_EXT) {
++	if (mvm->trans->cfg->nvm_type == IWL_NVM) {
+ 		if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data ||
+ 		    !mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data) {
+ 			IWL_ERR(mvm, "Can't parse empty OTP/NVM sections\n");
+diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/sta.c b/drivers/net/wireless/intel/iwlwifi/mvm/sta.c
+index 69057701641e..373ace38edab 100644
+--- a/drivers/net/wireless/intel/iwlwifi/mvm/sta.c
++++ b/drivers/net/wireless/intel/iwlwifi/mvm/sta.c
+@@ -3045,6 +3045,10 @@ static int iwl_mvm_send_sta_igtk(struct iwl_mvm *mvm,
+ 	igtk_cmd.sta_id = cpu_to_le32(sta_id);
+ 
+ 	if (remove_key) {
++		/* This is a valid situation for IGTK */
++		if (sta_id == IWL_MVM_INVALID_STA)
++			return 0;
++
+ 		igtk_cmd.ctrl_flags |= cpu_to_le32(STA_KEY_NOT_VALID);
+ 	} else {
+ 		struct ieee80211_key_seq seq;
+@@ -3352,9 +3356,9 @@ int iwl_mvm_remove_sta_key(struct iwl_mvm *mvm,
+ 	IWL_DEBUG_WEP(mvm, "mvm remove dynamic key: idx=%d sta=%d\n",
+ 		      keyconf->keyidx, sta_id);
+ 
+-	if (mvm_sta && (keyconf->cipher == WLAN_CIPHER_SUITE_AES_CMAC ||
+-			keyconf->cipher == WLAN_CIPHER_SUITE_BIP_GMAC_128 ||
+-			keyconf->cipher == WLAN_CIPHER_SUITE_BIP_GMAC_256))
++	if (keyconf->cipher == WLAN_CIPHER_SUITE_AES_CMAC ||
++	    keyconf->cipher == WLAN_CIPHER_SUITE_BIP_GMAC_128 ||
++	    keyconf->cipher == WLAN_CIPHER_SUITE_BIP_GMAC_256)
+ 		return iwl_mvm_send_sta_igtk(mvm, keyconf, sta_id, true);
+ 
+ 	if (!__test_and_clear_bit(keyconf->hw_key_idx, mvm->fw_key_table)) {
+diff --git a/drivers/net/wireless/marvell/mwifiex/sta_ioctl.c b/drivers/net/wireless/marvell/mwifiex/sta_ioctl.c
+index 6dd835f1efc2..fbfa0b15d0c8 100644
+--- a/drivers/net/wireless/marvell/mwifiex/sta_ioctl.c
++++ b/drivers/net/wireless/marvell/mwifiex/sta_ioctl.c
+@@ -232,6 +232,7 @@ static int mwifiex_process_country_ie(struct mwifiex_private *priv,
+ 
+ 	if (country_ie_len >
+ 	    (IEEE80211_COUNTRY_STRING_LEN + MWIFIEX_MAX_TRIPLET_802_11D)) {
++		rcu_read_unlock();
+ 		mwifiex_dbg(priv->adapter, ERROR,
+ 			    "11D: country_ie_len overflow!, deauth AP\n");
+ 		return -EINVAL;
+diff --git a/drivers/nfc/pn544/pn544.c b/drivers/nfc/pn544/pn544.c
+index 70e898e38b16..f30bdf95610f 100644
+--- a/drivers/nfc/pn544/pn544.c
++++ b/drivers/nfc/pn544/pn544.c
+@@ -704,7 +704,7 @@ static int pn544_hci_check_presence(struct nfc_hci_dev *hdev,
+ 		    target->nfcid1_len != 10)
+ 			return -EOPNOTSUPP;
+ 
+-		 return nfc_hci_send_cmd(hdev, NFC_HCI_RF_READER_A_GATE,
++		return nfc_hci_send_cmd(hdev, NFC_HCI_RF_READER_A_GATE,
+ 				     PN544_RF_READER_CMD_ACTIVATE_NEXT,
+ 				     target->nfcid1, target->nfcid1_len, NULL);
+ 	} else if (target->supported_protocols & (NFC_PROTO_JEWEL_MASK |
+diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
+index ad3fcad4d75b..5e1315900562 100644
+--- a/drivers/of/Kconfig
++++ b/drivers/of/Kconfig
+@@ -103,4 +103,8 @@ config OF_OVERLAY
+ config OF_NUMA
+ 	bool
+ 
++config OF_DMA_DEFAULT_COHERENT
++	# arches should select this if DMA is coherent by default for OF devices
++	bool
++
+ endif # OF
+diff --git a/drivers/of/address.c b/drivers/of/address.c
+index 7ddbf0a1ab86..c42aebba35ab 100644
+--- a/drivers/of/address.c
++++ b/drivers/of/address.c
+@@ -970,12 +970,16 @@ EXPORT_SYMBOL_GPL(of_dma_get_range);
+  * @np:	device node
+  *
+  * It returns true if "dma-coherent" property was found
+- * for this device in DT.
++ * for this device in the DT, or if DMA is coherent by
++ * default for OF devices on the current platform.
+  */
+ bool of_dma_is_coherent(struct device_node *np)
+ {
+ 	struct device_node *node = of_node_get(np);
+ 
++	if (IS_ENABLED(CONFIG_OF_DMA_DEFAULT_COHERENT))
++		return true;
++
+ 	while (node) {
+ 		if (of_property_read_bool(node, "dma-coherent")) {
+ 			of_node_put(node);
+diff --git a/drivers/pci/controller/dwc/pci-keystone-dw.c b/drivers/pci/controller/dwc/pci-keystone-dw.c
+index 0682213328e9..15c612e853af 100644
+--- a/drivers/pci/controller/dwc/pci-keystone-dw.c
++++ b/drivers/pci/controller/dwc/pci-keystone-dw.c
+@@ -425,7 +425,7 @@ void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
+ 	/* Disable Link training */
+ 	val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
+ 	val &= ~LTSSM_EN_VAL;
+-	ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
++	ks_dw_app_writel(ks_pcie, CMD_STATUS, val);
+ 
+ 	/* Initiate Link Training */
+ 	val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
+diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
+index 58e487352853..6f86583605a4 100644
+--- a/drivers/pci/controller/pci-tegra.c
++++ b/drivers/pci/controller/pci-tegra.c
+@@ -2398,7 +2398,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
+ 
+ 	pm_runtime_enable(pcie->dev);
+ 	err = pm_runtime_get_sync(pcie->dev);
+-	if (err) {
++	if (err < 0) {
+ 		dev_err(dev, "fail to enable pcie controller: %d\n", err);
+ 		goto teardown_msi;
+ 	}
+diff --git a/drivers/phy/qualcomm/phy-qcom-apq8064-sata.c b/drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
+index 69ce2afac015..c6925e3e878b 100644
+--- a/drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
++++ b/drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
+@@ -88,7 +88,7 @@ static int read_poll_timeout(void __iomem *addr, u32 mask)
+ 		if (readl_relaxed(addr) & mask)
+ 			return 0;
+ 
+-		 usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
++		usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
+ 	} while (!time_after(jiffies, timeout));
+ 
+ 	return (readl_relaxed(addr) & mask) ? 0 : -ETIMEDOUT;
+diff --git a/drivers/platform/x86/intel_scu_ipc.c b/drivers/platform/x86/intel_scu_ipc.c
+index 75c8fef7a482..54f131bec192 100644
+--- a/drivers/platform/x86/intel_scu_ipc.c
++++ b/drivers/platform/x86/intel_scu_ipc.c
+@@ -69,26 +69,22 @@
+ struct intel_scu_ipc_pdata_t {
+ 	u32 i2c_base;
+ 	u32 i2c_len;
+-	u8 irq_mode;
+ };
+ 
+ static const struct intel_scu_ipc_pdata_t intel_scu_ipc_lincroft_pdata = {
+ 	.i2c_base = 0xff12b000,
+ 	.i2c_len = 0x10,
+-	.irq_mode = 0,
+ };
+ 
+ /* Penwell and Cloverview */
+ static const struct intel_scu_ipc_pdata_t intel_scu_ipc_penwell_pdata = {
+ 	.i2c_base = 0xff12b000,
+ 	.i2c_len = 0x10,
+-	.irq_mode = 1,
+ };
+ 
+ static const struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata = {
+ 	.i2c_base  = 0xff00d000,
+ 	.i2c_len = 0x10,
+-	.irq_mode = 0,
+ };
+ 
+ struct intel_scu_ipc_dev {
+@@ -101,6 +97,9 @@ struct intel_scu_ipc_dev {
+ 
+ static struct intel_scu_ipc_dev  ipcdev; /* Only one for now */
+ 
++#define IPC_STATUS		0x04
++#define IPC_STATUS_IRQ		BIT(2)
++
+ /*
+  * IPC Read Buffer (Read Only):
+  * 16 byte buffer for receiving data from SCU, if IPC command
+@@ -122,11 +121,8 @@ static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
+  */
+ static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)
+ {
+-	if (scu->irq_mode) {
+-		reinit_completion(&scu->cmd_complete);
+-		writel(cmd | IPC_IOC, scu->ipc_base);
+-	}
+-	writel(cmd, scu->ipc_base);
++	reinit_completion(&scu->cmd_complete);
++	writel(cmd | IPC_IOC, scu->ipc_base);
+ }
+ 
+ /*
+@@ -612,9 +608,10 @@ EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
+ static irqreturn_t ioc(int irq, void *dev_id)
+ {
+ 	struct intel_scu_ipc_dev *scu = dev_id;
++	int status = ipc_read_status(scu);
+ 
+-	if (scu->irq_mode)
+-		complete(&scu->cmd_complete);
++	writel(status | IPC_STATUS_IRQ, scu->ipc_base + IPC_STATUS);
++	complete(&scu->cmd_complete);
+ 
+ 	return IRQ_HANDLED;
+ }
+@@ -640,8 +637,6 @@ static int ipc_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+ 	if (!pdata)
+ 		return -ENODEV;
+ 
+-	scu->irq_mode = pdata->irq_mode;
+-
+ 	err = pcim_enable_device(pdev);
+ 	if (err)
+ 		return err;
+diff --git a/drivers/power/supply/ltc2941-battery-gauge.c b/drivers/power/supply/ltc2941-battery-gauge.c
+index 4f129bb4c972..ff5febea1a21 100644
+--- a/drivers/power/supply/ltc2941-battery-gauge.c
++++ b/drivers/power/supply/ltc2941-battery-gauge.c
+@@ -448,7 +448,7 @@ static int ltc294x_i2c_remove(struct i2c_client *client)
+ {
+ 	struct ltc294x_info *info = i2c_get_clientdata(client);
+ 
+-	cancel_delayed_work(&info->work);
++	cancel_delayed_work_sync(&info->work);
+ 	power_supply_unregister(info->supply);
+ 	return 0;
+ }
+diff --git a/drivers/scsi/csiostor/csio_scsi.c b/drivers/scsi/csiostor/csio_scsi.c
+index e09c7f360dbd..0cb585759de6 100644
+--- a/drivers/scsi/csiostor/csio_scsi.c
++++ b/drivers/scsi/csiostor/csio_scsi.c
+@@ -1383,7 +1383,7 @@ csio_device_reset(struct device *dev,
+ 		return -EINVAL;
+ 
+ 	/* Delete NPIV lnodes */
+-	 csio_lnodes_exit(hw, 1);
++	csio_lnodes_exit(hw, 1);
+ 
+ 	/* Block upper IOs */
+ 	csio_lnodes_block_request(hw);
+diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c
+index c7533fa7f46e..36871760a5d3 100644
+--- a/drivers/scsi/qla2xxx/qla_dbg.c
++++ b/drivers/scsi/qla2xxx/qla_dbg.c
+@@ -2520,12 +2520,6 @@ qla83xx_fw_dump_failed:
+ /*                         Driver Debug Functions.                          */
+ /****************************************************************************/
+ 
+-static inline int
+-ql_mask_match(uint32_t level)
+-{
+-	return (level & ql2xextended_error_logging) == level;
+-}
+-
+ /*
+  * This function is for formatting and logging debug information.
+  * It is to be used when vha is available. It formats the message
+diff --git a/drivers/scsi/qla2xxx/qla_dbg.h b/drivers/scsi/qla2xxx/qla_dbg.h
+index 8877aa97d829..ceca6dd34db1 100644
+--- a/drivers/scsi/qla2xxx/qla_dbg.h
++++ b/drivers/scsi/qla2xxx/qla_dbg.h
+@@ -374,3 +374,9 @@ extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, uint32_t *,
+ extern void qla24xx_pause_risc(struct device_reg_24xx __iomem *,
+ 	struct qla_hw_data *);
+ extern int qla24xx_soft_reset(struct qla_hw_data *);
++
++static inline int
++ql_mask_match(uint level)
++{
++	return (level & ql2xextended_error_logging) == level;
++}
+diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c
+index 01ded6c6ad38..f9b3151f4b10 100644
+--- a/drivers/scsi/qla2xxx/qla_isr.c
++++ b/drivers/scsi/qla2xxx/qla_isr.c
+@@ -1876,6 +1876,18 @@ static void qla24xx_nvme_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
+ 		inbuf = (uint32_t *)&sts->nvme_ersp_data;
+ 		outbuf = (uint32_t *)fd->rspaddr;
+ 		iocb->u.nvme.rsp_pyld_len = le16_to_cpu(sts->nvme_rsp_pyld_len);
++		if (unlikely(iocb->u.nvme.rsp_pyld_len >
++		    sizeof(struct nvme_fc_ersp_iu))) {
++			if (ql_mask_match(ql_dbg_io)) {
++				WARN_ONCE(1, "Unexpected response payload length %u.\n",
++				    iocb->u.nvme.rsp_pyld_len);
++				ql_log(ql_log_warn, fcport->vha, 0x5100,
++				    "Unexpected response payload length %u.\n",
++				    iocb->u.nvme.rsp_pyld_len);
++			}
++			iocb->u.nvme.rsp_pyld_len =
++			    sizeof(struct nvme_fc_ersp_iu);
++		}
+ 		iter = iocb->u.nvme.rsp_pyld_len >> 2;
+ 		for (; iter; iter--)
+ 			*outbuf++ = swab32(*inbuf++);
+diff --git a/drivers/scsi/qla2xxx/qla_mbx.c b/drivers/scsi/qla2xxx/qla_mbx.c
+index abef3b29fa10..bef9faea5eee 100644
+--- a/drivers/scsi/qla2xxx/qla_mbx.c
++++ b/drivers/scsi/qla2xxx/qla_mbx.c
+@@ -5994,9 +5994,8 @@ qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
+ 	mcp->mb[7] = LSW(MSD(req_dma));
+ 	mcp->mb[8] = MSW(addr);
+ 	/* Setting RAM ID to valid */
+-	mcp->mb[10] |= BIT_7;
+ 	/* For MCTP RAM ID is 0x40 */
+-	mcp->mb[10] |= 0x40;
++	mcp->mb[10] = BIT_7 | 0x40;
+ 
+ 	mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
+ 	    MBX_0;
+diff --git a/drivers/scsi/qla2xxx/qla_nx.c b/drivers/scsi/qla2xxx/qla_nx.c
+index de2bc78449e7..3007eecfa509 100644
+--- a/drivers/scsi/qla2xxx/qla_nx.c
++++ b/drivers/scsi/qla2xxx/qla_nx.c
+@@ -1605,8 +1605,7 @@ qla82xx_get_bootld_offset(struct qla_hw_data *ha)
+ 	return (u8 *)&ha->hablob->fw->data[offset];
+ }
+ 
+-static __le32
+-qla82xx_get_fw_size(struct qla_hw_data *ha)
++static u32 qla82xx_get_fw_size(struct qla_hw_data *ha)
+ {
+ 	struct qla82xx_uri_data_desc *uri_desc = NULL;
+ 
+@@ -1617,7 +1616,7 @@ qla82xx_get_fw_size(struct qla_hw_data *ha)
+ 			return cpu_to_le32(uri_desc->size);
+ 	}
+ 
+-	return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]);
++	return get_unaligned_le32(&ha->hablob->fw->data[FW_SIZE_OFFSET]);
+ }
+ 
+ static u8 *
+@@ -1808,7 +1807,7 @@ qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
+ 	}
+ 
+ 	flashaddr = FLASH_ADDR_START;
+-	size = (__force u32)qla82xx_get_fw_size(ha) / 8;
++	size = qla82xx_get_fw_size(ha) / 8;
+ 	ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
+ 
+ 	for (i = 0; i < size; i++) {
+diff --git a/drivers/scsi/qla4xxx/ql4_os.c b/drivers/scsi/qla4xxx/ql4_os.c
+index f8acf101af3d..f59b8982b288 100644
+--- a/drivers/scsi/qla4xxx/ql4_os.c
++++ b/drivers/scsi/qla4xxx/ql4_os.c
+@@ -4146,7 +4146,7 @@ static void qla4xxx_mem_free(struct scsi_qla_host *ha)
+ 		dma_free_coherent(&ha->pdev->dev, ha->queues_len, ha->queues,
+ 				  ha->queues_dma);
+ 
+-	 if (ha->fw_dump)
++	if (ha->fw_dump)
+ 		vfree(ha->fw_dump);
+ 
+ 	ha->queues_len = 0;
+diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
+index 3601e770da16..af01be59a721 100644
+--- a/drivers/scsi/ufs/ufshcd.c
++++ b/drivers/scsi/ufs/ufshcd.c
+@@ -5044,6 +5044,7 @@ static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
+ 
+ 	hba->auto_bkops_enabled = false;
+ 	trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
++	hba->is_urgent_bkops_lvl_checked = false;
+ out:
+ 	return err;
+ }
+@@ -5068,6 +5069,7 @@ static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
+ 		hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
+ 		ufshcd_disable_auto_bkops(hba);
+ 	}
++	hba->is_urgent_bkops_lvl_checked = false;
+ }
+ 
+ static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
+@@ -5114,6 +5116,7 @@ static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
+ 		err = ufshcd_enable_auto_bkops(hba);
+ 	else
+ 		err = ufshcd_disable_auto_bkops(hba);
++	hba->urgent_bkops_lvl = curr_status;
+ out:
+ 	return err;
+ }
+diff --git a/drivers/usb/gadget/function/f_ecm.c b/drivers/usb/gadget/function/f_ecm.c
+index 460d5d7c984f..7f5cf488b2b1 100644
+--- a/drivers/usb/gadget/function/f_ecm.c
++++ b/drivers/usb/gadget/function/f_ecm.c
+@@ -52,6 +52,7 @@ struct f_ecm {
+ 	struct usb_ep			*notify;
+ 	struct usb_request		*notify_req;
+ 	u8				notify_state;
++	atomic_t			notify_count;
+ 	bool				is_open;
+ 
+ 	/* FIXME is_open needs some irq-ish locking
+@@ -380,7 +381,7 @@ static void ecm_do_notify(struct f_ecm *ecm)
+ 	int				status;
+ 
+ 	/* notification already in flight? */
+-	if (!req)
++	if (atomic_read(&ecm->notify_count))
+ 		return;
+ 
+ 	event = req->buf;
+@@ -420,10 +421,10 @@ static void ecm_do_notify(struct f_ecm *ecm)
+ 	event->bmRequestType = 0xA1;
+ 	event->wIndex = cpu_to_le16(ecm->ctrl_id);
+ 
+-	ecm->notify_req = NULL;
++	atomic_inc(&ecm->notify_count);
+ 	status = usb_ep_queue(ecm->notify, req, GFP_ATOMIC);
+ 	if (status < 0) {
+-		ecm->notify_req = req;
++		atomic_dec(&ecm->notify_count);
+ 		DBG(cdev, "notify --> %d\n", status);
+ 	}
+ }
+@@ -448,17 +449,19 @@ static void ecm_notify_complete(struct usb_ep *ep, struct usb_request *req)
+ 	switch (req->status) {
+ 	case 0:
+ 		/* no fault */
++		atomic_dec(&ecm->notify_count);
+ 		break;
+ 	case -ECONNRESET:
+ 	case -ESHUTDOWN:
++		atomic_set(&ecm->notify_count, 0);
+ 		ecm->notify_state = ECM_NOTIFY_NONE;
+ 		break;
+ 	default:
+ 		DBG(cdev, "event %02x --> %d\n",
+ 			event->bNotificationType, req->status);
++		atomic_dec(&ecm->notify_count);
+ 		break;
+ 	}
+-	ecm->notify_req = req;
+ 	ecm_do_notify(ecm);
+ }
+ 
+@@ -907,6 +910,11 @@ static void ecm_unbind(struct usb_configuration *c, struct usb_function *f)
+ 
+ 	usb_free_all_descriptors(f);
+ 
++	if (atomic_read(&ecm->notify_count)) {
++		usb_ep_dequeue(ecm->notify, ecm->notify_req);
++		atomic_set(&ecm->notify_count, 0);
++	}
++
+ 	kfree(ecm->notify_req->buf);
+ 	usb_ep_free_request(ecm->notify, ecm->notify_req);
+ }
+diff --git a/drivers/usb/gadget/function/f_ncm.c b/drivers/usb/gadget/function/f_ncm.c
+index 5780fba620ab..cfca4584ae13 100644
+--- a/drivers/usb/gadget/function/f_ncm.c
++++ b/drivers/usb/gadget/function/f_ncm.c
+@@ -54,6 +54,7 @@ struct f_ncm {
+ 	struct usb_ep			*notify;
+ 	struct usb_request		*notify_req;
+ 	u8				notify_state;
++	atomic_t			notify_count;
+ 	bool				is_open;
+ 
+ 	const struct ndp_parser_opts	*parser_opts;
+@@ -547,7 +548,7 @@ static void ncm_do_notify(struct f_ncm *ncm)
+ 	int				status;
+ 
+ 	/* notification already in flight? */
+-	if (!req)
++	if (atomic_read(&ncm->notify_count))
+ 		return;
+ 
+ 	event = req->buf;
+@@ -587,7 +588,8 @@ static void ncm_do_notify(struct f_ncm *ncm)
+ 	event->bmRequestType = 0xA1;
+ 	event->wIndex = cpu_to_le16(ncm->ctrl_id);
+ 
+-	ncm->notify_req = NULL;
++	atomic_inc(&ncm->notify_count);
++
+ 	/*
+ 	 * In double buffering if there is a space in FIFO,
+ 	 * completion callback can be called right after the call,
+@@ -597,7 +599,7 @@ static void ncm_do_notify(struct f_ncm *ncm)
+ 	status = usb_ep_queue(ncm->notify, req, GFP_ATOMIC);
+ 	spin_lock(&ncm->lock);
+ 	if (status < 0) {
+-		ncm->notify_req = req;
++		atomic_dec(&ncm->notify_count);
+ 		DBG(cdev, "notify --> %d\n", status);
+ 	}
+ }
+@@ -632,17 +634,19 @@ static void ncm_notify_complete(struct usb_ep *ep, struct usb_request *req)
+ 	case 0:
+ 		VDBG(cdev, "Notification %02x sent\n",
+ 		     event->bNotificationType);
++		atomic_dec(&ncm->notify_count);
+ 		break;
+ 	case -ECONNRESET:
+ 	case -ESHUTDOWN:
++		atomic_set(&ncm->notify_count, 0);
+ 		ncm->notify_state = NCM_NOTIFY_NONE;
+ 		break;
+ 	default:
+ 		DBG(cdev, "event %02x --> %d\n",
+ 			event->bNotificationType, req->status);
++		atomic_dec(&ncm->notify_count);
+ 		break;
+ 	}
+-	ncm->notify_req = req;
+ 	ncm_do_notify(ncm);
+ 	spin_unlock(&ncm->lock);
+ }
+@@ -1612,6 +1616,11 @@ static void ncm_unbind(struct usb_configuration *c, struct usb_function *f)
+ 	ncm_string_defs[0].id = 0;
+ 	usb_free_all_descriptors(f);
+ 
++	if (atomic_read(&ncm->notify_count)) {
++		usb_ep_dequeue(ncm->notify, ncm->notify_req);
++		atomic_set(&ncm->notify_count, 0);
++	}
++
+ 	kfree(ncm->notify_req->buf);
+ 	usb_ep_free_request(ncm->notify, ncm->notify_req);
+ }
+diff --git a/drivers/usb/gadget/legacy/cdc2.c b/drivers/usb/gadget/legacy/cdc2.c
+index da1c37933ca1..8d7a556ece30 100644
+--- a/drivers/usb/gadget/legacy/cdc2.c
++++ b/drivers/usb/gadget/legacy/cdc2.c
+@@ -225,7 +225,7 @@ static struct usb_composite_driver cdc_driver = {
+ 	.name		= "g_cdc",
+ 	.dev		= &device_desc,
+ 	.strings	= dev_strings,
+-	.max_speed	= USB_SPEED_HIGH,
++	.max_speed	= USB_SPEED_SUPER,
+ 	.bind		= cdc_bind,
+ 	.unbind		= cdc_unbind,
+ };
+diff --git a/drivers/usb/gadget/legacy/g_ffs.c b/drivers/usb/gadget/legacy/g_ffs.c
+index b640ed3fcf70..ae6d8f7092b8 100644
+--- a/drivers/usb/gadget/legacy/g_ffs.c
++++ b/drivers/usb/gadget/legacy/g_ffs.c
+@@ -149,7 +149,7 @@ static struct usb_composite_driver gfs_driver = {
+ 	.name		= DRIVER_NAME,
+ 	.dev		= &gfs_dev_desc,
+ 	.strings	= gfs_dev_strings,
+-	.max_speed	= USB_SPEED_HIGH,
++	.max_speed	= USB_SPEED_SUPER,
+ 	.bind		= gfs_bind,
+ 	.unbind		= gfs_unbind,
+ };
+diff --git a/drivers/usb/gadget/legacy/multi.c b/drivers/usb/gadget/legacy/multi.c
+index 50515f9e1022..ec9749845660 100644
+--- a/drivers/usb/gadget/legacy/multi.c
++++ b/drivers/usb/gadget/legacy/multi.c
+@@ -482,7 +482,7 @@ static struct usb_composite_driver multi_driver = {
+ 	.name		= "g_multi",
+ 	.dev		= &device_desc,
+ 	.strings	= dev_strings,
+-	.max_speed	= USB_SPEED_HIGH,
++	.max_speed	= USB_SPEED_SUPER,
+ 	.bind		= multi_bind,
+ 	.unbind		= multi_unbind,
+ 	.needs_serial	= 1,
+diff --git a/drivers/usb/gadget/legacy/ncm.c b/drivers/usb/gadget/legacy/ncm.c
+index 8465f081e921..c61e71ba7045 100644
+--- a/drivers/usb/gadget/legacy/ncm.c
++++ b/drivers/usb/gadget/legacy/ncm.c
+@@ -197,7 +197,7 @@ static struct usb_composite_driver ncm_driver = {
+ 	.name		= "g_ncm",
+ 	.dev		= &device_desc,
+ 	.strings	= dev_strings,
+-	.max_speed	= USB_SPEED_HIGH,
++	.max_speed	= USB_SPEED_SUPER,
+ 	.bind		= gncm_bind,
+ 	.unbind		= gncm_unbind,
+ };
+diff --git a/drivers/usb/typec/tcpci.c b/drivers/usb/typec/tcpci.c
+index c1f7073a56de..dfae41fe1331 100644
+--- a/drivers/usb/typec/tcpci.c
++++ b/drivers/usb/typec/tcpci.c
+@@ -581,6 +581,12 @@ static int tcpci_probe(struct i2c_client *client,
+ static int tcpci_remove(struct i2c_client *client)
+ {
+ 	struct tcpci_chip *chip = i2c_get_clientdata(client);
++	int err;
++
++	/* Disable chip interrupts before unregistering port */
++	err = tcpci_write16(chip->tcpci, TCPC_ALERT_MASK, 0);
++	if (err < 0)
++		return err;
+ 
+ 	tcpci_unregister_port(chip->tcpci);
+ 
+diff --git a/drivers/watchdog/watchdog_core.c b/drivers/watchdog/watchdog_core.c
+index eb8fa25f8eb2..8b1f37ffb65a 100644
+--- a/drivers/watchdog/watchdog_core.c
++++ b/drivers/watchdog/watchdog_core.c
+@@ -138,6 +138,25 @@ int watchdog_init_timeout(struct watchdog_device *wdd,
+ }
+ EXPORT_SYMBOL_GPL(watchdog_init_timeout);
+ 
++static int watchdog_reboot_notifier(struct notifier_block *nb,
++				    unsigned long code, void *data)
++{
++	struct watchdog_device *wdd;
++
++	wdd = container_of(nb, struct watchdog_device, reboot_nb);
++	if (code == SYS_DOWN || code == SYS_HALT) {
++		if (watchdog_active(wdd)) {
++			int ret;
++
++			ret = wdd->ops->stop(wdd);
++			if (ret)
++				return NOTIFY_BAD;
++		}
++	}
++
++	return NOTIFY_DONE;
++}
++
+ static int watchdog_restart_notifier(struct notifier_block *nb,
+ 				     unsigned long action, void *data)
+ {
+@@ -226,6 +245,19 @@ static int __watchdog_register_device(struct watchdog_device *wdd)
+ 		}
+ 	}
+ 
++	if (test_bit(WDOG_STOP_ON_REBOOT, &wdd->status)) {
++		wdd->reboot_nb.notifier_call = watchdog_reboot_notifier;
++
++		ret = register_reboot_notifier(&wdd->reboot_nb);
++		if (ret) {
++			pr_err("watchdog%d: Cannot register reboot notifier (%d)\n",
++			       wdd->id, ret);
++			watchdog_dev_unregister(wdd);
++			ida_simple_remove(&watchdog_ida, id);
++			return ret;
++		}
++	}
++
+ 	if (wdd->ops->restart) {
+ 		wdd->restart_nb.notifier_call = watchdog_restart_notifier;
+ 
+@@ -271,6 +303,9 @@ static void __watchdog_unregister_device(struct watchdog_device *wdd)
+ 	if (wdd->ops->restart)
+ 		unregister_restart_handler(&wdd->restart_nb);
+ 
++	if (test_bit(WDOG_STOP_ON_REBOOT, &wdd->status))
++		unregister_reboot_notifier(&wdd->reboot_nb);
++
+ 	watchdog_dev_unregister(wdd);
+ 	ida_simple_remove(&watchdog_ida, wdd->id);
+ }
+diff --git a/drivers/watchdog/watchdog_dev.c b/drivers/watchdog/watchdog_dev.c
+index 4b89333e8eb4..e64aa88e99da 100644
+--- a/drivers/watchdog/watchdog_dev.c
++++ b/drivers/watchdog/watchdog_dev.c
+@@ -42,7 +42,6 @@
+ #include <linux/miscdevice.h>	/* For handling misc devices */
+ #include <linux/module.h>	/* For module stuff/... */
+ #include <linux/mutex.h>	/* For mutexes */
+-#include <linux/reboot.h>	/* For reboot notifier */
+ #include <linux/slab.h>		/* For memory functions */
+ #include <linux/types.h>	/* For standard types (like size_t) */
+ #include <linux/watchdog.h>	/* For watchdog specific items */
+@@ -1048,25 +1047,6 @@ static void watchdog_cdev_unregister(struct watchdog_device *wdd)
+ 	put_device(&wd_data->dev);
+ }
+ 
+-static int watchdog_reboot_notifier(struct notifier_block *nb,
+-				    unsigned long code, void *data)
+-{
+-	struct watchdog_device *wdd;
+-
+-	wdd = container_of(nb, struct watchdog_device, reboot_nb);
+-	if (code == SYS_DOWN || code == SYS_HALT) {
+-		if (watchdog_active(wdd)) {
+-			int ret;
+-
+-			ret = wdd->ops->stop(wdd);
+-			if (ret)
+-				return NOTIFY_BAD;
+-		}
+-	}
+-
+-	return NOTIFY_DONE;
+-}
+-
+ /*
+  *	watchdog_dev_register: register a watchdog device
+  *	@wdd: watchdog device
+@@ -1085,22 +1065,8 @@ int watchdog_dev_register(struct watchdog_device *wdd)
+ 		return ret;
+ 
+ 	ret = watchdog_register_pretimeout(wdd);
+-	if (ret) {
++	if (ret)
+ 		watchdog_cdev_unregister(wdd);
+-		return ret;
+-	}
+-
+-	if (test_bit(WDOG_STOP_ON_REBOOT, &wdd->status)) {
+-		wdd->reboot_nb.notifier_call = watchdog_reboot_notifier;
+-
+-		ret = devm_register_reboot_notifier(&wdd->wd_data->dev,
+-						    &wdd->reboot_nb);
+-		if (ret) {
+-			pr_err("watchdog%d: Cannot register reboot notifier (%d)\n",
+-			       wdd->id, ret);
+-			watchdog_dev_unregister(wdd);
+-		}
+-	}
+ 
+ 	return ret;
+ }
+diff --git a/drivers/xen/xen-balloon.c b/drivers/xen/xen-balloon.c
+index 2acbfe104e46..3aab77916915 100644
+--- a/drivers/xen/xen-balloon.c
++++ b/drivers/xen/xen-balloon.c
+@@ -83,7 +83,7 @@ static void watch_target(struct xenbus_watch *watch,
+ 				  "%llu", &static_max) == 1))
+ 			static_max >>= PAGE_SHIFT - 10;
+ 		else
+-			static_max = new_target;
++			static_max = balloon_stats.current_pages;
+ 
+ 		target_diff = (xen_pv_domain() || xen_initial_domain()) ? 0
+ 				: static_max - balloon_stats.target_pages;
+diff --git a/fs/aio.c b/fs/aio.c
+index 911e23087dfb..b5fbf2061868 100644
+--- a/fs/aio.c
++++ b/fs/aio.c
+@@ -1600,6 +1600,14 @@ static int aio_fsync(struct fsync_iocb *req, const struct iocb *iocb,
+ 	return 0;
+ }
+ 
++static void aio_poll_put_work(struct work_struct *work)
++{
++	struct poll_iocb *req = container_of(work, struct poll_iocb, work);
++	struct aio_kiocb *iocb = container_of(req, struct aio_kiocb, poll);
++
++	iocb_put(iocb);
++}
++
+ static void aio_poll_complete_work(struct work_struct *work)
+ {
+ 	struct poll_iocb *req = container_of(work, struct poll_iocb, work);
+@@ -1664,6 +1672,8 @@ static int aio_poll_wake(struct wait_queue_entry *wait, unsigned mode, int sync,
+ 	list_del_init(&req->wait.entry);
+ 
+ 	if (mask && spin_trylock_irqsave(&iocb->ki_ctx->ctx_lock, flags)) {
++		struct kioctx *ctx = iocb->ki_ctx;
++
+ 		/*
+ 		 * Try to complete the iocb inline if we can. Use
+ 		 * irqsave/irqrestore because not all filesystems (e.g. fuse)
+@@ -1673,8 +1683,14 @@ static int aio_poll_wake(struct wait_queue_entry *wait, unsigned mode, int sync,
+ 		list_del(&iocb->ki_list);
+ 		iocb->ki_res.res = mangle_poll(mask);
+ 		req->done = true;
+-		spin_unlock_irqrestore(&iocb->ki_ctx->ctx_lock, flags);
+-		iocb_put(iocb);
++		if (iocb->ki_eventfd && eventfd_signal_count()) {
++			iocb = NULL;
++			INIT_WORK(&req->work, aio_poll_put_work);
++			schedule_work(&req->work);
++		}
++		spin_unlock_irqrestore(&ctx->ctx_lock, flags);
++		if (iocb)
++			iocb_put(iocb);
+ 	} else {
+ 		schedule_work(&req->work);
+ 	}
+diff --git a/fs/btrfs/ctree.c b/fs/btrfs/ctree.c
+index 84ff398ae70b..c9943d70e2cb 100644
+--- a/fs/btrfs/ctree.c
++++ b/fs/btrfs/ctree.c
+@@ -337,12 +337,10 @@ u64 btrfs_get_tree_mod_seq(struct btrfs_fs_info *fs_info,
+ 			   struct seq_list *elem)
+ {
+ 	write_lock(&fs_info->tree_mod_log_lock);
+-	spin_lock(&fs_info->tree_mod_seq_lock);
+ 	if (!elem->seq) {
+ 		elem->seq = btrfs_inc_tree_mod_seq(fs_info);
+ 		list_add_tail(&elem->list, &fs_info->tree_mod_seq_list);
+ 	}
+-	spin_unlock(&fs_info->tree_mod_seq_lock);
+ 	write_unlock(&fs_info->tree_mod_log_lock);
+ 
+ 	return elem->seq;
+@@ -362,7 +360,7 @@ void btrfs_put_tree_mod_seq(struct btrfs_fs_info *fs_info,
+ 	if (!seq_putting)
+ 		return;
+ 
+-	spin_lock(&fs_info->tree_mod_seq_lock);
++	write_lock(&fs_info->tree_mod_log_lock);
+ 	list_del(&elem->list);
+ 	elem->seq = 0;
+ 
+@@ -373,19 +371,17 @@ void btrfs_put_tree_mod_seq(struct btrfs_fs_info *fs_info,
+ 				 * blocker with lower sequence number exists, we
+ 				 * cannot remove anything from the log
+ 				 */
+-				spin_unlock(&fs_info->tree_mod_seq_lock);
++				write_unlock(&fs_info->tree_mod_log_lock);
+ 				return;
+ 			}
+ 			min_seq = cur_elem->seq;
+ 		}
+ 	}
+-	spin_unlock(&fs_info->tree_mod_seq_lock);
+ 
+ 	/*
+ 	 * anything that's lower than the lowest existing (read: blocked)
+ 	 * sequence number can be removed from the tree.
+ 	 */
+-	write_lock(&fs_info->tree_mod_log_lock);
+ 	tm_root = &fs_info->tree_mod_log;
+ 	for (node = rb_first(tm_root); node; node = next) {
+ 		next = rb_next(node);
+diff --git a/fs/btrfs/ctree.h b/fs/btrfs/ctree.h
+index d24ecbf938b6..15cb96ad15d8 100644
+--- a/fs/btrfs/ctree.h
++++ b/fs/btrfs/ctree.h
+@@ -893,14 +893,12 @@ struct btrfs_fs_info {
+ 	struct list_head delayed_iputs;
+ 	struct mutex cleaner_delayed_iput_mutex;
+ 
+-	/* this protects tree_mod_seq_list */
+-	spinlock_t tree_mod_seq_lock;
+ 	atomic64_t tree_mod_seq;
+-	struct list_head tree_mod_seq_list;
+ 
+-	/* this protects tree_mod_log */
++	/* this protects tree_mod_log and tree_mod_seq_list */
+ 	rwlock_t tree_mod_log_lock;
+ 	struct rb_root tree_mod_log;
++	struct list_head tree_mod_seq_list;
+ 
+ 	atomic_t async_delalloc_pages;
+ 
+diff --git a/fs/btrfs/delayed-ref.c b/fs/btrfs/delayed-ref.c
+index 7e5c81e80e15..09a12115b640 100644
+--- a/fs/btrfs/delayed-ref.c
++++ b/fs/btrfs/delayed-ref.c
+@@ -301,7 +301,7 @@ void btrfs_merge_delayed_refs(struct btrfs_trans_handle *trans,
+ 	if (head->is_data)
+ 		return;
+ 
+-	spin_lock(&fs_info->tree_mod_seq_lock);
++	read_lock(&fs_info->tree_mod_log_lock);
+ 	if (!list_empty(&fs_info->tree_mod_seq_list)) {
+ 		struct seq_list *elem;
+ 
+@@ -309,7 +309,7 @@ void btrfs_merge_delayed_refs(struct btrfs_trans_handle *trans,
+ 					struct seq_list, list);
+ 		seq = elem->seq;
+ 	}
+-	spin_unlock(&fs_info->tree_mod_seq_lock);
++	read_unlock(&fs_info->tree_mod_log_lock);
+ 
+ again:
+ 	for (node = rb_first(&head->ref_tree); node; node = rb_next(node)) {
+@@ -326,7 +326,7 @@ int btrfs_check_delayed_seq(struct btrfs_fs_info *fs_info, u64 seq)
+ 	struct seq_list *elem;
+ 	int ret = 0;
+ 
+-	spin_lock(&fs_info->tree_mod_seq_lock);
++	read_lock(&fs_info->tree_mod_log_lock);
+ 	if (!list_empty(&fs_info->tree_mod_seq_list)) {
+ 		elem = list_first_entry(&fs_info->tree_mod_seq_list,
+ 					struct seq_list, list);
+@@ -339,7 +339,7 @@ int btrfs_check_delayed_seq(struct btrfs_fs_info *fs_info, u64 seq)
+ 		}
+ 	}
+ 
+-	spin_unlock(&fs_info->tree_mod_seq_lock);
++	read_unlock(&fs_info->tree_mod_log_lock);
+ 	return ret;
+ }
+ 
+diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c
+index e12c37f457e0..9e467e8a8cb5 100644
+--- a/fs/btrfs/disk-io.c
++++ b/fs/btrfs/disk-io.c
+@@ -2031,7 +2031,7 @@ static void free_root_extent_buffers(struct btrfs_root *root)
+ }
+ 
+ /* helper to cleanup tree roots */
+-static void free_root_pointers(struct btrfs_fs_info *info, int chunk_root)
++static void free_root_pointers(struct btrfs_fs_info *info, bool free_chunk_root)
+ {
+ 	free_root_extent_buffers(info->tree_root);
+ 
+@@ -2040,7 +2040,7 @@ static void free_root_pointers(struct btrfs_fs_info *info, int chunk_root)
+ 	free_root_extent_buffers(info->csum_root);
+ 	free_root_extent_buffers(info->quota_root);
+ 	free_root_extent_buffers(info->uuid_root);
+-	if (chunk_root)
++	if (free_chunk_root)
+ 		free_root_extent_buffers(info->chunk_root);
+ 	free_root_extent_buffers(info->free_space_root);
+ }
+@@ -2645,7 +2645,6 @@ int open_ctree(struct super_block *sb,
+ 	spin_lock_init(&fs_info->fs_roots_radix_lock);
+ 	spin_lock_init(&fs_info->delayed_iput_lock);
+ 	spin_lock_init(&fs_info->defrag_inodes_lock);
+-	spin_lock_init(&fs_info->tree_mod_seq_lock);
+ 	spin_lock_init(&fs_info->super_lock);
+ 	spin_lock_init(&fs_info->qgroup_op_lock);
+ 	spin_lock_init(&fs_info->buffer_lock);
+@@ -3274,7 +3273,7 @@ fail_block_groups:
+ 	btrfs_put_block_group_cache(fs_info);
+ 
+ fail_tree_roots:
+-	free_root_pointers(fs_info, 1);
++	free_root_pointers(fs_info, true);
+ 	invalidate_inode_pages2(fs_info->btree_inode->i_mapping);
+ 
+ fail_sb_buffer:
+@@ -3302,7 +3301,7 @@ recovery_tree_root:
+ 	if (!btrfs_test_opt(fs_info, USEBACKUPROOT))
+ 		goto fail_tree_roots;
+ 
+-	free_root_pointers(fs_info, 0);
++	free_root_pointers(fs_info, false);
+ 
+ 	/* don't use the log in recovery mode, it won't be valid */
+ 	btrfs_set_super_log_root(disk_super, 0);
+@@ -3984,10 +3983,17 @@ void close_ctree(struct btrfs_fs_info *fs_info)
+ 	invalidate_inode_pages2(fs_info->btree_inode->i_mapping);
+ 	btrfs_stop_all_workers(fs_info);
+ 
+-	btrfs_free_block_groups(fs_info);
+-
+ 	clear_bit(BTRFS_FS_OPEN, &fs_info->flags);
+-	free_root_pointers(fs_info, 1);
++	free_root_pointers(fs_info, true);
++
++	/*
++	 * We must free the block groups after dropping the fs_roots as we could
++	 * have had an IO error and have left over tree log blocks that aren't
++	 * cleaned up until the fs roots are freed.  This makes the block group
++	 * accounting appear to be wrong because there's pending reserved bytes,
++	 * so make sure we do the block group cleanup afterwards.
++	 */
++	btrfs_free_block_groups(fs_info);
+ 
+ 	iput(fs_info->btree_inode);
+ 
+diff --git a/fs/btrfs/extent_io.c b/fs/btrfs/extent_io.c
+index fed44390c049..11efb4f5041c 100644
+--- a/fs/btrfs/extent_io.c
++++ b/fs/btrfs/extent_io.c
+@@ -4014,6 +4014,14 @@ retry:
+ 		 */
+ 		scanned = 1;
+ 		index = 0;
++
++		/*
++		 * If we're looping we could run into a page that is locked by a
++		 * writer and that writer could be waiting on writeback for a
++		 * page in our current bio, and thus deadlock, so flush the
++		 * write bio here.
++		 */
++		flush_write_bio(epd);
+ 		goto retry;
+ 	}
+ 
+diff --git a/fs/btrfs/tests/btrfs-tests.c b/fs/btrfs/tests/btrfs-tests.c
+index db72b3b6209e..2eec1dd3803a 100644
+--- a/fs/btrfs/tests/btrfs-tests.c
++++ b/fs/btrfs/tests/btrfs-tests.c
+@@ -102,7 +102,6 @@ struct btrfs_fs_info *btrfs_alloc_dummy_fs_info(u32 nodesize, u32 sectorsize)
+ 	spin_lock_init(&fs_info->qgroup_op_lock);
+ 	spin_lock_init(&fs_info->super_lock);
+ 	spin_lock_init(&fs_info->fs_roots_radix_lock);
+-	spin_lock_init(&fs_info->tree_mod_seq_lock);
+ 	mutex_init(&fs_info->qgroup_ioctl_lock);
+ 	mutex_init(&fs_info->qgroup_rescan_lock);
+ 	rwlock_init(&fs_info->tree_mod_log_lock);
+diff --git a/fs/btrfs/transaction.c b/fs/btrfs/transaction.c
+index 26317bca5649..4b1491e1b803 100644
+--- a/fs/btrfs/transaction.c
++++ b/fs/btrfs/transaction.c
+@@ -1936,6 +1936,14 @@ int btrfs_commit_transaction(struct btrfs_trans_handle *trans)
+ 	struct btrfs_transaction *prev_trans = NULL;
+ 	int ret;
+ 
++	/*
++	 * Some places just start a transaction to commit it.  We need to make
++	 * sure that if this commit fails that the abort code actually marks the
++	 * transaction as failed, so set trans->dirty to make the abort code do
++	 * the right thing.
++	 */
++	trans->dirty = true;
++
+ 	/* Stop the commit early if ->aborted is set */
+ 	if (unlikely(READ_ONCE(cur_trans->aborted))) {
+ 		ret = cur_trans->aborted;
+diff --git a/fs/btrfs/tree-log.c b/fs/btrfs/tree-log.c
+index fe7165c9d875..d4c86c6cbe39 100644
+--- a/fs/btrfs/tree-log.c
++++ b/fs/btrfs/tree-log.c
+@@ -3892,7 +3892,7 @@ static int log_csums(struct btrfs_trans_handle *trans,
+ static noinline int copy_items(struct btrfs_trans_handle *trans,
+ 			       struct btrfs_inode *inode,
+ 			       struct btrfs_path *dst_path,
+-			       struct btrfs_path *src_path, u64 *last_extent,
++			       struct btrfs_path *src_path,
+ 			       int start_slot, int nr, int inode_only,
+ 			       u64 logged_isize)
+ {
+@@ -3903,7 +3903,6 @@ static noinline int copy_items(struct btrfs_trans_handle *trans,
+ 	struct btrfs_file_extent_item *extent;
+ 	struct btrfs_inode_item *inode_item;
+ 	struct extent_buffer *src = src_path->nodes[0];
+-	struct btrfs_key first_key, last_key, key;
+ 	int ret;
+ 	struct btrfs_key *ins_keys;
+ 	u32 *ins_sizes;
+@@ -3911,9 +3910,6 @@ static noinline int copy_items(struct btrfs_trans_handle *trans,
+ 	int i;
+ 	struct list_head ordered_sums;
+ 	int skip_csum = inode->flags & BTRFS_INODE_NODATASUM;
+-	bool has_extents = false;
+-	bool need_find_last_extent = true;
+-	bool done = false;
+ 
+ 	INIT_LIST_HEAD(&ordered_sums);
+ 
+@@ -3922,8 +3918,6 @@ static noinline int copy_items(struct btrfs_trans_handle *trans,
+ 	if (!ins_data)
+ 		return -ENOMEM;
+ 
+-	first_key.objectid = (u64)-1;
+-
+ 	ins_sizes = (u32 *)ins_data;
+ 	ins_keys = (struct btrfs_key *)(ins_data + nr * sizeof(u32));
+ 
+@@ -3944,9 +3938,6 @@ static noinline int copy_items(struct btrfs_trans_handle *trans,
+ 
+ 		src_offset = btrfs_item_ptr_offset(src, start_slot + i);
+ 
+-		if (i == nr - 1)
+-			last_key = ins_keys[i];
+-
+ 		if (ins_keys[i].type == BTRFS_INODE_ITEM_KEY) {
+ 			inode_item = btrfs_item_ptr(dst_path->nodes[0],
+ 						    dst_path->slots[0],
+@@ -3960,20 +3951,6 @@ static noinline int copy_items(struct btrfs_trans_handle *trans,
+ 					   src_offset, ins_sizes[i]);
+ 		}
+ 
+-		/*
+-		 * We set need_find_last_extent here in case we know we were
+-		 * processing other items and then walk into the first extent in
+-		 * the inode.  If we don't hit an extent then nothing changes,
+-		 * we'll do the last search the next time around.
+-		 */
+-		if (ins_keys[i].type == BTRFS_EXTENT_DATA_KEY) {
+-			has_extents = true;
+-			if (first_key.objectid == (u64)-1)
+-				first_key = ins_keys[i];
+-		} else {
+-			need_find_last_extent = false;
+-		}
+-
+ 		/* take a reference on file data extents so that truncates
+ 		 * or deletes of this inode don't have to relog the inode
+ 		 * again
+@@ -4039,167 +4016,6 @@ static noinline int copy_items(struct btrfs_trans_handle *trans,
+ 		kfree(sums);
+ 	}
+ 
+-	if (!has_extents)
+-		return ret;
+-
+-	if (need_find_last_extent && *last_extent == first_key.offset) {
+-		/*
+-		 * We don't have any leafs between our current one and the one
+-		 * we processed before that can have file extent items for our
+-		 * inode (and have a generation number smaller than our current
+-		 * transaction id).
+-		 */
+-		need_find_last_extent = false;
+-	}
+-
+-	/*
+-	 * Because we use btrfs_search_forward we could skip leaves that were
+-	 * not modified and then assume *last_extent is valid when it really
+-	 * isn't.  So back up to the previous leaf and read the end of the last
+-	 * extent before we go and fill in holes.
+-	 */
+-	if (need_find_last_extent) {
+-		u64 len;
+-
+-		ret = btrfs_prev_leaf(inode->root, src_path);
+-		if (ret < 0)
+-			return ret;
+-		if (ret)
+-			goto fill_holes;
+-		if (src_path->slots[0])
+-			src_path->slots[0]--;
+-		src = src_path->nodes[0];
+-		btrfs_item_key_to_cpu(src, &key, src_path->slots[0]);
+-		if (key.objectid != btrfs_ino(inode) ||
+-		    key.type != BTRFS_EXTENT_DATA_KEY)
+-			goto fill_holes;
+-		extent = btrfs_item_ptr(src, src_path->slots[0],
+-					struct btrfs_file_extent_item);
+-		if (btrfs_file_extent_type(src, extent) ==
+-		    BTRFS_FILE_EXTENT_INLINE) {
+-			len = btrfs_file_extent_ram_bytes(src, extent);
+-			*last_extent = ALIGN(key.offset + len,
+-					     fs_info->sectorsize);
+-		} else {
+-			len = btrfs_file_extent_num_bytes(src, extent);
+-			*last_extent = key.offset + len;
+-		}
+-	}
+-fill_holes:
+-	/* So we did prev_leaf, now we need to move to the next leaf, but a few
+-	 * things could have happened
+-	 *
+-	 * 1) A merge could have happened, so we could currently be on a leaf
+-	 * that holds what we were copying in the first place.
+-	 * 2) A split could have happened, and now not all of the items we want
+-	 * are on the same leaf.
+-	 *
+-	 * So we need to adjust how we search for holes, we need to drop the
+-	 * path and re-search for the first extent key we found, and then walk
+-	 * forward until we hit the last one we copied.
+-	 */
+-	if (need_find_last_extent) {
+-		/* btrfs_prev_leaf could return 1 without releasing the path */
+-		btrfs_release_path(src_path);
+-		ret = btrfs_search_slot(NULL, inode->root, &first_key,
+-				src_path, 0, 0);
+-		if (ret < 0)
+-			return ret;
+-		ASSERT(ret == 0);
+-		src = src_path->nodes[0];
+-		i = src_path->slots[0];
+-	} else {
+-		i = start_slot;
+-	}
+-
+-	/*
+-	 * Ok so here we need to go through and fill in any holes we may have
+-	 * to make sure that holes are punched for those areas in case they had
+-	 * extents previously.
+-	 */
+-	while (!done) {
+-		u64 offset, len;
+-		u64 extent_end;
+-
+-		if (i >= btrfs_header_nritems(src_path->nodes[0])) {
+-			ret = btrfs_next_leaf(inode->root, src_path);
+-			if (ret < 0)
+-				return ret;
+-			ASSERT(ret == 0);
+-			src = src_path->nodes[0];
+-			i = 0;
+-			need_find_last_extent = true;
+-		}
+-
+-		btrfs_item_key_to_cpu(src, &key, i);
+-		if (!btrfs_comp_cpu_keys(&key, &last_key))
+-			done = true;
+-		if (key.objectid != btrfs_ino(inode) ||
+-		    key.type != BTRFS_EXTENT_DATA_KEY) {
+-			i++;
+-			continue;
+-		}
+-		extent = btrfs_item_ptr(src, i, struct btrfs_file_extent_item);
+-		if (btrfs_file_extent_type(src, extent) ==
+-		    BTRFS_FILE_EXTENT_INLINE) {
+-			len = btrfs_file_extent_ram_bytes(src, extent);
+-			extent_end = ALIGN(key.offset + len,
+-					   fs_info->sectorsize);
+-		} else {
+-			len = btrfs_file_extent_num_bytes(src, extent);
+-			extent_end = key.offset + len;
+-		}
+-		i++;
+-
+-		if (*last_extent == key.offset) {
+-			*last_extent = extent_end;
+-			continue;
+-		}
+-		offset = *last_extent;
+-		len = key.offset - *last_extent;
+-		ret = btrfs_insert_file_extent(trans, log, btrfs_ino(inode),
+-				offset, 0, 0, len, 0, len, 0, 0, 0);
+-		if (ret)
+-			break;
+-		*last_extent = extent_end;
+-	}
+-
+-	/*
+-	 * Check if there is a hole between the last extent found in our leaf
+-	 * and the first extent in the next leaf. If there is one, we need to
+-	 * log an explicit hole so that at replay time we can punch the hole.
+-	 */
+-	if (ret == 0 &&
+-	    key.objectid == btrfs_ino(inode) &&
+-	    key.type == BTRFS_EXTENT_DATA_KEY &&
+-	    i == btrfs_header_nritems(src_path->nodes[0])) {
+-		ret = btrfs_next_leaf(inode->root, src_path);
+-		need_find_last_extent = true;
+-		if (ret > 0) {
+-			ret = 0;
+-		} else if (ret == 0) {
+-			btrfs_item_key_to_cpu(src_path->nodes[0], &key,
+-					      src_path->slots[0]);
+-			if (key.objectid == btrfs_ino(inode) &&
+-			    key.type == BTRFS_EXTENT_DATA_KEY &&
+-			    *last_extent < key.offset) {
+-				const u64 len = key.offset - *last_extent;
+-
+-				ret = btrfs_insert_file_extent(trans, log,
+-							       btrfs_ino(inode),
+-							       *last_extent, 0,
+-							       0, len, 0, len,
+-							       0, 0, 0);
+-				*last_extent += len;
+-			}
+-		}
+-	}
+-	/*
+-	 * Need to let the callers know we dropped the path so they should
+-	 * re-search.
+-	 */
+-	if (!ret && need_find_last_extent)
+-		ret = 1;
+ 	return ret;
+ }
+ 
+@@ -4365,7 +4181,7 @@ static int btrfs_log_prealloc_extents(struct btrfs_trans_handle *trans,
+ 	const u64 i_size = i_size_read(&inode->vfs_inode);
+ 	const u64 ino = btrfs_ino(inode);
+ 	struct btrfs_path *dst_path = NULL;
+-	u64 last_extent = (u64)-1;
++	bool dropped_extents = false;
+ 	int ins_nr = 0;
+ 	int start_slot;
+ 	int ret;
+@@ -4387,8 +4203,7 @@ static int btrfs_log_prealloc_extents(struct btrfs_trans_handle *trans,
+ 		if (slot >= btrfs_header_nritems(leaf)) {
+ 			if (ins_nr > 0) {
+ 				ret = copy_items(trans, inode, dst_path, path,
+-						 &last_extent, start_slot,
+-						 ins_nr, 1, 0);
++						 start_slot, ins_nr, 1, 0);
+ 				if (ret < 0)
+ 					goto out;
+ 				ins_nr = 0;
+@@ -4412,8 +4227,7 @@ static int btrfs_log_prealloc_extents(struct btrfs_trans_handle *trans,
+ 			path->slots[0]++;
+ 			continue;
+ 		}
+-		if (last_extent == (u64)-1) {
+-			last_extent = key.offset;
++		if (!dropped_extents) {
+ 			/*
+ 			 * Avoid logging extent items logged in past fsync calls
+ 			 * and leading to duplicate keys in the log tree.
+@@ -4427,6 +4241,7 @@ static int btrfs_log_prealloc_extents(struct btrfs_trans_handle *trans,
+ 			} while (ret == -EAGAIN);
+ 			if (ret)
+ 				goto out;
++			dropped_extents = true;
+ 		}
+ 		if (ins_nr == 0)
+ 			start_slot = slot;
+@@ -4441,7 +4256,7 @@ static int btrfs_log_prealloc_extents(struct btrfs_trans_handle *trans,
+ 		}
+ 	}
+ 	if (ins_nr > 0) {
+-		ret = copy_items(trans, inode, dst_path, path, &last_extent,
++		ret = copy_items(trans, inode, dst_path, path,
+ 				 start_slot, ins_nr, 1, 0);
+ 		if (ret > 0)
+ 			ret = 0;
+@@ -4636,13 +4451,8 @@ static int btrfs_log_all_xattrs(struct btrfs_trans_handle *trans,
+ 
+ 		if (slot >= nritems) {
+ 			if (ins_nr > 0) {
+-				u64 last_extent = 0;
+-
+ 				ret = copy_items(trans, inode, dst_path, path,
+-						 &last_extent, start_slot,
+-						 ins_nr, 1, 0);
+-				/* can't be 1, extent items aren't processed */
+-				ASSERT(ret <= 0);
++						 start_slot, ins_nr, 1, 0);
+ 				if (ret < 0)
+ 					return ret;
+ 				ins_nr = 0;
+@@ -4666,13 +4476,8 @@ static int btrfs_log_all_xattrs(struct btrfs_trans_handle *trans,
+ 		cond_resched();
+ 	}
+ 	if (ins_nr > 0) {
+-		u64 last_extent = 0;
+-
+ 		ret = copy_items(trans, inode, dst_path, path,
+-				 &last_extent, start_slot,
+-				 ins_nr, 1, 0);
+-		/* can't be 1, extent items aren't processed */
+-		ASSERT(ret <= 0);
++				 start_slot, ins_nr, 1, 0);
+ 		if (ret < 0)
+ 			return ret;
+ 	}
+@@ -4681,100 +4486,119 @@ static int btrfs_log_all_xattrs(struct btrfs_trans_handle *trans,
+ }
+ 
+ /*
+- * If the no holes feature is enabled we need to make sure any hole between the
+- * last extent and the i_size of our inode is explicitly marked in the log. This
+- * is to make sure that doing something like:
+- *
+- *      1) create file with 128Kb of data
+- *      2) truncate file to 64Kb
+- *      3) truncate file to 256Kb
+- *      4) fsync file
+- *      5) <crash/power failure>
+- *      6) mount fs and trigger log replay
+- *
+- * Will give us a file with a size of 256Kb, the first 64Kb of data match what
+- * the file had in its first 64Kb of data at step 1 and the last 192Kb of the
+- * file correspond to a hole. The presence of explicit holes in a log tree is
+- * what guarantees that log replay will remove/adjust file extent items in the
+- * fs/subvol tree.
+- *
+- * Here we do not need to care about holes between extents, that is already done
+- * by copy_items(). We also only need to do this in the full sync path, where we
+- * lookup for extents from the fs/subvol tree only. In the fast path case, we
+- * lookup the list of modified extent maps and if any represents a hole, we
+- * insert a corresponding extent representing a hole in the log tree.
++ * When using the NO_HOLES feature if we punched a hole that causes the
++ * deletion of entire leafs or all the extent items of the first leaf (the one
++ * that contains the inode item and references) we may end up not processing
++ * any extents, because there are no leafs with a generation matching the
++ * current transaction that have extent items for our inode. So we need to find
++ * if any holes exist and then log them. We also need to log holes after any
++ * truncate operation that changes the inode's size.
+  */
+-static int btrfs_log_trailing_hole(struct btrfs_trans_handle *trans,
+-				   struct btrfs_root *root,
+-				   struct btrfs_inode *inode,
+-				   struct btrfs_path *path)
++static int btrfs_log_holes(struct btrfs_trans_handle *trans,
++			   struct btrfs_root *root,
++			   struct btrfs_inode *inode,
++			   struct btrfs_path *path)
+ {
+ 	struct btrfs_fs_info *fs_info = root->fs_info;
+-	int ret;
+ 	struct btrfs_key key;
+-	u64 hole_start;
+-	u64 hole_size;
+-	struct extent_buffer *leaf;
+-	struct btrfs_root *log = root->log_root;
+ 	const u64 ino = btrfs_ino(inode);
+ 	const u64 i_size = i_size_read(&inode->vfs_inode);
++	u64 prev_extent_end = 0;
++	int ret;
+ 
+-	if (!btrfs_fs_incompat(fs_info, NO_HOLES))
++	if (!btrfs_fs_incompat(fs_info, NO_HOLES) || i_size == 0)
+ 		return 0;
+ 
+ 	key.objectid = ino;
+ 	key.type = BTRFS_EXTENT_DATA_KEY;
+-	key.offset = (u64)-1;
++	key.offset = 0;
+ 
+ 	ret = btrfs_search_slot(NULL, root, &key, path, 0, 0);
+-	ASSERT(ret != 0);
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	ASSERT(path->slots[0] > 0);
+-	path->slots[0]--;
+-	leaf = path->nodes[0];
+-	btrfs_item_key_to_cpu(leaf, &key, path->slots[0]);
+-
+-	if (key.objectid != ino || key.type != BTRFS_EXTENT_DATA_KEY) {
+-		/* inode does not have any extents */
+-		hole_start = 0;
+-		hole_size = i_size;
+-	} else {
++	while (true) {
+ 		struct btrfs_file_extent_item *extent;
++		struct extent_buffer *leaf = path->nodes[0];
+ 		u64 len;
+ 
+-		/*
+-		 * If there's an extent beyond i_size, an explicit hole was
+-		 * already inserted by copy_items().
+-		 */
+-		if (key.offset >= i_size)
+-			return 0;
++		if (path->slots[0] >= btrfs_header_nritems(path->nodes[0])) {
++			ret = btrfs_next_leaf(root, path);
++			if (ret < 0)
++				return ret;
++			if (ret > 0) {
++				ret = 0;
++				break;
++			}
++			leaf = path->nodes[0];
++		}
++
++		btrfs_item_key_to_cpu(leaf, &key, path->slots[0]);
++		if (key.objectid != ino || key.type != BTRFS_EXTENT_DATA_KEY)
++			break;
++
++		/* We have a hole, log it. */
++		if (prev_extent_end < key.offset) {
++			const u64 hole_len = key.offset - prev_extent_end;
++
++			/*
++			 * Release the path to avoid deadlocks with other code
++			 * paths that search the root while holding locks on
++			 * leafs from the log root.
++			 */
++			btrfs_release_path(path);
++			ret = btrfs_insert_file_extent(trans, root->log_root,
++						       ino, prev_extent_end, 0,
++						       0, hole_len, 0, hole_len,
++						       0, 0, 0);
++			if (ret < 0)
++				return ret;
++
++			/*
++			 * Search for the same key again in the root. Since it's
++			 * an extent item and we are holding the inode lock, the
++			 * key must still exist. If it doesn't just emit warning
++			 * and return an error to fall back to a transaction
++			 * commit.
++			 */
++			ret = btrfs_search_slot(NULL, root, &key, path, 0, 0);
++			if (ret < 0)
++				return ret;
++			if (WARN_ON(ret > 0))
++				return -ENOENT;
++			leaf = path->nodes[0];
++		}
+ 
+ 		extent = btrfs_item_ptr(leaf, path->slots[0],
+ 					struct btrfs_file_extent_item);
+-
+ 		if (btrfs_file_extent_type(leaf, extent) ==
+-		    BTRFS_FILE_EXTENT_INLINE)
+-			return 0;
++		    BTRFS_FILE_EXTENT_INLINE) {
++			len = btrfs_file_extent_ram_bytes(leaf, extent);
++			prev_extent_end = ALIGN(key.offset + len,
++						fs_info->sectorsize);
++		} else {
++			len = btrfs_file_extent_num_bytes(leaf, extent);
++			prev_extent_end = key.offset + len;
++		}
+ 
+-		len = btrfs_file_extent_num_bytes(leaf, extent);
+-		/* Last extent goes beyond i_size, no need to log a hole. */
+-		if (key.offset + len > i_size)
+-			return 0;
+-		hole_start = key.offset + len;
+-		hole_size = i_size - hole_start;
++		path->slots[0]++;
++		cond_resched();
+ 	}
+-	btrfs_release_path(path);
+ 
+-	/* Last extent ends at i_size. */
+-	if (hole_size == 0)
+-		return 0;
++	if (prev_extent_end < i_size) {
++		u64 hole_len;
+ 
+-	hole_size = ALIGN(hole_size, fs_info->sectorsize);
+-	ret = btrfs_insert_file_extent(trans, log, ino, hole_start, 0, 0,
+-				       hole_size, 0, hole_size, 0, 0, 0);
+-	return ret;
++		btrfs_release_path(path);
++		hole_len = ALIGN(i_size - prev_extent_end, fs_info->sectorsize);
++		ret = btrfs_insert_file_extent(trans, root->log_root,
++					       ino, prev_extent_end, 0, 0,
++					       hole_len, 0, hole_len,
++					       0, 0, 0);
++		if (ret < 0)
++			return ret;
++	}
++
++	return 0;
+ }
+ 
+ /*
+@@ -4934,7 +4758,6 @@ static int btrfs_log_inode(struct btrfs_trans_handle *trans,
+ 	struct btrfs_key min_key;
+ 	struct btrfs_key max_key;
+ 	struct btrfs_root *log = root->log_root;
+-	u64 last_extent = 0;
+ 	int err = 0;
+ 	int ret;
+ 	int nritems;
+@@ -5108,7 +4931,7 @@ again:
+ 					ins_start_slot = path->slots[0];
+ 				}
+ 				ret = copy_items(trans, inode, dst_path, path,
+-						 &last_extent, ins_start_slot,
++						 ins_start_slot,
+ 						 ins_nr, inode_only,
+ 						 logged_isize);
+ 				if (ret < 0) {
+@@ -5161,17 +4984,13 @@ again:
+ 			if (ins_nr == 0)
+ 				goto next_slot;
+ 			ret = copy_items(trans, inode, dst_path, path,
+-					 &last_extent, ins_start_slot,
++					 ins_start_slot,
+ 					 ins_nr, inode_only, logged_isize);
+ 			if (ret < 0) {
+ 				err = ret;
+ 				goto out_unlock;
+ 			}
+ 			ins_nr = 0;
+-			if (ret) {
+-				btrfs_release_path(path);
+-				continue;
+-			}
+ 			goto next_slot;
+ 		}
+ 
+@@ -5184,18 +5003,13 @@ again:
+ 			goto next_slot;
+ 		}
+ 
+-		ret = copy_items(trans, inode, dst_path, path, &last_extent,
++		ret = copy_items(trans, inode, dst_path, path,
+ 				 ins_start_slot, ins_nr, inode_only,
+ 				 logged_isize);
+ 		if (ret < 0) {
+ 			err = ret;
+ 			goto out_unlock;
+ 		}
+-		if (ret) {
+-			ins_nr = 0;
+-			btrfs_release_path(path);
+-			continue;
+-		}
+ 		ins_nr = 1;
+ 		ins_start_slot = path->slots[0];
+ next_slot:
+@@ -5209,13 +5023,12 @@ next_slot:
+ 		}
+ 		if (ins_nr) {
+ 			ret = copy_items(trans, inode, dst_path, path,
+-					 &last_extent, ins_start_slot,
++					 ins_start_slot,
+ 					 ins_nr, inode_only, logged_isize);
+ 			if (ret < 0) {
+ 				err = ret;
+ 				goto out_unlock;
+ 			}
+-			ret = 0;
+ 			ins_nr = 0;
+ 		}
+ 		btrfs_release_path(path);
+@@ -5230,14 +5043,13 @@ next_key:
+ 		}
+ 	}
+ 	if (ins_nr) {
+-		ret = copy_items(trans, inode, dst_path, path, &last_extent,
++		ret = copy_items(trans, inode, dst_path, path,
+ 				 ins_start_slot, ins_nr, inode_only,
+ 				 logged_isize);
+ 		if (ret < 0) {
+ 			err = ret;
+ 			goto out_unlock;
+ 		}
+-		ret = 0;
+ 		ins_nr = 0;
+ 	}
+ 
+@@ -5250,7 +5062,7 @@ next_key:
+ 	if (max_key.type >= BTRFS_EXTENT_DATA_KEY && !fast_search) {
+ 		btrfs_release_path(path);
+ 		btrfs_release_path(dst_path);
+-		err = btrfs_log_trailing_hole(trans, root, inode, path);
++		err = btrfs_log_holes(trans, root, inode, path);
+ 		if (err)
+ 			goto out_unlock;
+ 	}
+diff --git a/fs/cifs/smb2pdu.c b/fs/cifs/smb2pdu.c
+index 43f29621e51f..0d4e4d97e6cf 100644
+--- a/fs/cifs/smb2pdu.c
++++ b/fs/cifs/smb2pdu.c
+@@ -259,9 +259,14 @@ smb2_reconnect(__le16 smb2_command, struct cifs_tcon *tcon)
+ 	}
+ 
+ 	rc = cifs_negotiate_protocol(0, tcon->ses);
+-	if (!rc && tcon->ses->need_reconnect)
++	if (!rc && tcon->ses->need_reconnect) {
+ 		rc = cifs_setup_session(0, tcon->ses, nls_codepage);
+-
++		if ((rc == -EACCES) && !tcon->retry) {
++			rc = -EHOSTDOWN;
++			mutex_unlock(&tcon->ses->session_mutex);
++			goto failed;
++		}
++	}
+ 	if (rc || !tcon->need_reconnect) {
+ 		mutex_unlock(&tcon->ses->session_mutex);
+ 		goto out;
+@@ -306,6 +311,7 @@ out:
+ 	case SMB2_SET_INFO:
+ 		rc = -EAGAIN;
+ 	}
++failed:
+ 	unload_nls(nls_codepage);
+ 	return rc;
+ }
+@@ -3130,8 +3136,8 @@ smb2_readv_callback(struct mid_q_entry *mid)
+ 	struct smb2_sync_hdr *shdr =
+ 				(struct smb2_sync_hdr *)rdata->iov[0].iov_base;
+ 	unsigned int credits_received = 0;
+-	struct smb_rqst rqst = { .rq_iov = rdata->iov,
+-				 .rq_nvec = 2,
++	struct smb_rqst rqst = { .rq_iov = &rdata->iov[1],
++				 .rq_nvec = 1,
+ 				 .rq_pages = rdata->pages,
+ 				 .rq_offset = rdata->page_offset,
+ 				 .rq_npages = rdata->nr_pages,
+diff --git a/fs/eventfd.c b/fs/eventfd.c
+index 08d3bd602f73..ce1d1711fbba 100644
+--- a/fs/eventfd.c
++++ b/fs/eventfd.c
+@@ -22,6 +22,8 @@
+ #include <linux/proc_fs.h>
+ #include <linux/seq_file.h>
+ 
++DEFINE_PER_CPU(int, eventfd_wake_count);
++
+ struct eventfd_ctx {
+ 	struct kref kref;
+ 	wait_queue_head_t wqh;
+@@ -55,12 +57,25 @@ __u64 eventfd_signal(struct eventfd_ctx *ctx, __u64 n)
+ {
+ 	unsigned long flags;
+ 
++	/*
++	 * Deadlock or stack overflow issues can happen if we recurse here
++	 * through waitqueue wakeup handlers. If the caller users potentially
++	 * nested waitqueues with custom wakeup handlers, then it should
++	 * check eventfd_signal_count() before calling this function. If
++	 * it returns true, the eventfd_signal() call should be deferred to a
++	 * safe context.
++	 */
++	if (WARN_ON_ONCE(this_cpu_read(eventfd_wake_count)))
++		return 0;
++
+ 	spin_lock_irqsave(&ctx->wqh.lock, flags);
++	this_cpu_inc(eventfd_wake_count);
+ 	if (ULLONG_MAX - ctx->count < n)
+ 		n = ULLONG_MAX - ctx->count;
+ 	ctx->count += n;
+ 	if (waitqueue_active(&ctx->wqh))
+ 		wake_up_locked_poll(&ctx->wqh, EPOLLIN);
++	this_cpu_dec(eventfd_wake_count);
+ 	spin_unlock_irqrestore(&ctx->wqh.lock, flags);
+ 
+ 	return n;
+diff --git a/fs/ext2/super.c b/fs/ext2/super.c
+index 364e647d87c0..80a3038e0e46 100644
+--- a/fs/ext2/super.c
++++ b/fs/ext2/super.c
+@@ -1093,9 +1093,9 @@ static int ext2_fill_super(struct super_block *sb, void *data, int silent)
+ 
+ 	if (EXT2_BLOCKS_PER_GROUP(sb) == 0)
+ 		goto cantfind_ext2;
+- 	sbi->s_groups_count = ((le32_to_cpu(es->s_blocks_count) -
+- 				le32_to_cpu(es->s_first_data_block) - 1)
+- 					/ EXT2_BLOCKS_PER_GROUP(sb)) + 1;
++	sbi->s_groups_count = ((le32_to_cpu(es->s_blocks_count) -
++				le32_to_cpu(es->s_first_data_block) - 1)
++					/ EXT2_BLOCKS_PER_GROUP(sb)) + 1;
+ 	db_count = (sbi->s_groups_count + EXT2_DESC_PER_BLOCK(sb) - 1) /
+ 		   EXT2_DESC_PER_BLOCK(sb);
+ 	sbi->s_group_desc = kmalloc_array (db_count,
+diff --git a/fs/ext4/page-io.c b/fs/ext4/page-io.c
+index db7590178dfc..9cc79b7b0df1 100644
+--- a/fs/ext4/page-io.c
++++ b/fs/ext4/page-io.c
+@@ -481,17 +481,26 @@ int ext4_bio_write_page(struct ext4_io_submit *io,
+ 	    nr_to_submit) {
+ 		gfp_t gfp_flags = GFP_NOFS;
+ 
++		/*
++		 * Since bounce page allocation uses a mempool, we can only use
++		 * a waiting mask (i.e. request guaranteed allocation) on the
++		 * first page of the bio.  Otherwise it can deadlock.
++		 */
++		if (io->io_bio)
++			gfp_flags = GFP_NOWAIT | __GFP_NOWARN;
+ 	retry_encrypt:
+ 		data_page = fscrypt_encrypt_page(inode, page, PAGE_SIZE, 0,
+ 						page->index, gfp_flags);
+ 		if (IS_ERR(data_page)) {
+ 			ret = PTR_ERR(data_page);
+-			if (ret == -ENOMEM && wbc->sync_mode == WB_SYNC_ALL) {
+-				if (io->io_bio) {
++			if (ret == -ENOMEM &&
++			    (io->io_bio || wbc->sync_mode == WB_SYNC_ALL)) {
++				gfp_flags = GFP_NOFS;
++				if (io->io_bio)
+ 					ext4_io_submit(io);
+-					congestion_wait(BLK_RW_ASYNC, HZ/50);
+-				}
+-				gfp_flags |= __GFP_NOFAIL;
++				else
++					gfp_flags |= __GFP_NOFAIL;
++				congestion_wait(BLK_RW_ASYNC, HZ/50);
+ 				goto retry_encrypt;
+ 			}
+ 			data_page = NULL;
+diff --git a/fs/f2fs/super.c b/fs/f2fs/super.c
+index 7a9cc64f5ca3..da348cf4ff56 100644
+--- a/fs/f2fs/super.c
++++ b/fs/f2fs/super.c
+@@ -1148,9 +1148,11 @@ static int f2fs_statfs_project(struct super_block *sb,
+ 		return PTR_ERR(dquot);
+ 	spin_lock(&dquot->dq_dqb_lock);
+ 
+-	limit = (dquot->dq_dqb.dqb_bsoftlimit ?
+-		 dquot->dq_dqb.dqb_bsoftlimit :
+-		 dquot->dq_dqb.dqb_bhardlimit) >> sb->s_blocksize_bits;
++	limit = min_not_zero(dquot->dq_dqb.dqb_bsoftlimit,
++					dquot->dq_dqb.dqb_bhardlimit);
++	if (limit)
++		limit >>= sb->s_blocksize_bits;
++
+ 	if (limit && buf->f_blocks > limit) {
+ 		curblock = dquot->dq_dqb.dqb_curspace >> sb->s_blocksize_bits;
+ 		buf->f_blocks = limit;
+@@ -1159,9 +1161,9 @@ static int f2fs_statfs_project(struct super_block *sb,
+ 			 (buf->f_blocks - curblock) : 0;
+ 	}
+ 
+-	limit = dquot->dq_dqb.dqb_isoftlimit ?
+-		dquot->dq_dqb.dqb_isoftlimit :
+-		dquot->dq_dqb.dqb_ihardlimit;
++	limit = min_not_zero(dquot->dq_dqb.dqb_isoftlimit,
++					dquot->dq_dqb.dqb_ihardlimit);
++
+ 	if (limit && buf->f_files > limit) {
+ 		buf->f_files = limit;
+ 		buf->f_ffree =
+diff --git a/fs/gfs2/file.c b/fs/gfs2/file.c
+index 08369c6cd127..143e7d518c5d 100644
+--- a/fs/gfs2/file.c
++++ b/fs/gfs2/file.c
+@@ -780,7 +780,7 @@ static ssize_t gfs2_file_write_iter(struct kiocb *iocb, struct iov_iter *from)
+ 	struct file *file = iocb->ki_filp;
+ 	struct inode *inode = file_inode(file);
+ 	struct gfs2_inode *ip = GFS2_I(inode);
+-	ssize_t written = 0, ret;
++	ssize_t ret;
+ 
+ 	ret = gfs2_rsqa_alloc(ip);
+ 	if (ret)
+@@ -800,68 +800,58 @@ static ssize_t gfs2_file_write_iter(struct kiocb *iocb, struct iov_iter *from)
+ 	inode_lock(inode);
+ 	ret = generic_write_checks(iocb, from);
+ 	if (ret <= 0)
+-		goto out;
+-
+-	/* We can write back this queue in page reclaim */
+-	current->backing_dev_info = inode_to_bdi(inode);
++		goto out_unlock;
+ 
+ 	ret = file_remove_privs(file);
+ 	if (ret)
+-		goto out2;
++		goto out_unlock;
+ 
+ 	ret = file_update_time(file);
+ 	if (ret)
+-		goto out2;
++		goto out_unlock;
+ 
+ 	if (iocb->ki_flags & IOCB_DIRECT) {
+ 		struct address_space *mapping = file->f_mapping;
+-		loff_t pos, endbyte;
+-		ssize_t buffered;
++		ssize_t buffered, ret2;
+ 
+-		written = gfs2_file_direct_write(iocb, from);
+-		if (written < 0 || !iov_iter_count(from))
+-			goto out2;
++		ret = gfs2_file_direct_write(iocb, from);
++		if (ret < 0 || !iov_iter_count(from))
++			goto out_unlock;
+ 
+-		ret = iomap_file_buffered_write(iocb, from, &gfs2_iomap_ops);
+-		if (unlikely(ret < 0))
+-			goto out2;
+-		buffered = ret;
++		iocb->ki_flags |= IOCB_DSYNC;
++		current->backing_dev_info = inode_to_bdi(inode);
++		buffered = iomap_file_buffered_write(iocb, from, &gfs2_iomap_ops);
++		current->backing_dev_info = NULL;
++		if (unlikely(buffered <= 0))
++			goto out_unlock;
+ 
+ 		/*
+ 		 * We need to ensure that the page cache pages are written to
+ 		 * disk and invalidated to preserve the expected O_DIRECT
+-		 * semantics.
++		 * semantics.  If the writeback or invalidate fails, only report
++		 * the direct I/O range as we don't know if the buffered pages
++		 * made it to disk.
+ 		 */
+-		pos = iocb->ki_pos;
+-		endbyte = pos + buffered - 1;
+-		ret = filemap_write_and_wait_range(mapping, pos, endbyte);
+-		if (!ret) {
+-			iocb->ki_pos += buffered;
+-			written += buffered;
+-			invalidate_mapping_pages(mapping,
+-						 pos >> PAGE_SHIFT,
+-						 endbyte >> PAGE_SHIFT);
+-		} else {
+-			/*
+-			 * We don't know how much we wrote, so just return
+-			 * the number of bytes which were direct-written
+-			 */
+-		}
++		iocb->ki_pos += buffered;
++		ret2 = generic_write_sync(iocb, buffered);
++		invalidate_mapping_pages(mapping,
++				(iocb->ki_pos - buffered) >> PAGE_SHIFT,
++				(iocb->ki_pos - 1) >> PAGE_SHIFT);
++		if (!ret || ret2 > 0)
++			ret += ret2;
+ 	} else {
++		current->backing_dev_info = inode_to_bdi(inode);
+ 		ret = iomap_file_buffered_write(iocb, from, &gfs2_iomap_ops);
+-		if (likely(ret > 0))
++		current->backing_dev_info = NULL;
++		if (likely(ret > 0)) {
+ 			iocb->ki_pos += ret;
++			ret = generic_write_sync(iocb, ret);
++		}
+ 	}
+ 
+-out2:
+-	current->backing_dev_info = NULL;
+-out:
++out_unlock:
+ 	inode_unlock(inode);
+-	if (likely(ret > 0)) {
+-		/* Handle various SYNC-type writes */
+-		ret = generic_write_sync(iocb, ret);
+-	}
+-	return written ? written : ret;
++	return ret;
+ }
+ 
+ static int fallocate_chunk(struct inode *inode, loff_t offset, loff_t len,
+diff --git a/fs/jbd2/journal.c b/fs/jbd2/journal.c
+index df390a69c49a..1a2339f2cb49 100644
+--- a/fs/jbd2/journal.c
++++ b/fs/jbd2/journal.c
+@@ -1002,6 +1002,7 @@ static void *jbd2_seq_info_start(struct seq_file *seq, loff_t *pos)
+ 
+ static void *jbd2_seq_info_next(struct seq_file *seq, void *v, loff_t *pos)
+ {
++	(*pos)++;
+ 	return NULL;
+ }
+ 
+diff --git a/fs/nfs/dir.c b/fs/nfs/dir.c
+index b8d686087952..4ae726e70d87 100644
+--- a/fs/nfs/dir.c
++++ b/fs/nfs/dir.c
+@@ -162,6 +162,17 @@ typedef struct {
+ 	bool eof;
+ } nfs_readdir_descriptor_t;
+ 
++static
++void nfs_readdir_init_array(struct page *page)
++{
++	struct nfs_cache_array *array;
++
++	array = kmap_atomic(page);
++	memset(array, 0, sizeof(struct nfs_cache_array));
++	array->eof_index = -1;
++	kunmap_atomic(array);
++}
++
+ /*
+  * we are freeing strings created by nfs_add_to_readdir_array()
+  */
+@@ -174,6 +185,7 @@ void nfs_readdir_clear_array(struct page *page)
+ 	array = kmap_atomic(page);
+ 	for (i = 0; i < array->size; i++)
+ 		kfree(array->array[i].string.name);
++	array->size = 0;
+ 	kunmap_atomic(array);
+ }
+ 
+@@ -610,6 +622,8 @@ int nfs_readdir_xdr_to_array(nfs_readdir_descriptor_t *desc, struct page *page,
+ 	int status = -ENOMEM;
+ 	unsigned int array_size = ARRAY_SIZE(pages);
+ 
++	nfs_readdir_init_array(page);
++
+ 	entry.prev_cookie = 0;
+ 	entry.cookie = desc->last_cookie;
+ 	entry.eof = 0;
+@@ -626,8 +640,6 @@ int nfs_readdir_xdr_to_array(nfs_readdir_descriptor_t *desc, struct page *page,
+ 	}
+ 
+ 	array = kmap(page);
+-	memset(array, 0, sizeof(struct nfs_cache_array));
+-	array->eof_index = -1;
+ 
+ 	status = nfs_readdir_alloc_pages(pages, array_size);
+ 	if (status < 0)
+@@ -681,6 +693,7 @@ int nfs_readdir_filler(nfs_readdir_descriptor_t *desc, struct page* page)
+ 	unlock_page(page);
+ 	return 0;
+  error:
++	nfs_readdir_clear_array(page);
+ 	unlock_page(page);
+ 	return ret;
+ }
+@@ -688,8 +701,6 @@ int nfs_readdir_filler(nfs_readdir_descriptor_t *desc, struct page* page)
+ static
+ void cache_page_release(nfs_readdir_descriptor_t *desc)
+ {
+-	if (!desc->page->mapping)
+-		nfs_readdir_clear_array(desc->page);
+ 	put_page(desc->page);
+ 	desc->page = NULL;
+ }
+@@ -703,19 +714,28 @@ struct page *get_cache_page(nfs_readdir_descriptor_t *desc)
+ 
+ /*
+  * Returns 0 if desc->dir_cookie was found on page desc->page_index
++ * and locks the page to prevent removal from the page cache.
+  */
+ static
+-int find_cache_page(nfs_readdir_descriptor_t *desc)
++int find_and_lock_cache_page(nfs_readdir_descriptor_t *desc)
+ {
+ 	int res;
+ 
+ 	desc->page = get_cache_page(desc);
+ 	if (IS_ERR(desc->page))
+ 		return PTR_ERR(desc->page);
+-
+-	res = nfs_readdir_search_array(desc);
++	res = lock_page_killable(desc->page);
+ 	if (res != 0)
+-		cache_page_release(desc);
++		goto error;
++	res = -EAGAIN;
++	if (desc->page->mapping != NULL) {
++		res = nfs_readdir_search_array(desc);
++		if (res == 0)
++			return 0;
++	}
++	unlock_page(desc->page);
++error:
++	cache_page_release(desc);
+ 	return res;
+ }
+ 
+@@ -730,7 +750,7 @@ int readdir_search_pagecache(nfs_readdir_descriptor_t *desc)
+ 		desc->last_cookie = 0;
+ 	}
+ 	do {
+-		res = find_cache_page(desc);
++		res = find_and_lock_cache_page(desc);
+ 	} while (res == -EAGAIN);
+ 	return res;
+ }
+@@ -769,7 +789,6 @@ int nfs_do_filldir(nfs_readdir_descriptor_t *desc)
+ 		desc->eof = true;
+ 
+ 	kunmap(desc->page);
+-	cache_page_release(desc);
+ 	dfprintk(DIRCACHE, "NFS: nfs_do_filldir() filling ended @ cookie %Lu; returning = %d\n",
+ 			(unsigned long long)*desc->dir_cookie, res);
+ 	return res;
+@@ -815,13 +834,13 @@ int uncached_readdir(nfs_readdir_descriptor_t *desc)
+ 
+ 	status = nfs_do_filldir(desc);
+ 
++ out_release:
++	nfs_readdir_clear_array(desc->page);
++	cache_page_release(desc);
+  out:
+ 	dfprintk(DIRCACHE, "NFS: %s: returns %d\n",
+ 			__func__, status);
+ 	return status;
+- out_release:
+-	cache_page_release(desc);
+-	goto out;
+ }
+ 
+ /* The file offset position represents the dirent entry number.  A
+@@ -886,6 +905,8 @@ static int nfs_readdir(struct file *file, struct dir_context *ctx)
+ 			break;
+ 
+ 		res = nfs_do_filldir(desc);
++		unlock_page(desc->page);
++		cache_page_release(desc);
+ 		if (res < 0)
+ 			break;
+ 	} while (!desc->eof);
+diff --git a/fs/nfsd/nfs4layouts.c b/fs/nfsd/nfs4layouts.c
+index 2b36aa037ce0..f4cf1c0793c6 100644
+--- a/fs/nfsd/nfs4layouts.c
++++ b/fs/nfsd/nfs4layouts.c
+@@ -676,7 +676,7 @@ nfsd4_cb_layout_done(struct nfsd4_callback *cb, struct rpc_task *task)
+ 
+ 		/* Client gets 2 lease periods to return it */
+ 		cutoff = ktime_add_ns(task->tk_start,
+-					 nn->nfsd4_lease * NSEC_PER_SEC * 2);
++					 (u64)nn->nfsd4_lease * NSEC_PER_SEC * 2);
+ 
+ 		if (ktime_before(now, cutoff)) {
+ 			rpc_delay(task, HZ/100); /* 10 mili-seconds */
+diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c
+index c8ce128e0054..ed73e86194fa 100644
+--- a/fs/nfsd/nfs4state.c
++++ b/fs/nfsd/nfs4state.c
+@@ -6075,7 +6075,7 @@ nfsd4_lock(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate,
+ 	}
+ 
+ 	if (fl_flags & FL_SLEEP) {
+-		nbl->nbl_time = jiffies;
++		nbl->nbl_time = get_seconds();
+ 		spin_lock(&nn->blocked_locks_lock);
+ 		list_add_tail(&nbl->nbl_list, &lock_sop->lo_blocked);
+ 		list_add_tail(&nbl->nbl_lru, &nn->blocked_locks_lru);
+diff --git a/fs/nfsd/state.h b/fs/nfsd/state.h
+index 0f07ad6dc1ef..594fc1a8b672 100644
+--- a/fs/nfsd/state.h
++++ b/fs/nfsd/state.h
+@@ -592,7 +592,7 @@ static inline bool nfsd4_stateid_generation_after(stateid_t *a, stateid_t *b)
+ struct nfsd4_blocked_lock {
+ 	struct list_head	nbl_list;
+ 	struct list_head	nbl_lru;
+-	unsigned long		nbl_time;
++	time_t			nbl_time;
+ 	struct file_lock	nbl_lock;
+ 	struct knfsd_fh		nbl_fh;
+ 	struct nfsd4_callback	nbl_cb;
+diff --git a/fs/nfsd/vfs.c b/fs/nfsd/vfs.c
+index 4fe8db314950..80cededcd10d 100644
+--- a/fs/nfsd/vfs.c
++++ b/fs/nfsd/vfs.c
+@@ -1016,6 +1016,7 @@ nfsd_vfs_write(struct svc_rqst *rqstp, struct svc_fh *fhp, struct file *file,
+ 	host_err = vfs_iter_write(file, &iter, &pos, flags);
+ 	if (host_err < 0)
+ 		goto out_nfserr;
++	*cnt = host_err;
+ 	nfsdstats.io_write += *cnt;
+ 	fsnotify_modify(file);
+ 
+diff --git a/fs/ocfs2/file.c b/fs/ocfs2/file.c
+index a3e077fcfeb9..fbd70111a2f1 100644
+--- a/fs/ocfs2/file.c
++++ b/fs/ocfs2/file.c
+@@ -2109,17 +2109,15 @@ static int ocfs2_is_io_unaligned(struct inode *inode, size_t count, loff_t pos)
+ static int ocfs2_inode_lock_for_extent_tree(struct inode *inode,
+ 					    struct buffer_head **di_bh,
+ 					    int meta_level,
+-					    int overwrite_io,
+ 					    int write_sem,
+ 					    int wait)
+ {
+ 	int ret = 0;
+ 
+ 	if (wait)
+-		ret = ocfs2_inode_lock(inode, NULL, meta_level);
++		ret = ocfs2_inode_lock(inode, di_bh, meta_level);
+ 	else
+-		ret = ocfs2_try_inode_lock(inode,
+-			overwrite_io ? NULL : di_bh, meta_level);
++		ret = ocfs2_try_inode_lock(inode, di_bh, meta_level);
+ 	if (ret < 0)
+ 		goto out;
+ 
+@@ -2144,6 +2142,7 @@ static int ocfs2_inode_lock_for_extent_tree(struct inode *inode,
+ 
+ out_unlock:
+ 	brelse(*di_bh);
++	*di_bh = NULL;
+ 	ocfs2_inode_unlock(inode, meta_level);
+ out:
+ 	return ret;
+@@ -2186,7 +2185,6 @@ static int ocfs2_prepare_inode_for_write(struct file *file,
+ 		ret = ocfs2_inode_lock_for_extent_tree(inode,
+ 						       &di_bh,
+ 						       meta_level,
+-						       overwrite_io,
+ 						       write_sem,
+ 						       wait);
+ 		if (ret < 0) {
+@@ -2244,13 +2242,13 @@ static int ocfs2_prepare_inode_for_write(struct file *file,
+ 							   &di_bh,
+ 							   meta_level,
+ 							   write_sem);
++			meta_level = 1;
++			write_sem = 1;
+ 			ret = ocfs2_inode_lock_for_extent_tree(inode,
+ 							       &di_bh,
+ 							       meta_level,
+-							       overwrite_io,
+-							       1,
++							       write_sem,
+ 							       wait);
+-			write_sem = 1;
+ 			if (ret < 0) {
+ 				if (ret != -EAGAIN)
+ 					mlog_errno(ret);
+diff --git a/fs/overlayfs/file.c b/fs/overlayfs/file.c
+index 0bd276e4ccbe..fa5ac5de807c 100644
+--- a/fs/overlayfs/file.c
++++ b/fs/overlayfs/file.c
+@@ -149,7 +149,7 @@ static loff_t ovl_llseek(struct file *file, loff_t offset, int whence)
+ 	struct inode *inode = file_inode(file);
+ 	struct fd real;
+ 	const struct cred *old_cred;
+-	ssize_t ret;
++	loff_t ret;
+ 
+ 	/*
+ 	 * The two special cases below do not need to involve real fs,
+diff --git a/fs/overlayfs/readdir.c b/fs/overlayfs/readdir.c
+index cc8303a806b4..11b7941c5dbc 100644
+--- a/fs/overlayfs/readdir.c
++++ b/fs/overlayfs/readdir.c
+@@ -507,7 +507,13 @@ get:
+ 		if (err)
+ 			goto fail;
+ 
+-		WARN_ON_ONCE(dir->d_sb->s_dev != stat.dev);
++		/*
++		 * Directory inode is always on overlay st_dev.
++		 * Non-dir with ovl_same_dev() could be on pseudo st_dev in case
++		 * of xino bits overflow.
++		 */
++		WARN_ON_ONCE(S_ISDIR(stat.mode) &&
++			     dir->d_sb->s_dev != stat.dev);
+ 		ino = stat.ino;
+ 	} else if (xinobits && !OVL_TYPE_UPPER(type)) {
+ 		ino = ovl_remap_lower_ino(ino, xinobits,
+diff --git a/fs/ubifs/dir.c b/fs/ubifs/dir.c
+index 5767b373a8ff..d7c0aa0626cd 100644
+--- a/fs/ubifs/dir.c
++++ b/fs/ubifs/dir.c
+@@ -242,6 +242,8 @@ static struct dentry *ubifs_lookup(struct inode *dir, struct dentry *dentry,
+ 	if (nm.hash) {
+ 		ubifs_assert(c, fname_len(&nm) == 0);
+ 		ubifs_assert(c, fname_name(&nm) == NULL);
++		if (nm.hash & ~UBIFS_S_KEY_HASH_MASK)
++			goto done; /* ENOENT */
+ 		dent_key_init_hash(c, &key, dir->i_ino, nm.hash);
+ 		err = ubifs_tnc_lookup_dh(c, &key, dent, nm.minor_hash);
+ 	} else {
+diff --git a/fs/ubifs/file.c b/fs/ubifs/file.c
+index 1b78f2e09218..65b4f63349c7 100644
+--- a/fs/ubifs/file.c
++++ b/fs/ubifs/file.c
+@@ -798,7 +798,9 @@ static int ubifs_do_bulk_read(struct ubifs_info *c, struct bu_info *bu,
+ 
+ 		if (page_offset > end_index)
+ 			break;
+-		page = find_or_create_page(mapping, page_offset, ra_gfp_mask);
++		page = pagecache_get_page(mapping, page_offset,
++				 FGP_LOCK|FGP_ACCESSED|FGP_CREAT|FGP_NOWAIT,
++				 ra_gfp_mask);
+ 		if (!page)
+ 			break;
+ 		if (!PageUptodate(page))
+diff --git a/fs/ubifs/ioctl.c b/fs/ubifs/ioctl.c
+index 0164bcc827f8..e666459f63c7 100644
+--- a/fs/ubifs/ioctl.c
++++ b/fs/ubifs/ioctl.c
+@@ -28,6 +28,11 @@
+ #include <linux/mount.h>
+ #include "ubifs.h"
+ 
++/* Need to be kept consistent with checked flags in ioctl2ubifs() */
++#define UBIFS_SUPPORTED_IOCTL_FLAGS \
++	(FS_COMPR_FL | FS_SYNC_FL | FS_APPEND_FL | \
++	 FS_IMMUTABLE_FL | FS_DIRSYNC_FL)
++
+ /**
+  * ubifs_set_inode_flags - set VFS inode flags.
+  * @inode: VFS inode to set flags for
+@@ -127,7 +132,8 @@ static int setflags(struct inode *inode, int flags)
+ 		}
+ 	}
+ 
+-	ui->flags = ioctl2ubifs(flags);
++	ui->flags &= ~ioctl2ubifs(UBIFS_SUPPORTED_IOCTL_FLAGS);
++	ui->flags |= ioctl2ubifs(flags);
+ 	ubifs_set_inode_flags(inode);
+ 	inode->i_ctime = current_time(inode);
+ 	release = ui->dirty;
+@@ -169,6 +175,9 @@ long ubifs_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+ 		if (get_user(flags, (int __user *) arg))
+ 			return -EFAULT;
+ 
++		if (flags & ~UBIFS_SUPPORTED_IOCTL_FLAGS)
++			return -EOPNOTSUPP;
++
+ 		if (!S_ISDIR(inode->i_mode))
+ 			flags &= ~FS_DIRSYNC_FL;
+ 
+diff --git a/fs/udf/super.c b/fs/udf/super.c
+index 7af011dc9ae8..6fd0f14e9dd2 100644
+--- a/fs/udf/super.c
++++ b/fs/udf/super.c
+@@ -999,7 +999,6 @@ static int check_partition_desc(struct super_block *sb,
+ 	switch (le32_to_cpu(p->accessType)) {
+ 	case PD_ACCESS_TYPE_READ_ONLY:
+ 	case PD_ACCESS_TYPE_WRITE_ONCE:
+-	case PD_ACCESS_TYPE_REWRITABLE:
+ 	case PD_ACCESS_TYPE_NONE:
+ 		goto force_ro;
+ 	}
+diff --git a/include/linux/eventfd.h b/include/linux/eventfd.h
+index ffcc7724ca21..dc4fd8a6644d 100644
+--- a/include/linux/eventfd.h
++++ b/include/linux/eventfd.h
+@@ -12,6 +12,8 @@
+ #include <linux/fcntl.h>
+ #include <linux/wait.h>
+ #include <linux/err.h>
++#include <linux/percpu-defs.h>
++#include <linux/percpu.h>
+ 
+ /*
+  * CAREFUL: Check include/uapi/asm-generic/fcntl.h when defining
+@@ -40,6 +42,13 @@ __u64 eventfd_signal(struct eventfd_ctx *ctx, __u64 n);
+ int eventfd_ctx_remove_wait_queue(struct eventfd_ctx *ctx, wait_queue_entry_t *wait,
+ 				  __u64 *cnt);
+ 
++DECLARE_PER_CPU(int, eventfd_wake_count);
++
++static inline bool eventfd_signal_count(void)
++{
++	return this_cpu_read(eventfd_wake_count);
++}
++
+ #else /* CONFIG_EVENTFD */
+ 
+ /*
+@@ -68,6 +77,11 @@ static inline int eventfd_ctx_remove_wait_queue(struct eventfd_ctx *ctx,
+ 	return -ENOSYS;
+ }
+ 
++static inline bool eventfd_signal_count(void)
++{
++	return false;
++}
++
+ #endif
+ 
+ #endif /* _LINUX_EVENTFD_H */
+diff --git a/include/linux/irq.h b/include/linux/irq.h
+index c9bffda04a45..6ecaf056ab63 100644
+--- a/include/linux/irq.h
++++ b/include/linux/irq.h
+@@ -208,6 +208,8 @@ struct irq_data {
+  * IRQD_SINGLE_TARGET		- IRQ allows only a single affinity target
+  * IRQD_DEFAULT_TRIGGER_SET	- Expected trigger already been set
+  * IRQD_CAN_RESERVE		- Can use reservation mode
++ * IRQD_MSI_NOMASK_QUIRK	- Non-maskable MSI quirk for affinity change
++ *				  required
+  */
+ enum {
+ 	IRQD_TRIGGER_MASK		= 0xf,
+@@ -230,6 +232,7 @@ enum {
+ 	IRQD_SINGLE_TARGET		= (1 << 24),
+ 	IRQD_DEFAULT_TRIGGER_SET	= (1 << 25),
+ 	IRQD_CAN_RESERVE		= (1 << 26),
++	IRQD_MSI_NOMASK_QUIRK		= (1 << 27),
+ };
+ 
+ #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
+@@ -389,6 +392,21 @@ static inline bool irqd_can_reserve(struct irq_data *d)
+ 	return __irqd_to_state(d) & IRQD_CAN_RESERVE;
+ }
+ 
++static inline void irqd_set_msi_nomask_quirk(struct irq_data *d)
++{
++	__irqd_to_state(d) |= IRQD_MSI_NOMASK_QUIRK;
++}
++
++static inline void irqd_clr_msi_nomask_quirk(struct irq_data *d)
++{
++	__irqd_to_state(d) &= ~IRQD_MSI_NOMASK_QUIRK;
++}
++
++static inline bool irqd_msi_nomask_quirk(struct irq_data *d)
++{
++	return __irqd_to_state(d) & IRQD_MSI_NOMASK_QUIRK;
++}
++
+ #undef __irqd_to_state
+ 
+ static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
+diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h
+index dccfa65aee96..8301f1df0682 100644
+--- a/include/linux/irqdomain.h
++++ b/include/linux/irqdomain.h
+@@ -202,6 +202,13 @@ enum {
+ 	/* Irq domain implements MSI remapping */
+ 	IRQ_DOMAIN_FLAG_MSI_REMAP	= (1 << 5),
+ 
++	/*
++	 * Quirk to handle MSI implementations which do not provide
++	 * masking. Currently known to affect x86, but partially
++	 * handled in core code.
++	 */
++	IRQ_DOMAIN_MSI_NOMASK_QUIRK	= (1 << 6),
++
+ 	/*
+ 	 * Flags starting from IRQ_DOMAIN_FLAG_NONCORE are reserved
+ 	 * for implementation specific purposes and ignored by the
+diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
+index 748016ae01e3..0f99ecc01bc7 100644
+--- a/include/linux/kvm_host.h
++++ b/include/linux/kvm_host.h
+@@ -186,7 +186,7 @@ struct kvm_async_pf {
+ 	struct list_head queue;
+ 	struct kvm_vcpu *vcpu;
+ 	struct mm_struct *mm;
+-	gva_t gva;
++	gpa_t cr2_or_gpa;
+ 	unsigned long addr;
+ 	struct kvm_arch_async_pf arch;
+ 	bool   wakeup_all;
+@@ -194,8 +194,8 @@ struct kvm_async_pf {
+ 
+ void kvm_clear_async_pf_completion_queue(struct kvm_vcpu *vcpu);
+ void kvm_check_async_pf_completion(struct kvm_vcpu *vcpu);
+-int kvm_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, unsigned long hva,
+-		       struct kvm_arch_async_pf *arch);
++int kvm_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
++		       unsigned long hva, struct kvm_arch_async_pf *arch);
+ int kvm_async_pf_wakeup_all(struct kvm_vcpu *vcpu);
+ #endif
+ 
+@@ -704,7 +704,7 @@ int kvm_clear_guest_page(struct kvm *kvm, gfn_t gfn, int offset, int len);
+ int kvm_clear_guest(struct kvm *kvm, gpa_t gpa, unsigned long len);
+ struct kvm_memory_slot *gfn_to_memslot(struct kvm *kvm, gfn_t gfn);
+ bool kvm_is_visible_gfn(struct kvm *kvm, gfn_t gfn);
+-unsigned long kvm_host_page_size(struct kvm *kvm, gfn_t gfn);
++unsigned long kvm_host_page_size(struct kvm_vcpu *vcpu, gfn_t gfn);
+ void mark_page_dirty(struct kvm *kvm, gfn_t gfn);
+ 
+ struct kvm_memslots *kvm_vcpu_memslots(struct kvm_vcpu *vcpu);
+diff --git a/include/linux/memblock.h b/include/linux/memblock.h
+index 516920549378..2acdd046df2d 100644
+--- a/include/linux/memblock.h
++++ b/include/linux/memblock.h
+@@ -265,21 +265,6 @@ void __next_mem_pfn_range(int *idx, int nid, unsigned long *out_start_pfn,
+ 	for_each_mem_range_rev(i, &memblock.memory, &memblock.reserved,	\
+ 			       nid, flags, p_start, p_end, p_nid)
+ 
+-/**
+- * for_each_resv_unavail_range - iterate through reserved and unavailable memory
+- * @i: u64 used as loop variable
+- * @p_start: ptr to phys_addr_t for start address of the range, can be %NULL
+- * @p_end: ptr to phys_addr_t for end address of the range, can be %NULL
+- *
+- * Walks over unavailable but reserved (reserved && !memory) areas of memblock.
+- * Available as soon as memblock is initialized.
+- * Note: because this memory does not belong to any physical node, flags and
+- * nid arguments do not make sense and thus not exported as arguments.
+- */
+-#define for_each_resv_unavail_range(i, p_start, p_end)			\
+-	for_each_mem_range(i, &memblock.reserved, &memblock.memory,	\
+-			   NUMA_NO_NODE, MEMBLOCK_NONE, p_start, p_end, NULL)
+-
+ static inline void memblock_set_region_flags(struct memblock_region *r,
+ 					     enum memblock_flags flags)
+ {
+diff --git a/include/linux/percpu-defs.h b/include/linux/percpu-defs.h
+index 2d2096ba1cfe..90b8ce813fa6 100644
+--- a/include/linux/percpu-defs.h
++++ b/include/linux/percpu-defs.h
+@@ -176,8 +176,7 @@
+  * Declaration/definition used for per-CPU variables that should be accessed
+  * as decrypted when memory encryption is enabled in the guest.
+  */
+-#if defined(CONFIG_VIRTUALIZATION) && defined(CONFIG_AMD_MEM_ENCRYPT)
+-
++#ifdef CONFIG_AMD_MEM_ENCRYPT
+ #define DECLARE_PER_CPU_DECRYPTED(type, name)				\
+ 	DECLARE_PER_CPU_SECTION(type, name, "..decrypted")
+ 
+diff --git a/include/media/v4l2-rect.h b/include/media/v4l2-rect.h
+index 595c3ba05f23..59745e5feb4d 100644
+--- a/include/media/v4l2-rect.h
++++ b/include/media/v4l2-rect.h
+@@ -63,10 +63,10 @@ static inline void v4l2_rect_map_inside(struct v4l2_rect *r,
+ 		r->left = boundary->left;
+ 	if (r->top < boundary->top)
+ 		r->top = boundary->top;
+-	if (r->left + r->width > boundary->width)
+-		r->left = boundary->width - r->width;
+-	if (r->top + r->height > boundary->height)
+-		r->top = boundary->height - r->height;
++	if (r->left + r->width > boundary->left + boundary->width)
++		r->left = boundary->left + boundary->width - r->width;
++	if (r->top + r->height > boundary->top + boundary->height)
++		r->top = boundary->top + boundary->height - r->height;
+ }
+ 
+ /**
+diff --git a/include/net/ipx.h b/include/net/ipx.h
+index baf090390998..9d1342807b59 100644
+--- a/include/net/ipx.h
++++ b/include/net/ipx.h
+@@ -47,11 +47,6 @@ struct ipxhdr {
+ /* From af_ipx.c */
+ extern int sysctl_ipx_pprop_broadcasting;
+ 
+-static __inline__ struct ipxhdr *ipx_hdr(struct sk_buff *skb)
+-{
+-	return (struct ipxhdr *)skb_transport_header(skb);
+-}
+-
+ struct ipx_interface {
+ 	/* IPX address */
+ 	__be32			if_netnum;
+diff --git a/ipc/msg.c b/ipc/msg.c
+index 883642cf2b27..ac4de3f67261 100644
+--- a/ipc/msg.c
++++ b/ipc/msg.c
+@@ -377,7 +377,7 @@ copy_msqid_from_user(struct msqid64_ds *out, void __user *buf, int version)
+  * NOTE: no locks must be held, the rwsem is taken inside this function.
+  */
+ static int msgctl_down(struct ipc_namespace *ns, int msqid, int cmd,
+-			struct msqid64_ds *msqid64)
++			struct ipc64_perm *perm, int msg_qbytes)
+ {
+ 	struct kern_ipc_perm *ipcp;
+ 	struct msg_queue *msq;
+@@ -387,7 +387,7 @@ static int msgctl_down(struct ipc_namespace *ns, int msqid, int cmd,
+ 	rcu_read_lock();
+ 
+ 	ipcp = ipcctl_obtain_check(ns, &msg_ids(ns), msqid, cmd,
+-				      &msqid64->msg_perm, msqid64->msg_qbytes);
++				      perm, msg_qbytes);
+ 	if (IS_ERR(ipcp)) {
+ 		err = PTR_ERR(ipcp);
+ 		goto out_unlock1;
+@@ -409,18 +409,18 @@ static int msgctl_down(struct ipc_namespace *ns, int msqid, int cmd,
+ 	{
+ 		DEFINE_WAKE_Q(wake_q);
+ 
+-		if (msqid64->msg_qbytes > ns->msg_ctlmnb &&
++		if (msg_qbytes > ns->msg_ctlmnb &&
+ 		    !capable(CAP_SYS_RESOURCE)) {
+ 			err = -EPERM;
+ 			goto out_unlock1;
+ 		}
+ 
+ 		ipc_lock_object(&msq->q_perm);
+-		err = ipc_update_perm(&msqid64->msg_perm, ipcp);
++		err = ipc_update_perm(perm, ipcp);
+ 		if (err)
+ 			goto out_unlock0;
+ 
+-		msq->q_qbytes = msqid64->msg_qbytes;
++		msq->q_qbytes = msg_qbytes;
+ 
+ 		msq->q_ctime = ktime_get_real_seconds();
+ 		/*
+@@ -603,9 +603,10 @@ long ksys_msgctl(int msqid, int cmd, struct msqid_ds __user *buf)
+ 	case IPC_SET:
+ 		if (copy_msqid_from_user(&msqid64, buf, version))
+ 			return -EFAULT;
+-		/* fallthru */
++		return msgctl_down(ns, msqid, cmd, &msqid64.msg_perm,
++				   msqid64.msg_qbytes);
+ 	case IPC_RMID:
+-		return msgctl_down(ns, msqid, cmd, &msqid64);
++		return msgctl_down(ns, msqid, cmd, NULL, 0);
+ 	default:
+ 		return  -EINVAL;
+ 	}
+@@ -724,9 +725,9 @@ long compat_ksys_msgctl(int msqid, int cmd, void __user *uptr)
+ 	case IPC_SET:
+ 		if (copy_compat_msqid_from_user(&msqid64, uptr, version))
+ 			return -EFAULT;
+-		/* fallthru */
++		return msgctl_down(ns, msqid, cmd, &msqid64.msg_perm, msqid64.msg_qbytes);
+ 	case IPC_RMID:
+-		return msgctl_down(ns, msqid, cmd, &msqid64);
++		return msgctl_down(ns, msqid, cmd, NULL, 0);
+ 	default:
+ 		return -EINVAL;
+ 	}
+diff --git a/kernel/events/core.c b/kernel/events/core.c
+index 16af86ab24c4..8c70ee23fbe9 100644
+--- a/kernel/events/core.c
++++ b/kernel/events/core.c
+@@ -5709,7 +5709,15 @@ accounting:
+ 	 */
+ 	user_lock_limit *= num_online_cpus();
+ 
+-	user_locked = atomic_long_read(&user->locked_vm) + user_extra;
++	user_locked = atomic_long_read(&user->locked_vm);
++
++	/*
++	 * sysctl_perf_event_mlock may have changed, so that
++	 *     user->locked_vm > user_lock_limit
++	 */
++	if (user_locked > user_lock_limit)
++		user_locked = user_lock_limit;
++	user_locked += user_extra;
+ 
+ 	if (user_locked > user_lock_limit)
+ 		extra = user_locked - user_lock_limit;
+diff --git a/kernel/irq/debugfs.c b/kernel/irq/debugfs.c
+index 6f636136cccc..b3f55dd581b0 100644
+--- a/kernel/irq/debugfs.c
++++ b/kernel/irq/debugfs.c
+@@ -113,6 +113,7 @@ static const struct irq_bit_descr irqdata_states[] = {
+ 	BIT_MASK_DESCR(IRQD_AFFINITY_MANAGED),
+ 	BIT_MASK_DESCR(IRQD_MANAGED_SHUTDOWN),
+ 	BIT_MASK_DESCR(IRQD_CAN_RESERVE),
++	BIT_MASK_DESCR(IRQD_MSI_NOMASK_QUIRK),
+ 
+ 	BIT_MASK_DESCR(IRQD_FORWARDED_TO_VCPU),
+ 
+diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c
+index 6e8520a81dd8..e0eda2bd3975 100644
+--- a/kernel/irq/irqdomain.c
++++ b/kernel/irq/irqdomain.c
+@@ -1421,6 +1421,7 @@ int irq_domain_push_irq(struct irq_domain *domain, int virq, void *arg)
+ 	if (rv) {
+ 		/* Restore the original irq_data. */
+ 		*root_irq_data = *child_irq_data;
++		kfree(child_irq_data);
+ 		goto error;
+ 	}
+ 
+diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c
+index 4ca2fd46645d..dc1186ce3ecd 100644
+--- a/kernel/irq/msi.c
++++ b/kernel/irq/msi.c
+@@ -453,8 +453,11 @@ int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
+ 			continue;
+ 
+ 		irq_data = irq_domain_get_irq_data(domain, desc->irq);
+-		if (!can_reserve)
++		if (!can_reserve) {
+ 			irqd_clr_can_reserve(irq_data);
++			if (domain->flags & IRQ_DOMAIN_MSI_NOMASK_QUIRK)
++				irqd_set_msi_nomask_quirk(irq_data);
++		}
+ 		ret = irq_domain_activate_irq(irq_data, can_reserve);
+ 		if (ret)
+ 			goto cleanup;
+diff --git a/kernel/module.c b/kernel/module.c
+index d3aaec62c142..70a75a7216ab 100644
+--- a/kernel/module.c
++++ b/kernel/module.c
+@@ -1729,6 +1729,8 @@ static int module_add_modinfo_attrs(struct module *mod)
+ error_out:
+ 	if (i > 0)
+ 		module_remove_modinfo_attrs(mod, --i);
++	else
++		kfree(mod->modinfo_attrs);
+ 	return error;
+ }
+ 
+diff --git a/kernel/padata.c b/kernel/padata.c
+index 6c06b3039fae..11c5f9c8779e 100644
+--- a/kernel/padata.c
++++ b/kernel/padata.c
+@@ -35,6 +35,8 @@
+ 
+ #define MAX_OBJ_NUM 1000
+ 
++static void padata_free_pd(struct parallel_data *pd);
++
+ static int padata_index_to_cpu(struct parallel_data *pd, int cpu_index)
+ {
+ 	int cpu, target_cpu;
+@@ -334,6 +336,7 @@ static void padata_serial_worker(struct work_struct *serial_work)
+ 	struct padata_serial_queue *squeue;
+ 	struct parallel_data *pd;
+ 	LIST_HEAD(local_list);
++	int cnt;
+ 
+ 	local_bh_disable();
+ 	squeue = container_of(serial_work, struct padata_serial_queue, work);
+@@ -343,6 +346,8 @@ static void padata_serial_worker(struct work_struct *serial_work)
+ 	list_replace_init(&squeue->serial.list, &local_list);
+ 	spin_unlock(&squeue->serial.lock);
+ 
++	cnt = 0;
++
+ 	while (!list_empty(&local_list)) {
+ 		struct padata_priv *padata;
+ 
+@@ -352,9 +357,12 @@ static void padata_serial_worker(struct work_struct *serial_work)
+ 		list_del_init(&padata->list);
+ 
+ 		padata->serial(padata);
+-		atomic_dec(&pd->refcnt);
++		cnt++;
+ 	}
+ 	local_bh_enable();
++
++	if (atomic_sub_and_test(cnt, &pd->refcnt))
++		padata_free_pd(pd);
+ }
+ 
+ /**
+@@ -501,8 +509,7 @@ static struct parallel_data *padata_alloc_pd(struct padata_instance *pinst,
+ 	timer_setup(&pd->timer, padata_reorder_timer, 0);
+ 	atomic_set(&pd->seq_nr, -1);
+ 	atomic_set(&pd->reorder_objects, 0);
+-	atomic_set(&pd->refcnt, 0);
+-	pd->pinst = pinst;
++	atomic_set(&pd->refcnt, 1);
+ 	spin_lock_init(&pd->lock);
+ 
+ 	return pd;
+@@ -526,31 +533,6 @@ static void padata_free_pd(struct parallel_data *pd)
+ 	kfree(pd);
+ }
+ 
+-/* Flush all objects out of the padata queues. */
+-static void padata_flush_queues(struct parallel_data *pd)
+-{
+-	int cpu;
+-	struct padata_parallel_queue *pqueue;
+-	struct padata_serial_queue *squeue;
+-
+-	for_each_cpu(cpu, pd->cpumask.pcpu) {
+-		pqueue = per_cpu_ptr(pd->pqueue, cpu);
+-		flush_work(&pqueue->work);
+-	}
+-
+-	del_timer_sync(&pd->timer);
+-
+-	if (atomic_read(&pd->reorder_objects))
+-		padata_reorder(pd);
+-
+-	for_each_cpu(cpu, pd->cpumask.cbcpu) {
+-		squeue = per_cpu_ptr(pd->squeue, cpu);
+-		flush_work(&squeue->work);
+-	}
+-
+-	BUG_ON(atomic_read(&pd->refcnt) != 0);
+-}
+-
+ static void __padata_start(struct padata_instance *pinst)
+ {
+ 	pinst->flags |= PADATA_INIT;
+@@ -564,10 +546,6 @@ static void __padata_stop(struct padata_instance *pinst)
+ 	pinst->flags &= ~PADATA_INIT;
+ 
+ 	synchronize_rcu();
+-
+-	get_online_cpus();
+-	padata_flush_queues(pinst->pd);
+-	put_online_cpus();
+ }
+ 
+ /* Replace the internal control structure with a new one. */
+@@ -588,8 +566,8 @@ static void padata_replace(struct padata_instance *pinst,
+ 	if (!cpumask_equal(pd_old->cpumask.cbcpu, pd_new->cpumask.cbcpu))
+ 		notification_mask |= PADATA_CPU_SERIAL;
+ 
+-	padata_flush_queues(pd_old);
+-	padata_free_pd(pd_old);
++	if (atomic_dec_and_test(&pd_old->refcnt))
++		padata_free_pd(pd_old);
+ 
+ 	if (notification_mask)
+ 		blocking_notifier_call_chain(&pinst->cpumask_change_notifier,
+diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
+index 845efadaf7ec..7a2fdc097c8c 100644
+--- a/kernel/printk/printk.c
++++ b/kernel/printk/printk.c
+@@ -2717,8 +2717,6 @@ void register_console(struct console *newcon)
+ 		 * for us.
+ 		 */
+ 		logbuf_lock_irqsave(flags);
+-		console_seq = syslog_seq;
+-		console_idx = syslog_idx;
+ 		/*
+ 		 * We're about to replay the log buffer.  Only do this to the
+ 		 * just-registered console to avoid excessive message spam to
+@@ -2730,6 +2728,8 @@ void register_console(struct console *newcon)
+ 		 */
+ 		exclusive_console = newcon;
+ 		exclusive_console_stop_seq = console_seq;
++		console_seq = syslog_seq;
++		console_idx = syslog_idx;
+ 		logbuf_unlock_irqrestore(flags);
+ 	}
+ 	console_unlock();
+diff --git a/kernel/rcu/tree_plugin.h b/kernel/rcu/tree_plugin.h
+index a97c20ea9bce..5f6de49dc78e 100644
+--- a/kernel/rcu/tree_plugin.h
++++ b/kernel/rcu/tree_plugin.h
+@@ -267,7 +267,7 @@ static void rcu_preempt_ctxt_queue(struct rcu_node *rnp, struct rcu_data *rdp)
+ 	 * blocked tasks.
+ 	 */
+ 	if (!rnp->gp_tasks && (blkd_state & RCU_GP_BLKD)) {
+-		rnp->gp_tasks = &t->rcu_node_entry;
++		WRITE_ONCE(rnp->gp_tasks, &t->rcu_node_entry);
+ 		WARN_ON_ONCE(rnp->completedqs == rnp->gp_seq);
+ 	}
+ 	if (!rnp->exp_tasks && (blkd_state & RCU_EXP_BLKD))
+@@ -392,7 +392,7 @@ static void rcu_preempt_note_context_switch(bool preempt)
+  */
+ static int rcu_preempt_blocked_readers_cgp(struct rcu_node *rnp)
+ {
+-	return rnp->gp_tasks != NULL;
++	return READ_ONCE(rnp->gp_tasks) != NULL;
+ }
+ 
+ /*
+@@ -557,7 +557,7 @@ static void rcu_read_unlock_special(struct task_struct *t)
+ 		trace_rcu_unlock_preempted_task(TPS("rcu_preempt"),
+ 						rnp->gp_seq, t->pid);
+ 		if (&t->rcu_node_entry == rnp->gp_tasks)
+-			rnp->gp_tasks = np;
++			WRITE_ONCE(rnp->gp_tasks, np);
+ 		if (&t->rcu_node_entry == rnp->exp_tasks)
+ 			rnp->exp_tasks = np;
+ 		if (IS_ENABLED(CONFIG_RCU_BOOST)) {
+@@ -716,7 +716,7 @@ rcu_preempt_check_blocked_tasks(struct rcu_state *rsp, struct rcu_node *rnp)
+ 		dump_blkd_tasks(rsp, rnp, 10);
+ 	if (rcu_preempt_has_tasks(rnp) &&
+ 	    (rnp->qsmaskinit || rnp->wait_blkd_tasks)) {
+-		rnp->gp_tasks = rnp->blkd_tasks.next;
++		WRITE_ONCE(rnp->gp_tasks, rnp->blkd_tasks.next);
+ 		t = container_of(rnp->gp_tasks, struct task_struct,
+ 				 rcu_node_entry);
+ 		trace_rcu_unlock_preempted_task(TPS("rcu_preempt-GPS"),
+@@ -883,7 +883,8 @@ dump_blkd_tasks(struct rcu_state *rsp, struct rcu_node *rnp, int ncheck)
+ 		pr_info("%s: %d:%d ->qsmask %#lx ->qsmaskinit %#lx ->qsmaskinitnext %#lx\n",
+ 			__func__, rnp1->grplo, rnp1->grphi, rnp1->qsmask, rnp1->qsmaskinit, rnp1->qsmaskinitnext);
+ 	pr_info("%s: ->gp_tasks %p ->boost_tasks %p ->exp_tasks %p\n",
+-		__func__, rnp->gp_tasks, rnp->boost_tasks, rnp->exp_tasks);
++		__func__, READ_ONCE(rnp->gp_tasks), rnp->boost_tasks,
++		rnp->exp_tasks);
+ 	pr_info("%s: ->blkd_tasks", __func__);
+ 	i = 0;
+ 	list_for_each(lhp, &rnp->blkd_tasks) {
+diff --git a/kernel/time/alarmtimer.c b/kernel/time/alarmtimer.c
+index f4255a65c44b..9eece67f29f3 100644
+--- a/kernel/time/alarmtimer.c
++++ b/kernel/time/alarmtimer.c
+@@ -91,6 +91,7 @@ static int alarmtimer_rtc_add_device(struct device *dev,
+ 	unsigned long flags;
+ 	struct rtc_device *rtc = to_rtc_device(dev);
+ 	struct wakeup_source *__ws;
++	int ret = 0;
+ 
+ 	if (rtcdev)
+ 		return -EBUSY;
+@@ -105,8 +106,8 @@ static int alarmtimer_rtc_add_device(struct device *dev,
+ 	spin_lock_irqsave(&rtcdev_lock, flags);
+ 	if (!rtcdev) {
+ 		if (!try_module_get(rtc->owner)) {
+-			spin_unlock_irqrestore(&rtcdev_lock, flags);
+-			return -1;
++			ret = -1;
++			goto unlock;
+ 		}
+ 
+ 		rtcdev = rtc;
+@@ -115,11 +116,12 @@ static int alarmtimer_rtc_add_device(struct device *dev,
+ 		ws = __ws;
+ 		__ws = NULL;
+ 	}
++unlock:
+ 	spin_unlock_irqrestore(&rtcdev_lock, flags);
+ 
+ 	wakeup_source_unregister(__ws);
+ 
+-	return 0;
++	return ret;
+ }
+ 
+ static inline void alarmtimer_rtc_timer_init(void)
+diff --git a/kernel/time/clocksource.c b/kernel/time/clocksource.c
+index 0e6e97a01942..f80bb104c41a 100644
+--- a/kernel/time/clocksource.c
++++ b/kernel/time/clocksource.c
+@@ -311,8 +311,15 @@ static void clocksource_watchdog(struct timer_list *unused)
+ 	next_cpu = cpumask_next(raw_smp_processor_id(), cpu_online_mask);
+ 	if (next_cpu >= nr_cpu_ids)
+ 		next_cpu = cpumask_first(cpu_online_mask);
+-	watchdog_timer.expires += WATCHDOG_INTERVAL;
+-	add_timer_on(&watchdog_timer, next_cpu);
++
++	/*
++	 * Arm timer if not already pending: could race with concurrent
++	 * pair clocksource_stop_watchdog() clocksource_start_watchdog().
++	 */
++	if (!timer_pending(&watchdog_timer)) {
++		watchdog_timer.expires += WATCHDOG_INTERVAL;
++		add_timer_on(&watchdog_timer, next_cpu);
++	}
+ out:
+ 	spin_unlock(&watchdog_lock);
+ }
+diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c
+index 37a435bac161..53795237e975 100644
+--- a/kernel/trace/ftrace.c
++++ b/kernel/trace/ftrace.c
+@@ -5072,8 +5072,8 @@ static const struct file_operations ftrace_notrace_fops = {
+ 
+ static DEFINE_MUTEX(graph_lock);
+ 
+-struct ftrace_hash *ftrace_graph_hash = EMPTY_HASH;
+-struct ftrace_hash *ftrace_graph_notrace_hash = EMPTY_HASH;
++struct ftrace_hash __rcu *ftrace_graph_hash = EMPTY_HASH;
++struct ftrace_hash __rcu *ftrace_graph_notrace_hash = EMPTY_HASH;
+ 
+ enum graph_filter_type {
+ 	GRAPH_FILTER_NOTRACE	= 0,
+@@ -5344,8 +5344,15 @@ ftrace_graph_release(struct inode *inode, struct file *file)
+ 
+ 		mutex_unlock(&graph_lock);
+ 
+-		/* Wait till all users are no longer using the old hash */
+-		synchronize_sched();
++		/*
++		 * We need to do a hard force of sched synchronization.
++		 * This is because we use preempt_disable() to do RCU, but
++		 * the function tracers can be called where RCU is not watching
++		 * (like before user_exit()). We can not rely on the RCU
++		 * infrastructure to do the synchronization, thus we must do it
++		 * ourselves.
++		 */
++		schedule_on_each_cpu(ftrace_sync);
+ 
+ 		free_ftrace_hash(old_hash);
+ 	}
+diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h
+index d11d7bfc3fa5..ee0c6a313ed1 100644
+--- a/kernel/trace/trace.h
++++ b/kernel/trace/trace.h
+@@ -872,22 +872,31 @@ extern void __trace_graph_return(struct trace_array *tr,
+ 				 unsigned long flags, int pc);
+ 
+ #ifdef CONFIG_DYNAMIC_FTRACE
+-extern struct ftrace_hash *ftrace_graph_hash;
+-extern struct ftrace_hash *ftrace_graph_notrace_hash;
++extern struct ftrace_hash __rcu *ftrace_graph_hash;
++extern struct ftrace_hash __rcu *ftrace_graph_notrace_hash;
+ 
+ static inline int ftrace_graph_addr(struct ftrace_graph_ent *trace)
+ {
+ 	unsigned long addr = trace->func;
+ 	int ret = 0;
++	struct ftrace_hash *hash;
+ 
+ 	preempt_disable_notrace();
+ 
+-	if (ftrace_hash_empty(ftrace_graph_hash)) {
++	/*
++	 * Have to open code "rcu_dereference_sched()" because the
++	 * function graph tracer can be called when RCU is not
++	 * "watching".
++	 * Protected with schedule_on_each_cpu(ftrace_sync)
++	 */
++	hash = rcu_dereference_protected(ftrace_graph_hash, !preemptible());
++
++	if (ftrace_hash_empty(hash)) {
+ 		ret = 1;
+ 		goto out;
+ 	}
+ 
+-	if (ftrace_lookup_ip(ftrace_graph_hash, addr)) {
++	if (ftrace_lookup_ip(hash, addr)) {
+ 
+ 		/*
+ 		 * This needs to be cleared on the return functions
+@@ -923,10 +932,20 @@ static inline void ftrace_graph_addr_finish(struct ftrace_graph_ret *trace)
+ static inline int ftrace_graph_notrace_addr(unsigned long addr)
+ {
+ 	int ret = 0;
++	struct ftrace_hash *notrace_hash;
+ 
+ 	preempt_disable_notrace();
+ 
+-	if (ftrace_lookup_ip(ftrace_graph_notrace_hash, addr))
++	/*
++	 * Have to open code "rcu_dereference_sched()" because the
++	 * function graph tracer can be called when RCU is not
++	 * "watching".
++	 * Protected with schedule_on_each_cpu(ftrace_sync)
++	 */
++	notrace_hash = rcu_dereference_protected(ftrace_graph_notrace_hash,
++						 !preemptible());
++
++	if (ftrace_lookup_ip(notrace_hash, addr))
+ 		ret = 1;
+ 
+ 	preempt_enable_notrace();
+diff --git a/kernel/trace/trace_sched_switch.c b/kernel/trace/trace_sched_switch.c
+index e288168661e1..e304196d7c28 100644
+--- a/kernel/trace/trace_sched_switch.c
++++ b/kernel/trace/trace_sched_switch.c
+@@ -89,8 +89,10 @@ static void tracing_sched_unregister(void)
+ 
+ static void tracing_start_sched_switch(int ops)
+ {
+-	bool sched_register = (!sched_cmdline_ref && !sched_tgid_ref);
++	bool sched_register;
++
+ 	mutex_lock(&sched_register_mutex);
++	sched_register = (!sched_cmdline_ref && !sched_tgid_ref);
+ 
+ 	switch (ops) {
+ 	case RECORD_CMDLINE:
+diff --git a/lib/test_kasan.c b/lib/test_kasan.c
+index ec657105edbf..bd0e067c4895 100644
+--- a/lib/test_kasan.c
++++ b/lib/test_kasan.c
+@@ -157,6 +157,7 @@ static noinline void __init kmalloc_oob_krealloc_more(void)
+ 	if (!ptr1 || !ptr2) {
+ 		pr_err("Allocation failed\n");
+ 		kfree(ptr1);
++		kfree(ptr2);
+ 		return;
+ 	}
+ 
+diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c
+index abc10dcbc9d5..aae7ff485671 100644
+--- a/mm/memory_hotplug.c
++++ b/mm/memory_hotplug.c
+@@ -1902,8 +1902,6 @@ void __ref __remove_memory(int nid, u64 start, u64 size)
+ 
+ 	BUG_ON(check_hotplug_memory_range(start, size));
+ 
+-	mem_hotplug_begin();
+-
+ 	/*
+ 	 * All memory blocks must be offlined before removing memory.  Check
+ 	 * whether all memory blocks in question are offline and trigger a BUG()
+@@ -1919,9 +1917,14 @@ void __ref __remove_memory(int nid, u64 start, u64 size)
+ 	memblock_free(start, size);
+ 	memblock_remove(start, size);
+ 
+-	/* remove memory block devices before removing memory */
++	/*
++	 * Memory block device removal under the device_hotplug_lock is
++	 * a barrier against racing online attempts.
++	 */
+ 	remove_memory_block_devices(start, size);
+ 
++	mem_hotplug_begin();
++
+ 	arch_remove_memory(nid, start, size, NULL);
+ 	__release_memory_resource(start, size);
+ 
+diff --git a/mm/migrate.c b/mm/migrate.c
+index 70f8ad4ade3f..a69b842f95da 100644
+--- a/mm/migrate.c
++++ b/mm/migrate.c
+@@ -1623,8 +1623,19 @@ static int do_pages_move(struct mm_struct *mm, nodemask_t task_nodes,
+ 			start = i;
+ 		} else if (node != current_node) {
+ 			err = do_move_pages_to_node(mm, &pagelist, current_node);
+-			if (err)
++			if (err) {
++				/*
++				 * Positive err means the number of failed
++				 * pages to migrate.  Since we are going to
++				 * abort and return the number of non-migrated
++				 * pages, so need to incude the rest of the
++				 * nr_pages that have not been attempted as
++				 * well.
++				 */
++				if (err > 0)
++					err += nr_pages - i - 1;
+ 				goto out;
++			}
+ 			err = store_status(status, start, current_node, i - start);
+ 			if (err)
+ 				goto out;
+@@ -1655,8 +1666,11 @@ static int do_pages_move(struct mm_struct *mm, nodemask_t task_nodes,
+ 			goto out_flush;
+ 
+ 		err = do_move_pages_to_node(mm, &pagelist, current_node);
+-		if (err)
++		if (err) {
++			if (err > 0)
++				err += nr_pages - i - 1;
+ 			goto out;
++		}
+ 		if (i > start) {
+ 			err = store_status(status, start, current_node, i - start);
+ 			if (err)
+@@ -1670,6 +1684,13 @@ out_flush:
+ 
+ 	/* Make sure we do not overwrite the existing error */
+ 	err1 = do_move_pages_to_node(mm, &pagelist, current_node);
++	/*
++	 * Don't have to report non-attempted pages here since:
++	 *     - If the above loop is done gracefully all pages have been
++	 *       attempted.
++	 *     - If the above loop is aborted it means a fatal error
++	 *       happened, should return ret.
++	 */
+ 	if (!err1)
+ 		err1 = store_status(status, start, current_node, i - start);
+ 	if (err >= 0)
+diff --git a/mm/page_alloc.c b/mm/page_alloc.c
+index 74fb5c338e8f..e5c610d711f3 100644
+--- a/mm/page_alloc.c
++++ b/mm/page_alloc.c
+@@ -6456,45 +6456,75 @@ void __init free_area_init_node(int nid, unsigned long *zones_size,
+ }
+ 
+ #if defined(CONFIG_HAVE_MEMBLOCK) && !defined(CONFIG_FLAT_NODE_MEM_MAP)
++
++/*
++ * Zero all valid struct pages in range [spfn, epfn), return number of struct
++ * pages zeroed
++ */
++static u64 zero_pfn_range(unsigned long spfn, unsigned long epfn)
++{
++	unsigned long pfn;
++	u64 pgcnt = 0;
++
++	for (pfn = spfn; pfn < epfn; pfn++) {
++		if (!pfn_valid(ALIGN_DOWN(pfn, pageblock_nr_pages))) {
++			pfn = ALIGN_DOWN(pfn, pageblock_nr_pages)
++				+ pageblock_nr_pages - 1;
++			continue;
++		}
++		mm_zero_struct_page(pfn_to_page(pfn));
++		pgcnt++;
++	}
++
++	return pgcnt;
++}
++
+ /*
+  * Only struct pages that are backed by physical memory are zeroed and
+  * initialized by going through __init_single_page(). But, there are some
+  * struct pages which are reserved in memblock allocator and their fields
+  * may be accessed (for example page_to_pfn() on some configuration accesses
+  * flags). We must explicitly zero those struct pages.
++ *
++ * This function also addresses a similar issue where struct pages are left
++ * uninitialized because the physical address range is not covered by
++ * memblock.memory or memblock.reserved. That could happen when memblock
++ * layout is manually configured via memmap=, or when the highest physical
++ * address (max_pfn) does not end on a section boundary.
+  */
+ void __init zero_resv_unavail(void)
+ {
+ 	phys_addr_t start, end;
+-	unsigned long pfn;
+ 	u64 i, pgcnt;
++	phys_addr_t next = 0;
+ 
+ 	/*
+-	 * Loop through ranges that are reserved, but do not have reported
+-	 * physical memory backing.
++	 * Loop through unavailable ranges not covered by memblock.memory.
+ 	 */
+ 	pgcnt = 0;
+-	for_each_resv_unavail_range(i, &start, &end) {
+-		for (pfn = PFN_DOWN(start); pfn < PFN_UP(end); pfn++) {
+-			if (!pfn_valid(ALIGN_DOWN(pfn, pageblock_nr_pages))) {
+-				pfn = ALIGN_DOWN(pfn, pageblock_nr_pages)
+-					+ pageblock_nr_pages - 1;
+-				continue;
+-			}
+-			mm_zero_struct_page(pfn_to_page(pfn));
+-			pgcnt++;
+-		}
++	for_each_mem_range(i, &memblock.memory, NULL,
++			NUMA_NO_NODE, MEMBLOCK_NONE, &start, &end, NULL) {
++		if (next < start)
++			pgcnt += zero_pfn_range(PFN_DOWN(next), PFN_UP(start));
++		next = end;
+ 	}
+ 
++	/*
++	 * Early sections always have a fully populated memmap for the whole
++	 * section - see pfn_valid(). If the last section has holes at the
++	 * end and that section is marked "online", the memmap will be
++	 * considered initialized. Make sure that memmap has a well defined
++	 * state.
++	 */
++	pgcnt += zero_pfn_range(PFN_DOWN(next),
++				round_up(max_pfn, PAGES_PER_SECTION));
++
+ 	/*
+ 	 * Struct pages that do not have backing memory. This could be because
+ 	 * firmware is using some of this memory, or for some other reasons.
+-	 * Once memblock is changed so such behaviour is not allowed: i.e.
+-	 * list of "reserved" memory must be a subset of list of "memory", then
+-	 * this code can be removed.
+ 	 */
+ 	if (pgcnt)
+-		pr_info("Reserved but unavailable: %lld pages", pgcnt);
++		pr_info("Zeroed struct page in unavailable ranges: %lld pages", pgcnt);
+ }
+ #endif /* CONFIG_HAVE_MEMBLOCK && !CONFIG_FLAT_NODE_MEM_MAP */
+ 
+diff --git a/net/hsr/hsr_slave.c b/net/hsr/hsr_slave.c
+index 56080da4aa77..5fee6ec7c93d 100644
+--- a/net/hsr/hsr_slave.c
++++ b/net/hsr/hsr_slave.c
+@@ -32,6 +32,8 @@ static rx_handler_result_t hsr_handle_frame(struct sk_buff **pskb)
+ 
+ 	rcu_read_lock(); /* hsr->node_db, hsr->ports */
+ 	port = hsr_port_get_rcu(skb->dev);
++	if (!port)
++		goto finish_pass;
+ 
+ 	if (hsr_addr_is_self(port->hsr, eth_hdr(skb)->h_source)) {
+ 		/* Directly kill frames sent by ourselves */
+diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c
+index e80eb1788f80..34fda81c7db0 100644
+--- a/net/ipv4/tcp.c
++++ b/net/ipv4/tcp.c
+@@ -2588,10 +2588,12 @@ int tcp_disconnect(struct sock *sk, int flags)
+ 	tp->snd_ssthresh = TCP_INFINITE_SSTHRESH;
+ 	tp->snd_cwnd_cnt = 0;
+ 	tp->window_clamp = 0;
++	tp->delivered = 0;
+ 	tp->delivered_ce = 0;
+ 	tcp_set_ca_state(sk, TCP_CA_Open);
+ 	tp->is_sack_reneg = 0;
+ 	tcp_clear_retrans(tp);
++	tp->total_retrans = 0;
+ 	inet_csk_delack_init(sk);
+ 	/* Initialize rcv_mss to TCP_MIN_MSS to avoid division by 0
+ 	 * issue in __tcp_select_window()
+@@ -2603,10 +2605,14 @@ int tcp_disconnect(struct sock *sk, int flags)
+ 	sk->sk_rx_dst = NULL;
+ 	tcp_saved_syn_free(tp);
+ 	tp->compressed_ack = 0;
++	tp->segs_in = 0;
++	tp->segs_out = 0;
+ 	tp->bytes_sent = 0;
+ 	tp->bytes_acked = 0;
+ 	tp->bytes_received = 0;
+ 	tp->bytes_retrans = 0;
++	tp->data_segs_in = 0;
++	tp->data_segs_out = 0;
+ 	tp->dsack_dups = 0;
+ 	tp->reord_seen = 0;
+ 
+diff --git a/net/l2tp/l2tp_core.c b/net/l2tp/l2tp_core.c
+index e4dec03a19fe..d0a295cd71ef 100644
+--- a/net/l2tp/l2tp_core.c
++++ b/net/l2tp/l2tp_core.c
+@@ -325,8 +325,13 @@ int l2tp_session_register(struct l2tp_session *session,
+ 
+ 		spin_lock_bh(&pn->l2tp_session_hlist_lock);
+ 
++		/* IP encap expects session IDs to be globally unique, while
++		 * UDP encap doesn't.
++		 */
+ 		hlist_for_each_entry(session_walk, g_head, global_hlist)
+-			if (session_walk->session_id == session->session_id) {
++			if (session_walk->session_id == session->session_id &&
++			    (session_walk->tunnel->encap == L2TP_ENCAPTYPE_IP ||
++			     tunnel->encap == L2TP_ENCAPTYPE_IP)) {
+ 				err = -EEXIST;
+ 				goto err_tlock_pnlock;
+ 			}
+diff --git a/net/rxrpc/af_rxrpc.c b/net/rxrpc/af_rxrpc.c
+index a74edb10cbfc..57f835d2442e 100644
+--- a/net/rxrpc/af_rxrpc.c
++++ b/net/rxrpc/af_rxrpc.c
+@@ -196,6 +196,7 @@ static int rxrpc_bind(struct socket *sock, struct sockaddr *saddr, int len)
+ service_in_use:
+ 	write_unlock(&local->services_lock);
+ 	rxrpc_unuse_local(local);
++	rxrpc_put_local(local);
+ 	ret = -EADDRINUSE;
+ error_unlock:
+ 	release_sock(&rx->sk);
+@@ -906,6 +907,7 @@ static int rxrpc_release_sock(struct sock *sk)
+ 	rxrpc_purge_queue(&sk->sk_receive_queue);
+ 
+ 	rxrpc_unuse_local(rx->local);
++	rxrpc_put_local(rx->local);
+ 	rx->local = NULL;
+ 	key_put(rx->key);
+ 	rx->key = NULL;
+diff --git a/net/rxrpc/ar-internal.h b/net/rxrpc/ar-internal.h
+index ccef6e40e002..9c4ee7513214 100644
+--- a/net/rxrpc/ar-internal.h
++++ b/net/rxrpc/ar-internal.h
+@@ -484,6 +484,7 @@ enum rxrpc_call_flag {
+ 	RXRPC_CALL_BEGAN_RX_TIMER,	/* We began the expect_rx_by timer */
+ 	RXRPC_CALL_RX_HEARD,		/* The peer responded at least once to this call */
+ 	RXRPC_CALL_RX_UNDERRUN,		/* Got data underrun */
++	RXRPC_CALL_DISCONNECTED,	/* The call has been disconnected */
+ };
+ 
+ /*
+@@ -1006,6 +1007,16 @@ void rxrpc_unuse_local(struct rxrpc_local *);
+ void rxrpc_queue_local(struct rxrpc_local *);
+ void rxrpc_destroy_all_locals(struct rxrpc_net *);
+ 
++static inline bool __rxrpc_unuse_local(struct rxrpc_local *local)
++{
++	return atomic_dec_return(&local->active_users) == 0;
++}
++
++static inline bool __rxrpc_use_local(struct rxrpc_local *local)
++{
++	return atomic_fetch_add_unless(&local->active_users, 1, 0) != 0;
++}
++
+ /*
+  * misc.c
+  */
+diff --git a/net/rxrpc/call_object.c b/net/rxrpc/call_object.c
+index 215f4d98baa0..17fdfce1625f 100644
+--- a/net/rxrpc/call_object.c
++++ b/net/rxrpc/call_object.c
+@@ -520,7 +520,7 @@ void rxrpc_release_call(struct rxrpc_sock *rx, struct rxrpc_call *call)
+ 
+ 	_debug("RELEASE CALL %p (%d CONN %p)", call, call->debug_id, conn);
+ 
+-	if (conn)
++	if (conn && !test_bit(RXRPC_CALL_DISCONNECTED, &call->flags))
+ 		rxrpc_disconnect_call(call);
+ 
+ 	for (i = 0; i < RXRPC_RXTX_BUFF_SIZE; i++) {
+@@ -654,6 +654,7 @@ static void rxrpc_rcu_destroy_call(struct rcu_head *rcu)
+ 	struct rxrpc_call *call = container_of(rcu, struct rxrpc_call, rcu);
+ 	struct rxrpc_net *rxnet = call->rxnet;
+ 
++	rxrpc_put_connection(call->conn);
+ 	rxrpc_put_peer(call->peer);
+ 	kfree(call->rxtx_buffer);
+ 	kfree(call->rxtx_annotations);
+@@ -677,7 +678,6 @@ void rxrpc_cleanup_call(struct rxrpc_call *call)
+ 
+ 	ASSERTCMP(call->state, ==, RXRPC_CALL_COMPLETE);
+ 	ASSERT(test_bit(RXRPC_CALL_RELEASED, &call->flags));
+-	ASSERTCMP(call->conn, ==, NULL);
+ 
+ 	/* Clean up the Rx/Tx buffer */
+ 	for (i = 0; i < RXRPC_RXTX_BUFF_SIZE; i++)
+diff --git a/net/rxrpc/conn_client.c b/net/rxrpc/conn_client.c
+index 38d548532024..4ffc7b87fec0 100644
+--- a/net/rxrpc/conn_client.c
++++ b/net/rxrpc/conn_client.c
+@@ -786,6 +786,7 @@ void rxrpc_disconnect_client_call(struct rxrpc_call *call)
+ 	u32 cid;
+ 
+ 	spin_lock(&conn->channel_lock);
++	set_bit(RXRPC_CALL_DISCONNECTED, &call->flags);
+ 
+ 	cid = call->cid;
+ 	if (cid) {
+@@ -793,7 +794,6 @@ void rxrpc_disconnect_client_call(struct rxrpc_call *call)
+ 		chan = &conn->channels[channel];
+ 	}
+ 	trace_rxrpc_client(conn, channel, rxrpc_client_chan_disconnect);
+-	call->conn = NULL;
+ 
+ 	/* Calls that have never actually been assigned a channel can simply be
+ 	 * discarded.  If the conn didn't get used either, it will follow
+@@ -909,7 +909,6 @@ out:
+ 	spin_unlock(&rxnet->client_conn_cache_lock);
+ out_2:
+ 	spin_unlock(&conn->channel_lock);
+-	rxrpc_put_connection(conn);
+ 	_leave("");
+ 	return;
+ 
+diff --git a/net/rxrpc/conn_event.c b/net/rxrpc/conn_event.c
+index b6fca8ebb117..126154a97a59 100644
+--- a/net/rxrpc/conn_event.c
++++ b/net/rxrpc/conn_event.c
+@@ -453,16 +453,12 @@ again:
+ /*
+  * connection-level event processor
+  */
+-void rxrpc_process_connection(struct work_struct *work)
++static void rxrpc_do_process_connection(struct rxrpc_connection *conn)
+ {
+-	struct rxrpc_connection *conn =
+-		container_of(work, struct rxrpc_connection, processor);
+ 	struct sk_buff *skb;
+ 	u32 abort_code = RX_PROTOCOL_ERROR;
+ 	int ret;
+ 
+-	rxrpc_see_connection(conn);
+-
+ 	if (test_and_clear_bit(RXRPC_CONN_EV_CHALLENGE, &conn->events))
+ 		rxrpc_secure_connection(conn);
+ 
+@@ -490,18 +486,33 @@ void rxrpc_process_connection(struct work_struct *work)
+ 		}
+ 	}
+ 
+-out:
+-	rxrpc_put_connection(conn);
+-	_leave("");
+ 	return;
+ 
+ requeue_and_leave:
+ 	skb_queue_head(&conn->rx_queue, skb);
+-	goto out;
++	return;
+ 
+ protocol_error:
+ 	if (rxrpc_abort_connection(conn, ret, abort_code) < 0)
+ 		goto requeue_and_leave;
+ 	rxrpc_free_skb(skb, rxrpc_skb_rx_freed);
+-	goto out;
++	return;
++}
++
++void rxrpc_process_connection(struct work_struct *work)
++{
++	struct rxrpc_connection *conn =
++		container_of(work, struct rxrpc_connection, processor);
++
++	rxrpc_see_connection(conn);
++
++	if (__rxrpc_use_local(conn->params.local)) {
++		rxrpc_do_process_connection(conn);
++		rxrpc_unuse_local(conn->params.local);
++	}
++
++	rxrpc_put_connection(conn);
++	_leave("");
++	return;
+ }
++
+diff --git a/net/rxrpc/conn_object.c b/net/rxrpc/conn_object.c
+index f338efd2880a..c4c4450891e0 100644
+--- a/net/rxrpc/conn_object.c
++++ b/net/rxrpc/conn_object.c
+@@ -226,9 +226,8 @@ void rxrpc_disconnect_call(struct rxrpc_call *call)
+ 	__rxrpc_disconnect_call(conn, call);
+ 	spin_unlock(&conn->channel_lock);
+ 
+-	call->conn = NULL;
++	set_bit(RXRPC_CALL_DISCONNECTED, &call->flags);
+ 	conn->idle_timestamp = jiffies;
+-	rxrpc_put_connection(conn);
+ }
+ 
+ /*
+diff --git a/net/rxrpc/input.c b/net/rxrpc/input.c
+index 2f91ab909191..d9beb28fc32f 100644
+--- a/net/rxrpc/input.c
++++ b/net/rxrpc/input.c
+@@ -612,10 +612,8 @@ ack:
+ 				  false, true,
+ 				  rxrpc_propose_ack_input_data);
+ 
+-	if (sp->hdr.seq == READ_ONCE(call->rx_hard_ack) + 1) {
+-		trace_rxrpc_notify_socket(call->debug_id, serial);
+-		rxrpc_notify_socket(call);
+-	}
++	trace_rxrpc_notify_socket(call->debug_id, serial);
++	rxrpc_notify_socket(call);
+ 
+ unlock:
+ 	spin_unlock(&call->input_lock);
+diff --git a/net/rxrpc/local_object.c b/net/rxrpc/local_object.c
+index 04f0976841a4..4c0087a48e87 100644
+--- a/net/rxrpc/local_object.c
++++ b/net/rxrpc/local_object.c
+@@ -368,11 +368,14 @@ void rxrpc_queue_local(struct rxrpc_local *local)
+ void rxrpc_put_local(struct rxrpc_local *local)
+ {
+ 	const void *here = __builtin_return_address(0);
++	unsigned int debug_id;
+ 	int n;
+ 
+ 	if (local) {
++		debug_id = local->debug_id;
++
+ 		n = atomic_dec_return(&local->usage);
+-		trace_rxrpc_local(local->debug_id, rxrpc_local_put, n, here);
++		trace_rxrpc_local(debug_id, rxrpc_local_put, n, here);
+ 
+ 		if (n == 0)
+ 			call_rcu(&local->rcu, rxrpc_local_rcu);
+@@ -384,14 +387,11 @@ void rxrpc_put_local(struct rxrpc_local *local)
+  */
+ struct rxrpc_local *rxrpc_use_local(struct rxrpc_local *local)
+ {
+-	unsigned int au;
+-
+ 	local = rxrpc_get_local_maybe(local);
+ 	if (!local)
+ 		return NULL;
+ 
+-	au = atomic_fetch_add_unless(&local->active_users, 1, 0);
+-	if (au == 0) {
++	if (!__rxrpc_use_local(local)) {
+ 		rxrpc_put_local(local);
+ 		return NULL;
+ 	}
+@@ -405,14 +405,11 @@ struct rxrpc_local *rxrpc_use_local(struct rxrpc_local *local)
+  */
+ void rxrpc_unuse_local(struct rxrpc_local *local)
+ {
+-	unsigned int au;
+-
+ 	if (local) {
+-		au = atomic_dec_return(&local->active_users);
+-		if (au == 0)
++		if (__rxrpc_unuse_local(local)) {
++			rxrpc_get_local(local);
+ 			rxrpc_queue_local(local);
+-		else
+-			rxrpc_put_local(local);
++		}
+ 	}
+ }
+ 
+@@ -469,7 +466,7 @@ static void rxrpc_local_processor(struct work_struct *work)
+ 
+ 	do {
+ 		again = false;
+-		if (atomic_read(&local->active_users) == 0) {
++		if (!__rxrpc_use_local(local)) {
+ 			rxrpc_local_destroyer(local);
+ 			break;
+ 		}
+@@ -483,6 +480,8 @@ static void rxrpc_local_processor(struct work_struct *work)
+ 			rxrpc_process_local_events(local);
+ 			again = true;
+ 		}
++
++		__rxrpc_unuse_local(local);
+ 	} while (again);
+ 
+ 	rxrpc_put_local(local);
+diff --git a/net/rxrpc/output.c b/net/rxrpc/output.c
+index 31e47cfb3e68..b0aa08e3796d 100644
+--- a/net/rxrpc/output.c
++++ b/net/rxrpc/output.c
+@@ -133,7 +133,7 @@ static size_t rxrpc_fill_out_ack(struct rxrpc_connection *conn,
+ int rxrpc_send_ack_packet(struct rxrpc_call *call, bool ping,
+ 			  rxrpc_serial_t *_serial)
+ {
+-	struct rxrpc_connection *conn = NULL;
++	struct rxrpc_connection *conn;
+ 	struct rxrpc_ack_buffer *pkt;
+ 	struct msghdr msg;
+ 	struct kvec iov[2];
+@@ -143,18 +143,14 @@ int rxrpc_send_ack_packet(struct rxrpc_call *call, bool ping,
+ 	int ret;
+ 	u8 reason;
+ 
+-	spin_lock_bh(&call->lock);
+-	if (call->conn)
+-		conn = rxrpc_get_connection_maybe(call->conn);
+-	spin_unlock_bh(&call->lock);
+-	if (!conn)
++	if (test_bit(RXRPC_CALL_DISCONNECTED, &call->flags))
+ 		return -ECONNRESET;
+ 
+ 	pkt = kzalloc(sizeof(*pkt), GFP_KERNEL);
+-	if (!pkt) {
+-		rxrpc_put_connection(conn);
++	if (!pkt)
+ 		return -ENOMEM;
+-	}
++
++	conn = call->conn;
+ 
+ 	msg.msg_name	= &call->peer->srx.transport;
+ 	msg.msg_namelen	= call->peer->srx.transport_len;
+@@ -249,7 +245,6 @@ int rxrpc_send_ack_packet(struct rxrpc_call *call, bool ping,
+ 	}
+ 
+ out:
+-	rxrpc_put_connection(conn);
+ 	kfree(pkt);
+ 	return ret;
+ }
+@@ -259,7 +254,7 @@ out:
+  */
+ int rxrpc_send_abort_packet(struct rxrpc_call *call)
+ {
+-	struct rxrpc_connection *conn = NULL;
++	struct rxrpc_connection *conn;
+ 	struct rxrpc_abort_buffer pkt;
+ 	struct msghdr msg;
+ 	struct kvec iov[1];
+@@ -276,13 +271,11 @@ int rxrpc_send_abort_packet(struct rxrpc_call *call)
+ 	    test_bit(RXRPC_CALL_TX_LAST, &call->flags))
+ 		return 0;
+ 
+-	spin_lock_bh(&call->lock);
+-	if (call->conn)
+-		conn = rxrpc_get_connection_maybe(call->conn);
+-	spin_unlock_bh(&call->lock);
+-	if (!conn)
++	if (test_bit(RXRPC_CALL_DISCONNECTED, &call->flags))
+ 		return -ECONNRESET;
+ 
++	conn = call->conn;
++
+ 	msg.msg_name	= &call->peer->srx.transport;
+ 	msg.msg_namelen	= call->peer->srx.transport_len;
+ 	msg.msg_control	= NULL;
+@@ -317,8 +310,6 @@ int rxrpc_send_abort_packet(struct rxrpc_call *call)
+ 		trace_rxrpc_tx_packet(call->debug_id, &pkt.whdr,
+ 				      rxrpc_tx_point_call_abort);
+ 	rxrpc_tx_backoff(call, ret);
+-
+-	rxrpc_put_connection(conn);
+ 	return ret;
+ }
+ 
+diff --git a/net/rxrpc/peer_event.c b/net/rxrpc/peer_event.c
+index 42582a9ff81d..85bdc31d3dbf 100644
+--- a/net/rxrpc/peer_event.c
++++ b/net/rxrpc/peer_event.c
+@@ -357,27 +357,31 @@ static void rxrpc_peer_keepalive_dispatch(struct rxrpc_net *rxnet,
+ 		if (!rxrpc_get_peer_maybe(peer))
+ 			continue;
+ 
+-		spin_unlock_bh(&rxnet->peer_hash_lock);
+-
+-		keepalive_at = peer->last_tx_at + RXRPC_KEEPALIVE_TIME;
+-		slot = keepalive_at - base;
+-		_debug("%02x peer %u t=%d {%pISp}",
+-		       cursor, peer->debug_id, slot, &peer->srx.transport);
++		if (__rxrpc_use_local(peer->local)) {
++			spin_unlock_bh(&rxnet->peer_hash_lock);
++
++			keepalive_at = peer->last_tx_at + RXRPC_KEEPALIVE_TIME;
++			slot = keepalive_at - base;
++			_debug("%02x peer %u t=%d {%pISp}",
++			       cursor, peer->debug_id, slot, &peer->srx.transport);
++
++			if (keepalive_at <= base ||
++			    keepalive_at > base + RXRPC_KEEPALIVE_TIME) {
++				rxrpc_send_keepalive(peer);
++				slot = RXRPC_KEEPALIVE_TIME;
++			}
+ 
+-		if (keepalive_at <= base ||
+-		    keepalive_at > base + RXRPC_KEEPALIVE_TIME) {
+-			rxrpc_send_keepalive(peer);
+-			slot = RXRPC_KEEPALIVE_TIME;
++			/* A transmission to this peer occurred since last we
++			 * examined it so put it into the appropriate future
++			 * bucket.
++			 */
++			slot += cursor;
++			slot &= mask;
++			spin_lock_bh(&rxnet->peer_hash_lock);
++			list_add_tail(&peer->keepalive_link,
++				      &rxnet->peer_keepalive[slot & mask]);
++			rxrpc_unuse_local(peer->local);
+ 		}
+-
+-		/* A transmission to this peer occurred since last we examined
+-		 * it so put it into the appropriate future bucket.
+-		 */
+-		slot += cursor;
+-		slot &= mask;
+-		spin_lock_bh(&rxnet->peer_hash_lock);
+-		list_add_tail(&peer->keepalive_link,
+-			      &rxnet->peer_keepalive[slot & mask]);
+ 		rxrpc_put_peer_locked(peer);
+ 	}
+ 
+diff --git a/net/sched/cls_rsvp.h b/net/sched/cls_rsvp.h
+index 6d30a291bcd2..eb1dd2afc5a1 100644
+--- a/net/sched/cls_rsvp.h
++++ b/net/sched/cls_rsvp.h
+@@ -466,10 +466,8 @@ static u32 gen_tunnel(struct rsvp_head *data)
+ 
+ static const struct nla_policy rsvp_policy[TCA_RSVP_MAX + 1] = {
+ 	[TCA_RSVP_CLASSID]	= { .type = NLA_U32 },
+-	[TCA_RSVP_DST]		= { .type = NLA_BINARY,
+-				    .len = RSVP_DST_LEN * sizeof(u32) },
+-	[TCA_RSVP_SRC]		= { .type = NLA_BINARY,
+-				    .len = RSVP_DST_LEN * sizeof(u32) },
++	[TCA_RSVP_DST]		= { .len = RSVP_DST_LEN * sizeof(u32) },
++	[TCA_RSVP_SRC]		= { .len = RSVP_DST_LEN * sizeof(u32) },
+ 	[TCA_RSVP_PINFO]	= { .len = sizeof(struct tc_rsvp_pinfo) },
+ };
+ 
+diff --git a/net/sched/cls_tcindex.c b/net/sched/cls_tcindex.c
+index edf27365f91c..db4b5d9ffaf7 100644
+--- a/net/sched/cls_tcindex.c
++++ b/net/sched/cls_tcindex.c
+@@ -333,12 +333,31 @@ tcindex_set_parms(struct net *net, struct tcf_proto *tp, unsigned long base,
+ 	cp->fall_through = p->fall_through;
+ 	cp->tp = tp;
+ 
++	if (tb[TCA_TCINDEX_HASH])
++		cp->hash = nla_get_u32(tb[TCA_TCINDEX_HASH]);
++
++	if (tb[TCA_TCINDEX_MASK])
++		cp->mask = nla_get_u16(tb[TCA_TCINDEX_MASK]);
++
++	if (tb[TCA_TCINDEX_SHIFT])
++		cp->shift = nla_get_u32(tb[TCA_TCINDEX_SHIFT]);
++
++	if (!cp->hash) {
++		/* Hash not specified, use perfect hash if the upper limit
++		 * of the hashing index is below the threshold.
++		 */
++		if ((cp->mask >> cp->shift) < PERFECT_HASH_THRESHOLD)
++			cp->hash = (cp->mask >> cp->shift) + 1;
++		else
++			cp->hash = DEFAULT_HASH_SIZE;
++	}
++
+ 	if (p->perfect) {
+ 		int i;
+ 
+ 		if (tcindex_alloc_perfect_hash(net, cp) < 0)
+ 			goto errout;
+-		for (i = 0; i < cp->hash; i++)
++		for (i = 0; i < min(cp->hash, p->hash); i++)
+ 			cp->perfect[i].res = p->perfect[i].res;
+ 		balloc = 1;
+ 	}
+@@ -346,19 +365,10 @@ tcindex_set_parms(struct net *net, struct tcf_proto *tp, unsigned long base,
+ 
+ 	err = tcindex_filter_result_init(&new_filter_result);
+ 	if (err < 0)
+-		goto errout1;
++		goto errout_alloc;
+ 	if (old_r)
+ 		cr = r->res;
+ 
+-	if (tb[TCA_TCINDEX_HASH])
+-		cp->hash = nla_get_u32(tb[TCA_TCINDEX_HASH]);
+-
+-	if (tb[TCA_TCINDEX_MASK])
+-		cp->mask = nla_get_u16(tb[TCA_TCINDEX_MASK]);
+-
+-	if (tb[TCA_TCINDEX_SHIFT])
+-		cp->shift = nla_get_u32(tb[TCA_TCINDEX_SHIFT]);
+-
+ 	err = -EBUSY;
+ 
+ 	/* Hash already allocated, make sure that we still meet the
+@@ -376,16 +386,6 @@ tcindex_set_parms(struct net *net, struct tcf_proto *tp, unsigned long base,
+ 	if (tb[TCA_TCINDEX_FALL_THROUGH])
+ 		cp->fall_through = nla_get_u32(tb[TCA_TCINDEX_FALL_THROUGH]);
+ 
+-	if (!cp->hash) {
+-		/* Hash not specified, use perfect hash if the upper limit
+-		 * of the hashing index is below the threshold.
+-		 */
+-		if ((cp->mask >> cp->shift) < PERFECT_HASH_THRESHOLD)
+-			cp->hash = (cp->mask >> cp->shift) + 1;
+-		else
+-			cp->hash = DEFAULT_HASH_SIZE;
+-	}
+-
+ 	if (!cp->perfect && !cp->h)
+ 		cp->alloc_hash = cp->hash;
+ 
+@@ -484,7 +484,6 @@ errout_alloc:
+ 		tcindex_free_perfect_hash(cp);
+ 	else if (balloc == 2)
+ 		kfree(cp->h);
+-errout1:
+ 	tcf_exts_destroy(&new_filter_result.exts);
+ errout:
+ 	kfree(cp);
+diff --git a/net/sunrpc/auth_gss/svcauth_gss.c b/net/sunrpc/auth_gss/svcauth_gss.c
+index 24c7a1e2bd34..68830e88b6e9 100644
+--- a/net/sunrpc/auth_gss/svcauth_gss.c
++++ b/net/sunrpc/auth_gss/svcauth_gss.c
+@@ -1224,6 +1224,7 @@ static int gss_proxy_save_rsc(struct cache_detail *cd,
+ 		dprintk("RPC:       No creds found!\n");
+ 		goto out;
+ 	} else {
++		struct timespec64 boot;
+ 
+ 		/* steal creds */
+ 		rsci.cred = ud->creds;
+@@ -1244,6 +1245,9 @@ static int gss_proxy_save_rsc(struct cache_detail *cd,
+ 						&expiry, GFP_KERNEL);
+ 		if (status)
+ 			goto out;
++
++		getboottime64(&boot);
++		expiry -= boot.tv_sec;
+ 	}
+ 
+ 	rsci.h.expiry_time = expiry;
+diff --git a/samples/bpf/Makefile b/samples/bpf/Makefile
+index 75d4b48601aa..85a6e8f5a75d 100644
+--- a/samples/bpf/Makefile
++++ b/samples/bpf/Makefile
+@@ -221,7 +221,7 @@ all:
+ 
+ clean:
+ 	$(MAKE) -C ../../ M=$(CURDIR) clean
+-	@rm -f *~
++	@find $(CURDIR) -type f -name '*~' -delete
+ 
+ $(LIBBPF): FORCE
+ # Fix up variables inherited from Kbuild that tools/ build system won't like
+diff --git a/scripts/find-unused-docs.sh b/scripts/find-unused-docs.sh
+index 3f46f8977dc4..ee6a50e33aba 100755
+--- a/scripts/find-unused-docs.sh
++++ b/scripts/find-unused-docs.sh
+@@ -54,7 +54,7 @@ for file in `find $1 -name '*.c'`; do
+ 	if [[ ${FILES_INCLUDED[$file]+_} ]]; then
+ 	continue;
+ 	fi
+-	str=$(scripts/kernel-doc -text -export "$file" 2>/dev/null)
++	str=$(scripts/kernel-doc -export "$file" 2>/dev/null)
+ 	if [[ -n "$str" ]]; then
+ 	echo "$file"
+ 	fi
+diff --git a/sound/drivers/dummy.c b/sound/drivers/dummy.c
+index 9af154db530a..b78cc8d86a8b 100644
+--- a/sound/drivers/dummy.c
++++ b/sound/drivers/dummy.c
+@@ -929,7 +929,7 @@ static void print_formats(struct snd_dummy *dummy,
+ {
+ 	int i;
+ 
+-	for (i = 0; i < SNDRV_PCM_FORMAT_LAST; i++) {
++	for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
+ 		if (dummy->pcm_hw.formats & (1ULL << i))
+ 			snd_iprintf(buffer, " %s", snd_pcm_format_name(i));
+ 	}
+diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
+index d63fea5d1c92..3ee5b7b9b595 100644
+--- a/sound/pci/hda/hda_intel.c
++++ b/sound/pci/hda/hda_intel.c
+@@ -2324,6 +2324,8 @@ static struct snd_pci_quirk power_save_blacklist[] = {
+ 	/* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
+ 	SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
+ 	/* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
++	SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0),
++	/* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
+ 	SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
+ 	/* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
+ 	/* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
+diff --git a/sound/usb/validate.c b/sound/usb/validate.c
+index 389e8657434a..5a3c4f7882b0 100644
+--- a/sound/usb/validate.c
++++ b/sound/usb/validate.c
+@@ -110,7 +110,7 @@ static bool validate_processing_unit(const void *p,
+ 	default:
+ 		if (v->type == UAC1_EXTENSION_UNIT)
+ 			return true; /* OK */
+-		switch (d->wProcessType) {
++		switch (le16_to_cpu(d->wProcessType)) {
+ 		case UAC_PROCESS_UP_DOWNMIX:
+ 		case UAC_PROCESS_DOLBY_PROLOGIC:
+ 			if (d->bLength < len + 1) /* bNrModes */
+@@ -125,7 +125,7 @@ static bool validate_processing_unit(const void *p,
+ 	case UAC_VERSION_2:
+ 		if (v->type == UAC2_EXTENSION_UNIT_V2)
+ 			return true; /* OK */
+-		switch (d->wProcessType) {
++		switch (le16_to_cpu(d->wProcessType)) {
+ 		case UAC2_PROCESS_UP_DOWNMIX:
+ 		case UAC2_PROCESS_DOLBY_PROLOCIC: /* SiC! */
+ 			if (d->bLength < len + 1) /* bNrModes */
+@@ -142,7 +142,7 @@ static bool validate_processing_unit(const void *p,
+ 			len += 2; /* wClusterDescrID */
+ 			break;
+ 		}
+-		switch (d->wProcessType) {
++		switch (le16_to_cpu(d->wProcessType)) {
+ 		case UAC3_PROCESS_UP_DOWNMIX:
+ 			if (d->bLength < len + 1) /* bNrModes */
+ 				return false;
+diff --git a/tools/kvm/kvm_stat/kvm_stat b/tools/kvm/kvm_stat/kvm_stat
+index ba7ee74ee533..f6ca0a216f3c 100755
+--- a/tools/kvm/kvm_stat/kvm_stat
++++ b/tools/kvm/kvm_stat/kvm_stat
+@@ -271,6 +271,7 @@ class ArchX86(Arch):
+     def __init__(self, exit_reasons):
+         self.sc_perf_evt_open = 298
+         self.ioctl_numbers = IOCTL_NUMBERS
++        self.exit_reason_field = 'exit_reason'
+         self.exit_reasons = exit_reasons
+ 
+     def debugfs_is_child(self, field):
+@@ -290,6 +291,7 @@ class ArchPPC(Arch):
+         # numbers depend on the wordsize.
+         char_ptr_size = ctypes.sizeof(ctypes.c_char_p)
+         self.ioctl_numbers['SET_FILTER'] = 0x80002406 | char_ptr_size << 16
++        self.exit_reason_field = 'exit_nr'
+         self.exit_reasons = {}
+ 
+     def debugfs_is_child(self, field):
+@@ -301,6 +303,7 @@ class ArchA64(Arch):
+     def __init__(self):
+         self.sc_perf_evt_open = 241
+         self.ioctl_numbers = IOCTL_NUMBERS
++        self.exit_reason_field = 'esr_ec'
+         self.exit_reasons = AARCH64_EXIT_REASONS
+ 
+     def debugfs_is_child(self, field):
+@@ -312,6 +315,7 @@ class ArchS390(Arch):
+     def __init__(self):
+         self.sc_perf_evt_open = 331
+         self.ioctl_numbers = IOCTL_NUMBERS
++        self.exit_reason_field = None
+         self.exit_reasons = None
+ 
+     def debugfs_is_child(self, field):
+@@ -542,8 +546,8 @@ class TracepointProvider(Provider):
+         """
+         filters = {}
+         filters['kvm_userspace_exit'] = ('reason', USERSPACE_EXIT_REASONS)
+-        if ARCH.exit_reasons:
+-            filters['kvm_exit'] = ('exit_reason', ARCH.exit_reasons)
++        if ARCH.exit_reason_field and ARCH.exit_reasons:
++            filters['kvm_exit'] = (ARCH.exit_reason_field, ARCH.exit_reasons)
+         return filters
+ 
+     def _get_available_fields(self):
+diff --git a/virt/kvm/arm/aarch32.c b/virt/kvm/arm/aarch32.c
+index 6880236974b8..d915548759a4 100644
+--- a/virt/kvm/arm/aarch32.c
++++ b/virt/kvm/arm/aarch32.c
+@@ -21,6 +21,7 @@
+  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+ 
++#include <linux/bits.h>
+ #include <linux/kvm_host.h>
+ #include <asm/kvm_emulate.h>
+ #include <asm/kvm_hyp.h>
+@@ -39,25 +40,115 @@ static const u8 return_offsets[8][2] = {
+ 	[7] = { 4, 4 },		/* FIQ, unused */
+ };
+ 
++/*
++ * When an exception is taken, most CPSR fields are left unchanged in the
++ * handler. However, some are explicitly overridden (e.g. M[4:0]).
++ *
++ * The SPSR/SPSR_ELx layouts differ, and the below is intended to work with
++ * either format. Note: SPSR.J bit doesn't exist in SPSR_ELx, but this bit was
++ * obsoleted by the ARMv7 virtualization extensions and is RES0.
++ *
++ * For the SPSR layout seen from AArch32, see:
++ * - ARM DDI 0406C.d, page B1-1148
++ * - ARM DDI 0487E.a, page G8-6264
++ *
++ * For the SPSR_ELx layout for AArch32 seen from AArch64, see:
++ * - ARM DDI 0487E.a, page C5-426
++ *
++ * Here we manipulate the fields in order of the AArch32 SPSR_ELx layout, from
++ * MSB to LSB.
++ */
++static unsigned long get_except32_cpsr(struct kvm_vcpu *vcpu, u32 mode)
++{
++	u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR);
++	unsigned long old, new;
++
++	old = *vcpu_cpsr(vcpu);
++	new = 0;
++
++	new |= (old & PSR_AA32_N_BIT);
++	new |= (old & PSR_AA32_Z_BIT);
++	new |= (old & PSR_AA32_C_BIT);
++	new |= (old & PSR_AA32_V_BIT);
++	new |= (old & PSR_AA32_Q_BIT);
++
++	// CPSR.IT[7:0] are set to zero upon any exception
++	// See ARM DDI 0487E.a, section G1.12.3
++	// See ARM DDI 0406C.d, section B1.8.3
++
++	new |= (old & PSR_AA32_DIT_BIT);
++
++	// CPSR.SSBS is set to SCTLR.DSSBS upon any exception
++	// See ARM DDI 0487E.a, page G8-6244
++	if (sctlr & BIT(31))
++		new |= PSR_AA32_SSBS_BIT;
++
++	// CPSR.PAN is unchanged unless SCTLR.SPAN == 0b0
++	// SCTLR.SPAN is RES1 when ARMv8.1-PAN is not implemented
++	// See ARM DDI 0487E.a, page G8-6246
++	new |= (old & PSR_AA32_PAN_BIT);
++	if (!(sctlr & BIT(23)))
++		new |= PSR_AA32_PAN_BIT;
++
++	// SS does not exist in AArch32, so ignore
++
++	// CPSR.IL is set to zero upon any exception
++	// See ARM DDI 0487E.a, page G1-5527
++
++	new |= (old & PSR_AA32_GE_MASK);
++
++	// CPSR.IT[7:0] are set to zero upon any exception
++	// See prior comment above
++
++	// CPSR.E is set to SCTLR.EE upon any exception
++	// See ARM DDI 0487E.a, page G8-6245
++	// See ARM DDI 0406C.d, page B4-1701
++	if (sctlr & BIT(25))
++		new |= PSR_AA32_E_BIT;
++
++	// CPSR.A is unchanged upon an exception to Undefined, Supervisor
++	// CPSR.A is set upon an exception to other modes
++	// See ARM DDI 0487E.a, pages G1-5515 to G1-5516
++	// See ARM DDI 0406C.d, page B1-1182
++	new |= (old & PSR_AA32_A_BIT);
++	if (mode != PSR_AA32_MODE_UND && mode != PSR_AA32_MODE_SVC)
++		new |= PSR_AA32_A_BIT;
++
++	// CPSR.I is set upon any exception
++	// See ARM DDI 0487E.a, pages G1-5515 to G1-5516
++	// See ARM DDI 0406C.d, page B1-1182
++	new |= PSR_AA32_I_BIT;
++
++	// CPSR.F is set upon an exception to FIQ
++	// CPSR.F is unchanged upon an exception to other modes
++	// See ARM DDI 0487E.a, pages G1-5515 to G1-5516
++	// See ARM DDI 0406C.d, page B1-1182
++	new |= (old & PSR_AA32_F_BIT);
++	if (mode == PSR_AA32_MODE_FIQ)
++		new |= PSR_AA32_F_BIT;
++
++	// CPSR.T is set to SCTLR.TE upon any exception
++	// See ARM DDI 0487E.a, page G8-5514
++	// See ARM DDI 0406C.d, page B1-1181
++	if (sctlr & BIT(30))
++		new |= PSR_AA32_T_BIT;
++
++	new |= mode;
++
++	return new;
++}
++
+ static void prepare_fault32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset)
+ {
+-	unsigned long cpsr;
+-	unsigned long new_spsr_value = *vcpu_cpsr(vcpu);
+-	bool is_thumb = (new_spsr_value & PSR_AA32_T_BIT);
++	unsigned long spsr = *vcpu_cpsr(vcpu);
++	bool is_thumb = (spsr & PSR_AA32_T_BIT);
+ 	u32 return_offset = return_offsets[vect_offset >> 2][is_thumb];
+ 	u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR);
+ 
+-	cpsr = mode | PSR_AA32_I_BIT;
+-
+-	if (sctlr & (1 << 30))
+-		cpsr |= PSR_AA32_T_BIT;
+-	if (sctlr & (1 << 25))
+-		cpsr |= PSR_AA32_E_BIT;
+-
+-	*vcpu_cpsr(vcpu) = cpsr;
++	*vcpu_cpsr(vcpu) = get_except32_cpsr(vcpu, mode);
+ 
+ 	/* Note: These now point to the banked copies */
+-	vcpu_write_spsr(vcpu, new_spsr_value);
++	vcpu_write_spsr(vcpu, host_spsr_to_spsr32(spsr));
+ 	*vcpu_reg32(vcpu, 14) = *vcpu_pc(vcpu) + return_offset;
+ 
+ 	/* Branch to exception vector */
+@@ -95,7 +186,7 @@ static void inject_abt32(struct kvm_vcpu *vcpu, bool is_pabt,
+ 		fsr = &vcpu_cp15(vcpu, c5_DFSR);
+ 	}
+ 
+-	prepare_fault32(vcpu, PSR_AA32_MODE_ABT | PSR_AA32_A_BIT, vect_offset);
++	prepare_fault32(vcpu, PSR_AA32_MODE_ABT, vect_offset);
+ 
+ 	*far = addr;
+ 
+diff --git a/virt/kvm/arm/mmio.c b/virt/kvm/arm/mmio.c
+index 3caee91bca08..878e0edb2e1b 100644
+--- a/virt/kvm/arm/mmio.c
++++ b/virt/kvm/arm/mmio.c
+@@ -117,6 +117,9 @@ int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
+ 			data = (data ^ mask) - mask;
+ 		}
+ 
++		if (!vcpu->arch.mmio_decode.sixty_four)
++			data = data & 0xffffffff;
++
+ 		trace_kvm_mmio(KVM_TRACE_MMIO_READ, len, run->mmio.phys_addr,
+ 			       &data);
+ 		data = vcpu_data_host_to_guest(vcpu, data, len);
+@@ -137,6 +140,7 @@ static int decode_hsr(struct kvm_vcpu *vcpu, bool *is_write, int *len)
+ 	unsigned long rt;
+ 	int access_size;
+ 	bool sign_extend;
++	bool sixty_four;
+ 
+ 	if (kvm_vcpu_dabt_iss1tw(vcpu)) {
+ 		/* page table accesses IO mem: tell guest to fix its TTBR */
+@@ -150,11 +154,13 @@ static int decode_hsr(struct kvm_vcpu *vcpu, bool *is_write, int *len)
+ 
+ 	*is_write = kvm_vcpu_dabt_iswrite(vcpu);
+ 	sign_extend = kvm_vcpu_dabt_issext(vcpu);
++	sixty_four = kvm_vcpu_dabt_issf(vcpu);
+ 	rt = kvm_vcpu_dabt_get_rd(vcpu);
+ 
+ 	*len = access_size;
+ 	vcpu->arch.mmio_decode.sign_extend = sign_extend;
+ 	vcpu->arch.mmio_decode.rt = rt;
++	vcpu->arch.mmio_decode.sixty_four = sixty_four;
+ 
+ 	return 0;
+ }
+diff --git a/virt/kvm/async_pf.c b/virt/kvm/async_pf.c
+index 23c2519c5b32..c9861c2315e8 100644
+--- a/virt/kvm/async_pf.c
++++ b/virt/kvm/async_pf.c
+@@ -76,7 +76,7 @@ static void async_pf_execute(struct work_struct *work)
+ 	struct mm_struct *mm = apf->mm;
+ 	struct kvm_vcpu *vcpu = apf->vcpu;
+ 	unsigned long addr = apf->addr;
+-	gva_t gva = apf->gva;
++	gpa_t cr2_or_gpa = apf->cr2_or_gpa;
+ 	int locked = 1;
+ 
+ 	might_sleep();
+@@ -104,7 +104,7 @@ static void async_pf_execute(struct work_struct *work)
+ 	 * this point
+ 	 */
+ 
+-	trace_kvm_async_pf_completed(addr, gva);
++	trace_kvm_async_pf_completed(addr, cr2_or_gpa);
+ 
+ 	if (swq_has_sleeper(&vcpu->wq))
+ 		swake_up_one(&vcpu->wq);
+@@ -177,8 +177,8 @@ void kvm_check_async_pf_completion(struct kvm_vcpu *vcpu)
+ 	}
+ }
+ 
+-int kvm_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, unsigned long hva,
+-		       struct kvm_arch_async_pf *arch)
++int kvm_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
++		       unsigned long hva, struct kvm_arch_async_pf *arch)
+ {
+ 	struct kvm_async_pf *work;
+ 
+@@ -197,7 +197,7 @@ int kvm_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, unsigned long hva,
+ 
+ 	work->wakeup_all = false;
+ 	work->vcpu = vcpu;
+-	work->gva = gva;
++	work->cr2_or_gpa = cr2_or_gpa;
+ 	work->addr = hva;
+ 	work->arch = *arch;
+ 	work->mm = current->mm;
+diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c
+index 9502b1a44232..beec19fcf8cd 100644
+--- a/virt/kvm/kvm_main.c
++++ b/virt/kvm/kvm_main.c
+@@ -1294,14 +1294,14 @@ bool kvm_is_visible_gfn(struct kvm *kvm, gfn_t gfn)
+ }
+ EXPORT_SYMBOL_GPL(kvm_is_visible_gfn);
+ 
+-unsigned long kvm_host_page_size(struct kvm *kvm, gfn_t gfn)
++unsigned long kvm_host_page_size(struct kvm_vcpu *vcpu, gfn_t gfn)
+ {
+ 	struct vm_area_struct *vma;
+ 	unsigned long addr, size;
+ 
+ 	size = PAGE_SIZE;
+ 
+-	addr = gfn_to_hva(kvm, gfn);
++	addr = kvm_vcpu_gfn_to_hva_prot(vcpu, gfn, NULL);
+ 	if (kvm_is_error_hva(addr))
+ 		return PAGE_SIZE;
+