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idella4 13/12/06 14:13:04 |
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Added: xen-CVE-2013-6885-XSA-82.patch |
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Log: |
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revbumps; add sec XSA-82.patch, remove old |
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(Portage version: 2.2.0/cvs/Linux x86_64, signed Manifest commit with key 0xB8072B0D) |
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Revision Changes Path |
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1.1 app-emulation/xen/files/xen-CVE-2013-6885-XSA-82.patch |
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file : http://sources.gentoo.org/viewvc.cgi/gentoo-x86/app-emulation/xen/files/xen-CVE-2013-6885-XSA-82.patch?rev=1.1&view=markup |
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plain: http://sources.gentoo.org/viewvc.cgi/gentoo-x86/app-emulation/xen/files/xen-CVE-2013-6885-XSA-82.patch?rev=1.1&content-type=text/plain |
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Index: xen-CVE-2013-6885-XSA-82.patch |
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=================================================================== |
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http://seclists.org/oss-sec/2013/q4/att-385/xsa82.patch |
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x86/AMD: work around erratum 793 |
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The recommendation is to set a bit in an MSR - do this if the firmware |
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didn't, considering that otherwise we expose ourselves to a guest |
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induced DoS. |
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|
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This is CVE-2013-6885 / XSA-82. |
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Signed-off-by: Jan Beulich <jbeulich@××××.com> |
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Acked-by: Suravee Suthikulpanit <suravee.suthikulpanit@×××.com> |
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|
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--- a/xen/arch/x86/cpu/amd.c |
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+++ b/xen/arch/x86/cpu/amd.c |
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@@ -476,6 +476,20 @@ static void __devinit init_amd(struct cp |
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"*** Pass \"allow_unsafe\" if you're trusting" |
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" all your (PV) guest kernels. ***\n"); |
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|
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+ if (c->x86 == 0x16 && c->x86_model <= 0xf) { |
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+ rdmsrl(MSR_AMD64_LS_CFG, value); |
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+ if (!(value & (1 << 15))) { |
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+ static bool_t warned; |
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+ |
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+ if (c == &boot_cpu_data || opt_cpu_info || |
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+ !test_and_set_bool(warned)) |
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+ printk(KERN_WARNING |
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+ "CPU%u: Applying workaround for erratum 793\n", |
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+ smp_processor_id()); |
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+ wrmsrl(MSR_AMD64_LS_CFG, value | (1 << 15)); |
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+ } |
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+ } |
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+ |
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/* AMD CPUs do not support SYSENTER outside of legacy mode. */ |
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clear_bit(X86_FEATURE_SEP, c->x86_capability); |
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|
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--- a/xen/include/asm-x86/msr-index.h |
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+++ b/xen/include/asm-x86/msr-index.h |
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@@ -213,6 +213,7 @@ |
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|
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/* AMD64 MSRs */ |
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#define MSR_AMD64_NB_CFG 0xc001001f |
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+#define MSR_AMD64_LS_CFG 0xc0011020 |
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#define MSR_AMD64_IC_CFG 0xc0011021 |
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#define MSR_AMD64_DC_CFG 0xc0011022 |
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#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46 |
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