Gentoo Archives: gentoo-commits

From: Mike Pagano <mpagano@g.o>
To: gentoo-commits@l.g.o
Subject: [gentoo-commits] proj/linux-patches:4.14 commit in: /
Date: Wed, 30 May 2018 11:43:04
Message-Id: 1527680570.ab22674da00d00aff48540c57c2979d195b2d87f.mpagano@gentoo
1 commit: ab22674da00d00aff48540c57c2979d195b2d87f
2 Author: Mike Pagano <mpagano <AT> gentoo <DOT> org>
3 AuthorDate: Wed May 30 11:42:50 2018 +0000
4 Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org>
5 CommitDate: Wed May 30 11:42:50 2018 +0000
6 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=ab22674d
7
8 Linux patches 4.14.45 and 4.14.46
9
10 0000_README | 8 +
11 1044_linux-4.14.45.patch | 16573 +++++++++++++++++++++++++++++++++++++++++++++
12 1045_linux-4.14.46.patch | 850 +++
13 3 files changed, 17431 insertions(+)
14
15 diff --git a/0000_README b/0000_README
16 index f2b1b86..63dde0e 100644
17 --- a/0000_README
18 +++ b/0000_README
19 @@ -219,6 +219,14 @@ Patch: 1043_linux-4.14.44.patch
20 From: http://www.kernel.org
21 Desc: Linux 4.14.44
22
23 +Patch: 1044_linux-4.14.45.patch
24 +From: http://www.kernel.org
25 +Desc: Linux 4.14.45
26 +
27 +Patch: 1045_linux-4.14.46.patch
28 +From: http://www.kernel.org
29 +Desc: Linux 4.14.46
30 +
31 Patch: 1500_XATTR_USER_PREFIX.patch
32 From: https://bugs.gentoo.org/show_bug.cgi?id=470644
33 Desc: Support for namespace user.pax.* on tmpfs.
34
35 diff --git a/1044_linux-4.14.45.patch b/1044_linux-4.14.45.patch
36 new file mode 100644
37 index 0000000..878e473
38 --- /dev/null
39 +++ b/1044_linux-4.14.45.patch
40 @@ -0,0 +1,16573 @@
41 +diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
42 +index 7eda08eb8a1e..a2b6a8a565a7 100644
43 +--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
44 ++++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
45 +@@ -20,6 +20,7 @@ Required properties :
46 + - "allwinner,sun50i-a64-ccu"
47 + - "allwinner,sun50i-a64-r-ccu"
48 + - "allwinner,sun50i-h5-ccu"
49 ++ - "allwinner,sun50i-h6-ccu"
50 + - "nextthing,gr8-ccu"
51 +
52 + - reg: Must contain the registers base address and length
53 +@@ -31,6 +32,9 @@ Required properties :
54 + - #clock-cells : must contain 1
55 + - #reset-cells : must contain 1
56 +
57 ++For the main CCU on H6, one more clock is needed:
58 ++- "iosc": the SoC's internal frequency oscillator
59 ++
60 + For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:
61 + - "pll-periph": the SoC's peripheral PLL from the main CCU
62 + - "iosc": the SoC's internal frequency oscillator
63 +diff --git a/Documentation/devicetree/bindings/dma/mv-xor-v2.txt b/Documentation/devicetree/bindings/dma/mv-xor-v2.txt
64 +index 217a90eaabe7..9c38bbe7e6d7 100644
65 +--- a/Documentation/devicetree/bindings/dma/mv-xor-v2.txt
66 ++++ b/Documentation/devicetree/bindings/dma/mv-xor-v2.txt
67 +@@ -11,7 +11,11 @@ Required properties:
68 + interrupts.
69 +
70 + Optional properties:
71 +-- clocks: Optional reference to the clock used by the XOR engine.
72 ++- clocks: Optional reference to the clocks used by the XOR engine.
73 ++- clock-names: mandatory if there is a second clock, in this case the
74 ++ name must be "core" for the first clock and "reg" for the second
75 ++ one
76 ++
77 +
78 + Example:
79 +
80 +diff --git a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
81 +index 47284f85ec80..c3f9826692bc 100644
82 +--- a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
83 ++++ b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
84 +@@ -20,7 +20,8 @@ Required subnode-properties:
85 + gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0,
86 + i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0,
87 + spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart1grp0,
88 +- uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0
89 ++ uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0,
90 ++ uart5nocts
91 + cpuclkout: cpuclkoutgrp0
92 + udlclkout: udlclkoutgrp0
93 + i2c1: i2c1grp0
94 +@@ -37,7 +38,7 @@ Required subnode-properties:
95 + uart2: uart2grp0, uart2grp1
96 + uart3: uart3grp0
97 + uart4: uart4grp0
98 +- uart5: uart5grp0
99 ++ uart5: uart5grp0, uart5nocts
100 + nand: nandgrp0
101 + sdio0: sdio0grp0
102 + sdio1: sdio1grp0
103 +diff --git a/Makefile b/Makefile
104 +index 787cf6605209..f3ea74e7a516 100644
105 +--- a/Makefile
106 ++++ b/Makefile
107 +@@ -1,7 +1,7 @@
108 + # SPDX-License-Identifier: GPL-2.0
109 + VERSION = 4
110 + PATCHLEVEL = 14
111 +-SUBLEVEL = 44
112 ++SUBLEVEL = 45
113 + EXTRAVERSION =
114 + NAME = Petit Gorille
115 +
116 +diff --git a/arch/alpha/include/asm/xchg.h b/arch/alpha/include/asm/xchg.h
117 +index 68dfb3cb7145..02a7c2fa6106 100644
118 +--- a/arch/alpha/include/asm/xchg.h
119 ++++ b/arch/alpha/include/asm/xchg.h
120 +@@ -12,6 +12,10 @@
121 + * Atomic exchange.
122 + * Since it can be used to implement critical sections
123 + * it must clobber "memory" (also for interrupts in UP).
124 ++ *
125 ++ * The leading and the trailing memory barriers guarantee that these
126 ++ * operations are fully ordered.
127 ++ *
128 + */
129 +
130 + static inline unsigned long
131 +@@ -19,6 +23,7 @@ ____xchg(_u8, volatile char *m, unsigned long val)
132 + {
133 + unsigned long ret, tmp, addr64;
134 +
135 ++ smp_mb();
136 + __asm__ __volatile__(
137 + " andnot %4,7,%3\n"
138 + " insbl %1,%4,%1\n"
139 +@@ -43,6 +48,7 @@ ____xchg(_u16, volatile short *m, unsigned long val)
140 + {
141 + unsigned long ret, tmp, addr64;
142 +
143 ++ smp_mb();
144 + __asm__ __volatile__(
145 + " andnot %4,7,%3\n"
146 + " inswl %1,%4,%1\n"
147 +@@ -67,6 +73,7 @@ ____xchg(_u32, volatile int *m, unsigned long val)
148 + {
149 + unsigned long dummy;
150 +
151 ++ smp_mb();
152 + __asm__ __volatile__(
153 + "1: ldl_l %0,%4\n"
154 + " bis $31,%3,%1\n"
155 +@@ -87,6 +94,7 @@ ____xchg(_u64, volatile long *m, unsigned long val)
156 + {
157 + unsigned long dummy;
158 +
159 ++ smp_mb();
160 + __asm__ __volatile__(
161 + "1: ldq_l %0,%4\n"
162 + " bis $31,%3,%1\n"
163 +@@ -128,10 +136,12 @@ ____xchg(, volatile void *ptr, unsigned long x, int size)
164 + * store NEW in MEM. Return the initial value in MEM. Success is
165 + * indicated by comparing RETURN with OLD.
166 + *
167 +- * The memory barrier should be placed in SMP only when we actually
168 +- * make the change. If we don't change anything (so if the returned
169 +- * prev is equal to old) then we aren't acquiring anything new and
170 +- * we don't need any memory barrier as far I can tell.
171 ++ * The leading and the trailing memory barriers guarantee that these
172 ++ * operations are fully ordered.
173 ++ *
174 ++ * The trailing memory barrier is placed in SMP unconditionally, in
175 ++ * order to guarantee that dependency ordering is preserved when a
176 ++ * dependency is headed by an unsuccessful operation.
177 + */
178 +
179 + static inline unsigned long
180 +@@ -139,6 +149,7 @@ ____cmpxchg(_u8, volatile char *m, unsigned char old, unsigned char new)
181 + {
182 + unsigned long prev, tmp, cmp, addr64;
183 +
184 ++ smp_mb();
185 + __asm__ __volatile__(
186 + " andnot %5,7,%4\n"
187 + " insbl %1,%5,%1\n"
188 +@@ -150,8 +161,8 @@ ____cmpxchg(_u8, volatile char *m, unsigned char old, unsigned char new)
189 + " or %1,%2,%2\n"
190 + " stq_c %2,0(%4)\n"
191 + " beq %2,3f\n"
192 +- __ASM__MB
193 + "2:\n"
194 ++ __ASM__MB
195 + ".subsection 2\n"
196 + "3: br 1b\n"
197 + ".previous"
198 +@@ -166,6 +177,7 @@ ____cmpxchg(_u16, volatile short *m, unsigned short old, unsigned short new)
199 + {
200 + unsigned long prev, tmp, cmp, addr64;
201 +
202 ++ smp_mb();
203 + __asm__ __volatile__(
204 + " andnot %5,7,%4\n"
205 + " inswl %1,%5,%1\n"
206 +@@ -177,8 +189,8 @@ ____cmpxchg(_u16, volatile short *m, unsigned short old, unsigned short new)
207 + " or %1,%2,%2\n"
208 + " stq_c %2,0(%4)\n"
209 + " beq %2,3f\n"
210 +- __ASM__MB
211 + "2:\n"
212 ++ __ASM__MB
213 + ".subsection 2\n"
214 + "3: br 1b\n"
215 + ".previous"
216 +@@ -193,6 +205,7 @@ ____cmpxchg(_u32, volatile int *m, int old, int new)
217 + {
218 + unsigned long prev, cmp;
219 +
220 ++ smp_mb();
221 + __asm__ __volatile__(
222 + "1: ldl_l %0,%5\n"
223 + " cmpeq %0,%3,%1\n"
224 +@@ -200,8 +213,8 @@ ____cmpxchg(_u32, volatile int *m, int old, int new)
225 + " mov %4,%1\n"
226 + " stl_c %1,%2\n"
227 + " beq %1,3f\n"
228 +- __ASM__MB
229 + "2:\n"
230 ++ __ASM__MB
231 + ".subsection 2\n"
232 + "3: br 1b\n"
233 + ".previous"
234 +@@ -216,6 +229,7 @@ ____cmpxchg(_u64, volatile long *m, unsigned long old, unsigned long new)
235 + {
236 + unsigned long prev, cmp;
237 +
238 ++ smp_mb();
239 + __asm__ __volatile__(
240 + "1: ldq_l %0,%5\n"
241 + " cmpeq %0,%3,%1\n"
242 +@@ -223,8 +237,8 @@ ____cmpxchg(_u64, volatile long *m, unsigned long old, unsigned long new)
243 + " mov %4,%1\n"
244 + " stq_c %1,%2\n"
245 + " beq %1,3f\n"
246 +- __ASM__MB
247 + "2:\n"
248 ++ __ASM__MB
249 + ".subsection 2\n"
250 + "3: br 1b\n"
251 + ".previous"
252 +diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
253 +index c84e67fdea09..4383313b064a 100644
254 +--- a/arch/arc/Kconfig
255 ++++ b/arch/arc/Kconfig
256 +@@ -487,7 +487,6 @@ config ARC_CURR_IN_REG
257 +
258 + config ARC_EMUL_UNALIGNED
259 + bool "Emulate unaligned memory access (userspace only)"
260 +- default N
261 + select SYSCTL_ARCH_UNALIGN_NO_WARN
262 + select SYSCTL_ARCH_UNALIGN_ALLOW
263 + depends on ISA_ARCOMPACT
264 +diff --git a/arch/arc/include/asm/bug.h b/arch/arc/include/asm/bug.h
265 +index ea022d47896c..21ec82466d62 100644
266 +--- a/arch/arc/include/asm/bug.h
267 ++++ b/arch/arc/include/asm/bug.h
268 +@@ -23,7 +23,8 @@ void die(const char *str, struct pt_regs *regs, unsigned long address);
269 +
270 + #define BUG() do { \
271 + pr_warn("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
272 +- dump_stack(); \
273 ++ barrier_before_unreachable(); \
274 ++ __builtin_trap(); \
275 + } while (0)
276 +
277 + #define HAVE_ARCH_BUG
278 +diff --git a/arch/arc/kernel/mcip.c b/arch/arc/kernel/mcip.c
279 +index f61a52b01625..5fe84e481654 100644
280 +--- a/arch/arc/kernel/mcip.c
281 ++++ b/arch/arc/kernel/mcip.c
282 +@@ -22,10 +22,79 @@ static DEFINE_RAW_SPINLOCK(mcip_lock);
283 +
284 + static char smp_cpuinfo_buf[128];
285 +
286 ++/*
287 ++ * Set mask to halt GFRC if any online core in SMP cluster is halted.
288 ++ * Only works for ARC HS v3.0+, on earlier versions has no effect.
289 ++ */
290 ++static void mcip_update_gfrc_halt_mask(int cpu)
291 ++{
292 ++ struct bcr_generic gfrc;
293 ++ unsigned long flags;
294 ++ u32 gfrc_halt_mask;
295 ++
296 ++ READ_BCR(ARC_REG_GFRC_BUILD, gfrc);
297 ++
298 ++ /*
299 ++ * CMD_GFRC_SET_CORE and CMD_GFRC_READ_CORE commands were added in
300 ++ * GFRC 0x3 version.
301 ++ */
302 ++ if (gfrc.ver < 0x3)
303 ++ return;
304 ++
305 ++ raw_spin_lock_irqsave(&mcip_lock, flags);
306 ++
307 ++ __mcip_cmd(CMD_GFRC_READ_CORE, 0);
308 ++ gfrc_halt_mask = read_aux_reg(ARC_REG_MCIP_READBACK);
309 ++ gfrc_halt_mask |= BIT(cpu);
310 ++ __mcip_cmd_data(CMD_GFRC_SET_CORE, 0, gfrc_halt_mask);
311 ++
312 ++ raw_spin_unlock_irqrestore(&mcip_lock, flags);
313 ++}
314 ++
315 ++static void mcip_update_debug_halt_mask(int cpu)
316 ++{
317 ++ u32 mcip_mask = 0;
318 ++ unsigned long flags;
319 ++
320 ++ raw_spin_lock_irqsave(&mcip_lock, flags);
321 ++
322 ++ /*
323 ++ * mcip_mask is same for CMD_DEBUG_SET_SELECT and CMD_DEBUG_SET_MASK
324 ++ * commands. So read it once instead of reading both CMD_DEBUG_READ_MASK
325 ++ * and CMD_DEBUG_READ_SELECT.
326 ++ */
327 ++ __mcip_cmd(CMD_DEBUG_READ_SELECT, 0);
328 ++ mcip_mask = read_aux_reg(ARC_REG_MCIP_READBACK);
329 ++
330 ++ mcip_mask |= BIT(cpu);
331 ++
332 ++ __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, mcip_mask);
333 ++ /*
334 ++ * Parameter specified halt cause:
335 ++ * STATUS32[H]/actionpoint/breakpoint/self-halt
336 ++ * We choose all of them (0xF).
337 ++ */
338 ++ __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xF, mcip_mask);
339 ++
340 ++ raw_spin_unlock_irqrestore(&mcip_lock, flags);
341 ++}
342 ++
343 + static void mcip_setup_per_cpu(int cpu)
344 + {
345 ++ struct mcip_bcr mp;
346 ++
347 ++ READ_BCR(ARC_REG_MCIP_BCR, mp);
348 ++
349 + smp_ipi_irq_setup(cpu, IPI_IRQ);
350 + smp_ipi_irq_setup(cpu, SOFTIRQ_IRQ);
351 ++
352 ++ /* Update GFRC halt mask as new CPU came online */
353 ++ if (mp.gfrc)
354 ++ mcip_update_gfrc_halt_mask(cpu);
355 ++
356 ++ /* Update MCIP debug mask as new CPU came online */
357 ++ if (mp.dbg)
358 ++ mcip_update_debug_halt_mask(cpu);
359 + }
360 +
361 + static void mcip_ipi_send(int cpu)
362 +@@ -101,11 +170,6 @@ static void mcip_probe_n_setup(void)
363 + IS_AVAIL1(mp.gfrc, "GFRC"));
364 +
365 + cpuinfo_arc700[0].extn.gfrc = mp.gfrc;
366 +-
367 +- if (mp.dbg) {
368 +- __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf);
369 +- __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
370 +- }
371 + }
372 +
373 + struct plat_smp_ops plat_smp_ops = {
374 +diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
375 +index 6df9d94a9537..115eecc0d9a4 100644
376 +--- a/arch/arc/kernel/smp.c
377 ++++ b/arch/arc/kernel/smp.c
378 +@@ -24,6 +24,7 @@
379 + #include <linux/reboot.h>
380 + #include <linux/irqdomain.h>
381 + #include <linux/export.h>
382 ++#include <linux/of_fdt.h>
383 +
384 + #include <asm/processor.h>
385 + #include <asm/setup.h>
386 +@@ -47,6 +48,42 @@ void __init smp_prepare_boot_cpu(void)
387 + {
388 + }
389 +
390 ++static int __init arc_get_cpu_map(const char *name, struct cpumask *cpumask)
391 ++{
392 ++ unsigned long dt_root = of_get_flat_dt_root();
393 ++ const char *buf;
394 ++
395 ++ buf = of_get_flat_dt_prop(dt_root, name, NULL);
396 ++ if (!buf)
397 ++ return -EINVAL;
398 ++
399 ++ if (cpulist_parse(buf, cpumask))
400 ++ return -EINVAL;
401 ++
402 ++ return 0;
403 ++}
404 ++
405 ++/*
406 ++ * Read from DeviceTree and setup cpu possible mask. If there is no
407 ++ * "possible-cpus" property in DeviceTree pretend all [0..NR_CPUS-1] exist.
408 ++ */
409 ++static void __init arc_init_cpu_possible(void)
410 ++{
411 ++ struct cpumask cpumask;
412 ++
413 ++ if (arc_get_cpu_map("possible-cpus", &cpumask)) {
414 ++ pr_warn("Failed to get possible-cpus from dtb, pretending all %u cpus exist\n",
415 ++ NR_CPUS);
416 ++
417 ++ cpumask_setall(&cpumask);
418 ++ }
419 ++
420 ++ if (!cpumask_test_cpu(0, &cpumask))
421 ++ panic("Master cpu (cpu[0]) is missed in cpu possible mask!");
422 ++
423 ++ init_cpu_possible(&cpumask);
424 ++}
425 ++
426 + /*
427 + * Called from setup_arch() before calling setup_processor()
428 + *
429 +@@ -58,10 +95,7 @@ void __init smp_prepare_boot_cpu(void)
430 + */
431 + void __init smp_init_cpus(void)
432 + {
433 +- unsigned int i;
434 +-
435 +- for (i = 0; i < NR_CPUS; i++)
436 +- set_cpu_possible(i, true);
437 ++ arc_init_cpu_possible();
438 +
439 + if (plat_smp_ops.init_early_smp)
440 + plat_smp_ops.init_early_smp();
441 +@@ -70,16 +104,12 @@ void __init smp_init_cpus(void)
442 + /* called from init ( ) => process 1 */
443 + void __init smp_prepare_cpus(unsigned int max_cpus)
444 + {
445 +- int i;
446 +-
447 + /*
448 + * if platform didn't set the present map already, do it now
449 + * boot cpu is set to present already by init/main.c
450 + */
451 +- if (num_present_cpus() <= 1) {
452 +- for (i = 0; i < max_cpus; i++)
453 +- set_cpu_present(i, true);
454 +- }
455 ++ if (num_present_cpus() <= 1)
456 ++ init_cpu_present(cpu_possible_mask);
457 + }
458 +
459 + void __init smp_cpus_done(unsigned int max_cpus)
460 +diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/at91-tse850-3.dts
461 +index 5f29010cdbd8..4ef80a703eda 100644
462 +--- a/arch/arm/boot/dts/at91-tse850-3.dts
463 ++++ b/arch/arm/boot/dts/at91-tse850-3.dts
464 +@@ -245,7 +245,7 @@
465 + };
466 +
467 + eeprom@50 {
468 +- compatible = "nxp,24c02", "atmel,24c02";
469 ++ compatible = "nxp,se97b", "atmel,24c02";
470 + reg = <0x50>;
471 + pagesize = <16>;
472 + };
473 +diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi
474 +index 61e158003509..168c002f0ca0 100644
475 +--- a/arch/arm/boot/dts/bcm2836.dtsi
476 ++++ b/arch/arm/boot/dts/bcm2836.dtsi
477 +@@ -9,7 +9,7 @@
478 + <0x40000000 0x40000000 0x00001000>;
479 + dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
480 +
481 +- local_intc: local_intc {
482 ++ local_intc: local_intc@40000000 {
483 + compatible = "brcm,bcm2836-l1-intc";
484 + reg = <0x40000000 0x100>;
485 + interrupt-controller;
486 +diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi
487 +index bc1cca5cf43c..d5d058a568c3 100644
488 +--- a/arch/arm/boot/dts/bcm2837.dtsi
489 ++++ b/arch/arm/boot/dts/bcm2837.dtsi
490 +@@ -8,7 +8,7 @@
491 + <0x40000000 0x40000000 0x00001000>;
492 + dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
493 +
494 +- local_intc: local_intc {
495 ++ local_intc: local_intc@40000000 {
496 + compatible = "brcm,bcm2836-l1-intc";
497 + reg = <0x40000000 0x100>;
498 + interrupt-controller;
499 +diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
500 +index 013431e3d7c3..4745e3c7806b 100644
501 +--- a/arch/arm/boot/dts/bcm283x.dtsi
502 ++++ b/arch/arm/boot/dts/bcm283x.dtsi
503 +@@ -251,7 +251,7 @@
504 +
505 + jtag_gpio4: jtag_gpio4 {
506 + brcm,pins = <4 5 6 12 13>;
507 +- brcm,function = <BCM2835_FSEL_ALT4>;
508 ++ brcm,function = <BCM2835_FSEL_ALT5>;
509 + };
510 + jtag_gpio22: jtag_gpio22 {
511 + brcm,pins = <22 23 24 25 26 27>;
512 +@@ -396,8 +396,8 @@
513 +
514 + i2s: i2s@7e203000 {
515 + compatible = "brcm,bcm2835-i2s";
516 +- reg = <0x7e203000 0x20>,
517 +- <0x7e101098 0x02>;
518 ++ reg = <0x7e203000 0x24>;
519 ++ clocks = <&clocks BCM2835_CLOCK_PCM>;
520 +
521 + dmas = <&dma 2>,
522 + <&dma 3>;
523 +diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
524 +index 6a44b8021702..f0e2008f7490 100644
525 +--- a/arch/arm/boot/dts/bcm958625hr.dts
526 ++++ b/arch/arm/boot/dts/bcm958625hr.dts
527 +@@ -49,7 +49,7 @@
528 +
529 + memory {
530 + device_type = "memory";
531 +- reg = <0x60000000 0x80000000>;
532 ++ reg = <0x60000000 0x20000000>;
533 + };
534 +
535 + gpio-restart {
536 +diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts
537 +index 41c9132eb550..64363f75c01a 100644
538 +--- a/arch/arm/boot/dts/dra71-evm.dts
539 ++++ b/arch/arm/boot/dts/dra71-evm.dts
540 +@@ -24,13 +24,13 @@
541 +
542 + regulator-name = "vddshv8";
543 + regulator-min-microvolt = <1800000>;
544 +- regulator-max-microvolt = <3000000>;
545 ++ regulator-max-microvolt = <3300000>;
546 + regulator-boot-on;
547 + vin-supply = <&evm_5v0>;
548 +
549 + gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
550 + states = <1800000 0x0
551 +- 3000000 0x1>;
552 ++ 3300000 0x1>;
553 + };
554 +
555 + evm_1v8_sw: fixedregulator-evm_1v8 {
556 +diff --git a/arch/arm/boot/dts/imx6dl-icore-rqs.dts b/arch/arm/boot/dts/imx6dl-icore-rqs.dts
557 +index cf42c2f5cdc7..1281bc39b7ab 100644
558 +--- a/arch/arm/boot/dts/imx6dl-icore-rqs.dts
559 ++++ b/arch/arm/boot/dts/imx6dl-icore-rqs.dts
560 +@@ -42,7 +42,7 @@
561 +
562 + /dts-v1/;
563 +
564 +-#include "imx6q.dtsi"
565 ++#include "imx6dl.dtsi"
566 + #include "imx6qdl-icore-rqs.dtsi"
567 +
568 + / {
569 +diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
570 +index ae45af1ad062..3cc1fb9ce441 100644
571 +--- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
572 ++++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
573 +@@ -213,37 +213,37 @@
574 + &iomuxc {
575 + pinctrl_enet1: enet1grp {
576 + fsl,pins = <
577 +- MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
578 +- MX7D_PAD_SD2_WP__ENET1_MDC 0x3
579 +- MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
580 +- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
581 +- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
582 +- MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
583 +- MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
584 +- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
585 +- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
586 +- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
587 +- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
588 +- MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
589 +- MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
590 +- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
591 ++ MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x30
592 ++ MX7D_PAD_SD2_WP__ENET1_MDC 0x30
593 ++ MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x11
594 ++ MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x11
595 ++ MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x11
596 ++ MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x11
597 ++ MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x11
598 ++ MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x11
599 ++ MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x11
600 ++ MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11
601 ++ MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11
602 ++ MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11
603 ++ MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x11
604 ++ MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
605 + >;
606 + };
607 +
608 + pinctrl_enet2: enet2grp {
609 + fsl,pins = <
610 +- MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
611 +- MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
612 +- MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
613 +- MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
614 +- MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
615 +- MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
616 +- MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
617 +- MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
618 +- MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
619 +- MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
620 +- MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
621 +- MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
622 ++ MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x11
623 ++ MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x11
624 ++ MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x11
625 ++ MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x11
626 ++ MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x11
627 ++ MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x11
628 ++ MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x11
629 ++ MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x11
630 ++ MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x11
631 ++ MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x11
632 ++ MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x11
633 ++ MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x11
634 + >;
635 + };
636 +
637 +diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
638 +index 95da5cb9d37a..b6ebe79261c6 100644
639 +--- a/arch/arm/boot/dts/r8a7791-porter.dts
640 ++++ b/arch/arm/boot/dts/r8a7791-porter.dts
641 +@@ -427,7 +427,7 @@
642 + "dclkin.0", "dclkin.1";
643 +
644 + ports {
645 +- port@1 {
646 ++ port@0 {
647 + endpoint {
648 + remote-endpoint = <&adv7511_in>;
649 + };
650 +diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
651 +index 4916c65e0ace..5c0a76493d22 100644
652 +--- a/arch/arm/boot/dts/rk3036.dtsi
653 ++++ b/arch/arm/boot/dts/rk3036.dtsi
654 +@@ -261,7 +261,7 @@
655 + max-frequency = <37500000>;
656 + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
657 + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
658 +- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
659 ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
660 + fifo-depth = <0x100>;
661 + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
662 + resets = <&cru SRST_SDIO>;
663 +@@ -279,7 +279,7 @@
664 + max-frequency = <37500000>;
665 + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
666 + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
667 +- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
668 ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
669 + default-sample-phase = <158>;
670 + disable-wp;
671 + dmas = <&pdma 12>;
672 +diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
673 +index 06814421eed2..f59f7cc62be6 100644
674 +--- a/arch/arm/boot/dts/rk322x.dtsi
675 ++++ b/arch/arm/boot/dts/rk322x.dtsi
676 +@@ -600,7 +600,7 @@
677 + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
678 + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
679 + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
680 +- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
681 ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
682 + fifo-depth = <0x100>;
683 + pinctrl-names = "default";
684 + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
685 +@@ -613,7 +613,7 @@
686 + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
687 + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
688 + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
689 +- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
690 ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
691 + fifo-depth = <0x100>;
692 + pinctrl-names = "default";
693 + pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
694 +@@ -628,7 +628,7 @@
695 + max-frequency = <37500000>;
696 + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
697 + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
698 +- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
699 ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
700 + bus-width = <8>;
701 + default-sample-phase = <158>;
702 + fifo-depth = <0x100>;
703 +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
704 +index 356ed1e62452..f7a951afd281 100644
705 +--- a/arch/arm/boot/dts/rk3288.dtsi
706 ++++ b/arch/arm/boot/dts/rk3288.dtsi
707 +@@ -927,6 +927,7 @@
708 + i2s: i2s@ff890000 {
709 + compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
710 + reg = <0x0 0xff890000 0x0 0x10000>;
711 ++ #sound-dai-cells = <0>;
712 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
713 + #address-cells = <1>;
714 + #size-cells = <0>;
715 +@@ -1122,6 +1123,7 @@
716 + compatible = "rockchip,rk3288-dw-hdmi";
717 + reg = <0x0 0xff980000 0x0 0x20000>;
718 + reg-io-width = <4>;
719 ++ #sound-dai-cells = <0>;
720 + rockchip,grf = <&grf>;
721 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
722 + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
723 +diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
724 +index 7e24dc8e82d4..8d9f42a422cb 100644
725 +--- a/arch/arm/boot/dts/socfpga.dtsi
726 ++++ b/arch/arm/boot/dts/socfpga.dtsi
727 +@@ -827,7 +827,7 @@
728 + timer@fffec600 {
729 + compatible = "arm,cortex-a9-twd-timer";
730 + reg = <0xfffec600 0x100>;
731 +- interrupts = <1 13 0xf04>;
732 ++ interrupts = <1 13 0xf01>;
733 + clocks = <&mpu_periph_clk>;
734 + };
735 +
736 +diff --git a/arch/arm/include/asm/vdso.h b/arch/arm/include/asm/vdso.h
737 +index 9c99e817535e..5b85889f82ee 100644
738 +--- a/arch/arm/include/asm/vdso.h
739 ++++ b/arch/arm/include/asm/vdso.h
740 +@@ -12,8 +12,6 @@ struct mm_struct;
741 +
742 + void arm_install_vdso(struct mm_struct *mm, unsigned long addr);
743 +
744 +-extern char vdso_start, vdso_end;
745 +-
746 + extern unsigned int vdso_total_pages;
747 +
748 + #else /* CONFIG_VDSO */
749 +diff --git a/arch/arm/kernel/vdso.c b/arch/arm/kernel/vdso.c
750 +index a4d6dc0f2427..f4dd7f9663c1 100644
751 +--- a/arch/arm/kernel/vdso.c
752 ++++ b/arch/arm/kernel/vdso.c
753 +@@ -39,6 +39,8 @@
754 +
755 + static struct page **vdso_text_pagelist;
756 +
757 ++extern char vdso_start[], vdso_end[];
758 ++
759 + /* Total number of pages needed for the data and text portions of the VDSO. */
760 + unsigned int vdso_total_pages __ro_after_init;
761 +
762 +@@ -197,13 +199,13 @@ static int __init vdso_init(void)
763 + unsigned int text_pages;
764 + int i;
765 +
766 +- if (memcmp(&vdso_start, "\177ELF", 4)) {
767 ++ if (memcmp(vdso_start, "\177ELF", 4)) {
768 + pr_err("VDSO is not a valid ELF object!\n");
769 + return -ENOEXEC;
770 + }
771 +
772 +- text_pages = (&vdso_end - &vdso_start) >> PAGE_SHIFT;
773 +- pr_debug("vdso: %i text pages at base %p\n", text_pages, &vdso_start);
774 ++ text_pages = (vdso_end - vdso_start) >> PAGE_SHIFT;
775 ++ pr_debug("vdso: %i text pages at base %p\n", text_pages, vdso_start);
776 +
777 + /* Allocate the VDSO text pagelist */
778 + vdso_text_pagelist = kcalloc(text_pages, sizeof(struct page *),
779 +@@ -218,7 +220,7 @@ static int __init vdso_init(void)
780 + for (i = 0; i < text_pages; i++) {
781 + struct page *page;
782 +
783 +- page = virt_to_page(&vdso_start + i * PAGE_SIZE);
784 ++ page = virt_to_page(vdso_start + i * PAGE_SIZE);
785 + vdso_text_pagelist[i] = page;
786 + }
787 +
788 +@@ -229,7 +231,7 @@ static int __init vdso_init(void)
789 +
790 + cntvct_ok = cntvct_functional();
791 +
792 +- patch_vdso(&vdso_start);
793 ++ patch_vdso(vdso_start);
794 +
795 + return 0;
796 + }
797 +diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
798 +index a3e78074be70..62eb7d668890 100644
799 +--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
800 ++++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
801 +@@ -127,8 +127,8 @@ static struct gpiod_lookup_table mmc_gpios_table = {
802 + .dev_id = "da830-mmc.0",
803 + .table = {
804 + /* CD: gpio3_12: gpio60: chip 1 contains gpio range 32-63*/
805 +- GPIO_LOOKUP("davinci_gpio.1", 28, "cd", GPIO_ACTIVE_LOW),
806 +- GPIO_LOOKUP("davinci_gpio.1", 29, "wp", GPIO_ACTIVE_LOW),
807 ++ GPIO_LOOKUP("davinci_gpio.0", 28, "cd", GPIO_ACTIVE_LOW),
808 ++ GPIO_LOOKUP("davinci_gpio.0", 29, "wp", GPIO_ACTIVE_LOW),
809 + },
810 + };
811 +
812 +diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
813 +index 43e3e188f521..fa512413a471 100644
814 +--- a/arch/arm/mach-omap1/clock.c
815 ++++ b/arch/arm/mach-omap1/clock.c
816 +@@ -1011,17 +1011,17 @@ static int clk_debugfs_register_one(struct clk *c)
817 + return -ENOMEM;
818 + c->dent = d;
819 +
820 +- d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
821 ++ d = debugfs_create_u8("usecount", S_IRUGO, c->dent, &c->usecount);
822 + if (!d) {
823 + err = -ENOMEM;
824 + goto err_out;
825 + }
826 +- d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
827 ++ d = debugfs_create_ulong("rate", S_IRUGO, c->dent, &c->rate);
828 + if (!d) {
829 + err = -ENOMEM;
830 + goto err_out;
831 + }
832 +- d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
833 ++ d = debugfs_create_x8("flags", S_IRUGO, c->dent, &c->flags);
834 + if (!d) {
835 + err = -ENOMEM;
836 + goto err_out;
837 +diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
838 +index 4bb6751864a5..fc5fb776a710 100644
839 +--- a/arch/arm/mach-omap2/omap-wakeupgen.c
840 ++++ b/arch/arm/mach-omap2/omap-wakeupgen.c
841 +@@ -299,8 +299,6 @@ static void irq_save_context(void)
842 + if (soc_is_dra7xx())
843 + return;
844 +
845 +- if (!sar_base)
846 +- sar_base = omap4_get_sar_ram_base();
847 + if (wakeupgen_ops && wakeupgen_ops->save_context)
848 + wakeupgen_ops->save_context();
849 + }
850 +@@ -598,6 +596,8 @@ static int __init wakeupgen_init(struct device_node *node,
851 + irq_hotplug_init();
852 + irq_pm_init();
853 +
854 ++ sar_base = omap4_get_sar_ram_base();
855 ++
856 + return 0;
857 + }
858 + IRQCHIP_DECLARE(ti_wakeupgen, "ti,omap4-wugen-mpu", wakeupgen_init);
859 +diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
860 +index 366158a54fcd..6f68576e5695 100644
861 +--- a/arch/arm/mach-omap2/pm.c
862 ++++ b/arch/arm/mach-omap2/pm.c
863 +@@ -186,7 +186,7 @@ static void omap_pm_end(void)
864 + cpu_idle_poll_ctrl(false);
865 + }
866 +
867 +-static void omap_pm_finish(void)
868 ++static void omap_pm_wake(void)
869 + {
870 + if (soc_is_omap34xx())
871 + omap_prcm_irq_complete();
872 +@@ -196,7 +196,7 @@ static const struct platform_suspend_ops omap_pm_ops = {
873 + .begin = omap_pm_begin,
874 + .end = omap_pm_end,
875 + .enter = omap_pm_enter,
876 +- .finish = omap_pm_finish,
877 ++ .wake = omap_pm_wake,
878 + .valid = suspend_valid_only_mem,
879 + };
880 +
881 +diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
882 +index ece09c9461f7..d61fbd7a2840 100644
883 +--- a/arch/arm/mach-omap2/timer.c
884 ++++ b/arch/arm/mach-omap2/timer.c
885 +@@ -156,12 +156,6 @@ static struct clock_event_device clockevent_gpt = {
886 + .tick_resume = omap2_gp_timer_shutdown,
887 + };
888 +
889 +-static struct property device_disabled = {
890 +- .name = "status",
891 +- .length = sizeof("disabled"),
892 +- .value = "disabled",
893 +-};
894 +-
895 + static const struct of_device_id omap_timer_match[] __initconst = {
896 + { .compatible = "ti,omap2420-timer", },
897 + { .compatible = "ti,omap3430-timer", },
898 +@@ -203,8 +197,17 @@ static struct device_node * __init omap_get_timer_dt(const struct of_device_id *
899 + of_get_property(np, "ti,timer-secure", NULL)))
900 + continue;
901 +
902 +- if (!of_device_is_compatible(np, "ti,omap-counter32k"))
903 +- of_add_property(np, &device_disabled);
904 ++ if (!of_device_is_compatible(np, "ti,omap-counter32k")) {
905 ++ struct property *prop;
906 ++
907 ++ prop = kzalloc(sizeof(*prop), GFP_KERNEL);
908 ++ if (!prop)
909 ++ return NULL;
910 ++ prop->name = "status";
911 ++ prop->value = "disabled";
912 ++ prop->length = strlen(prop->value);
913 ++ of_add_property(np, prop);
914 ++ }
915 + return np;
916 + }
917 +
918 +diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
919 +index 2a7bb6ccdcb7..a810f4dd34b1 100644
920 +--- a/arch/arm/mach-orion5x/Kconfig
921 ++++ b/arch/arm/mach-orion5x/Kconfig
922 +@@ -58,7 +58,6 @@ config MACH_KUROBOX_PRO
923 +
924 + config MACH_DNS323
925 + bool "D-Link DNS-323"
926 +- select GENERIC_NET_UTILS
927 + select I2C_BOARDINFO if I2C
928 + help
929 + Say 'Y' here if you want your kernel to support the
930 +@@ -66,7 +65,6 @@ config MACH_DNS323
931 +
932 + config MACH_TS209
933 + bool "QNAP TS-109/TS-209"
934 +- select GENERIC_NET_UTILS
935 + help
936 + Say 'Y' here if you want your kernel to support the
937 + QNAP TS-109/TS-209 platform.
938 +@@ -101,7 +99,6 @@ config MACH_LINKSTATION_LS_HGL
939 +
940 + config MACH_TS409
941 + bool "QNAP TS-409"
942 +- select GENERIC_NET_UTILS
943 + help
944 + Say 'Y' here if you want your kernel to support the
945 + QNAP TS-409 platform.
946 +diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
947 +index cd483bfb5ca8..d13344b2ddcd 100644
948 +--- a/arch/arm/mach-orion5x/dns323-setup.c
949 ++++ b/arch/arm/mach-orion5x/dns323-setup.c
950 +@@ -173,10 +173,42 @@ static struct mv643xx_eth_platform_data dns323_eth_data = {
951 + .phy_addr = MV643XX_ETH_PHY_ADDR(8),
952 + };
953 +
954 ++/* dns323_parse_hex_*() taken from tsx09-common.c; should a common copy of these
955 ++ * functions be kept somewhere?
956 ++ */
957 ++static int __init dns323_parse_hex_nibble(char n)
958 ++{
959 ++ if (n >= '0' && n <= '9')
960 ++ return n - '0';
961 ++
962 ++ if (n >= 'A' && n <= 'F')
963 ++ return n - 'A' + 10;
964 ++
965 ++ if (n >= 'a' && n <= 'f')
966 ++ return n - 'a' + 10;
967 ++
968 ++ return -1;
969 ++}
970 ++
971 ++static int __init dns323_parse_hex_byte(const char *b)
972 ++{
973 ++ int hi;
974 ++ int lo;
975 ++
976 ++ hi = dns323_parse_hex_nibble(b[0]);
977 ++ lo = dns323_parse_hex_nibble(b[1]);
978 ++
979 ++ if (hi < 0 || lo < 0)
980 ++ return -1;
981 ++
982 ++ return (hi << 4) | lo;
983 ++}
984 ++
985 + static int __init dns323_read_mac_addr(void)
986 + {
987 + u_int8_t addr[6];
988 +- void __iomem *mac_page;
989 ++ int i;
990 ++ char *mac_page;
991 +
992 + /* MAC address is stored as a regular ol' string in /dev/mtdblock4
993 + * (0x007d0000-0x00800000) starting at offset 196480 (0x2ff80).
994 +@@ -185,8 +217,23 @@ static int __init dns323_read_mac_addr(void)
995 + if (!mac_page)
996 + return -ENOMEM;
997 +
998 +- if (!mac_pton((__force const char *) mac_page, addr))
999 +- goto error_fail;
1000 ++ /* Sanity check the string we're looking at */
1001 ++ for (i = 0; i < 5; i++) {
1002 ++ if (*(mac_page + (i * 3) + 2) != ':') {
1003 ++ goto error_fail;
1004 ++ }
1005 ++ }
1006 ++
1007 ++ for (i = 0; i < 6; i++) {
1008 ++ int byte;
1009 ++
1010 ++ byte = dns323_parse_hex_byte(mac_page + (i * 3));
1011 ++ if (byte < 0) {
1012 ++ goto error_fail;
1013 ++ }
1014 ++
1015 ++ addr[i] = byte;
1016 ++ }
1017 +
1018 + iounmap(mac_page);
1019 + printk("DNS-323: Found ethernet MAC address: %pM\n", addr);
1020 +diff --git a/arch/arm/mach-orion5x/tsx09-common.c b/arch/arm/mach-orion5x/tsx09-common.c
1021 +index 89774985d380..905d4f2dd0b8 100644
1022 +--- a/arch/arm/mach-orion5x/tsx09-common.c
1023 ++++ b/arch/arm/mach-orion5x/tsx09-common.c
1024 +@@ -53,12 +53,53 @@ struct mv643xx_eth_platform_data qnap_tsx09_eth_data = {
1025 + .phy_addr = MV643XX_ETH_PHY_ADDR(8),
1026 + };
1027 +
1028 ++static int __init qnap_tsx09_parse_hex_nibble(char n)
1029 ++{
1030 ++ if (n >= '0' && n <= '9')
1031 ++ return n - '0';
1032 ++
1033 ++ if (n >= 'A' && n <= 'F')
1034 ++ return n - 'A' + 10;
1035 ++
1036 ++ if (n >= 'a' && n <= 'f')
1037 ++ return n - 'a' + 10;
1038 ++
1039 ++ return -1;
1040 ++}
1041 ++
1042 ++static int __init qnap_tsx09_parse_hex_byte(const char *b)
1043 ++{
1044 ++ int hi;
1045 ++ int lo;
1046 ++
1047 ++ hi = qnap_tsx09_parse_hex_nibble(b[0]);
1048 ++ lo = qnap_tsx09_parse_hex_nibble(b[1]);
1049 ++
1050 ++ if (hi < 0 || lo < 0)
1051 ++ return -1;
1052 ++
1053 ++ return (hi << 4) | lo;
1054 ++}
1055 ++
1056 + static int __init qnap_tsx09_check_mac_addr(const char *addr_str)
1057 + {
1058 + u_int8_t addr[6];
1059 ++ int i;
1060 +
1061 +- if (!mac_pton(addr_str, addr))
1062 +- return -1;
1063 ++ for (i = 0; i < 6; i++) {
1064 ++ int byte;
1065 ++
1066 ++ /*
1067 ++ * Enforce "xx:xx:xx:xx:xx:xx\n" format.
1068 ++ */
1069 ++ if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n'))
1070 ++ return -1;
1071 ++
1072 ++ byte = qnap_tsx09_parse_hex_byte(addr_str + (i * 3));
1073 ++ if (byte < 0)
1074 ++ return -1;
1075 ++ addr[i] = byte;
1076 ++ }
1077 +
1078 + printk(KERN_INFO "tsx09: found ethernet mac address %pM\n", addr);
1079 +
1080 +@@ -77,12 +118,12 @@ void __init qnap_tsx09_find_mac_addr(u32 mem_base, u32 size)
1081 + unsigned long addr;
1082 +
1083 + for (addr = mem_base; addr < (mem_base + size); addr += 1024) {
1084 +- void __iomem *nor_page;
1085 ++ char *nor_page;
1086 + int ret = 0;
1087 +
1088 + nor_page = ioremap(addr, 1024);
1089 + if (nor_page != NULL) {
1090 +- ret = qnap_tsx09_check_mac_addr((__force const char *)nor_page);
1091 ++ ret = qnap_tsx09_check_mac_addr(nor_page);
1092 + iounmap(nor_page);
1093 + }
1094 +
1095 +diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
1096 +index 7a327bd32521..ebef8aacea83 100644
1097 +--- a/arch/arm/plat-omap/dmtimer.c
1098 ++++ b/arch/arm/plat-omap/dmtimer.c
1099 +@@ -890,11 +890,8 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
1100 + timer->irq = irq->start;
1101 + timer->pdev = pdev;
1102 +
1103 +- /* Skip pm_runtime_enable for OMAP1 */
1104 +- if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
1105 +- pm_runtime_enable(dev);
1106 +- pm_runtime_irq_safe(dev);
1107 +- }
1108 ++ pm_runtime_enable(dev);
1109 ++ pm_runtime_irq_safe(dev);
1110 +
1111 + if (!timer->reserved) {
1112 + ret = pm_runtime_get_sync(dev);
1113 +diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi
1114 +index 4220fbdcb24a..ff5c4c47b22b 100644
1115 +--- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi
1116 ++++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi
1117 +@@ -98,7 +98,7 @@
1118 + clock-output-names = "clk125mhz";
1119 + };
1120 +
1121 +- pci {
1122 ++ pcie@30000000 {
1123 + compatible = "pci-host-ecam-generic";
1124 + device_type = "pci";
1125 + #interrupt-cells = <1>;
1126 +@@ -118,6 +118,7 @@
1127 + ranges =
1128 + <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000
1129 + 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>;
1130 ++ bus-range = <0 0xff>;
1131 + interrupt-map-mask = <0 0 0 7>;
1132 + interrupt-map =
1133 + /* addr pin ic icaddr icintr */
1134 +diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
1135 +index 887b61c872dd..ab00be277c6f 100644
1136 +--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
1137 ++++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
1138 +@@ -484,8 +484,8 @@
1139 + blsp2_spi5: spi@075ba000{
1140 + compatible = "qcom,spi-qup-v2.2.1";
1141 + reg = <0x075ba000 0x600>;
1142 +- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1143 +- clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
1144 ++ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1145 ++ clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
1146 + <&gcc GCC_BLSP2_AHB_CLK>;
1147 + clock-names = "core", "iface";
1148 + pinctrl-names = "default", "sleep";
1149 +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
1150 +index d4f80786e7c2..28257724a56e 100644
1151 +--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
1152 ++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
1153 +@@ -136,11 +136,12 @@
1154 + phy-mode = "rgmii";
1155 + pinctrl-names = "default";
1156 + pinctrl-0 = <&rgmiim1_pins>;
1157 ++ snps,force_thresh_dma_mode;
1158 + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
1159 + snps,reset-active-low;
1160 + snps,reset-delays-us = <0 10000 50000>;
1161 +- tx_delay = <0x26>;
1162 +- rx_delay = <0x11>;
1163 ++ tx_delay = <0x24>;
1164 ++ rx_delay = <0x18>;
1165 + status = "okay";
1166 + };
1167 +
1168 +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
1169 +index 41d61840fb99..d70e409e2b0c 100644
1170 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
1171 ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
1172 +@@ -683,7 +683,7 @@
1173 + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1174 + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
1175 + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1176 +- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
1177 ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1178 + fifo-depth = <0x100>;
1179 + status = "disabled";
1180 + };
1181 +@@ -694,7 +694,7 @@
1182 + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1183 + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
1184 + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1185 +- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
1186 ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1187 + fifo-depth = <0x100>;
1188 + status = "disabled";
1189 + };
1190 +@@ -705,7 +705,7 @@
1191 + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1192 + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
1193 + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1194 +- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
1195 ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1196 + fifo-depth = <0x100>;
1197 + status = "disabled";
1198 + };
1199 +diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
1200 +index 1070c8264c13..2313aea0e69e 100644
1201 +--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
1202 ++++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
1203 +@@ -257,7 +257,7 @@
1204 + max-frequency = <150000000>;
1205 + clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
1206 + <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
1207 +- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
1208 ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1209 + fifo-depth = <0x100>;
1210 + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1211 + resets = <&cru SRST_SDIO0>;
1212 +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
1213 +index 199a5118b20d..264a6bb60c53 100644
1214 +--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
1215 ++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
1216 +@@ -406,8 +406,9 @@
1217 + wlan_pd_n: wlan-pd-n {
1218 + compatible = "regulator-fixed";
1219 + regulator-name = "wlan_pd_n";
1220 ++ pinctrl-names = "default";
1221 ++ pinctrl-0 = <&wlan_module_reset_l>;
1222 +
1223 +- /* Note the wlan_module_reset_l pinctrl */
1224 + enable-active-high;
1225 + gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
1226 +
1227 +@@ -940,12 +941,6 @@ ap_i2c_audio: &i2c8 {
1228 + pinctrl-0 = <
1229 + &ap_pwroff /* AP will auto-assert this when in S3 */
1230 + &clk_32k /* This pin is always 32k on gru boards */
1231 +-
1232 +- /*
1233 +- * We want this driven low ASAP; firmware should help us, but
1234 +- * we can help ourselves too.
1235 +- */
1236 +- &wlan_module_reset_l
1237 + >;
1238 +
1239 + pcfg_output_low: pcfg-output-low {
1240 +@@ -1125,12 +1120,7 @@ ap_i2c_audio: &i2c8 {
1241 + };
1242 +
1243 + wlan_module_reset_l: wlan-module-reset-l {
1244 +- /*
1245 +- * We want this driven low ASAP (As {Soon,Strongly} As
1246 +- * Possible), to avoid leakage through the powered-down
1247 +- * WiFi.
1248 +- */
1249 +- rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_output_low>;
1250 ++ rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>;
1251 + };
1252 +
1253 + bt_host_wake_l: bt-host-wake-l {
1254 +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
1255 +index 0f873c897d0d..ce592a4c0c4c 100644
1256 +--- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
1257 ++++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
1258 +@@ -457,7 +457,7 @@
1259 + assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
1260 + assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
1261 + assigned-clock-rates = <100000000>;
1262 +- ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
1263 ++ ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
1264 + num-lanes = <4>;
1265 + pinctrl-names = "default";
1266 + pinctrl-0 = <&pcie_clkreqn_cpm>;
1267 +diff --git a/arch/arm64/include/asm/atomic_lse.h b/arch/arm64/include/asm/atomic_lse.h
1268 +index 9ef0797380cb..f9b0b09153e0 100644
1269 +--- a/arch/arm64/include/asm/atomic_lse.h
1270 ++++ b/arch/arm64/include/asm/atomic_lse.h
1271 +@@ -117,7 +117,7 @@ static inline void atomic_and(int i, atomic_t *v)
1272 + /* LSE atomics */
1273 + " mvn %w[i], %w[i]\n"
1274 + " stclr %w[i], %[v]")
1275 +- : [i] "+r" (w0), [v] "+Q" (v->counter)
1276 ++ : [i] "+&r" (w0), [v] "+Q" (v->counter)
1277 + : "r" (x1)
1278 + : __LL_SC_CLOBBERS);
1279 + }
1280 +@@ -135,7 +135,7 @@ static inline int atomic_fetch_and##name(int i, atomic_t *v) \
1281 + /* LSE atomics */ \
1282 + " mvn %w[i], %w[i]\n" \
1283 + " ldclr" #mb " %w[i], %w[i], %[v]") \
1284 +- : [i] "+r" (w0), [v] "+Q" (v->counter) \
1285 ++ : [i] "+&r" (w0), [v] "+Q" (v->counter) \
1286 + : "r" (x1) \
1287 + : __LL_SC_CLOBBERS, ##cl); \
1288 + \
1289 +@@ -161,7 +161,7 @@ static inline void atomic_sub(int i, atomic_t *v)
1290 + /* LSE atomics */
1291 + " neg %w[i], %w[i]\n"
1292 + " stadd %w[i], %[v]")
1293 +- : [i] "+r" (w0), [v] "+Q" (v->counter)
1294 ++ : [i] "+&r" (w0), [v] "+Q" (v->counter)
1295 + : "r" (x1)
1296 + : __LL_SC_CLOBBERS);
1297 + }
1298 +@@ -180,7 +180,7 @@ static inline int atomic_sub_return##name(int i, atomic_t *v) \
1299 + " neg %w[i], %w[i]\n" \
1300 + " ldadd" #mb " %w[i], w30, %[v]\n" \
1301 + " add %w[i], %w[i], w30") \
1302 +- : [i] "+r" (w0), [v] "+Q" (v->counter) \
1303 ++ : [i] "+&r" (w0), [v] "+Q" (v->counter) \
1304 + : "r" (x1) \
1305 + : __LL_SC_CLOBBERS , ##cl); \
1306 + \
1307 +@@ -207,7 +207,7 @@ static inline int atomic_fetch_sub##name(int i, atomic_t *v) \
1308 + /* LSE atomics */ \
1309 + " neg %w[i], %w[i]\n" \
1310 + " ldadd" #mb " %w[i], %w[i], %[v]") \
1311 +- : [i] "+r" (w0), [v] "+Q" (v->counter) \
1312 ++ : [i] "+&r" (w0), [v] "+Q" (v->counter) \
1313 + : "r" (x1) \
1314 + : __LL_SC_CLOBBERS, ##cl); \
1315 + \
1316 +@@ -314,7 +314,7 @@ static inline void atomic64_and(long i, atomic64_t *v)
1317 + /* LSE atomics */
1318 + " mvn %[i], %[i]\n"
1319 + " stclr %[i], %[v]")
1320 +- : [i] "+r" (x0), [v] "+Q" (v->counter)
1321 ++ : [i] "+&r" (x0), [v] "+Q" (v->counter)
1322 + : "r" (x1)
1323 + : __LL_SC_CLOBBERS);
1324 + }
1325 +@@ -332,7 +332,7 @@ static inline long atomic64_fetch_and##name(long i, atomic64_t *v) \
1326 + /* LSE atomics */ \
1327 + " mvn %[i], %[i]\n" \
1328 + " ldclr" #mb " %[i], %[i], %[v]") \
1329 +- : [i] "+r" (x0), [v] "+Q" (v->counter) \
1330 ++ : [i] "+&r" (x0), [v] "+Q" (v->counter) \
1331 + : "r" (x1) \
1332 + : __LL_SC_CLOBBERS, ##cl); \
1333 + \
1334 +@@ -358,7 +358,7 @@ static inline void atomic64_sub(long i, atomic64_t *v)
1335 + /* LSE atomics */
1336 + " neg %[i], %[i]\n"
1337 + " stadd %[i], %[v]")
1338 +- : [i] "+r" (x0), [v] "+Q" (v->counter)
1339 ++ : [i] "+&r" (x0), [v] "+Q" (v->counter)
1340 + : "r" (x1)
1341 + : __LL_SC_CLOBBERS);
1342 + }
1343 +@@ -377,7 +377,7 @@ static inline long atomic64_sub_return##name(long i, atomic64_t *v) \
1344 + " neg %[i], %[i]\n" \
1345 + " ldadd" #mb " %[i], x30, %[v]\n" \
1346 + " add %[i], %[i], x30") \
1347 +- : [i] "+r" (x0), [v] "+Q" (v->counter) \
1348 ++ : [i] "+&r" (x0), [v] "+Q" (v->counter) \
1349 + : "r" (x1) \
1350 + : __LL_SC_CLOBBERS, ##cl); \
1351 + \
1352 +@@ -404,7 +404,7 @@ static inline long atomic64_fetch_sub##name(long i, atomic64_t *v) \
1353 + /* LSE atomics */ \
1354 + " neg %[i], %[i]\n" \
1355 + " ldadd" #mb " %[i], %[i], %[v]") \
1356 +- : [i] "+r" (x0), [v] "+Q" (v->counter) \
1357 ++ : [i] "+&r" (x0), [v] "+Q" (v->counter) \
1358 + : "r" (x1) \
1359 + : __LL_SC_CLOBBERS, ##cl); \
1360 + \
1361 +@@ -435,7 +435,7 @@ static inline long atomic64_dec_if_positive(atomic64_t *v)
1362 + " sub x30, x30, %[ret]\n"
1363 + " cbnz x30, 1b\n"
1364 + "2:")
1365 +- : [ret] "+r" (x0), [v] "+Q" (v->counter)
1366 ++ : [ret] "+&r" (x0), [v] "+Q" (v->counter)
1367 + :
1368 + : __LL_SC_CLOBBERS, "cc", "memory");
1369 +
1370 +@@ -516,7 +516,7 @@ static inline long __cmpxchg_double##name(unsigned long old1, \
1371 + " eor %[old1], %[old1], %[oldval1]\n" \
1372 + " eor %[old2], %[old2], %[oldval2]\n" \
1373 + " orr %[old1], %[old1], %[old2]") \
1374 +- : [old1] "+r" (x0), [old2] "+r" (x1), \
1375 ++ : [old1] "+&r" (x0), [old2] "+&r" (x1), \
1376 + [v] "+Q" (*(unsigned long *)ptr) \
1377 + : [new1] "r" (x2), [new2] "r" (x3), [ptr] "r" (x4), \
1378 + [oldval1] "r" (oldval1), [oldval2] "r" (oldval2) \
1379 +diff --git a/arch/arm64/include/asm/stacktrace.h b/arch/arm64/include/asm/stacktrace.h
1380 +index 6ad30776e984..99390755c0c4 100644
1381 +--- a/arch/arm64/include/asm/stacktrace.h
1382 ++++ b/arch/arm64/include/asm/stacktrace.h
1383 +@@ -27,7 +27,7 @@ struct stackframe {
1384 + unsigned long fp;
1385 + unsigned long pc;
1386 + #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1387 +- unsigned int graph;
1388 ++ int graph;
1389 + #endif
1390 + };
1391 +
1392 +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
1393 +index 52f15cd896e1..b5a28336c077 100644
1394 +--- a/arch/arm64/kernel/cpu_errata.c
1395 ++++ b/arch/arm64/kernel/cpu_errata.c
1396 +@@ -178,7 +178,7 @@ static int enable_smccc_arch_workaround_1(void *data)
1397 + case PSCI_CONDUIT_HVC:
1398 + arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
1399 + ARM_SMCCC_ARCH_WORKAROUND_1, &res);
1400 +- if (res.a0)
1401 ++ if ((int)res.a0 < 0)
1402 + return 0;
1403 + cb = call_hvc_arch_workaround_1;
1404 + smccc_start = __smccc_workaround_1_hvc_start;
1405 +@@ -188,7 +188,7 @@ static int enable_smccc_arch_workaround_1(void *data)
1406 + case PSCI_CONDUIT_SMC:
1407 + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
1408 + ARM_SMCCC_ARCH_WORKAROUND_1, &res);
1409 +- if (res.a0)
1410 ++ if ((int)res.a0 < 0)
1411 + return 0;
1412 + cb = call_smc_arch_workaround_1;
1413 + smccc_start = __smccc_workaround_1_smc_start;
1414 +diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
1415 +index 9eaef51f83ff..1984e739f155 100644
1416 +--- a/arch/arm64/kernel/perf_event.c
1417 ++++ b/arch/arm64/kernel/perf_event.c
1418 +@@ -914,9 +914,9 @@ static void __armv8pmu_probe_pmu(void *info)
1419 + int pmuver;
1420 +
1421 + dfr0 = read_sysreg(id_aa64dfr0_el1);
1422 +- pmuver = cpuid_feature_extract_signed_field(dfr0,
1423 ++ pmuver = cpuid_feature_extract_unsigned_field(dfr0,
1424 + ID_AA64DFR0_PMUVER_SHIFT);
1425 +- if (pmuver < 1)
1426 ++ if (pmuver == 0xf || pmuver == 0)
1427 + return;
1428 +
1429 + probe->present = true;
1430 +diff --git a/arch/arm64/kernel/stacktrace.c b/arch/arm64/kernel/stacktrace.c
1431 +index 76809ccd309c..d5718a060672 100644
1432 +--- a/arch/arm64/kernel/stacktrace.c
1433 ++++ b/arch/arm64/kernel/stacktrace.c
1434 +@@ -59,6 +59,11 @@ int notrace unwind_frame(struct task_struct *tsk, struct stackframe *frame)
1435 + #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1436 + if (tsk->ret_stack &&
1437 + (frame->pc == (unsigned long)return_to_handler)) {
1438 ++ if (WARN_ON_ONCE(frame->graph == -1))
1439 ++ return -EINVAL;
1440 ++ if (frame->graph < -1)
1441 ++ frame->graph += FTRACE_NOTRACE_DEPTH;
1442 ++
1443 + /*
1444 + * This is a case where function graph tracer has
1445 + * modified a return address (LR) in a stack frame
1446 +diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
1447 +index a4391280fba9..f258636273c9 100644
1448 +--- a/arch/arm64/kernel/time.c
1449 ++++ b/arch/arm64/kernel/time.c
1450 +@@ -52,7 +52,7 @@ unsigned long profile_pc(struct pt_regs *regs)
1451 + frame.fp = regs->regs[29];
1452 + frame.pc = regs->pc;
1453 + #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1454 +- frame.graph = -1; /* no task info */
1455 ++ frame.graph = current->curr_ret_stack;
1456 + #endif
1457 + do {
1458 + int ret = unwind_frame(NULL, &frame);
1459 +diff --git a/arch/cris/include/arch-v10/arch/bug.h b/arch/cris/include/arch-v10/arch/bug.h
1460 +index 905afeacfedf..06da9d49152a 100644
1461 +--- a/arch/cris/include/arch-v10/arch/bug.h
1462 ++++ b/arch/cris/include/arch-v10/arch/bug.h
1463 +@@ -44,18 +44,25 @@ struct bug_frame {
1464 + * not be used like this with newer versions of gcc.
1465 + */
1466 + #define BUG() \
1467 ++do { \
1468 + __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\
1469 + "movu.w " __stringify(__LINE__) ",$r0\n\t"\
1470 + "jump 0f\n\t" \
1471 + ".section .rodata\n" \
1472 + "0:\t.string \"" __FILE__ "\"\n\t" \
1473 +- ".previous")
1474 ++ ".previous"); \
1475 ++ unreachable(); \
1476 ++} while (0)
1477 + #endif
1478 +
1479 + #else
1480 +
1481 + /* This just causes an oops. */
1482 +-#define BUG() (*(int *)0 = 0)
1483 ++#define BUG() \
1484 ++do { \
1485 ++ barrier_before_unreachable(); \
1486 ++ __builtin_trap(); \
1487 ++} while (0)
1488 +
1489 + #endif
1490 +
1491 +diff --git a/arch/ia64/include/asm/bug.h b/arch/ia64/include/asm/bug.h
1492 +index bd3eeb8d1cfa..66b37a532765 100644
1493 +--- a/arch/ia64/include/asm/bug.h
1494 ++++ b/arch/ia64/include/asm/bug.h
1495 +@@ -4,7 +4,11 @@
1496 +
1497 + #ifdef CONFIG_BUG
1498 + #define ia64_abort() __builtin_trap()
1499 +-#define BUG() do { printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); ia64_abort(); } while (0)
1500 ++#define BUG() do { \
1501 ++ printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
1502 ++ barrier_before_unreachable(); \
1503 ++ ia64_abort(); \
1504 ++} while (0)
1505 +
1506 + /* should this BUG be made generic? */
1507 + #define HAVE_ARCH_BUG
1508 +diff --git a/arch/ia64/kernel/err_inject.c b/arch/ia64/kernel/err_inject.c
1509 +index 85bba43e7d5d..658a8e06a69b 100644
1510 +--- a/arch/ia64/kernel/err_inject.c
1511 ++++ b/arch/ia64/kernel/err_inject.c
1512 +@@ -142,7 +142,7 @@ store_virtual_to_phys(struct device *dev, struct device_attribute *attr,
1513 + u64 virt_addr=simple_strtoull(buf, NULL, 16);
1514 + int ret;
1515 +
1516 +- ret = get_user_pages(virt_addr, 1, FOLL_WRITE, NULL, NULL);
1517 ++ ret = get_user_pages_fast(virt_addr, 1, FOLL_WRITE, NULL);
1518 + if (ret<=0) {
1519 + #ifdef ERR_INJ_DEBUG
1520 + printk("Virtual address %lx is not existing.\n",virt_addr);
1521 +diff --git a/arch/m68k/coldfire/device.c b/arch/m68k/coldfire/device.c
1522 +index 84938fdbbada..908d58347790 100644
1523 +--- a/arch/m68k/coldfire/device.c
1524 ++++ b/arch/m68k/coldfire/device.c
1525 +@@ -135,7 +135,11 @@ static struct platform_device mcf_fec0 = {
1526 + .id = 0,
1527 + .num_resources = ARRAY_SIZE(mcf_fec0_resources),
1528 + .resource = mcf_fec0_resources,
1529 +- .dev.platform_data = FEC_PDATA,
1530 ++ .dev = {
1531 ++ .dma_mask = &mcf_fec0.dev.coherent_dma_mask,
1532 ++ .coherent_dma_mask = DMA_BIT_MASK(32),
1533 ++ .platform_data = FEC_PDATA,
1534 ++ }
1535 + };
1536 +
1537 + #ifdef MCFFEC_BASE1
1538 +@@ -167,7 +171,11 @@ static struct platform_device mcf_fec1 = {
1539 + .id = 1,
1540 + .num_resources = ARRAY_SIZE(mcf_fec1_resources),
1541 + .resource = mcf_fec1_resources,
1542 +- .dev.platform_data = FEC_PDATA,
1543 ++ .dev = {
1544 ++ .dma_mask = &mcf_fec1.dev.coherent_dma_mask,
1545 ++ .coherent_dma_mask = DMA_BIT_MASK(32),
1546 ++ .platform_data = FEC_PDATA,
1547 ++ }
1548 + };
1549 + #endif /* MCFFEC_BASE1 */
1550 + #endif /* CONFIG_FEC */
1551 +diff --git a/arch/m68k/include/asm/bug.h b/arch/m68k/include/asm/bug.h
1552 +index b7e2bf1ba4a6..275dca1435bf 100644
1553 +--- a/arch/m68k/include/asm/bug.h
1554 ++++ b/arch/m68k/include/asm/bug.h
1555 +@@ -8,16 +8,19 @@
1556 + #ifndef CONFIG_SUN3
1557 + #define BUG() do { \
1558 + pr_crit("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
1559 ++ barrier_before_unreachable(); \
1560 + __builtin_trap(); \
1561 + } while (0)
1562 + #else
1563 + #define BUG() do { \
1564 + pr_crit("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
1565 ++ barrier_before_unreachable(); \
1566 + panic("BUG!"); \
1567 + } while (0)
1568 + #endif
1569 + #else
1570 + #define BUG() do { \
1571 ++ barrier_before_unreachable(); \
1572 + __builtin_trap(); \
1573 + } while (0)
1574 + #endif
1575 +diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
1576 +index d99f5242169e..b3aec101a65d 100644
1577 +--- a/arch/mips/cavium-octeon/octeon-irq.c
1578 ++++ b/arch/mips/cavium-octeon/octeon-irq.c
1579 +@@ -2271,7 +2271,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
1580 +
1581 + parent_irq = irq_of_parse_and_map(ciu_node, 0);
1582 + if (!parent_irq) {
1583 +- pr_err("ERROR: Couldn't acquire parent_irq for %s\n.",
1584 ++ pr_err("ERROR: Couldn't acquire parent_irq for %s\n",
1585 + ciu_node->name);
1586 + return -EINVAL;
1587 + }
1588 +@@ -2283,7 +2283,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
1589 +
1590 + addr = of_get_address(ciu_node, 0, NULL, NULL);
1591 + if (!addr) {
1592 +- pr_err("ERROR: Couldn't acquire reg(0) %s\n.", ciu_node->name);
1593 ++ pr_err("ERROR: Couldn't acquire reg(0) %s\n", ciu_node->name);
1594 + return -EINVAL;
1595 + }
1596 + host_data->raw_reg = (u64)phys_to_virt(
1597 +@@ -2291,7 +2291,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
1598 +
1599 + addr = of_get_address(ciu_node, 1, NULL, NULL);
1600 + if (!addr) {
1601 +- pr_err("ERROR: Couldn't acquire reg(1) %s\n.", ciu_node->name);
1602 ++ pr_err("ERROR: Couldn't acquire reg(1) %s\n", ciu_node->name);
1603 + return -EINVAL;
1604 + }
1605 + host_data->en_reg = (u64)phys_to_virt(
1606 +@@ -2299,7 +2299,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
1607 +
1608 + r = of_property_read_u32(ciu_node, "cavium,max-bits", &val);
1609 + if (r) {
1610 +- pr_err("ERROR: Couldn't read cavium,max-bits from %s\n.",
1611 ++ pr_err("ERROR: Couldn't read cavium,max-bits from %s\n",
1612 + ciu_node->name);
1613 + return r;
1614 + }
1615 +@@ -2309,7 +2309,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
1616 + &octeon_irq_domain_cib_ops,
1617 + host_data);
1618 + if (!cib_domain) {
1619 +- pr_err("ERROR: Couldn't irq_domain_add_linear()\n.");
1620 ++ pr_err("ERROR: Couldn't irq_domain_add_linear()\n");
1621 + return -ENOMEM;
1622 + }
1623 +
1624 +diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
1625 +index aa3800c82332..d99ca862dae3 100644
1626 +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
1627 ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
1628 +@@ -167,7 +167,7 @@
1629 + #define AR71XX_AHB_DIV_MASK 0x7
1630 +
1631 + #define AR724X_PLL_REG_CPU_CONFIG 0x00
1632 +-#define AR724X_PLL_REG_PCIE_CONFIG 0x18
1633 ++#define AR724X_PLL_REG_PCIE_CONFIG 0x10
1634 +
1635 + #define AR724X_PLL_FB_SHIFT 0
1636 + #define AR724X_PLL_FB_MASK 0x3ff
1637 +diff --git a/arch/mips/include/asm/machine.h b/arch/mips/include/asm/machine.h
1638 +index e0d9b373d415..f83879dadd1e 100644
1639 +--- a/arch/mips/include/asm/machine.h
1640 ++++ b/arch/mips/include/asm/machine.h
1641 +@@ -52,7 +52,7 @@ mips_machine_is_compatible(const struct mips_machine *mach, const void *fdt)
1642 + if (!mach->matches)
1643 + return NULL;
1644 +
1645 +- for (match = mach->matches; match->compatible; match++) {
1646 ++ for (match = mach->matches; match->compatible[0]; match++) {
1647 + if (fdt_node_check_compatible(fdt, 0, match->compatible) == 0)
1648 + return match;
1649 + }
1650 +diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
1651 +index c552c20237d4..006105fb12fe 100644
1652 +--- a/arch/mips/kernel/ptrace.c
1653 ++++ b/arch/mips/kernel/ptrace.c
1654 +@@ -454,7 +454,7 @@ static int fpr_get_msa(struct task_struct *target,
1655 + /*
1656 + * Copy the floating-point context to the supplied NT_PRFPREG buffer.
1657 + * Choose the appropriate helper for general registers, and then copy
1658 +- * the FCSR register separately.
1659 ++ * the FCSR and FIR registers separately.
1660 + */
1661 + static int fpr_get(struct task_struct *target,
1662 + const struct user_regset *regset,
1663 +@@ -462,6 +462,7 @@ static int fpr_get(struct task_struct *target,
1664 + void *kbuf, void __user *ubuf)
1665 + {
1666 + const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t);
1667 ++ const int fir_pos = fcr31_pos + sizeof(u32);
1668 + int err;
1669 +
1670 + if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t))
1671 +@@ -474,6 +475,12 @@ static int fpr_get(struct task_struct *target,
1672 + err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1673 + &target->thread.fpu.fcr31,
1674 + fcr31_pos, fcr31_pos + sizeof(u32));
1675 ++ if (err)
1676 ++ return err;
1677 ++
1678 ++ err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1679 ++ &boot_cpu_data.fpu_id,
1680 ++ fir_pos, fir_pos + sizeof(u32));
1681 +
1682 + return err;
1683 + }
1684 +@@ -522,7 +529,8 @@ static int fpr_set_msa(struct task_struct *target,
1685 + /*
1686 + * Copy the supplied NT_PRFPREG buffer to the floating-point context.
1687 + * Choose the appropriate helper for general registers, and then copy
1688 +- * the FCSR register separately.
1689 ++ * the FCSR register separately. Ignore the incoming FIR register
1690 ++ * contents though, as the register is read-only.
1691 + *
1692 + * We optimize for the case where `count % sizeof(elf_fpreg_t) == 0',
1693 + * which is supposed to have been guaranteed by the kernel before
1694 +@@ -536,6 +544,7 @@ static int fpr_set(struct task_struct *target,
1695 + const void *kbuf, const void __user *ubuf)
1696 + {
1697 + const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t);
1698 ++ const int fir_pos = fcr31_pos + sizeof(u32);
1699 + u32 fcr31;
1700 + int err;
1701 +
1702 +@@ -563,6 +572,11 @@ static int fpr_set(struct task_struct *target,
1703 + ptrace_setfcr31(target, fcr31);
1704 + }
1705 +
1706 ++ if (count > 0)
1707 ++ err = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
1708 ++ fir_pos,
1709 ++ fir_pos + sizeof(u32));
1710 ++
1711 + return err;
1712 + }
1713 +
1714 +@@ -784,7 +798,7 @@ long arch_ptrace(struct task_struct *child, long request,
1715 + fregs = get_fpu_regs(child);
1716 +
1717 + #ifdef CONFIG_32BIT
1718 +- if (test_thread_flag(TIF_32BIT_FPREGS)) {
1719 ++ if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
1720 + /*
1721 + * The odd registers are actually the high
1722 + * order bits of the values stored in the even
1723 +@@ -873,7 +887,7 @@ long arch_ptrace(struct task_struct *child, long request,
1724 +
1725 + init_fp_ctx(child);
1726 + #ifdef CONFIG_32BIT
1727 +- if (test_thread_flag(TIF_32BIT_FPREGS)) {
1728 ++ if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
1729 + /*
1730 + * The odd registers are actually the high
1731 + * order bits of the values stored in the even
1732 +diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
1733 +index 40e212d6b26b..4a157d3249ac 100644
1734 +--- a/arch/mips/kernel/ptrace32.c
1735 ++++ b/arch/mips/kernel/ptrace32.c
1736 +@@ -98,7 +98,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
1737 + break;
1738 + }
1739 + fregs = get_fpu_regs(child);
1740 +- if (test_thread_flag(TIF_32BIT_FPREGS)) {
1741 ++ if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
1742 + /*
1743 + * The odd registers are actually the high
1744 + * order bits of the values stored in the even
1745 +@@ -205,7 +205,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
1746 + sizeof(child->thread.fpu));
1747 + child->thread.fpu.fcr31 = 0;
1748 + }
1749 +- if (test_thread_flag(TIF_32BIT_FPREGS)) {
1750 ++ if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
1751 + /*
1752 + * The odd registers are actually the high
1753 + * order bits of the values stored in the even
1754 +diff --git a/arch/mips/kvm/mips.c b/arch/mips/kvm/mips.c
1755 +index 75fdeaa8c62f..9730ba734afe 100644
1756 +--- a/arch/mips/kvm/mips.c
1757 ++++ b/arch/mips/kvm/mips.c
1758 +@@ -45,7 +45,7 @@ struct kvm_stats_debugfs_item debugfs_entries[] = {
1759 + { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
1760 + { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
1761 + { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
1762 +- { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
1763 ++ { "cop_unusable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
1764 + { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
1765 + { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
1766 + { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
1767 +diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
1768 +index 6f534b209971..e12dfa48b478 100644
1769 +--- a/arch/mips/mm/c-r4k.c
1770 ++++ b/arch/mips/mm/c-r4k.c
1771 +@@ -851,9 +851,12 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
1772 + /*
1773 + * Either no secondary cache or the available caches don't have the
1774 + * subset property so we have to flush the primary caches
1775 +- * explicitly
1776 ++ * explicitly.
1777 ++ * If we would need IPI to perform an INDEX-type operation, then
1778 ++ * we have to use the HIT-type alternative as IPI cannot be used
1779 ++ * here due to interrupts possibly being disabled.
1780 + */
1781 +- if (size >= dcache_size) {
1782 ++ if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
1783 + r4k_blast_dcache();
1784 + } else {
1785 + R4600_HIT_CACHEOP_WAR_IMPL;
1786 +@@ -890,7 +893,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
1787 + return;
1788 + }
1789 +
1790 +- if (size >= dcache_size) {
1791 ++ if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
1792 + r4k_blast_dcache();
1793 + } else {
1794 + R4600_HIT_CACHEOP_WAR_IMPL;
1795 +diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
1796 +index 651974192c4d..b479926f0167 100644
1797 +--- a/arch/powerpc/boot/Makefile
1798 ++++ b/arch/powerpc/boot/Makefile
1799 +@@ -101,7 +101,8 @@ $(addprefix $(obj)/,$(zlib-y)): \
1800 + libfdt := fdt.c fdt_ro.c fdt_wip.c fdt_sw.c fdt_rw.c fdt_strerror.c
1801 + libfdtheader := fdt.h libfdt.h libfdt_internal.h
1802 +
1803 +-$(addprefix $(obj)/,$(libfdt) libfdt-wrapper.o simpleboot.o epapr.o opal.o): \
1804 ++$(addprefix $(obj)/,$(libfdt) libfdt-wrapper.o simpleboot.o epapr.o opal.o \
1805 ++ treeboot-akebono.o treeboot-currituck.o treeboot-iss4xx.o): \
1806 + $(addprefix $(obj)/,$(libfdtheader))
1807 +
1808 + src-wlib-y := string.S crt0.S stdio.c decompress.c main.c \
1809 +diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
1810 +index ccf10c2f8899..c3bdd2d8ec90 100644
1811 +--- a/arch/powerpc/include/asm/exception-64s.h
1812 ++++ b/arch/powerpc/include/asm/exception-64s.h
1813 +@@ -69,6 +69,27 @@
1814 + */
1815 + #define EX_R3 EX_DAR
1816 +
1817 ++#define STF_ENTRY_BARRIER_SLOT \
1818 ++ STF_ENTRY_BARRIER_FIXUP_SECTION; \
1819 ++ nop; \
1820 ++ nop; \
1821 ++ nop
1822 ++
1823 ++#define STF_EXIT_BARRIER_SLOT \
1824 ++ STF_EXIT_BARRIER_FIXUP_SECTION; \
1825 ++ nop; \
1826 ++ nop; \
1827 ++ nop; \
1828 ++ nop; \
1829 ++ nop; \
1830 ++ nop
1831 ++
1832 ++/*
1833 ++ * r10 must be free to use, r13 must be paca
1834 ++ */
1835 ++#define INTERRUPT_TO_KERNEL \
1836 ++ STF_ENTRY_BARRIER_SLOT
1837 ++
1838 + /*
1839 + * Macros for annotating the expected destination of (h)rfid
1840 + *
1841 +@@ -85,16 +106,19 @@
1842 + rfid
1843 +
1844 + #define RFI_TO_USER \
1845 ++ STF_EXIT_BARRIER_SLOT; \
1846 + RFI_FLUSH_SLOT; \
1847 + rfid; \
1848 + b rfi_flush_fallback
1849 +
1850 + #define RFI_TO_USER_OR_KERNEL \
1851 ++ STF_EXIT_BARRIER_SLOT; \
1852 + RFI_FLUSH_SLOT; \
1853 + rfid; \
1854 + b rfi_flush_fallback
1855 +
1856 + #define RFI_TO_GUEST \
1857 ++ STF_EXIT_BARRIER_SLOT; \
1858 + RFI_FLUSH_SLOT; \
1859 + rfid; \
1860 + b rfi_flush_fallback
1861 +@@ -103,21 +127,25 @@
1862 + hrfid
1863 +
1864 + #define HRFI_TO_USER \
1865 ++ STF_EXIT_BARRIER_SLOT; \
1866 + RFI_FLUSH_SLOT; \
1867 + hrfid; \
1868 + b hrfi_flush_fallback
1869 +
1870 + #define HRFI_TO_USER_OR_KERNEL \
1871 ++ STF_EXIT_BARRIER_SLOT; \
1872 + RFI_FLUSH_SLOT; \
1873 + hrfid; \
1874 + b hrfi_flush_fallback
1875 +
1876 + #define HRFI_TO_GUEST \
1877 ++ STF_EXIT_BARRIER_SLOT; \
1878 + RFI_FLUSH_SLOT; \
1879 + hrfid; \
1880 + b hrfi_flush_fallback
1881 +
1882 + #define HRFI_TO_UNKNOWN \
1883 ++ STF_EXIT_BARRIER_SLOT; \
1884 + RFI_FLUSH_SLOT; \
1885 + hrfid; \
1886 + b hrfi_flush_fallback
1887 +@@ -249,6 +277,7 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
1888 + #define __EXCEPTION_PROLOG_1(area, extra, vec) \
1889 + OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \
1890 + OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \
1891 ++ INTERRUPT_TO_KERNEL; \
1892 + SAVE_CTR(r10, area); \
1893 + mfcr r9; \
1894 + extra(vec); \
1895 +diff --git a/arch/powerpc/include/asm/feature-fixups.h b/arch/powerpc/include/asm/feature-fixups.h
1896 +index 1e82eb3caabd..a9b64df34e2a 100644
1897 +--- a/arch/powerpc/include/asm/feature-fixups.h
1898 ++++ b/arch/powerpc/include/asm/feature-fixups.h
1899 +@@ -187,6 +187,22 @@ label##3: \
1900 + FTR_ENTRY_OFFSET label##1b-label##3b; \
1901 + .popsection;
1902 +
1903 ++#define STF_ENTRY_BARRIER_FIXUP_SECTION \
1904 ++953: \
1905 ++ .pushsection __stf_entry_barrier_fixup,"a"; \
1906 ++ .align 2; \
1907 ++954: \
1908 ++ FTR_ENTRY_OFFSET 953b-954b; \
1909 ++ .popsection;
1910 ++
1911 ++#define STF_EXIT_BARRIER_FIXUP_SECTION \
1912 ++955: \
1913 ++ .pushsection __stf_exit_barrier_fixup,"a"; \
1914 ++ .align 2; \
1915 ++956: \
1916 ++ FTR_ENTRY_OFFSET 955b-956b; \
1917 ++ .popsection;
1918 ++
1919 + #define RFI_FLUSH_FIXUP_SECTION \
1920 + 951: \
1921 + .pushsection __rfi_flush_fixup,"a"; \
1922 +@@ -199,6 +215,9 @@ label##3: \
1923 + #ifndef __ASSEMBLY__
1924 + #include <linux/types.h>
1925 +
1926 ++extern long stf_barrier_fallback;
1927 ++extern long __start___stf_entry_barrier_fixup, __stop___stf_entry_barrier_fixup;
1928 ++extern long __start___stf_exit_barrier_fixup, __stop___stf_exit_barrier_fixup;
1929 + extern long __start___rfi_flush_fixup, __stop___rfi_flush_fixup;
1930 +
1931 + void apply_feature_fixups(void);
1932 +diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
1933 +index eca3f9c68907..5a740feb7bd7 100644
1934 +--- a/arch/powerpc/include/asm/hvcall.h
1935 ++++ b/arch/powerpc/include/asm/hvcall.h
1936 +@@ -337,6 +337,9 @@
1937 + #define H_CPU_CHAR_L1D_FLUSH_ORI30 (1ull << 61) // IBM bit 2
1938 + #define H_CPU_CHAR_L1D_FLUSH_TRIG2 (1ull << 60) // IBM bit 3
1939 + #define H_CPU_CHAR_L1D_THREAD_PRIV (1ull << 59) // IBM bit 4
1940 ++#define H_CPU_CHAR_BRANCH_HINTS_HONORED (1ull << 58) // IBM bit 5
1941 ++#define H_CPU_CHAR_THREAD_RECONFIG_CTRL (1ull << 57) // IBM bit 6
1942 ++#define H_CPU_CHAR_COUNT_CACHE_DISABLED (1ull << 56) // IBM bit 7
1943 +
1944 + #define H_CPU_BEHAV_FAVOUR_SECURITY (1ull << 63) // IBM bit 0
1945 + #define H_CPU_BEHAV_L1D_FLUSH_PR (1ull << 62) // IBM bit 1
1946 +diff --git a/arch/powerpc/include/asm/irq_work.h b/arch/powerpc/include/asm/irq_work.h
1947 +index c6d3078bd8c3..b8b0be8f1a07 100644
1948 +--- a/arch/powerpc/include/asm/irq_work.h
1949 ++++ b/arch/powerpc/include/asm/irq_work.h
1950 +@@ -6,5 +6,6 @@ static inline bool arch_irq_work_has_interrupt(void)
1951 + {
1952 + return true;
1953 + }
1954 ++extern void arch_irq_work_raise(void);
1955 +
1956 + #endif /* _ASM_POWERPC_IRQ_WORK_H */
1957 +diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
1958 +index b8366df50d19..e6bd59353e40 100644
1959 +--- a/arch/powerpc/include/asm/paca.h
1960 ++++ b/arch/powerpc/include/asm/paca.h
1961 +@@ -238,8 +238,7 @@ struct paca_struct {
1962 + */
1963 + u64 exrfi[EX_SIZE] __aligned(0x80);
1964 + void *rfi_flush_fallback_area;
1965 +- u64 l1d_flush_congruence;
1966 +- u64 l1d_flush_sets;
1967 ++ u64 l1d_flush_size;
1968 + #endif
1969 + };
1970 +
1971 +diff --git a/arch/powerpc/include/asm/security_features.h b/arch/powerpc/include/asm/security_features.h
1972 +new file mode 100644
1973 +index 000000000000..44989b22383c
1974 +--- /dev/null
1975 ++++ b/arch/powerpc/include/asm/security_features.h
1976 +@@ -0,0 +1,85 @@
1977 ++/* SPDX-License-Identifier: GPL-2.0+ */
1978 ++/*
1979 ++ * Security related feature bit definitions.
1980 ++ *
1981 ++ * Copyright 2018, Michael Ellerman, IBM Corporation.
1982 ++ */
1983 ++
1984 ++#ifndef _ASM_POWERPC_SECURITY_FEATURES_H
1985 ++#define _ASM_POWERPC_SECURITY_FEATURES_H
1986 ++
1987 ++
1988 ++extern unsigned long powerpc_security_features;
1989 ++extern bool rfi_flush;
1990 ++
1991 ++/* These are bit flags */
1992 ++enum stf_barrier_type {
1993 ++ STF_BARRIER_NONE = 0x1,
1994 ++ STF_BARRIER_FALLBACK = 0x2,
1995 ++ STF_BARRIER_EIEIO = 0x4,
1996 ++ STF_BARRIER_SYNC_ORI = 0x8,
1997 ++};
1998 ++
1999 ++void setup_stf_barrier(void);
2000 ++void do_stf_barrier_fixups(enum stf_barrier_type types);
2001 ++
2002 ++static inline void security_ftr_set(unsigned long feature)
2003 ++{
2004 ++ powerpc_security_features |= feature;
2005 ++}
2006 ++
2007 ++static inline void security_ftr_clear(unsigned long feature)
2008 ++{
2009 ++ powerpc_security_features &= ~feature;
2010 ++}
2011 ++
2012 ++static inline bool security_ftr_enabled(unsigned long feature)
2013 ++{
2014 ++ return !!(powerpc_security_features & feature);
2015 ++}
2016 ++
2017 ++
2018 ++// Features indicating support for Spectre/Meltdown mitigations
2019 ++
2020 ++// The L1-D cache can be flushed with ori r30,r30,0
2021 ++#define SEC_FTR_L1D_FLUSH_ORI30 0x0000000000000001ull
2022 ++
2023 ++// The L1-D cache can be flushed with mtspr 882,r0 (aka SPRN_TRIG2)
2024 ++#define SEC_FTR_L1D_FLUSH_TRIG2 0x0000000000000002ull
2025 ++
2026 ++// ori r31,r31,0 acts as a speculation barrier
2027 ++#define SEC_FTR_SPEC_BAR_ORI31 0x0000000000000004ull
2028 ++
2029 ++// Speculation past bctr is disabled
2030 ++#define SEC_FTR_BCCTRL_SERIALISED 0x0000000000000008ull
2031 ++
2032 ++// Entries in L1-D are private to a SMT thread
2033 ++#define SEC_FTR_L1D_THREAD_PRIV 0x0000000000000010ull
2034 ++
2035 ++// Indirect branch prediction cache disabled
2036 ++#define SEC_FTR_COUNT_CACHE_DISABLED 0x0000000000000020ull
2037 ++
2038 ++
2039 ++// Features indicating need for Spectre/Meltdown mitigations
2040 ++
2041 ++// The L1-D cache should be flushed on MSR[HV] 1->0 transition (hypervisor to guest)
2042 ++#define SEC_FTR_L1D_FLUSH_HV 0x0000000000000040ull
2043 ++
2044 ++// The L1-D cache should be flushed on MSR[PR] 0->1 transition (kernel to userspace)
2045 ++#define SEC_FTR_L1D_FLUSH_PR 0x0000000000000080ull
2046 ++
2047 ++// A speculation barrier should be used for bounds checks (Spectre variant 1)
2048 ++#define SEC_FTR_BNDS_CHK_SPEC_BAR 0x0000000000000100ull
2049 ++
2050 ++// Firmware configuration indicates user favours security over performance
2051 ++#define SEC_FTR_FAVOUR_SECURITY 0x0000000000000200ull
2052 ++
2053 ++
2054 ++// Features enabled by default
2055 ++#define SEC_FTR_DEFAULT \
2056 ++ (SEC_FTR_L1D_FLUSH_HV | \
2057 ++ SEC_FTR_L1D_FLUSH_PR | \
2058 ++ SEC_FTR_BNDS_CHK_SPEC_BAR | \
2059 ++ SEC_FTR_FAVOUR_SECURITY)
2060 ++
2061 ++#endif /* _ASM_POWERPC_SECURITY_FEATURES_H */
2062 +diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
2063 +index 469b7fdc9be4..bbcdf929be54 100644
2064 +--- a/arch/powerpc/include/asm/setup.h
2065 ++++ b/arch/powerpc/include/asm/setup.h
2066 +@@ -49,7 +49,7 @@ enum l1d_flush_type {
2067 + L1D_FLUSH_MTTRIG = 0x8,
2068 + };
2069 +
2070 +-void __init setup_rfi_flush(enum l1d_flush_type, bool enable);
2071 ++void setup_rfi_flush(enum l1d_flush_type, bool enable);
2072 + void do_rfi_flush_fixups(enum l1d_flush_type types);
2073 +
2074 + #endif /* !__ASSEMBLY__ */
2075 +diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
2076 +index 6c6cce937dd8..1479c61e29c5 100644
2077 +--- a/arch/powerpc/kernel/Makefile
2078 ++++ b/arch/powerpc/kernel/Makefile
2079 +@@ -42,7 +42,7 @@ obj-$(CONFIG_VDSO32) += vdso32/
2080 + obj-$(CONFIG_PPC_WATCHDOG) += watchdog.o
2081 + obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
2082 + obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_ppc970.o cpu_setup_pa6t.o
2083 +-obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power.o
2084 ++obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power.o security.o
2085 + obj-$(CONFIG_PPC_BOOK3S_64) += mce.o mce_power.o
2086 + obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_book3e.o
2087 + obj-$(CONFIG_PPC64) += vdso64/
2088 +diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
2089 +index 748cdc4bb89a..2e5ea300258a 100644
2090 +--- a/arch/powerpc/kernel/asm-offsets.c
2091 ++++ b/arch/powerpc/kernel/asm-offsets.c
2092 +@@ -239,8 +239,7 @@ int main(void)
2093 + OFFSET(PACA_IN_NMI, paca_struct, in_nmi);
2094 + OFFSET(PACA_RFI_FLUSH_FALLBACK_AREA, paca_struct, rfi_flush_fallback_area);
2095 + OFFSET(PACA_EXRFI, paca_struct, exrfi);
2096 +- OFFSET(PACA_L1D_FLUSH_CONGRUENCE, paca_struct, l1d_flush_congruence);
2097 +- OFFSET(PACA_L1D_FLUSH_SETS, paca_struct, l1d_flush_sets);
2098 ++ OFFSET(PACA_L1D_FLUSH_SIZE, paca_struct, l1d_flush_size);
2099 +
2100 + #endif
2101 + OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id);
2102 +diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
2103 +index 679bbe714e85..9daede99c131 100644
2104 +--- a/arch/powerpc/kernel/cpu_setup_power.S
2105 ++++ b/arch/powerpc/kernel/cpu_setup_power.S
2106 +@@ -28,6 +28,7 @@ _GLOBAL(__setup_cpu_power7)
2107 + beqlr
2108 + li r0,0
2109 + mtspr SPRN_LPID,r0
2110 ++ mtspr SPRN_PCR,r0
2111 + mfspr r3,SPRN_LPCR
2112 + li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
2113 + bl __init_LPCR_ISA206
2114 +@@ -42,6 +43,7 @@ _GLOBAL(__restore_cpu_power7)
2115 + beqlr
2116 + li r0,0
2117 + mtspr SPRN_LPID,r0
2118 ++ mtspr SPRN_PCR,r0
2119 + mfspr r3,SPRN_LPCR
2120 + li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
2121 + bl __init_LPCR_ISA206
2122 +@@ -59,6 +61,7 @@ _GLOBAL(__setup_cpu_power8)
2123 + beqlr
2124 + li r0,0
2125 + mtspr SPRN_LPID,r0
2126 ++ mtspr SPRN_PCR,r0
2127 + mfspr r3,SPRN_LPCR
2128 + ori r3, r3, LPCR_PECEDH
2129 + li r4,0 /* LPES = 0 */
2130 +@@ -81,6 +84,7 @@ _GLOBAL(__restore_cpu_power8)
2131 + beqlr
2132 + li r0,0
2133 + mtspr SPRN_LPID,r0
2134 ++ mtspr SPRN_PCR,r0
2135 + mfspr r3,SPRN_LPCR
2136 + ori r3, r3, LPCR_PECEDH
2137 + li r4,0 /* LPES = 0 */
2138 +@@ -103,6 +107,7 @@ _GLOBAL(__setup_cpu_power9)
2139 + mtspr SPRN_PSSCR,r0
2140 + mtspr SPRN_LPID,r0
2141 + mtspr SPRN_PID,r0
2142 ++ mtspr SPRN_PCR,r0
2143 + mfspr r3,SPRN_LPCR
2144 + LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
2145 + or r3, r3, r4
2146 +@@ -128,6 +133,7 @@ _GLOBAL(__restore_cpu_power9)
2147 + mtspr SPRN_PSSCR,r0
2148 + mtspr SPRN_LPID,r0
2149 + mtspr SPRN_PID,r0
2150 ++ mtspr SPRN_PCR,r0
2151 + mfspr r3,SPRN_LPCR
2152 + LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
2153 + or r3, r3, r4
2154 +diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c b/arch/powerpc/kernel/dt_cpu_ftrs.c
2155 +index f047ae1b6271..2dba206b065a 100644
2156 +--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
2157 ++++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
2158 +@@ -137,6 +137,7 @@ static void __restore_cpu_cpufeatures(void)
2159 + if (hv_mode) {
2160 + mtspr(SPRN_LPID, 0);
2161 + mtspr(SPRN_HFSCR, system_registers.hfscr);
2162 ++ mtspr(SPRN_PCR, 0);
2163 + }
2164 + mtspr(SPRN_FSCR, system_registers.fscr);
2165 +
2166 +diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
2167 +index f9ca4bb3d48e..c09f0a6f8495 100644
2168 +--- a/arch/powerpc/kernel/exceptions-64s.S
2169 ++++ b/arch/powerpc/kernel/exceptions-64s.S
2170 +@@ -825,7 +825,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_TM)
2171 + #endif
2172 +
2173 +
2174 +-EXC_REAL_MASKABLE(decrementer, 0x900, 0x80)
2175 ++EXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80)
2176 + EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900)
2177 + TRAMP_KVM(PACA_EXGEN, 0x900)
2178 + EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
2179 +@@ -901,6 +901,7 @@ EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
2180 + mtctr r13; \
2181 + GET_PACA(r13); \
2182 + std r10,PACA_EXGEN+EX_R10(r13); \
2183 ++ INTERRUPT_TO_KERNEL; \
2184 + KVMTEST_PR(0xc00); /* uses r10, branch to do_kvm_0xc00_system_call */ \
2185 + HMT_MEDIUM; \
2186 + mfctr r9;
2187 +@@ -909,7 +910,8 @@ EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
2188 + #define SYSCALL_KVMTEST \
2189 + HMT_MEDIUM; \
2190 + mr r9,r13; \
2191 +- GET_PACA(r13);
2192 ++ GET_PACA(r13); \
2193 ++ INTERRUPT_TO_KERNEL;
2194 + #endif
2195 +
2196 + #define LOAD_SYSCALL_HANDLER(reg) \
2197 +@@ -1434,45 +1436,56 @@ masked_##_H##interrupt: \
2198 + b .; \
2199 + MASKED_DEC_HANDLER(_H)
2200 +
2201 ++TRAMP_REAL_BEGIN(stf_barrier_fallback)
2202 ++ std r9,PACA_EXRFI+EX_R9(r13)
2203 ++ std r10,PACA_EXRFI+EX_R10(r13)
2204 ++ sync
2205 ++ ld r9,PACA_EXRFI+EX_R9(r13)
2206 ++ ld r10,PACA_EXRFI+EX_R10(r13)
2207 ++ ori 31,31,0
2208 ++ .rept 14
2209 ++ b 1f
2210 ++1:
2211 ++ .endr
2212 ++ blr
2213 ++
2214 + TRAMP_REAL_BEGIN(rfi_flush_fallback)
2215 + SET_SCRATCH0(r13);
2216 + GET_PACA(r13);
2217 + std r9,PACA_EXRFI+EX_R9(r13)
2218 + std r10,PACA_EXRFI+EX_R10(r13)
2219 + std r11,PACA_EXRFI+EX_R11(r13)
2220 +- std r12,PACA_EXRFI+EX_R12(r13)
2221 +- std r8,PACA_EXRFI+EX_R13(r13)
2222 + mfctr r9
2223 + ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
2224 +- ld r11,PACA_L1D_FLUSH_SETS(r13)
2225 +- ld r12,PACA_L1D_FLUSH_CONGRUENCE(r13)
2226 +- /*
2227 +- * The load adresses are at staggered offsets within cachelines,
2228 +- * which suits some pipelines better (on others it should not
2229 +- * hurt).
2230 +- */
2231 +- addi r12,r12,8
2232 ++ ld r11,PACA_L1D_FLUSH_SIZE(r13)
2233 ++ srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
2234 + mtctr r11
2235 + DCBT_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
2236 +
2237 + /* order ld/st prior to dcbt stop all streams with flushing */
2238 + sync
2239 +-1: li r8,0
2240 +- .rept 8 /* 8-way set associative */
2241 +- ldx r11,r10,r8
2242 +- add r8,r8,r12
2243 +- xor r11,r11,r11 // Ensure r11 is 0 even if fallback area is not
2244 +- add r8,r8,r11 // Add 0, this creates a dependency on the ldx
2245 +- .endr
2246 +- addi r10,r10,128 /* 128 byte cache line */
2247 ++
2248 ++ /*
2249 ++ * The load adresses are at staggered offsets within cachelines,
2250 ++ * which suits some pipelines better (on others it should not
2251 ++ * hurt).
2252 ++ */
2253 ++1:
2254 ++ ld r11,(0x80 + 8)*0(r10)
2255 ++ ld r11,(0x80 + 8)*1(r10)
2256 ++ ld r11,(0x80 + 8)*2(r10)
2257 ++ ld r11,(0x80 + 8)*3(r10)
2258 ++ ld r11,(0x80 + 8)*4(r10)
2259 ++ ld r11,(0x80 + 8)*5(r10)
2260 ++ ld r11,(0x80 + 8)*6(r10)
2261 ++ ld r11,(0x80 + 8)*7(r10)
2262 ++ addi r10,r10,0x80*8
2263 + bdnz 1b
2264 +
2265 + mtctr r9
2266 + ld r9,PACA_EXRFI+EX_R9(r13)
2267 + ld r10,PACA_EXRFI+EX_R10(r13)
2268 + ld r11,PACA_EXRFI+EX_R11(r13)
2269 +- ld r12,PACA_EXRFI+EX_R12(r13)
2270 +- ld r8,PACA_EXRFI+EX_R13(r13)
2271 + GET_SCRATCH0(r13);
2272 + rfid
2273 +
2274 +@@ -1482,39 +1495,37 @@ TRAMP_REAL_BEGIN(hrfi_flush_fallback)
2275 + std r9,PACA_EXRFI+EX_R9(r13)
2276 + std r10,PACA_EXRFI+EX_R10(r13)
2277 + std r11,PACA_EXRFI+EX_R11(r13)
2278 +- std r12,PACA_EXRFI+EX_R12(r13)
2279 +- std r8,PACA_EXRFI+EX_R13(r13)
2280 + mfctr r9
2281 + ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
2282 +- ld r11,PACA_L1D_FLUSH_SETS(r13)
2283 +- ld r12,PACA_L1D_FLUSH_CONGRUENCE(r13)
2284 +- /*
2285 +- * The load adresses are at staggered offsets within cachelines,
2286 +- * which suits some pipelines better (on others it should not
2287 +- * hurt).
2288 +- */
2289 +- addi r12,r12,8
2290 ++ ld r11,PACA_L1D_FLUSH_SIZE(r13)
2291 ++ srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
2292 + mtctr r11
2293 + DCBT_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
2294 +
2295 + /* order ld/st prior to dcbt stop all streams with flushing */
2296 + sync
2297 +-1: li r8,0
2298 +- .rept 8 /* 8-way set associative */
2299 +- ldx r11,r10,r8
2300 +- add r8,r8,r12
2301 +- xor r11,r11,r11 // Ensure r11 is 0 even if fallback area is not
2302 +- add r8,r8,r11 // Add 0, this creates a dependency on the ldx
2303 +- .endr
2304 +- addi r10,r10,128 /* 128 byte cache line */
2305 ++
2306 ++ /*
2307 ++ * The load adresses are at staggered offsets within cachelines,
2308 ++ * which suits some pipelines better (on others it should not
2309 ++ * hurt).
2310 ++ */
2311 ++1:
2312 ++ ld r11,(0x80 + 8)*0(r10)
2313 ++ ld r11,(0x80 + 8)*1(r10)
2314 ++ ld r11,(0x80 + 8)*2(r10)
2315 ++ ld r11,(0x80 + 8)*3(r10)
2316 ++ ld r11,(0x80 + 8)*4(r10)
2317 ++ ld r11,(0x80 + 8)*5(r10)
2318 ++ ld r11,(0x80 + 8)*6(r10)
2319 ++ ld r11,(0x80 + 8)*7(r10)
2320 ++ addi r10,r10,0x80*8
2321 + bdnz 1b
2322 +
2323 + mtctr r9
2324 + ld r9,PACA_EXRFI+EX_R9(r13)
2325 + ld r10,PACA_EXRFI+EX_R10(r13)
2326 + ld r11,PACA_EXRFI+EX_R11(r13)
2327 +- ld r12,PACA_EXRFI+EX_R12(r13)
2328 +- ld r8,PACA_EXRFI+EX_R13(r13)
2329 + GET_SCRATCH0(r13);
2330 + hrfid
2331 +
2332 +diff --git a/arch/powerpc/kernel/idle_book3s.S b/arch/powerpc/kernel/idle_book3s.S
2333 +index 1125c9be9e06..e35cebd45c35 100644
2334 +--- a/arch/powerpc/kernel/idle_book3s.S
2335 ++++ b/arch/powerpc/kernel/idle_book3s.S
2336 +@@ -838,6 +838,8 @@ BEGIN_FTR_SECTION
2337 + mtspr SPRN_PTCR,r4
2338 + ld r4,_RPR(r1)
2339 + mtspr SPRN_RPR,r4
2340 ++ ld r4,_AMOR(r1)
2341 ++ mtspr SPRN_AMOR,r4
2342 + END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2343 +
2344 + ld r4,_TSCR(r1)
2345 +diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
2346 +new file mode 100644
2347 +index 000000000000..b98a722da915
2348 +--- /dev/null
2349 ++++ b/arch/powerpc/kernel/security.c
2350 +@@ -0,0 +1,237 @@
2351 ++// SPDX-License-Identifier: GPL-2.0+
2352 ++//
2353 ++// Security related flags and so on.
2354 ++//
2355 ++// Copyright 2018, Michael Ellerman, IBM Corporation.
2356 ++
2357 ++#include <linux/kernel.h>
2358 ++#include <linux/device.h>
2359 ++#include <linux/seq_buf.h>
2360 ++
2361 ++#include <asm/debugfs.h>
2362 ++#include <asm/security_features.h>
2363 ++
2364 ++
2365 ++unsigned long powerpc_security_features __read_mostly = SEC_FTR_DEFAULT;
2366 ++
2367 ++ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
2368 ++{
2369 ++ bool thread_priv;
2370 ++
2371 ++ thread_priv = security_ftr_enabled(SEC_FTR_L1D_THREAD_PRIV);
2372 ++
2373 ++ if (rfi_flush || thread_priv) {
2374 ++ struct seq_buf s;
2375 ++ seq_buf_init(&s, buf, PAGE_SIZE - 1);
2376 ++
2377 ++ seq_buf_printf(&s, "Mitigation: ");
2378 ++
2379 ++ if (rfi_flush)
2380 ++ seq_buf_printf(&s, "RFI Flush");
2381 ++
2382 ++ if (rfi_flush && thread_priv)
2383 ++ seq_buf_printf(&s, ", ");
2384 ++
2385 ++ if (thread_priv)
2386 ++ seq_buf_printf(&s, "L1D private per thread");
2387 ++
2388 ++ seq_buf_printf(&s, "\n");
2389 ++
2390 ++ return s.len;
2391 ++ }
2392 ++
2393 ++ if (!security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV) &&
2394 ++ !security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR))
2395 ++ return sprintf(buf, "Not affected\n");
2396 ++
2397 ++ return sprintf(buf, "Vulnerable\n");
2398 ++}
2399 ++
2400 ++ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
2401 ++{
2402 ++ if (!security_ftr_enabled(SEC_FTR_BNDS_CHK_SPEC_BAR))
2403 ++ return sprintf(buf, "Not affected\n");
2404 ++
2405 ++ return sprintf(buf, "Vulnerable\n");
2406 ++}
2407 ++
2408 ++ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
2409 ++{
2410 ++ bool bcs, ccd, ori;
2411 ++ struct seq_buf s;
2412 ++
2413 ++ seq_buf_init(&s, buf, PAGE_SIZE - 1);
2414 ++
2415 ++ bcs = security_ftr_enabled(SEC_FTR_BCCTRL_SERIALISED);
2416 ++ ccd = security_ftr_enabled(SEC_FTR_COUNT_CACHE_DISABLED);
2417 ++ ori = security_ftr_enabled(SEC_FTR_SPEC_BAR_ORI31);
2418 ++
2419 ++ if (bcs || ccd) {
2420 ++ seq_buf_printf(&s, "Mitigation: ");
2421 ++
2422 ++ if (bcs)
2423 ++ seq_buf_printf(&s, "Indirect branch serialisation (kernel only)");
2424 ++
2425 ++ if (bcs && ccd)
2426 ++ seq_buf_printf(&s, ", ");
2427 ++
2428 ++ if (ccd)
2429 ++ seq_buf_printf(&s, "Indirect branch cache disabled");
2430 ++ } else
2431 ++ seq_buf_printf(&s, "Vulnerable");
2432 ++
2433 ++ if (ori)
2434 ++ seq_buf_printf(&s, ", ori31 speculation barrier enabled");
2435 ++
2436 ++ seq_buf_printf(&s, "\n");
2437 ++
2438 ++ return s.len;
2439 ++}
2440 ++
2441 ++/*
2442 ++ * Store-forwarding barrier support.
2443 ++ */
2444 ++
2445 ++static enum stf_barrier_type stf_enabled_flush_types;
2446 ++static bool no_stf_barrier;
2447 ++bool stf_barrier;
2448 ++
2449 ++static int __init handle_no_stf_barrier(char *p)
2450 ++{
2451 ++ pr_info("stf-barrier: disabled on command line.");
2452 ++ no_stf_barrier = true;
2453 ++ return 0;
2454 ++}
2455 ++
2456 ++early_param("no_stf_barrier", handle_no_stf_barrier);
2457 ++
2458 ++/* This is the generic flag used by other architectures */
2459 ++static int __init handle_ssbd(char *p)
2460 ++{
2461 ++ if (!p || strncmp(p, "auto", 5) == 0 || strncmp(p, "on", 2) == 0 ) {
2462 ++ /* Until firmware tells us, we have the barrier with auto */
2463 ++ return 0;
2464 ++ } else if (strncmp(p, "off", 3) == 0) {
2465 ++ handle_no_stf_barrier(NULL);
2466 ++ return 0;
2467 ++ } else
2468 ++ return 1;
2469 ++
2470 ++ return 0;
2471 ++}
2472 ++early_param("spec_store_bypass_disable", handle_ssbd);
2473 ++
2474 ++/* This is the generic flag used by other architectures */
2475 ++static int __init handle_no_ssbd(char *p)
2476 ++{
2477 ++ handle_no_stf_barrier(NULL);
2478 ++ return 0;
2479 ++}
2480 ++early_param("nospec_store_bypass_disable", handle_no_ssbd);
2481 ++
2482 ++static void stf_barrier_enable(bool enable)
2483 ++{
2484 ++ if (enable)
2485 ++ do_stf_barrier_fixups(stf_enabled_flush_types);
2486 ++ else
2487 ++ do_stf_barrier_fixups(STF_BARRIER_NONE);
2488 ++
2489 ++ stf_barrier = enable;
2490 ++}
2491 ++
2492 ++void setup_stf_barrier(void)
2493 ++{
2494 ++ enum stf_barrier_type type;
2495 ++ bool enable, hv;
2496 ++
2497 ++ hv = cpu_has_feature(CPU_FTR_HVMODE);
2498 ++
2499 ++ /* Default to fallback in case fw-features are not available */
2500 ++ if (cpu_has_feature(CPU_FTR_ARCH_300))
2501 ++ type = STF_BARRIER_EIEIO;
2502 ++ else if (cpu_has_feature(CPU_FTR_ARCH_207S))
2503 ++ type = STF_BARRIER_SYNC_ORI;
2504 ++ else if (cpu_has_feature(CPU_FTR_ARCH_206))
2505 ++ type = STF_BARRIER_FALLBACK;
2506 ++ else
2507 ++ type = STF_BARRIER_NONE;
2508 ++
2509 ++ enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
2510 ++ (security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR) ||
2511 ++ (security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV) && hv));
2512 ++
2513 ++ if (type == STF_BARRIER_FALLBACK) {
2514 ++ pr_info("stf-barrier: fallback barrier available\n");
2515 ++ } else if (type == STF_BARRIER_SYNC_ORI) {
2516 ++ pr_info("stf-barrier: hwsync barrier available\n");
2517 ++ } else if (type == STF_BARRIER_EIEIO) {
2518 ++ pr_info("stf-barrier: eieio barrier available\n");
2519 ++ }
2520 ++
2521 ++ stf_enabled_flush_types = type;
2522 ++
2523 ++ if (!no_stf_barrier)
2524 ++ stf_barrier_enable(enable);
2525 ++}
2526 ++
2527 ++ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
2528 ++{
2529 ++ if (stf_barrier && stf_enabled_flush_types != STF_BARRIER_NONE) {
2530 ++ const char *type;
2531 ++ switch (stf_enabled_flush_types) {
2532 ++ case STF_BARRIER_EIEIO:
2533 ++ type = "eieio";
2534 ++ break;
2535 ++ case STF_BARRIER_SYNC_ORI:
2536 ++ type = "hwsync";
2537 ++ break;
2538 ++ case STF_BARRIER_FALLBACK:
2539 ++ type = "fallback";
2540 ++ break;
2541 ++ default:
2542 ++ type = "unknown";
2543 ++ }
2544 ++ return sprintf(buf, "Mitigation: Kernel entry/exit barrier (%s)\n", type);
2545 ++ }
2546 ++
2547 ++ if (!security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV) &&
2548 ++ !security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR))
2549 ++ return sprintf(buf, "Not affected\n");
2550 ++
2551 ++ return sprintf(buf, "Vulnerable\n");
2552 ++}
2553 ++
2554 ++#ifdef CONFIG_DEBUG_FS
2555 ++static int stf_barrier_set(void *data, u64 val)
2556 ++{