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commit: 4f2fd56455090dfa618857616f3ca1afc10663e3 |
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Author: Andreas K. Hüttel <dilfridge <AT> gentoo <DOT> org> |
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AuthorDate: Sat Jul 30 18:41:18 2022 +0000 |
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Commit: Andreas K. Hüttel <dilfridge <AT> gentoo <DOT> org> |
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CommitDate: Sat Jul 30 18:41:18 2022 +0000 |
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URL: https://gitweb.gentoo.org/proj/catalyst.git/commit/?id=4f2fd564 |
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|
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arch: Add subarch definition for riscv64 softfloat musl |
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|
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Signed-off-by: Andreas K. Hüttel <dilfridge <AT> gentoo.org> |
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|
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catalyst/arch/riscv.py | 6 ++++++ |
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1 file changed, 6 insertions(+) |
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|
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diff --git a/catalyst/arch/riscv.py b/catalyst/arch/riscv.py |
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index d7b76c37..975bce99 100644 |
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--- a/catalyst/arch/riscv.py |
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+++ b/catalyst/arch/riscv.py |
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@@ -34,6 +34,12 @@ class arch_rv64_lp64(generic_riscv): |
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def __init__(self,myspec): |
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generic_riscv.__init__(self,myspec) |
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|
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+class arch_rv64_lp64_musl(generic_riscv): |
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+ "builder class for rv64_lp64_musl" |
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+ def __init__(self,myspec): |
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+ generic_riscv.__init__(self,myspec) |
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+ self.settings["CHOST"]="riscv64-gentoo-linux-musl" |
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+ |
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class arch_rv32_ilp32d(generic_riscv): |
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"builder class for rv32_ilp32d" |
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def __init__(self,myspec): |
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