Gentoo Archives: gentoo-commits

From: Mike Pagano <mpagano@g.o>
To: gentoo-commits@l.g.o
Subject: [gentoo-commits] proj/linux-patches:4.4 commit in: /
Date: Fri, 28 Feb 2020 15:24:39
Message-Id: 1582903450.05bfa562ae7c77a1bf18314cc532a108211f0643.mpagano@gentoo
1 commit: 05bfa562ae7c77a1bf18314cc532a108211f0643
2 Author: Mike Pagano <mpagano <AT> gentoo <DOT> org>
3 AuthorDate: Fri Feb 28 15:24:10 2020 +0000
4 Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org>
5 CommitDate: Fri Feb 28 15:24:10 2020 +0000
6 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=05bfa562
7
8 Linux patch 4.4.215
9
10 Signed-off-by: Mike Pagano <mpagano <AT> gentoo.org>
11
12 0000_README | 4 +
13 1214_linux-4.4.215.patch | 11340 +++++++++++++++++++++++++++++++++++++++++++++
14 2 files changed, 11344 insertions(+)
15
16 diff --git a/0000_README b/0000_README
17 index a0335a4..b4dfa87 100644
18 --- a/0000_README
19 +++ b/0000_README
20 @@ -899,6 +899,10 @@ Patch: 1213_linux-4.4.214.patch
21 From: http://www.kernel.org
22 Desc: Linux 4.4.214
23
24 +Patch: 1214_linux-4.4.215.patch
25 +From: http://www.kernel.org
26 +Desc: Linux 4.4.215
27 +
28 Patch: 1500_XATTR_USER_PREFIX.patch
29 From: https://bugs.gentoo.org/show_bug.cgi?id=470644
30 Desc: Support for namespace user.pax.* on tmpfs.
31
32 diff --git a/1214_linux-4.4.215.patch b/1214_linux-4.4.215.patch
33 new file mode 100644
34 index 0000000..09b41e2
35 --- /dev/null
36 +++ b/1214_linux-4.4.215.patch
37 @@ -0,0 +1,11340 @@
38 +diff --git a/Makefile b/Makefile
39 +index 89f09ef4c552..9118ca43acb4 100644
40 +--- a/Makefile
41 ++++ b/Makefile
42 +@@ -1,6 +1,6 @@
43 + VERSION = 4
44 + PATCHLEVEL = 4
45 +-SUBLEVEL = 214
46 ++SUBLEVEL = 215
47 + EXTRAVERSION =
48 + NAME = Blurry Fish Butt
49 +
50 +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
51 +index 2ba69df49cf8..45f2a5930379 100644
52 +--- a/arch/arm/Kconfig
53 ++++ b/arch/arm/Kconfig
54 +@@ -2000,7 +2000,7 @@ config XIP_PHYS_ADDR
55 + config KEXEC
56 + bool "Kexec system call (EXPERIMENTAL)"
57 + depends on (!SMP || PM_SLEEP_SMP)
58 +- depends on !CPU_V7M
59 ++ depends on MMU
60 + select KEXEC_CORE
61 + help
62 + kexec is a system call that implements the ability to shutdown your
63 +diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
64 +index 6afa909865b5..8636e2321ab7 100644
65 +--- a/arch/arm/boot/dts/r8a7779.dtsi
66 ++++ b/arch/arm/boot/dts/r8a7779.dtsi
67 +@@ -63,6 +63,14 @@
68 + <0xf0000100 0x100>;
69 + };
70 +
71 ++ timer@f0000200 {
72 ++ compatible = "arm,cortex-a9-global-timer";
73 ++ reg = <0xf0000200 0x100>;
74 ++ interrupts = <GIC_PPI 11
75 ++ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
76 ++ clocks = <&cpg_clocks R8A7779_CLK_ZS>;
77 ++ };
78 ++
79 + timer@f0000600 {
80 + compatible = "arm,cortex-a9-twd-timer";
81 + reg = <0xf0000600 0x20>;
82 +diff --git a/arch/microblaze/kernel/cpu/cache.c b/arch/microblaze/kernel/cpu/cache.c
83 +index 0bde47e4fa69..dcba53803fa5 100644
84 +--- a/arch/microblaze/kernel/cpu/cache.c
85 ++++ b/arch/microblaze/kernel/cpu/cache.c
86 +@@ -92,7 +92,8 @@ static inline void __disable_dcache_nomsr(void)
87 + #define CACHE_LOOP_LIMITS(start, end, cache_line_length, cache_size) \
88 + do { \
89 + int align = ~(cache_line_length - 1); \
90 +- end = min(start + cache_size, end); \
91 ++ if (start < UINT_MAX - cache_size) \
92 ++ end = min(start + cache_size, end); \
93 + start &= align; \
94 + } while (0)
95 +
96 +diff --git a/arch/mips/loongson64/loongson-3/platform.c b/arch/mips/loongson64/loongson-3/platform.c
97 +index 25a97cc0ee33..0db4cc3196eb 100644
98 +--- a/arch/mips/loongson64/loongson-3/platform.c
99 ++++ b/arch/mips/loongson64/loongson-3/platform.c
100 +@@ -31,6 +31,9 @@ static int __init loongson3_platform_init(void)
101 + continue;
102 +
103 + pdev = kzalloc(sizeof(struct platform_device), GFP_KERNEL);
104 ++ if (!pdev)
105 ++ return -ENOMEM;
106 ++
107 + pdev->name = loongson_sysconf.sensors[i].name;
108 + pdev->id = loongson_sysconf.sensors[i].id;
109 + pdev->dev.platform_data = &loongson_sysconf.sensors[i];
110 +diff --git a/arch/s390/include/asm/timex.h b/arch/s390/include/asm/timex.h
111 +index dcb6312a0b91..ec94e8812283 100644
112 +--- a/arch/s390/include/asm/timex.h
113 ++++ b/arch/s390/include/asm/timex.h
114 +@@ -82,7 +82,7 @@ static inline void get_tod_clock_ext(char *clk)
115 +
116 + static inline unsigned long long get_tod_clock(void)
117 + {
118 +- unsigned char clk[STORE_CLOCK_EXT_SIZE];
119 ++ char clk[STORE_CLOCK_EXT_SIZE];
120 +
121 + get_tod_clock_ext(clk);
122 + return *((unsigned long long *)&clk[1]);
123 +diff --git a/arch/s390/kernel/mcount.S b/arch/s390/kernel/mcount.S
124 +index 6c1c7d399bf9..78ba14546e00 100644
125 +--- a/arch/s390/kernel/mcount.S
126 ++++ b/arch/s390/kernel/mcount.S
127 +@@ -23,6 +23,12 @@ ENTRY(ftrace_stub)
128 + #define STACK_PTREGS (STACK_FRAME_OVERHEAD)
129 + #define STACK_PTREGS_GPRS (STACK_PTREGS + __PT_GPRS)
130 + #define STACK_PTREGS_PSW (STACK_PTREGS + __PT_PSW)
131 ++#ifdef __PACK_STACK
132 ++/* allocate just enough for r14, r15 and backchain */
133 ++#define TRACED_FUNC_FRAME_SIZE 24
134 ++#else
135 ++#define TRACED_FUNC_FRAME_SIZE STACK_FRAME_OVERHEAD
136 ++#endif
137 +
138 + ENTRY(_mcount)
139 + BR_EX %r14
140 +@@ -34,9 +40,16 @@ ENTRY(ftrace_caller)
141 + #ifndef CC_USING_HOTPATCH
142 + aghi %r0,MCOUNT_RETURN_FIXUP
143 + #endif
144 +- aghi %r15,-STACK_FRAME_SIZE
145 ++ # allocate stack frame for ftrace_caller to contain traced function
146 ++ aghi %r15,-TRACED_FUNC_FRAME_SIZE
147 + stg %r1,__SF_BACKCHAIN(%r15)
148 ++ stg %r0,(__SF_GPRS+8*8)(%r15)
149 ++ stg %r15,(__SF_GPRS+9*8)(%r15)
150 ++ # allocate pt_regs and stack frame for ftrace_trace_function
151 ++ aghi %r15,-STACK_FRAME_SIZE
152 + stg %r1,(STACK_PTREGS_GPRS+15*8)(%r15)
153 ++ aghi %r1,-TRACED_FUNC_FRAME_SIZE
154 ++ stg %r1,__SF_BACKCHAIN(%r15)
155 + stg %r0,(STACK_PTREGS_PSW+8)(%r15)
156 + stmg %r2,%r14,(STACK_PTREGS_GPRS+2*8)(%r15)
157 + #ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
158 +diff --git a/arch/sh/include/cpu-sh2a/cpu/sh7269.h b/arch/sh/include/cpu-sh2a/cpu/sh7269.h
159 +index 2a0ca8780f0d..e4caddd443da 100644
160 +--- a/arch/sh/include/cpu-sh2a/cpu/sh7269.h
161 ++++ b/arch/sh/include/cpu-sh2a/cpu/sh7269.h
162 +@@ -79,8 +79,15 @@ enum {
163 + GPIO_FN_WDTOVF,
164 +
165 + /* CAN */
166 +- GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1,
167 +- GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1, GPIO_FN_CRX0_CRX1_CRX2,
168 ++ GPIO_FN_CTX2, GPIO_FN_CRX2,
169 ++ GPIO_FN_CTX1, GPIO_FN_CRX1,
170 ++ GPIO_FN_CTX0, GPIO_FN_CRX0,
171 ++ GPIO_FN_CTX0_CTX1, GPIO_FN_CRX0_CRX1,
172 ++ GPIO_FN_CTX0_CTX1_CTX2, GPIO_FN_CRX0_CRX1_CRX2,
173 ++ GPIO_FN_CTX2_PJ21, GPIO_FN_CRX2_PJ20,
174 ++ GPIO_FN_CTX1_PJ23, GPIO_FN_CRX1_PJ22,
175 ++ GPIO_FN_CTX0_CTX1_PJ23, GPIO_FN_CRX0_CRX1_PJ22,
176 ++ GPIO_FN_CTX0_CTX1_CTX2_PJ21, GPIO_FN_CRX0_CRX1_CRX2_PJ20,
177 +
178 + /* DMAC */
179 + GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0,
180 +diff --git a/arch/x86/entry/vdso/vdso32-setup.c b/arch/x86/entry/vdso/vdso32-setup.c
181 +index 3f9d1a83891a..50c1f77cab15 100644
182 +--- a/arch/x86/entry/vdso/vdso32-setup.c
183 ++++ b/arch/x86/entry/vdso/vdso32-setup.c
184 +@@ -10,6 +10,7 @@
185 + #include <linux/smp.h>
186 + #include <linux/kernel.h>
187 + #include <linux/mm_types.h>
188 ++#include <linux/elf.h>
189 +
190 + #include <asm/processor.h>
191 + #include <asm/vdso.h>
192 +diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
193 +index 94491e4d21a7..01ec126c5969 100644
194 +--- a/arch/x86/include/asm/cpufeatures.h
195 ++++ b/arch/x86/include/asm/cpufeatures.h
196 +@@ -301,6 +301,7 @@
197 + /* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */
198 + #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
199 + #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
200 ++#define X86_FEATURE_RDPID (16*32+ 22) /* RDPID instruction */
201 +
202 + /* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */
203 + #define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */
204 +diff --git a/arch/x86/include/asm/vgtod.h b/arch/x86/include/asm/vgtod.h
205 +index f556c4843aa1..51e7533bbf79 100644
206 +--- a/arch/x86/include/asm/vgtod.h
207 ++++ b/arch/x86/include/asm/vgtod.h
208 +@@ -83,8 +83,13 @@ static inline unsigned int __getcpu(void)
209 + * works on all CPUs. This is volatile so that it orders
210 + * correctly wrt barrier() and to keep gcc from cleverly
211 + * hoisting it out of the calling function.
212 ++ *
213 ++ * If RDPID is available, use it.
214 + */
215 +- asm volatile ("lsl %1,%0" : "=r" (p) : "r" (__PER_CPU_SEG));
216 ++ alternative_io ("lsl %[p],%[seg]",
217 ++ ".byte 0xf3,0x0f,0xc7,0xf8", /* RDPID %eax/rax */
218 ++ X86_FEATURE_RDPID,
219 ++ [p] "=a" (p), [seg] "r" (__PER_CPU_SEG));
220 +
221 + return p;
222 + }
223 +diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
224 +index 2116176c1721..37f5c2608844 100644
225 +--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
226 ++++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
227 +@@ -560,9 +560,12 @@ static const struct sysfs_ops threshold_ops = {
228 + .store = store,
229 + };
230 +
231 ++static void threshold_block_release(struct kobject *kobj);
232 ++
233 + static struct kobj_type threshold_ktype = {
234 + .sysfs_ops = &threshold_ops,
235 + .default_attrs = default_attrs,
236 ++ .release = threshold_block_release,
237 + };
238 +
239 + static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank,
240 +@@ -765,8 +768,12 @@ static int threshold_create_device(unsigned int cpu)
241 + return err;
242 + }
243 +
244 +-static void deallocate_threshold_block(unsigned int cpu,
245 +- unsigned int bank)
246 ++static void threshold_block_release(struct kobject *kobj)
247 ++{
248 ++ kfree(to_block(kobj));
249 ++}
250 ++
251 ++static void deallocate_threshold_block(unsigned int cpu, unsigned int bank)
252 + {
253 + struct threshold_block *pos = NULL;
254 + struct threshold_block *tmp = NULL;
255 +@@ -776,13 +783,11 @@ static void deallocate_threshold_block(unsigned int cpu,
256 + return;
257 +
258 + list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
259 +- kobject_put(&pos->kobj);
260 + list_del(&pos->miscj);
261 +- kfree(pos);
262 ++ kobject_put(&pos->kobj);
263 + }
264 +
265 +- kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
266 +- per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
267 ++ kobject_put(&head->blocks->kobj);
268 + }
269 +
270 + static void __threshold_remove_blocks(struct threshold_bank *b)
271 +diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
272 +index f4795f5c579d..f876414ca8a3 100644
273 +--- a/arch/x86/kvm/cpuid.c
274 ++++ b/arch/x86/kvm/cpuid.c
275 +@@ -267,13 +267,18 @@ static int __do_cpuid_ent_emulated(struct kvm_cpuid_entry2 *entry,
276 + {
277 + switch (func) {
278 + case 0:
279 +- entry->eax = 1; /* only one leaf currently */
280 ++ entry->eax = 7;
281 + ++*nent;
282 + break;
283 + case 1:
284 + entry->ecx = F(MOVBE);
285 + ++*nent;
286 + break;
287 ++ case 7:
288 ++ entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
289 ++ if (index == 0)
290 ++ entry->ecx = F(RDPID);
291 ++ ++*nent;
292 + default:
293 + break;
294 + }
295 +diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
296 +index ffbdd201c1f1..767be5e61913 100644
297 +--- a/arch/x86/kvm/emulate.c
298 ++++ b/arch/x86/kvm/emulate.c
299 +@@ -3519,6 +3519,16 @@ static int em_cwd(struct x86_emulate_ctxt *ctxt)
300 + return X86EMUL_CONTINUE;
301 + }
302 +
303 ++static int em_rdpid(struct x86_emulate_ctxt *ctxt)
304 ++{
305 ++ u64 tsc_aux = 0;
306 ++
307 ++ if (ctxt->ops->get_msr(ctxt, MSR_TSC_AUX, &tsc_aux))
308 ++ return emulate_gp(ctxt, 0);
309 ++ ctxt->dst.val = tsc_aux;
310 ++ return X86EMUL_CONTINUE;
311 ++}
312 ++
313 + static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
314 + {
315 + u64 tsc = 0;
316 +@@ -4379,10 +4389,20 @@ static const struct opcode group8[] = {
317 + F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
318 + };
319 +
320 ++/*
321 ++ * The "memory" destination is actually always a register, since we come
322 ++ * from the register case of group9.
323 ++ */
324 ++static const struct gprefix pfx_0f_c7_7 = {
325 ++ N, N, N, II(DstMem | ModRM | Op3264 | EmulateOnUD, em_rdpid, rdtscp),
326 ++};
327 ++
328 ++
329 + static const struct group_dual group9 = { {
330 + N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
331 + }, {
332 +- N, N, N, N, N, N, N, N,
333 ++ N, N, N, N, N, N, N,
334 ++ GP(0, &pfx_0f_c7_7),
335 + } };
336 +
337 + static const struct opcode group11[] = {
338 +diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
339 +index ce8c4ae25c15..078b2176f2a2 100644
340 +--- a/arch/x86/kvm/lapic.c
341 ++++ b/arch/x86/kvm/lapic.c
342 +@@ -536,9 +536,11 @@ static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
343 + static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
344 + {
345 + u8 val;
346 +- if (pv_eoi_get_user(vcpu, &val) < 0)
347 ++ if (pv_eoi_get_user(vcpu, &val) < 0) {
348 + apic_debug("Can't read EOI MSR value: 0x%llx\n",
349 + (unsigned long long)vcpu->arch.pv_eoi.msr_val);
350 ++ return false;
351 ++ }
352 + return val & 0x1;
353 + }
354 +
355 +diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
356 +index 6c2b45f5d501..78daf891abec 100644
357 +--- a/arch/x86/kvm/vmx.c
358 ++++ b/arch/x86/kvm/vmx.c
359 +@@ -4275,6 +4275,26 @@ static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
360 + (ss.selector & SEGMENT_RPL_MASK));
361 + }
362 +
363 ++static bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu,
364 ++ unsigned int port, int size);
365 ++static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
366 ++ struct vmcs12 *vmcs12)
367 ++{
368 ++ unsigned long exit_qualification;
369 ++ unsigned short port;
370 ++ int size;
371 ++
372 ++ if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
373 ++ return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
374 ++
375 ++ exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
376 ++
377 ++ port = exit_qualification >> 16;
378 ++ size = (exit_qualification & 7) + 1;
379 ++
380 ++ return nested_vmx_check_io_bitmaps(vcpu, port, size);
381 ++}
382 ++
383 + /*
384 + * Check if guest state is valid. Returns true if valid, false if
385 + * not.
386 +@@ -7624,23 +7644,17 @@ static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
387 + static const int kvm_vmx_max_exit_handlers =
388 + ARRAY_SIZE(kvm_vmx_exit_handlers);
389 +
390 +-static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
391 +- struct vmcs12 *vmcs12)
392 ++/*
393 ++ * Return true if an IO instruction with the specified port and size should cause
394 ++ * a VM-exit into L1.
395 ++ */
396 ++bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port,
397 ++ int size)
398 + {
399 +- unsigned long exit_qualification;
400 ++ struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
401 + gpa_t bitmap, last_bitmap;
402 +- unsigned int port;
403 +- int size;
404 + u8 b;
405 +
406 +- if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
407 +- return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
408 +-
409 +- exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
410 +-
411 +- port = exit_qualification >> 16;
412 +- size = (exit_qualification & 7) + 1;
413 +-
414 + last_bitmap = (gpa_t)-1;
415 + b = -1;
416 +
417 +@@ -10740,11 +10754,71 @@ static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
418 + to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
419 + }
420 +
421 ++static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
422 ++ struct x86_instruction_info *info)
423 ++{
424 ++ struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
425 ++ unsigned short port;
426 ++ bool intercept;
427 ++ int size;
428 ++
429 ++ if (info->intercept == x86_intercept_in ||
430 ++ info->intercept == x86_intercept_ins) {
431 ++ port = info->src_val;
432 ++ size = info->dst_bytes;
433 ++ } else {
434 ++ port = info->dst_val;
435 ++ size = info->src_bytes;
436 ++ }
437 ++
438 ++ /*
439 ++ * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
440 ++ * VM-exits depend on the 'unconditional IO exiting' VM-execution
441 ++ * control.
442 ++ *
443 ++ * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
444 ++ */
445 ++ if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
446 ++ intercept = nested_cpu_has(vmcs12,
447 ++ CPU_BASED_UNCOND_IO_EXITING);
448 ++ else
449 ++ intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
450 ++
451 ++ return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
452 ++}
453 ++
454 + static int vmx_check_intercept(struct kvm_vcpu *vcpu,
455 + struct x86_instruction_info *info,
456 + enum x86_intercept_stage stage)
457 + {
458 +- return X86EMUL_CONTINUE;
459 ++ struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
460 ++ struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
461 ++
462 ++ switch (info->intercept) {
463 ++ /*
464 ++ * RDPID causes #UD if disabled through secondary execution controls.
465 ++ * Because it is marked as EmulateOnUD, we need to intercept it here.
466 ++ */
467 ++ case x86_intercept_rdtscp:
468 ++ if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
469 ++ ctxt->exception.vector = UD_VECTOR;
470 ++ ctxt->exception.error_code_valid = false;
471 ++ return X86EMUL_PROPAGATE_FAULT;
472 ++ }
473 ++ break;
474 ++
475 ++ case x86_intercept_in:
476 ++ case x86_intercept_ins:
477 ++ case x86_intercept_out:
478 ++ case x86_intercept_outs:
479 ++ return vmx_check_intercept_io(vcpu, info);
480 ++
481 ++ /* TODO: check more intercepts... */
482 ++ default:
483 ++ break;
484 ++ }
485 ++
486 ++ return X86EMUL_UNHANDLEABLE;
487 + }
488 +
489 + static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
490 +diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
491 +deleted file mode 100644
492 +index 3791ce8d269e..000000000000
493 +--- a/arch/x86/kvm/vmx/vmx.c
494 ++++ /dev/null
495 +@@ -1,8033 +0,0 @@
496 +-// SPDX-License-Identifier: GPL-2.0-only
497 +-/*
498 +- * Kernel-based Virtual Machine driver for Linux
499 +- *
500 +- * This module enables machines with Intel VT-x extensions to run virtual
501 +- * machines without emulation or binary translation.
502 +- *
503 +- * Copyright (C) 2006 Qumranet, Inc.
504 +- * Copyright 2010 Red Hat, Inc. and/or its affiliates.
505 +- *
506 +- * Authors:
507 +- * Avi Kivity <avi@××××××××.com>
508 +- * Yaniv Kamay <yaniv@××××××××.com>
509 +- */
510 +-
511 +-#include <linux/frame.h>
512 +-#include <linux/highmem.h>
513 +-#include <linux/hrtimer.h>
514 +-#include <linux/kernel.h>
515 +-#include <linux/kvm_host.h>
516 +-#include <linux/module.h>
517 +-#include <linux/moduleparam.h>
518 +-#include <linux/mod_devicetable.h>
519 +-#include <linux/mm.h>
520 +-#include <linux/sched.h>
521 +-#include <linux/sched/smt.h>
522 +-#include <linux/slab.h>
523 +-#include <linux/tboot.h>
524 +-#include <linux/trace_events.h>
525 +-
526 +-#include <asm/apic.h>
527 +-#include <asm/asm.h>
528 +-#include <asm/cpu.h>
529 +-#include <asm/debugreg.h>
530 +-#include <asm/desc.h>
531 +-#include <asm/fpu/internal.h>
532 +-#include <asm/io.h>
533 +-#include <asm/irq_remapping.h>
534 +-#include <asm/kexec.h>
535 +-#include <asm/perf_event.h>
536 +-#include <asm/mce.h>
537 +-#include <asm/mmu_context.h>
538 +-#include <asm/mshyperv.h>
539 +-#include <asm/spec-ctrl.h>
540 +-#include <asm/virtext.h>
541 +-#include <asm/vmx.h>
542 +-
543 +-#include "capabilities.h"
544 +-#include "cpuid.h"
545 +-#include "evmcs.h"
546 +-#include "irq.h"
547 +-#include "kvm_cache_regs.h"
548 +-#include "lapic.h"
549 +-#include "mmu.h"
550 +-#include "nested.h"
551 +-#include "ops.h"
552 +-#include "pmu.h"
553 +-#include "trace.h"
554 +-#include "vmcs.h"
555 +-#include "vmcs12.h"
556 +-#include "vmx.h"
557 +-#include "x86.h"
558 +-
559 +-MODULE_AUTHOR("Qumranet");
560 +-MODULE_LICENSE("GPL");
561 +-
562 +-static const struct x86_cpu_id vmx_cpu_id[] = {
563 +- X86_FEATURE_MATCH(X86_FEATURE_VMX),
564 +- {}
565 +-};
566 +-MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
567 +-
568 +-bool __read_mostly enable_vpid = 1;
569 +-module_param_named(vpid, enable_vpid, bool, 0444);
570 +-
571 +-static bool __read_mostly enable_vnmi = 1;
572 +-module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
573 +-
574 +-bool __read_mostly flexpriority_enabled = 1;
575 +-module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
576 +-
577 +-bool __read_mostly enable_ept = 1;
578 +-module_param_named(ept, enable_ept, bool, S_IRUGO);
579 +-
580 +-bool __read_mostly enable_unrestricted_guest = 1;
581 +-module_param_named(unrestricted_guest,
582 +- enable_unrestricted_guest, bool, S_IRUGO);
583 +-
584 +-bool __read_mostly enable_ept_ad_bits = 1;
585 +-module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
586 +-
587 +-static bool __read_mostly emulate_invalid_guest_state = true;
588 +-module_param(emulate_invalid_guest_state, bool, S_IRUGO);
589 +-
590 +-static bool __read_mostly fasteoi = 1;
591 +-module_param(fasteoi, bool, S_IRUGO);
592 +-
593 +-static bool __read_mostly enable_apicv = 1;
594 +-module_param(enable_apicv, bool, S_IRUGO);
595 +-
596 +-/*
597 +- * If nested=1, nested virtualization is supported, i.e., guests may use
598 +- * VMX and be a hypervisor for its own guests. If nested=0, guests may not
599 +- * use VMX instructions.
600 +- */
601 +-static bool __read_mostly nested = 1;
602 +-module_param(nested, bool, S_IRUGO);
603 +-
604 +-bool __read_mostly enable_pml = 1;
605 +-module_param_named(pml, enable_pml, bool, S_IRUGO);
606 +-
607 +-static bool __read_mostly dump_invalid_vmcs = 0;
608 +-module_param(dump_invalid_vmcs, bool, 0644);
609 +-
610 +-#define MSR_BITMAP_MODE_X2APIC 1
611 +-#define MSR_BITMAP_MODE_X2APIC_APICV 2
612 +-
613 +-#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
614 +-
615 +-/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
616 +-static int __read_mostly cpu_preemption_timer_multi;
617 +-static bool __read_mostly enable_preemption_timer = 1;
618 +-#ifdef CONFIG_X86_64
619 +-module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
620 +-#endif
621 +-
622 +-#define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
623 +-#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
624 +-#define KVM_VM_CR0_ALWAYS_ON \
625 +- (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
626 +- X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
627 +-#define KVM_CR4_GUEST_OWNED_BITS \
628 +- (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
629 +- | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
630 +-
631 +-#define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
632 +-#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
633 +-#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
634 +-
635 +-#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
636 +-
637 +-#define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
638 +- RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
639 +- RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
640 +- RTIT_STATUS_BYTECNT))
641 +-
642 +-#define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
643 +- (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
644 +-
645 +-/*
646 +- * These 2 parameters are used to config the controls for Pause-Loop Exiting:
647 +- * ple_gap: upper bound on the amount of time between two successive
648 +- * executions of PAUSE in a loop. Also indicate if ple enabled.
649 +- * According to test, this time is usually smaller than 128 cycles.
650 +- * ple_window: upper bound on the amount of time a guest is allowed to execute
651 +- * in a PAUSE loop. Tests indicate that most spinlocks are held for
652 +- * less than 2^12 cycles
653 +- * Time is measured based on a counter that runs at the same rate as the TSC,
654 +- * refer SDM volume 3b section 21.6.13 & 22.1.3.
655 +- */
656 +-static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
657 +-module_param(ple_gap, uint, 0444);
658 +-
659 +-static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
660 +-module_param(ple_window, uint, 0444);
661 +-
662 +-/* Default doubles per-vcpu window every exit. */
663 +-static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
664 +-module_param(ple_window_grow, uint, 0444);
665 +-
666 +-/* Default resets per-vcpu window every exit to ple_window. */
667 +-static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
668 +-module_param(ple_window_shrink, uint, 0444);
669 +-
670 +-/* Default is to compute the maximum so we can never overflow. */
671 +-static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
672 +-module_param(ple_window_max, uint, 0444);
673 +-
674 +-/* Default is SYSTEM mode, 1 for host-guest mode */
675 +-int __read_mostly pt_mode = PT_MODE_SYSTEM;
676 +-module_param(pt_mode, int, S_IRUGO);
677 +-
678 +-static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
679 +-static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
680 +-static DEFINE_MUTEX(vmx_l1d_flush_mutex);
681 +-
682 +-/* Storage for pre module init parameter parsing */
683 +-static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
684 +-
685 +-static const struct {
686 +- const char *option;
687 +- bool for_parse;
688 +-} vmentry_l1d_param[] = {
689 +- [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
690 +- [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
691 +- [VMENTER_L1D_FLUSH_COND] = {"cond", true},
692 +- [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
693 +- [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
694 +- [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
695 +-};
696 +-
697 +-#define L1D_CACHE_ORDER 4
698 +-static void *vmx_l1d_flush_pages;
699 +-
700 +-static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
701 +-{
702 +- struct page *page;
703 +- unsigned int i;
704 +-
705 +- if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
706 +- l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
707 +- return 0;
708 +- }
709 +-
710 +- if (!enable_ept) {
711 +- l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
712 +- return 0;
713 +- }
714 +-
715 +- if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
716 +- u64 msr;
717 +-
718 +- rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
719 +- if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
720 +- l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
721 +- return 0;
722 +- }
723 +- }
724 +-
725 +- /* If set to auto use the default l1tf mitigation method */
726 +- if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
727 +- switch (l1tf_mitigation) {
728 +- case L1TF_MITIGATION_OFF:
729 +- l1tf = VMENTER_L1D_FLUSH_NEVER;
730 +- break;
731 +- case L1TF_MITIGATION_FLUSH_NOWARN:
732 +- case L1TF_MITIGATION_FLUSH:
733 +- case L1TF_MITIGATION_FLUSH_NOSMT:
734 +- l1tf = VMENTER_L1D_FLUSH_COND;
735 +- break;
736 +- case L1TF_MITIGATION_FULL:
737 +- case L1TF_MITIGATION_FULL_FORCE:
738 +- l1tf = VMENTER_L1D_FLUSH_ALWAYS;
739 +- break;
740 +- }
741 +- } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
742 +- l1tf = VMENTER_L1D_FLUSH_ALWAYS;
743 +- }
744 +-
745 +- if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
746 +- !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
747 +- /*
748 +- * This allocation for vmx_l1d_flush_pages is not tied to a VM
749 +- * lifetime and so should not be charged to a memcg.
750 +- */
751 +- page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
752 +- if (!page)
753 +- return -ENOMEM;
754 +- vmx_l1d_flush_pages = page_address(page);
755 +-
756 +- /*
757 +- * Initialize each page with a different pattern in
758 +- * order to protect against KSM in the nested
759 +- * virtualization case.
760 +- */
761 +- for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
762 +- memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
763 +- PAGE_SIZE);
764 +- }
765 +- }
766 +-
767 +- l1tf_vmx_mitigation = l1tf;
768 +-
769 +- if (l1tf != VMENTER_L1D_FLUSH_NEVER)
770 +- static_branch_enable(&vmx_l1d_should_flush);
771 +- else
772 +- static_branch_disable(&vmx_l1d_should_flush);
773 +-
774 +- if (l1tf == VMENTER_L1D_FLUSH_COND)
775 +- static_branch_enable(&vmx_l1d_flush_cond);
776 +- else
777 +- static_branch_disable(&vmx_l1d_flush_cond);
778 +- return 0;
779 +-}
780 +-
781 +-static int vmentry_l1d_flush_parse(const char *s)
782 +-{
783 +- unsigned int i;
784 +-
785 +- if (s) {
786 +- for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
787 +- if (vmentry_l1d_param[i].for_parse &&
788 +- sysfs_streq(s, vmentry_l1d_param[i].option))
789 +- return i;
790 +- }
791 +- }
792 +- return -EINVAL;
793 +-}
794 +-
795 +-static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
796 +-{
797 +- int l1tf, ret;
798 +-
799 +- l1tf = vmentry_l1d_flush_parse(s);
800 +- if (l1tf < 0)
801 +- return l1tf;
802 +-
803 +- if (!boot_cpu_has(X86_BUG_L1TF))
804 +- return 0;
805 +-
806 +- /*
807 +- * Has vmx_init() run already? If not then this is the pre init
808 +- * parameter parsing. In that case just store the value and let
809 +- * vmx_init() do the proper setup after enable_ept has been
810 +- * established.
811 +- */
812 +- if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
813 +- vmentry_l1d_flush_param = l1tf;
814 +- return 0;
815 +- }
816 +-
817 +- mutex_lock(&vmx_l1d_flush_mutex);
818 +- ret = vmx_setup_l1d_flush(l1tf);
819 +- mutex_unlock(&vmx_l1d_flush_mutex);
820 +- return ret;
821 +-}
822 +-
823 +-static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
824 +-{
825 +- if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
826 +- return sprintf(s, "???\n");
827 +-
828 +- return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
829 +-}
830 +-
831 +-static const struct kernel_param_ops vmentry_l1d_flush_ops = {
832 +- .set = vmentry_l1d_flush_set,
833 +- .get = vmentry_l1d_flush_get,
834 +-};
835 +-module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
836 +-
837 +-static bool guest_state_valid(struct kvm_vcpu *vcpu);
838 +-static u32 vmx_segment_access_rights(struct kvm_segment *var);
839 +-static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
840 +- u32 msr, int type);
841 +-
842 +-void vmx_vmexit(void);
843 +-
844 +-#define vmx_insn_failed(fmt...) \
845 +-do { \
846 +- WARN_ONCE(1, fmt); \
847 +- pr_warn_ratelimited(fmt); \
848 +-} while (0)
849 +-
850 +-asmlinkage void vmread_error(unsigned long field, bool fault)
851 +-{
852 +- if (fault)
853 +- kvm_spurious_fault();
854 +- else
855 +- vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
856 +-}
857 +-
858 +-noinline void vmwrite_error(unsigned long field, unsigned long value)
859 +-{
860 +- vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
861 +- field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
862 +-}
863 +-
864 +-noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
865 +-{
866 +- vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
867 +-}
868 +-
869 +-noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
870 +-{
871 +- vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
872 +-}
873 +-
874 +-noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
875 +-{
876 +- vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
877 +- ext, vpid, gva);
878 +-}
879 +-
880 +-noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
881 +-{
882 +- vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
883 +- ext, eptp, gpa);
884 +-}
885 +-
886 +-static DEFINE_PER_CPU(struct vmcs *, vmxarea);
887 +-DEFINE_PER_CPU(struct vmcs *, current_vmcs);
888 +-/*
889 +- * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
890 +- * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
891 +- */
892 +-static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
893 +-
894 +-/*
895 +- * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
896 +- * can find which vCPU should be waken up.
897 +- */
898 +-static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
899 +-static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
900 +-
901 +-static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
902 +-static DEFINE_SPINLOCK(vmx_vpid_lock);
903 +-
904 +-struct vmcs_config vmcs_config;
905 +-struct vmx_capability vmx_capability;
906 +-
907 +-#define VMX_SEGMENT_FIELD(seg) \
908 +- [VCPU_SREG_##seg] = { \
909 +- .selector = GUEST_##seg##_SELECTOR, \
910 +- .base = GUEST_##seg##_BASE, \
911 +- .limit = GUEST_##seg##_LIMIT, \
912 +- .ar_bytes = GUEST_##seg##_AR_BYTES, \
913 +- }
914 +-
915 +-static const struct kvm_vmx_segment_field {
916 +- unsigned selector;
917 +- unsigned base;
918 +- unsigned limit;
919 +- unsigned ar_bytes;
920 +-} kvm_vmx_segment_fields[] = {
921 +- VMX_SEGMENT_FIELD(CS),
922 +- VMX_SEGMENT_FIELD(DS),
923 +- VMX_SEGMENT_FIELD(ES),
924 +- VMX_SEGMENT_FIELD(FS),
925 +- VMX_SEGMENT_FIELD(GS),
926 +- VMX_SEGMENT_FIELD(SS),
927 +- VMX_SEGMENT_FIELD(TR),
928 +- VMX_SEGMENT_FIELD(LDTR),
929 +-};
930 +-
931 +-u64 host_efer;
932 +-static unsigned long host_idt_base;
933 +-
934 +-/*
935 +- * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
936 +- * will emulate SYSCALL in legacy mode if the vendor string in guest
937 +- * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
938 +- * support this emulation, IA32_STAR must always be included in
939 +- * vmx_msr_index[], even in i386 builds.
940 +- */
941 +-const u32 vmx_msr_index[] = {
942 +-#ifdef CONFIG_X86_64
943 +- MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
944 +-#endif
945 +- MSR_EFER, MSR_TSC_AUX, MSR_STAR,
946 +- MSR_IA32_TSX_CTRL,
947 +-};
948 +-
949 +-#if IS_ENABLED(CONFIG_HYPERV)
950 +-static bool __read_mostly enlightened_vmcs = true;
951 +-module_param(enlightened_vmcs, bool, 0444);
952 +-
953 +-/* check_ept_pointer() should be under protection of ept_pointer_lock. */
954 +-static void check_ept_pointer_match(struct kvm *kvm)
955 +-{
956 +- struct kvm_vcpu *vcpu;
957 +- u64 tmp_eptp = INVALID_PAGE;
958 +- int i;
959 +-
960 +- kvm_for_each_vcpu(i, vcpu, kvm) {
961 +- if (!VALID_PAGE(tmp_eptp)) {
962 +- tmp_eptp = to_vmx(vcpu)->ept_pointer;
963 +- } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
964 +- to_kvm_vmx(kvm)->ept_pointers_match
965 +- = EPT_POINTERS_MISMATCH;
966 +- return;
967 +- }
968 +- }
969 +-
970 +- to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
971 +-}
972 +-
973 +-static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
974 +- void *data)
975 +-{
976 +- struct kvm_tlb_range *range = data;
977 +-
978 +- return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
979 +- range->pages);
980 +-}
981 +-
982 +-static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
983 +- struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
984 +-{
985 +- u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
986 +-
987 +- /*
988 +- * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
989 +- * of the base of EPT PML4 table, strip off EPT configuration
990 +- * information.
991 +- */
992 +- if (range)
993 +- return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
994 +- kvm_fill_hv_flush_list_func, (void *)range);
995 +- else
996 +- return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
997 +-}
998 +-
999 +-static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
1000 +- struct kvm_tlb_range *range)
1001 +-{
1002 +- struct kvm_vcpu *vcpu;
1003 +- int ret = 0, i;
1004 +-
1005 +- spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
1006 +-
1007 +- if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
1008 +- check_ept_pointer_match(kvm);
1009 +-
1010 +- if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
1011 +- kvm_for_each_vcpu(i, vcpu, kvm) {
1012 +- /* If ept_pointer is invalid pointer, bypass flush request. */
1013 +- if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
1014 +- ret |= __hv_remote_flush_tlb_with_range(
1015 +- kvm, vcpu, range);
1016 +- }
1017 +- } else {
1018 +- ret = __hv_remote_flush_tlb_with_range(kvm,
1019 +- kvm_get_vcpu(kvm, 0), range);
1020 +- }
1021 +-
1022 +- spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
1023 +- return ret;
1024 +-}
1025 +-static int hv_remote_flush_tlb(struct kvm *kvm)
1026 +-{
1027 +- return hv_remote_flush_tlb_with_range(kvm, NULL);
1028 +-}
1029 +-
1030 +-static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
1031 +-{
1032 +- struct hv_enlightened_vmcs *evmcs;
1033 +- struct hv_partition_assist_pg **p_hv_pa_pg =
1034 +- &vcpu->kvm->arch.hyperv.hv_pa_pg;
1035 +- /*
1036 +- * Synthetic VM-Exit is not enabled in current code and so All
1037 +- * evmcs in singe VM shares same assist page.
1038 +- */
1039 +- if (!*p_hv_pa_pg)
1040 +- *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
1041 +-
1042 +- if (!*p_hv_pa_pg)
1043 +- return -ENOMEM;
1044 +-
1045 +- evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
1046 +-
1047 +- evmcs->partition_assist_page =
1048 +- __pa(*p_hv_pa_pg);
1049 +- evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
1050 +- evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
1051 +-
1052 +- return 0;
1053 +-}
1054 +-
1055 +-#endif /* IS_ENABLED(CONFIG_HYPERV) */
1056 +-
1057 +-/*
1058 +- * Comment's format: document - errata name - stepping - processor name.
1059 +- * Refer from
1060 +- * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1061 +- */
1062 +-static u32 vmx_preemption_cpu_tfms[] = {
1063 +-/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1064 +-0x000206E6,
1065 +-/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1066 +-/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1067 +-/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1068 +-0x00020652,
1069 +-/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1070 +-0x00020655,
1071 +-/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1072 +-/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1073 +-/*
1074 +- * 320767.pdf - AAP86 - B1 -
1075 +- * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1076 +- */
1077 +-0x000106E5,
1078 +-/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1079 +-0x000106A0,
1080 +-/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1081 +-0x000106A1,
1082 +-/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1083 +-0x000106A4,
1084 +- /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1085 +- /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1086 +- /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1087 +-0x000106A5,
1088 +- /* Xeon E3-1220 V2 */
1089 +-0x000306A8,
1090 +-};
1091 +-
1092 +-static inline bool cpu_has_broken_vmx_preemption_timer(void)
1093 +-{
1094 +- u32 eax = cpuid_eax(0x00000001), i;
1095 +-
1096 +- /* Clear the reserved bits */
1097 +- eax &= ~(0x3U << 14 | 0xfU << 28);
1098 +- for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1099 +- if (eax == vmx_preemption_cpu_tfms[i])
1100 +- return true;
1101 +-
1102 +- return false;
1103 +-}
1104 +-
1105 +-static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1106 +-{
1107 +- return flexpriority_enabled && lapic_in_kernel(vcpu);
1108 +-}
1109 +-
1110 +-static inline bool report_flexpriority(void)
1111 +-{
1112 +- return flexpriority_enabled;
1113 +-}
1114 +-
1115 +-static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1116 +-{
1117 +- int i;
1118 +-
1119 +- for (i = 0; i < vmx->nmsrs; ++i)
1120 +- if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1121 +- return i;
1122 +- return -1;
1123 +-}
1124 +-
1125 +-struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1126 +-{
1127 +- int i;
1128 +-
1129 +- i = __find_msr_index(vmx, msr);
1130 +- if (i >= 0)
1131 +- return &vmx->guest_msrs[i];
1132 +- return NULL;
1133 +-}
1134 +-
1135 +-static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
1136 +-{
1137 +- int ret = 0;
1138 +-
1139 +- u64 old_msr_data = msr->data;
1140 +- msr->data = data;
1141 +- if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
1142 +- preempt_disable();
1143 +- ret = kvm_set_shared_msr(msr->index, msr->data,
1144 +- msr->mask);
1145 +- preempt_enable();
1146 +- if (ret)
1147 +- msr->data = old_msr_data;
1148 +- }
1149 +- return ret;
1150 +-}
1151 +-
1152 +-void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1153 +-{
1154 +- vmcs_clear(loaded_vmcs->vmcs);
1155 +- if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1156 +- vmcs_clear(loaded_vmcs->shadow_vmcs);
1157 +- loaded_vmcs->cpu = -1;
1158 +- loaded_vmcs->launched = 0;
1159 +-}
1160 +-
1161 +-#ifdef CONFIG_KEXEC_CORE
1162 +-/*
1163 +- * This bitmap is used to indicate whether the vmclear
1164 +- * operation is enabled on all cpus. All disabled by
1165 +- * default.
1166 +- */
1167 +-static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1168 +-
1169 +-static inline void crash_enable_local_vmclear(int cpu)
1170 +-{
1171 +- cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1172 +-}
1173 +-
1174 +-static inline void crash_disable_local_vmclear(int cpu)
1175 +-{
1176 +- cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1177 +-}
1178 +-
1179 +-static inline int crash_local_vmclear_enabled(int cpu)
1180 +-{
1181 +- return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1182 +-}
1183 +-
1184 +-static void crash_vmclear_local_loaded_vmcss(void)
1185 +-{
1186 +- int cpu = raw_smp_processor_id();
1187 +- struct loaded_vmcs *v;
1188 +-
1189 +- if (!crash_local_vmclear_enabled(cpu))
1190 +- return;
1191 +-
1192 +- list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1193 +- loaded_vmcss_on_cpu_link)
1194 +- vmcs_clear(v->vmcs);
1195 +-}
1196 +-#else
1197 +-static inline void crash_enable_local_vmclear(int cpu) { }
1198 +-static inline void crash_disable_local_vmclear(int cpu) { }
1199 +-#endif /* CONFIG_KEXEC_CORE */
1200 +-
1201 +-static void __loaded_vmcs_clear(void *arg)
1202 +-{
1203 +- struct loaded_vmcs *loaded_vmcs = arg;
1204 +- int cpu = raw_smp_processor_id();
1205 +-
1206 +- if (loaded_vmcs->cpu != cpu)
1207 +- return; /* vcpu migration can race with cpu offline */
1208 +- if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1209 +- per_cpu(current_vmcs, cpu) = NULL;
1210 +- crash_disable_local_vmclear(cpu);
1211 +- list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1212 +-
1213 +- /*
1214 +- * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1215 +- * is before setting loaded_vmcs->vcpu to -1 which is done in
1216 +- * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1217 +- * then adds the vmcs into percpu list before it is deleted.
1218 +- */
1219 +- smp_wmb();
1220 +-
1221 +- loaded_vmcs_init(loaded_vmcs);
1222 +- crash_enable_local_vmclear(cpu);
1223 +-}
1224 +-
1225 +-void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1226 +-{
1227 +- int cpu = loaded_vmcs->cpu;
1228 +-
1229 +- if (cpu != -1)
1230 +- smp_call_function_single(cpu,
1231 +- __loaded_vmcs_clear, loaded_vmcs, 1);
1232 +-}
1233 +-
1234 +-static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1235 +- unsigned field)
1236 +-{
1237 +- bool ret;
1238 +- u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1239 +-
1240 +- if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
1241 +- kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
1242 +- vmx->segment_cache.bitmask = 0;
1243 +- }
1244 +- ret = vmx->segment_cache.bitmask & mask;
1245 +- vmx->segment_cache.bitmask |= mask;
1246 +- return ret;
1247 +-}
1248 +-
1249 +-static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1250 +-{
1251 +- u16 *p = &vmx->segment_cache.seg[seg].selector;
1252 +-
1253 +- if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1254 +- *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1255 +- return *p;
1256 +-}
1257 +-
1258 +-static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1259 +-{
1260 +- ulong *p = &vmx->segment_cache.seg[seg].base;
1261 +-
1262 +- if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1263 +- *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1264 +- return *p;
1265 +-}
1266 +-
1267 +-static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1268 +-{
1269 +- u32 *p = &vmx->segment_cache.seg[seg].limit;
1270 +-
1271 +- if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1272 +- *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1273 +- return *p;
1274 +-}
1275 +-
1276 +-static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1277 +-{
1278 +- u32 *p = &vmx->segment_cache.seg[seg].ar;
1279 +-
1280 +- if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1281 +- *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1282 +- return *p;
1283 +-}
1284 +-
1285 +-void update_exception_bitmap(struct kvm_vcpu *vcpu)
1286 +-{
1287 +- u32 eb;
1288 +-
1289 +- eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1290 +- (1u << DB_VECTOR) | (1u << AC_VECTOR);
1291 +- /*
1292 +- * Guest access to VMware backdoor ports could legitimately
1293 +- * trigger #GP because of TSS I/O permission bitmap.
1294 +- * We intercept those #GP and allow access to them anyway
1295 +- * as VMware does.
1296 +- */
1297 +- if (enable_vmware_backdoor)
1298 +- eb |= (1u << GP_VECTOR);
1299 +- if ((vcpu->guest_debug &
1300 +- (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1301 +- (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1302 +- eb |= 1u << BP_VECTOR;
1303 +- if (to_vmx(vcpu)->rmode.vm86_active)
1304 +- eb = ~0;
1305 +- if (enable_ept)
1306 +- eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1307 +-
1308 +- /* When we are running a nested L2 guest and L1 specified for it a
1309 +- * certain exception bitmap, we must trap the same exceptions and pass
1310 +- * them to L1. When running L2, we will only handle the exceptions
1311 +- * specified above if L1 did not want them.
1312 +- */
1313 +- if (is_guest_mode(vcpu))
1314 +- eb |= get_vmcs12(vcpu)->exception_bitmap;
1315 +-
1316 +- vmcs_write32(EXCEPTION_BITMAP, eb);
1317 +-}
1318 +-
1319 +-/*
1320 +- * Check if MSR is intercepted for currently loaded MSR bitmap.
1321 +- */
1322 +-static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
1323 +-{
1324 +- unsigned long *msr_bitmap;
1325 +- int f = sizeof(unsigned long);
1326 +-
1327 +- if (!cpu_has_vmx_msr_bitmap())
1328 +- return true;
1329 +-
1330 +- msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
1331 +-
1332 +- if (msr <= 0x1fff) {
1333 +- return !!test_bit(msr, msr_bitmap + 0x800 / f);
1334 +- } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1335 +- msr &= 0x1fff;
1336 +- return !!test_bit(msr, msr_bitmap + 0xc00 / f);
1337 +- }
1338 +-
1339 +- return true;
1340 +-}
1341 +-
1342 +-static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1343 +- unsigned long entry, unsigned long exit)
1344 +-{
1345 +- vm_entry_controls_clearbit(vmx, entry);
1346 +- vm_exit_controls_clearbit(vmx, exit);
1347 +-}
1348 +-
1349 +-int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
1350 +-{
1351 +- unsigned int i;
1352 +-
1353 +- for (i = 0; i < m->nr; ++i) {
1354 +- if (m->val[i].index == msr)
1355 +- return i;
1356 +- }
1357 +- return -ENOENT;
1358 +-}
1359 +-
1360 +-static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1361 +-{
1362 +- int i;
1363 +- struct msr_autoload *m = &vmx->msr_autoload;
1364 +-
1365 +- switch (msr) {
1366 +- case MSR_EFER:
1367 +- if (cpu_has_load_ia32_efer()) {
1368 +- clear_atomic_switch_msr_special(vmx,
1369 +- VM_ENTRY_LOAD_IA32_EFER,
1370 +- VM_EXIT_LOAD_IA32_EFER);
1371 +- return;
1372 +- }
1373 +- break;
1374 +- case MSR_CORE_PERF_GLOBAL_CTRL:
1375 +- if (cpu_has_load_perf_global_ctrl()) {
1376 +- clear_atomic_switch_msr_special(vmx,
1377 +- VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1378 +- VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1379 +- return;
1380 +- }
1381 +- break;
1382 +- }
1383 +- i = vmx_find_msr_index(&m->guest, msr);
1384 +- if (i < 0)
1385 +- goto skip_guest;
1386 +- --m->guest.nr;
1387 +- m->guest.val[i] = m->guest.val[m->guest.nr];
1388 +- vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
1389 +-
1390 +-skip_guest:
1391 +- i = vmx_find_msr_index(&m->host, msr);
1392 +- if (i < 0)
1393 +- return;
1394 +-
1395 +- --m->host.nr;
1396 +- m->host.val[i] = m->host.val[m->host.nr];
1397 +- vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
1398 +-}
1399 +-
1400 +-static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1401 +- unsigned long entry, unsigned long exit,
1402 +- unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1403 +- u64 guest_val, u64 host_val)
1404 +-{
1405 +- vmcs_write64(guest_val_vmcs, guest_val);
1406 +- if (host_val_vmcs != HOST_IA32_EFER)
1407 +- vmcs_write64(host_val_vmcs, host_val);
1408 +- vm_entry_controls_setbit(vmx, entry);
1409 +- vm_exit_controls_setbit(vmx, exit);
1410 +-}
1411 +-
1412 +-static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1413 +- u64 guest_val, u64 host_val, bool entry_only)
1414 +-{
1415 +- int i, j = 0;
1416 +- struct msr_autoload *m = &vmx->msr_autoload;
1417 +-
1418 +- switch (msr) {
1419 +- case MSR_EFER:
1420 +- if (cpu_has_load_ia32_efer()) {
1421 +- add_atomic_switch_msr_special(vmx,
1422 +- VM_ENTRY_LOAD_IA32_EFER,
1423 +- VM_EXIT_LOAD_IA32_EFER,
1424 +- GUEST_IA32_EFER,
1425 +- HOST_IA32_EFER,
1426 +- guest_val, host_val);
1427 +- return;
1428 +- }
1429 +- break;
1430 +- case MSR_CORE_PERF_GLOBAL_CTRL:
1431 +- if (cpu_has_load_perf_global_ctrl()) {
1432 +- add_atomic_switch_msr_special(vmx,
1433 +- VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1434 +- VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1435 +- GUEST_IA32_PERF_GLOBAL_CTRL,
1436 +- HOST_IA32_PERF_GLOBAL_CTRL,
1437 +- guest_val, host_val);
1438 +- return;
1439 +- }
1440 +- break;
1441 +- case MSR_IA32_PEBS_ENABLE:
1442 +- /* PEBS needs a quiescent period after being disabled (to write
1443 +- * a record). Disabling PEBS through VMX MSR swapping doesn't
1444 +- * provide that period, so a CPU could write host's record into
1445 +- * guest's memory.
1446 +- */
1447 +- wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1448 +- }
1449 +-
1450 +- i = vmx_find_msr_index(&m->guest, msr);
1451 +- if (!entry_only)
1452 +- j = vmx_find_msr_index(&m->host, msr);
1453 +-
1454 +- if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
1455 +- (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) {
1456 +- printk_once(KERN_WARNING "Not enough msr switch entries. "
1457 +- "Can't add msr %x\n", msr);
1458 +- return;
1459 +- }
1460 +- if (i < 0) {
1461 +- i = m->guest.nr++;
1462 +- vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
1463 +- }
1464 +- m->guest.val[i].index = msr;
1465 +- m->guest.val[i].value = guest_val;
1466 +-
1467 +- if (entry_only)
1468 +- return;
1469 +-
1470 +- if (j < 0) {
1471 +- j = m->host.nr++;
1472 +- vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
1473 +- }
1474 +- m->host.val[j].index = msr;
1475 +- m->host.val[j].value = host_val;
1476 +-}
1477 +-
1478 +-static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1479 +-{
1480 +- u64 guest_efer = vmx->vcpu.arch.efer;
1481 +- u64 ignore_bits = 0;
1482 +-
1483 +- /* Shadow paging assumes NX to be available. */
1484 +- if (!enable_ept)
1485 +- guest_efer |= EFER_NX;
1486 +-
1487 +- /*
1488 +- * LMA and LME handled by hardware; SCE meaningless outside long mode.
1489 +- */
1490 +- ignore_bits |= EFER_SCE;
1491 +-#ifdef CONFIG_X86_64
1492 +- ignore_bits |= EFER_LMA | EFER_LME;
1493 +- /* SCE is meaningful only in long mode on Intel */
1494 +- if (guest_efer & EFER_LMA)
1495 +- ignore_bits &= ~(u64)EFER_SCE;
1496 +-#endif
1497 +-
1498 +- /*
1499 +- * On EPT, we can't emulate NX, so we must switch EFER atomically.
1500 +- * On CPUs that support "load IA32_EFER", always switch EFER
1501 +- * atomically, since it's faster than switching it manually.
1502 +- */
1503 +- if (cpu_has_load_ia32_efer() ||
1504 +- (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1505 +- if (!(guest_efer & EFER_LMA))
1506 +- guest_efer &= ~EFER_LME;
1507 +- if (guest_efer != host_efer)
1508 +- add_atomic_switch_msr(vmx, MSR_EFER,
1509 +- guest_efer, host_efer, false);
1510 +- else
1511 +- clear_atomic_switch_msr(vmx, MSR_EFER);
1512 +- return false;
1513 +- } else {
1514 +- clear_atomic_switch_msr(vmx, MSR_EFER);
1515 +-
1516 +- guest_efer &= ~ignore_bits;
1517 +- guest_efer |= host_efer & ignore_bits;
1518 +-
1519 +- vmx->guest_msrs[efer_offset].data = guest_efer;
1520 +- vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1521 +-
1522 +- return true;
1523 +- }
1524 +-}
1525 +-
1526 +-#ifdef CONFIG_X86_32
1527 +-/*
1528 +- * On 32-bit kernels, VM exits still load the FS and GS bases from the
1529 +- * VMCS rather than the segment table. KVM uses this helper to figure
1530 +- * out the current bases to poke them into the VMCS before entry.
1531 +- */
1532 +-static unsigned long segment_base(u16 selector)
1533 +-{
1534 +- struct desc_struct *table;
1535 +- unsigned long v;
1536 +-
1537 +- if (!(selector & ~SEGMENT_RPL_MASK))
1538 +- return 0;
1539 +-
1540 +- table = get_current_gdt_ro();
1541 +-
1542 +- if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1543 +- u16 ldt_selector = kvm_read_ldt();
1544 +-
1545 +- if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1546 +- return 0;
1547 +-
1548 +- table = (struct desc_struct *)segment_base(ldt_selector);
1549 +- }
1550 +- v = get_desc_base(&table[selector >> 3]);
1551 +- return v;
1552 +-}
1553 +-#endif
1554 +-
1555 +-static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1556 +-{
1557 +- u32 i;
1558 +-
1559 +- wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1560 +- wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1561 +- wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1562 +- wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1563 +- for (i = 0; i < addr_range; i++) {
1564 +- wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1565 +- wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1566 +- }
1567 +-}
1568 +-
1569 +-static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1570 +-{
1571 +- u32 i;
1572 +-
1573 +- rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1574 +- rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1575 +- rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1576 +- rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1577 +- for (i = 0; i < addr_range; i++) {
1578 +- rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1579 +- rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1580 +- }
1581 +-}
1582 +-
1583 +-static void pt_guest_enter(struct vcpu_vmx *vmx)
1584 +-{
1585 +- if (pt_mode == PT_MODE_SYSTEM)
1586 +- return;
1587 +-
1588 +- /*
1589 +- * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1590 +- * Save host state before VM entry.
1591 +- */
1592 +- rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1593 +- if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1594 +- wrmsrl(MSR_IA32_RTIT_CTL, 0);
1595 +- pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1596 +- pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1597 +- }
1598 +-}
1599 +-
1600 +-static void pt_guest_exit(struct vcpu_vmx *vmx)
1601 +-{
1602 +- if (pt_mode == PT_MODE_SYSTEM)
1603 +- return;
1604 +-
1605 +- if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1606 +- pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1607 +- pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1608 +- }
1609 +-
1610 +- /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1611 +- wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1612 +-}
1613 +-
1614 +-void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1615 +- unsigned long fs_base, unsigned long gs_base)
1616 +-{
1617 +- if (unlikely(fs_sel != host->fs_sel)) {
1618 +- if (!(fs_sel & 7))
1619 +- vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1620 +- else
1621 +- vmcs_write16(HOST_FS_SELECTOR, 0);
1622 +- host->fs_sel = fs_sel;
1623 +- }
1624 +- if (unlikely(gs_sel != host->gs_sel)) {
1625 +- if (!(gs_sel & 7))
1626 +- vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1627 +- else
1628 +- vmcs_write16(HOST_GS_SELECTOR, 0);
1629 +- host->gs_sel = gs_sel;
1630 +- }
1631 +- if (unlikely(fs_base != host->fs_base)) {
1632 +- vmcs_writel(HOST_FS_BASE, fs_base);
1633 +- host->fs_base = fs_base;
1634 +- }
1635 +- if (unlikely(gs_base != host->gs_base)) {
1636 +- vmcs_writel(HOST_GS_BASE, gs_base);
1637 +- host->gs_base = gs_base;
1638 +- }
1639 +-}
1640 +-
1641 +-void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1642 +-{
1643 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
1644 +- struct vmcs_host_state *host_state;
1645 +-#ifdef CONFIG_X86_64
1646 +- int cpu = raw_smp_processor_id();
1647 +-#endif
1648 +- unsigned long fs_base, gs_base;
1649 +- u16 fs_sel, gs_sel;
1650 +- int i;
1651 +-
1652 +- vmx->req_immediate_exit = false;
1653 +-
1654 +- /*
1655 +- * Note that guest MSRs to be saved/restored can also be changed
1656 +- * when guest state is loaded. This happens when guest transitions
1657 +- * to/from long-mode by setting MSR_EFER.LMA.
1658 +- */
1659 +- if (!vmx->guest_msrs_ready) {
1660 +- vmx->guest_msrs_ready = true;
1661 +- for (i = 0; i < vmx->save_nmsrs; ++i)
1662 +- kvm_set_shared_msr(vmx->guest_msrs[i].index,
1663 +- vmx->guest_msrs[i].data,
1664 +- vmx->guest_msrs[i].mask);
1665 +-
1666 +- }
1667 +- if (vmx->guest_state_loaded)
1668 +- return;
1669 +-
1670 +- host_state = &vmx->loaded_vmcs->host_state;
1671 +-
1672 +- /*
1673 +- * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1674 +- * allow segment selectors with cpl > 0 or ti == 1.
1675 +- */
1676 +- host_state->ldt_sel = kvm_read_ldt();
1677 +-
1678 +-#ifdef CONFIG_X86_64
1679 +- savesegment(ds, host_state->ds_sel);
1680 +- savesegment(es, host_state->es_sel);
1681 +-
1682 +- gs_base = cpu_kernelmode_gs_base(cpu);
1683 +- if (likely(is_64bit_mm(current->mm))) {
1684 +- save_fsgs_for_kvm();
1685 +- fs_sel = current->thread.fsindex;
1686 +- gs_sel = current->thread.gsindex;
1687 +- fs_base = current->thread.fsbase;
1688 +- vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1689 +- } else {
1690 +- savesegment(fs, fs_sel);
1691 +- savesegment(gs, gs_sel);
1692 +- fs_base = read_msr(MSR_FS_BASE);
1693 +- vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1694 +- }
1695 +-
1696 +- wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1697 +-#else
1698 +- savesegment(fs, fs_sel);
1699 +- savesegment(gs, gs_sel);
1700 +- fs_base = segment_base(fs_sel);
1701 +- gs_base = segment_base(gs_sel);
1702 +-#endif
1703 +-
1704 +- vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1705 +- vmx->guest_state_loaded = true;
1706 +-}
1707 +-
1708 +-static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1709 +-{
1710 +- struct vmcs_host_state *host_state;
1711 +-
1712 +- if (!vmx->guest_state_loaded)
1713 +- return;
1714 +-
1715 +- host_state = &vmx->loaded_vmcs->host_state;
1716 +-
1717 +- ++vmx->vcpu.stat.host_state_reload;
1718 +-
1719 +-#ifdef CONFIG_X86_64
1720 +- rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1721 +-#endif
1722 +- if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1723 +- kvm_load_ldt(host_state->ldt_sel);
1724 +-#ifdef CONFIG_X86_64
1725 +- load_gs_index(host_state->gs_sel);
1726 +-#else
1727 +- loadsegment(gs, host_state->gs_sel);
1728 +-#endif
1729 +- }
1730 +- if (host_state->fs_sel & 7)
1731 +- loadsegment(fs, host_state->fs_sel);
1732 +-#ifdef CONFIG_X86_64
1733 +- if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1734 +- loadsegment(ds, host_state->ds_sel);
1735 +- loadsegment(es, host_state->es_sel);
1736 +- }
1737 +-#endif
1738 +- invalidate_tss_limit();
1739 +-#ifdef CONFIG_X86_64
1740 +- wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1741 +-#endif
1742 +- load_fixmap_gdt(raw_smp_processor_id());
1743 +- vmx->guest_state_loaded = false;
1744 +- vmx->guest_msrs_ready = false;
1745 +-}
1746 +-
1747 +-#ifdef CONFIG_X86_64
1748 +-static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1749 +-{
1750 +- preempt_disable();
1751 +- if (vmx->guest_state_loaded)
1752 +- rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1753 +- preempt_enable();
1754 +- return vmx->msr_guest_kernel_gs_base;
1755 +-}
1756 +-
1757 +-static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1758 +-{
1759 +- preempt_disable();
1760 +- if (vmx->guest_state_loaded)
1761 +- wrmsrl(MSR_KERNEL_GS_BASE, data);
1762 +- preempt_enable();
1763 +- vmx->msr_guest_kernel_gs_base = data;
1764 +-}
1765 +-#endif
1766 +-
1767 +-static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1768 +-{
1769 +- struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1770 +- struct pi_desc old, new;
1771 +- unsigned int dest;
1772 +-
1773 +- /*
1774 +- * In case of hot-plug or hot-unplug, we may have to undo
1775 +- * vmx_vcpu_pi_put even if there is no assigned device. And we
1776 +- * always keep PI.NDST up to date for simplicity: it makes the
1777 +- * code easier, and CPU migration is not a fast path.
1778 +- */
1779 +- if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1780 +- return;
1781 +-
1782 +- /*
1783 +- * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1784 +- * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1785 +- * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1786 +- * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1787 +- * correctly.
1788 +- */
1789 +- if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1790 +- pi_clear_sn(pi_desc);
1791 +- goto after_clear_sn;
1792 +- }
1793 +-
1794 +- /* The full case. */
1795 +- do {
1796 +- old.control = new.control = pi_desc->control;
1797 +-
1798 +- dest = cpu_physical_id(cpu);
1799 +-
1800 +- if (x2apic_enabled())
1801 +- new.ndst = dest;
1802 +- else
1803 +- new.ndst = (dest << 8) & 0xFF00;
1804 +-
1805 +- new.sn = 0;
1806 +- } while (cmpxchg64(&pi_desc->control, old.control,
1807 +- new.control) != old.control);
1808 +-
1809 +-after_clear_sn:
1810 +-
1811 +- /*
1812 +- * Clear SN before reading the bitmap. The VT-d firmware
1813 +- * writes the bitmap and reads SN atomically (5.2.3 in the
1814 +- * spec), so it doesn't really have a memory barrier that
1815 +- * pairs with this, but we cannot do that and we need one.
1816 +- */
1817 +- smp_mb__after_atomic();
1818 +-
1819 +- if (!pi_is_pir_empty(pi_desc))
1820 +- pi_set_on(pi_desc);
1821 +-}
1822 +-
1823 +-void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1824 +-{
1825 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
1826 +- bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1827 +-
1828 +- if (!already_loaded) {
1829 +- loaded_vmcs_clear(vmx->loaded_vmcs);
1830 +- local_irq_disable();
1831 +- crash_disable_local_vmclear(cpu);
1832 +-
1833 +- /*
1834 +- * Read loaded_vmcs->cpu should be before fetching
1835 +- * loaded_vmcs->loaded_vmcss_on_cpu_link.
1836 +- * See the comments in __loaded_vmcs_clear().
1837 +- */
1838 +- smp_rmb();
1839 +-
1840 +- list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1841 +- &per_cpu(loaded_vmcss_on_cpu, cpu));
1842 +- crash_enable_local_vmclear(cpu);
1843 +- local_irq_enable();
1844 +- }
1845 +-
1846 +- if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1847 +- per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1848 +- vmcs_load(vmx->loaded_vmcs->vmcs);
1849 +- indirect_branch_prediction_barrier();
1850 +- }
1851 +-
1852 +- if (!already_loaded) {
1853 +- void *gdt = get_current_gdt_ro();
1854 +- unsigned long sysenter_esp;
1855 +-
1856 +- kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1857 +-
1858 +- /*
1859 +- * Linux uses per-cpu TSS and GDT, so set these when switching
1860 +- * processors. See 22.2.4.
1861 +- */
1862 +- vmcs_writel(HOST_TR_BASE,
1863 +- (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1864 +- vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
1865 +-
1866 +- rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1867 +- vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1868 +-
1869 +- vmx->loaded_vmcs->cpu = cpu;
1870 +- }
1871 +-
1872 +- /* Setup TSC multiplier */
1873 +- if (kvm_has_tsc_control &&
1874 +- vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1875 +- decache_tsc_multiplier(vmx);
1876 +-}
1877 +-
1878 +-/*
1879 +- * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1880 +- * vcpu mutex is already taken.
1881 +- */
1882 +-void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1883 +-{
1884 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
1885 +-
1886 +- vmx_vcpu_load_vmcs(vcpu, cpu);
1887 +-
1888 +- vmx_vcpu_pi_load(vcpu, cpu);
1889 +-
1890 +- vmx->host_pkru = read_pkru();
1891 +- vmx->host_debugctlmsr = get_debugctlmsr();
1892 +-}
1893 +-
1894 +-static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1895 +-{
1896 +- struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1897 +-
1898 +- if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1899 +- !irq_remapping_cap(IRQ_POSTING_CAP) ||
1900 +- !kvm_vcpu_apicv_active(vcpu))
1901 +- return;
1902 +-
1903 +- /* Set SN when the vCPU is preempted */
1904 +- if (vcpu->preempted)
1905 +- pi_set_sn(pi_desc);
1906 +-}
1907 +-
1908 +-static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1909 +-{
1910 +- vmx_vcpu_pi_put(vcpu);
1911 +-
1912 +- vmx_prepare_switch_to_host(to_vmx(vcpu));
1913 +-}
1914 +-
1915 +-static bool emulation_required(struct kvm_vcpu *vcpu)
1916 +-{
1917 +- return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1918 +-}
1919 +-
1920 +-static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1921 +-
1922 +-unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1923 +-{
1924 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
1925 +- unsigned long rflags, save_rflags;
1926 +-
1927 +- if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1928 +- kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1929 +- rflags = vmcs_readl(GUEST_RFLAGS);
1930 +- if (vmx->rmode.vm86_active) {
1931 +- rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1932 +- save_rflags = vmx->rmode.save_rflags;
1933 +- rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1934 +- }
1935 +- vmx->rflags = rflags;
1936 +- }
1937 +- return vmx->rflags;
1938 +-}
1939 +-
1940 +-void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1941 +-{
1942 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
1943 +- unsigned long old_rflags;
1944 +-
1945 +- if (enable_unrestricted_guest) {
1946 +- kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1947 +- vmx->rflags = rflags;
1948 +- vmcs_writel(GUEST_RFLAGS, rflags);
1949 +- return;
1950 +- }
1951 +-
1952 +- old_rflags = vmx_get_rflags(vcpu);
1953 +- vmx->rflags = rflags;
1954 +- if (vmx->rmode.vm86_active) {
1955 +- vmx->rmode.save_rflags = rflags;
1956 +- rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1957 +- }
1958 +- vmcs_writel(GUEST_RFLAGS, rflags);
1959 +-
1960 +- if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1961 +- vmx->emulation_required = emulation_required(vcpu);
1962 +-}
1963 +-
1964 +-u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1965 +-{
1966 +- u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1967 +- int ret = 0;
1968 +-
1969 +- if (interruptibility & GUEST_INTR_STATE_STI)
1970 +- ret |= KVM_X86_SHADOW_INT_STI;
1971 +- if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1972 +- ret |= KVM_X86_SHADOW_INT_MOV_SS;
1973 +-
1974 +- return ret;
1975 +-}
1976 +-
1977 +-void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1978 +-{
1979 +- u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1980 +- u32 interruptibility = interruptibility_old;
1981 +-
1982 +- interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1983 +-
1984 +- if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1985 +- interruptibility |= GUEST_INTR_STATE_MOV_SS;
1986 +- else if (mask & KVM_X86_SHADOW_INT_STI)
1987 +- interruptibility |= GUEST_INTR_STATE_STI;
1988 +-
1989 +- if ((interruptibility != interruptibility_old))
1990 +- vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1991 +-}
1992 +-
1993 +-static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1994 +-{
1995 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
1996 +- unsigned long value;
1997 +-
1998 +- /*
1999 +- * Any MSR write that attempts to change bits marked reserved will
2000 +- * case a #GP fault.
2001 +- */
2002 +- if (data & vmx->pt_desc.ctl_bitmask)
2003 +- return 1;
2004 +-
2005 +- /*
2006 +- * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
2007 +- * result in a #GP unless the same write also clears TraceEn.
2008 +- */
2009 +- if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
2010 +- ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
2011 +- return 1;
2012 +-
2013 +- /*
2014 +- * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
2015 +- * and FabricEn would cause #GP, if
2016 +- * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
2017 +- */
2018 +- if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
2019 +- !(data & RTIT_CTL_FABRIC_EN) &&
2020 +- !intel_pt_validate_cap(vmx->pt_desc.caps,
2021 +- PT_CAP_single_range_output))
2022 +- return 1;
2023 +-
2024 +- /*
2025 +- * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
2026 +- * utilize encodings marked reserved will casue a #GP fault.
2027 +- */
2028 +- value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
2029 +- if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
2030 +- !test_bit((data & RTIT_CTL_MTC_RANGE) >>
2031 +- RTIT_CTL_MTC_RANGE_OFFSET, &value))
2032 +- return 1;
2033 +- value = intel_pt_validate_cap(vmx->pt_desc.caps,
2034 +- PT_CAP_cycle_thresholds);
2035 +- if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
2036 +- !test_bit((data & RTIT_CTL_CYC_THRESH) >>
2037 +- RTIT_CTL_CYC_THRESH_OFFSET, &value))
2038 +- return 1;
2039 +- value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
2040 +- if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
2041 +- !test_bit((data & RTIT_CTL_PSB_FREQ) >>
2042 +- RTIT_CTL_PSB_FREQ_OFFSET, &value))
2043 +- return 1;
2044 +-
2045 +- /*
2046 +- * If ADDRx_CFG is reserved or the encodings is >2 will
2047 +- * cause a #GP fault.
2048 +- */
2049 +- value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
2050 +- if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
2051 +- return 1;
2052 +- value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
2053 +- if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
2054 +- return 1;
2055 +- value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
2056 +- if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
2057 +- return 1;
2058 +- value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
2059 +- if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
2060 +- return 1;
2061 +-
2062 +- return 0;
2063 +-}
2064 +-
2065 +-static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
2066 +-{
2067 +- unsigned long rip;
2068 +-
2069 +- /*
2070 +- * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
2071 +- * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
2072 +- * set when EPT misconfig occurs. In practice, real hardware updates
2073 +- * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
2074 +- * (namely Hyper-V) don't set it due to it being undefined behavior,
2075 +- * i.e. we end up advancing IP with some random value.
2076 +- */
2077 +- if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
2078 +- to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
2079 +- rip = kvm_rip_read(vcpu);
2080 +- rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2081 +- kvm_rip_write(vcpu, rip);
2082 +- } else {
2083 +- if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
2084 +- return 0;
2085 +- }
2086 +-
2087 +- /* skipping an emulated instruction also counts */
2088 +- vmx_set_interrupt_shadow(vcpu, 0);
2089 +-
2090 +- return 1;
2091 +-}
2092 +-
2093 +-static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
2094 +-{
2095 +- /*
2096 +- * Ensure that we clear the HLT state in the VMCS. We don't need to
2097 +- * explicitly skip the instruction because if the HLT state is set,
2098 +- * then the instruction is already executing and RIP has already been
2099 +- * advanced.
2100 +- */
2101 +- if (kvm_hlt_in_guest(vcpu->kvm) &&
2102 +- vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
2103 +- vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
2104 +-}
2105 +-
2106 +-static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2107 +-{
2108 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
2109 +- unsigned nr = vcpu->arch.exception.nr;
2110 +- bool has_error_code = vcpu->arch.exception.has_error_code;
2111 +- u32 error_code = vcpu->arch.exception.error_code;
2112 +- u32 intr_info = nr | INTR_INFO_VALID_MASK;
2113 +-
2114 +- kvm_deliver_exception_payload(vcpu);
2115 +-
2116 +- if (has_error_code) {
2117 +- vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2118 +- intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2119 +- }
2120 +-
2121 +- if (vmx->rmode.vm86_active) {
2122 +- int inc_eip = 0;
2123 +- if (kvm_exception_is_soft(nr))
2124 +- inc_eip = vcpu->arch.event_exit_inst_len;
2125 +- kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
2126 +- return;
2127 +- }
2128 +-
2129 +- WARN_ON_ONCE(vmx->emulation_required);
2130 +-
2131 +- if (kvm_exception_is_soft(nr)) {
2132 +- vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2133 +- vmx->vcpu.arch.event_exit_inst_len);
2134 +- intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2135 +- } else
2136 +- intr_info |= INTR_TYPE_HARD_EXCEPTION;
2137 +-
2138 +- vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2139 +-
2140 +- vmx_clear_hlt(vcpu);
2141 +-}
2142 +-
2143 +-static bool vmx_rdtscp_supported(void)
2144 +-{
2145 +- return cpu_has_vmx_rdtscp();
2146 +-}
2147 +-
2148 +-static bool vmx_invpcid_supported(void)
2149 +-{
2150 +- return cpu_has_vmx_invpcid();
2151 +-}
2152 +-
2153 +-/*
2154 +- * Swap MSR entry in host/guest MSR entry array.
2155 +- */
2156 +-static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2157 +-{
2158 +- struct shared_msr_entry tmp;
2159 +-
2160 +- tmp = vmx->guest_msrs[to];
2161 +- vmx->guest_msrs[to] = vmx->guest_msrs[from];
2162 +- vmx->guest_msrs[from] = tmp;
2163 +-}
2164 +-
2165 +-/*
2166 +- * Set up the vmcs to automatically save and restore system
2167 +- * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2168 +- * mode, as fiddling with msrs is very expensive.
2169 +- */
2170 +-static void setup_msrs(struct vcpu_vmx *vmx)
2171 +-{
2172 +- int save_nmsrs, index;
2173 +-
2174 +- save_nmsrs = 0;
2175 +-#ifdef CONFIG_X86_64
2176 +- /*
2177 +- * The SYSCALL MSRs are only needed on long mode guests, and only
2178 +- * when EFER.SCE is set.
2179 +- */
2180 +- if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
2181 +- index = __find_msr_index(vmx, MSR_STAR);
2182 +- if (index >= 0)
2183 +- move_msr_up(vmx, index, save_nmsrs++);
2184 +- index = __find_msr_index(vmx, MSR_LSTAR);
2185 +- if (index >= 0)
2186 +- move_msr_up(vmx, index, save_nmsrs++);
2187 +- index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2188 +- if (index >= 0)
2189 +- move_msr_up(vmx, index, save_nmsrs++);
2190 +- }
2191 +-#endif
2192 +- index = __find_msr_index(vmx, MSR_EFER);
2193 +- if (index >= 0 && update_transition_efer(vmx, index))
2194 +- move_msr_up(vmx, index, save_nmsrs++);
2195 +- index = __find_msr_index(vmx, MSR_TSC_AUX);
2196 +- if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
2197 +- move_msr_up(vmx, index, save_nmsrs++);
2198 +- index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
2199 +- if (index >= 0)
2200 +- move_msr_up(vmx, index, save_nmsrs++);
2201 +-
2202 +- vmx->save_nmsrs = save_nmsrs;
2203 +- vmx->guest_msrs_ready = false;
2204 +-
2205 +- if (cpu_has_vmx_msr_bitmap())
2206 +- vmx_update_msr_bitmap(&vmx->vcpu);
2207 +-}
2208 +-
2209 +-static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
2210 +-{
2211 +- struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2212 +-
2213 +- if (is_guest_mode(vcpu) &&
2214 +- (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
2215 +- return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
2216 +-
2217 +- return vcpu->arch.tsc_offset;
2218 +-}
2219 +-
2220 +-static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2221 +-{
2222 +- struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2223 +- u64 g_tsc_offset = 0;
2224 +-
2225 +- /*
2226 +- * We're here if L1 chose not to trap WRMSR to TSC. According
2227 +- * to the spec, this should set L1's TSC; The offset that L1
2228 +- * set for L2 remains unchanged, and still needs to be added
2229 +- * to the newly set TSC to get L2's TSC.
2230 +- */
2231 +- if (is_guest_mode(vcpu) &&
2232 +- (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
2233 +- g_tsc_offset = vmcs12->tsc_offset;
2234 +-
2235 +- trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2236 +- vcpu->arch.tsc_offset - g_tsc_offset,
2237 +- offset);
2238 +- vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
2239 +- return offset + g_tsc_offset;
2240 +-}
2241 +-
2242 +-/*
2243 +- * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2244 +- * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2245 +- * all guests if the "nested" module option is off, and can also be disabled
2246 +- * for a single guest by disabling its VMX cpuid bit.
2247 +- */
2248 +-bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2249 +-{
2250 +- return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
2251 +-}
2252 +-
2253 +-static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
2254 +- uint64_t val)
2255 +-{
2256 +- uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
2257 +-
2258 +- return !(val & ~valid_bits);
2259 +-}
2260 +-
2261 +-static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
2262 +-{
2263 +- switch (msr->index) {
2264 +- case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2265 +- if (!nested)
2266 +- return 1;
2267 +- return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
2268 +- default:
2269 +- return 1;
2270 +- }
2271 +-}
2272 +-
2273 +-/*
2274 +- * Reads an msr value (of 'msr_index') into 'pdata'.
2275 +- * Returns 0 on success, non-0 otherwise.
2276 +- * Assumes vcpu_load() was already called.
2277 +- */
2278 +-static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2279 +-{
2280 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
2281 +- struct shared_msr_entry *msr;
2282 +- u32 index;
2283 +-
2284 +- switch (msr_info->index) {
2285 +-#ifdef CONFIG_X86_64
2286 +- case MSR_FS_BASE:
2287 +- msr_info->data = vmcs_readl(GUEST_FS_BASE);
2288 +- break;
2289 +- case MSR_GS_BASE:
2290 +- msr_info->data = vmcs_readl(GUEST_GS_BASE);
2291 +- break;
2292 +- case MSR_KERNEL_GS_BASE:
2293 +- msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
2294 +- break;
2295 +-#endif
2296 +- case MSR_EFER:
2297 +- return kvm_get_msr_common(vcpu, msr_info);
2298 +- case MSR_IA32_TSX_CTRL:
2299 +- if (!msr_info->host_initiated &&
2300 +- !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2301 +- return 1;
2302 +- goto find_shared_msr;
2303 +- case MSR_IA32_UMWAIT_CONTROL:
2304 +- if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2305 +- return 1;
2306 +-
2307 +- msr_info->data = vmx->msr_ia32_umwait_control;
2308 +- break;
2309 +- case MSR_IA32_SPEC_CTRL:
2310 +- if (!msr_info->host_initiated &&
2311 +- !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2312 +- return 1;
2313 +-
2314 +- msr_info->data = to_vmx(vcpu)->spec_ctrl;
2315 +- break;
2316 +- case MSR_IA32_SYSENTER_CS:
2317 +- msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2318 +- break;
2319 +- case MSR_IA32_SYSENTER_EIP:
2320 +- msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2321 +- break;
2322 +- case MSR_IA32_SYSENTER_ESP:
2323 +- msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2324 +- break;
2325 +- case MSR_IA32_BNDCFGS:
2326 +- if (!kvm_mpx_supported() ||
2327 +- (!msr_info->host_initiated &&
2328 +- !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2329 +- return 1;
2330 +- msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2331 +- break;
2332 +- case MSR_IA32_MCG_EXT_CTL:
2333 +- if (!msr_info->host_initiated &&
2334 +- !(vmx->msr_ia32_feature_control &
2335 +- FEATURE_CONTROL_LMCE))
2336 +- return 1;
2337 +- msr_info->data = vcpu->arch.mcg_ext_ctl;
2338 +- break;
2339 +- case MSR_IA32_FEATURE_CONTROL:
2340 +- msr_info->data = vmx->msr_ia32_feature_control;
2341 +- break;
2342 +- case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2343 +- if (!nested_vmx_allowed(vcpu))
2344 +- return 1;
2345 +- return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
2346 +- &msr_info->data);
2347 +- case MSR_IA32_RTIT_CTL:
2348 +- if (pt_mode != PT_MODE_HOST_GUEST)
2349 +- return 1;
2350 +- msr_info->data = vmx->pt_desc.guest.ctl;
2351 +- break;
2352 +- case MSR_IA32_RTIT_STATUS:
2353 +- if (pt_mode != PT_MODE_HOST_GUEST)
2354 +- return 1;
2355 +- msr_info->data = vmx->pt_desc.guest.status;
2356 +- break;
2357 +- case MSR_IA32_RTIT_CR3_MATCH:
2358 +- if ((pt_mode != PT_MODE_HOST_GUEST) ||
2359 +- !intel_pt_validate_cap(vmx->pt_desc.caps,
2360 +- PT_CAP_cr3_filtering))
2361 +- return 1;
2362 +- msr_info->data = vmx->pt_desc.guest.cr3_match;
2363 +- break;
2364 +- case MSR_IA32_RTIT_OUTPUT_BASE:
2365 +- if ((pt_mode != PT_MODE_HOST_GUEST) ||
2366 +- (!intel_pt_validate_cap(vmx->pt_desc.caps,
2367 +- PT_CAP_topa_output) &&
2368 +- !intel_pt_validate_cap(vmx->pt_desc.caps,
2369 +- PT_CAP_single_range_output)))
2370 +- return 1;
2371 +- msr_info->data = vmx->pt_desc.guest.output_base;
2372 +- break;
2373 +- case MSR_IA32_RTIT_OUTPUT_MASK:
2374 +- if ((pt_mode != PT_MODE_HOST_GUEST) ||
2375 +- (!intel_pt_validate_cap(vmx->pt_desc.caps,
2376 +- PT_CAP_topa_output) &&
2377 +- !intel_pt_validate_cap(vmx->pt_desc.caps,
2378 +- PT_CAP_single_range_output)))
2379 +- return 1;
2380 +- msr_info->data = vmx->pt_desc.guest.output_mask;
2381 +- break;
2382 +- case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2383 +- index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2384 +- if ((pt_mode != PT_MODE_HOST_GUEST) ||
2385 +- (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2386 +- PT_CAP_num_address_ranges)))
2387 +- return 1;
2388 +- if (is_noncanonical_address(data, vcpu))
2389 +- return 1;
2390 +- if (index % 2)
2391 +- msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
2392 +- else
2393 +- msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
2394 +- break;
2395 +- case MSR_TSC_AUX:
2396 +- if (!msr_info->host_initiated &&
2397 +- !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2398 +- return 1;
2399 +- goto find_shared_msr;
2400 +- default:
2401 +- find_shared_msr:
2402 +- msr = find_msr_entry(vmx, msr_info->index);
2403 +- if (msr) {
2404 +- msr_info->data = msr->data;
2405 +- break;
2406 +- }
2407 +- return kvm_get_msr_common(vcpu, msr_info);
2408 +- }
2409 +-
2410 +- return 0;
2411 +-}
2412 +-
2413 +-/*
2414 +- * Writes msr value into the appropriate "register".
2415 +- * Returns 0 on success, non-0 otherwise.
2416 +- * Assumes vcpu_load() was already called.
2417 +- */
2418 +-static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2419 +-{
2420 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
2421 +- struct shared_msr_entry *msr;
2422 +- int ret = 0;
2423 +- u32 msr_index = msr_info->index;
2424 +- u64 data = msr_info->data;
2425 +- u32 index;
2426 +-
2427 +- switch (msr_index) {
2428 +- case MSR_EFER:
2429 +- ret = kvm_set_msr_common(vcpu, msr_info);
2430 +- break;
2431 +-#ifdef CONFIG_X86_64
2432 +- case MSR_FS_BASE:
2433 +- vmx_segment_cache_clear(vmx);
2434 +- vmcs_writel(GUEST_FS_BASE, data);
2435 +- break;
2436 +- case MSR_GS_BASE:
2437 +- vmx_segment_cache_clear(vmx);
2438 +- vmcs_writel(GUEST_GS_BASE, data);
2439 +- break;
2440 +- case MSR_KERNEL_GS_BASE:
2441 +- vmx_write_guest_kernel_gs_base(vmx, data);
2442 +- break;
2443 +-#endif
2444 +- case MSR_IA32_SYSENTER_CS:
2445 +- if (is_guest_mode(vcpu))
2446 +- get_vmcs12(vcpu)->guest_sysenter_cs = data;
2447 +- vmcs_write32(GUEST_SYSENTER_CS, data);
2448 +- break;
2449 +- case MSR_IA32_SYSENTER_EIP:
2450 +- if (is_guest_mode(vcpu))
2451 +- get_vmcs12(vcpu)->guest_sysenter_eip = data;
2452 +- vmcs_writel(GUEST_SYSENTER_EIP, data);
2453 +- break;
2454 +- case MSR_IA32_SYSENTER_ESP:
2455 +- if (is_guest_mode(vcpu))
2456 +- get_vmcs12(vcpu)->guest_sysenter_esp = data;
2457 +- vmcs_writel(GUEST_SYSENTER_ESP, data);
2458 +- break;
2459 +- case MSR_IA32_DEBUGCTLMSR:
2460 +- if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
2461 +- VM_EXIT_SAVE_DEBUG_CONTROLS)
2462 +- get_vmcs12(vcpu)->guest_ia32_debugctl = data;
2463 +-
2464 +- ret = kvm_set_msr_common(vcpu, msr_info);
2465 +- break;
2466 +-
2467 +- case MSR_IA32_BNDCFGS:
2468 +- if (!kvm_mpx_supported() ||
2469 +- (!msr_info->host_initiated &&
2470 +- !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2471 +- return 1;
2472 +- if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
2473 +- (data & MSR_IA32_BNDCFGS_RSVD))
2474 +- return 1;
2475 +- vmcs_write64(GUEST_BNDCFGS, data);
2476 +- break;
2477 +- case MSR_IA32_UMWAIT_CONTROL:
2478 +- if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2479 +- return 1;
2480 +-
2481 +- /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2482 +- if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2483 +- return 1;
2484 +-
2485 +- vmx->msr_ia32_umwait_control = data;
2486 +- break;
2487 +- case MSR_IA32_SPEC_CTRL:
2488 +- if (!msr_info->host_initiated &&
2489 +- !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2490 +- return 1;
2491 +-
2492 +- /* The STIBP bit doesn't fault even if it's not advertised */
2493 +- if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
2494 +- return 1;
2495 +-
2496 +- vmx->spec_ctrl = data;
2497 +-
2498 +- if (!data)
2499 +- break;
2500 +-
2501 +- /*
2502 +- * For non-nested:
2503 +- * When it's written (to non-zero) for the first time, pass
2504 +- * it through.
2505 +- *
2506 +- * For nested:
2507 +- * The handling of the MSR bitmap for L2 guests is done in
2508 +- * nested_vmx_prepare_msr_bitmap. We should not touch the
2509 +- * vmcs02.msr_bitmap here since it gets completely overwritten
2510 +- * in the merging. We update the vmcs01 here for L1 as well
2511 +- * since it will end up touching the MSR anyway now.
2512 +- */
2513 +- vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2514 +- MSR_IA32_SPEC_CTRL,
2515 +- MSR_TYPE_RW);
2516 +- break;
2517 +- case MSR_IA32_TSX_CTRL:
2518 +- if (!msr_info->host_initiated &&
2519 +- !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2520 +- return 1;
2521 +- if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2522 +- return 1;
2523 +- goto find_shared_msr;
2524 +- case MSR_IA32_PRED_CMD:
2525 +- if (!msr_info->host_initiated &&
2526 +- !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2527 +- return 1;
2528 +-
2529 +- if (data & ~PRED_CMD_IBPB)
2530 +- return 1;
2531 +-
2532 +- if (!data)
2533 +- break;
2534 +-
2535 +- wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2536 +-
2537 +- /*
2538 +- * For non-nested:
2539 +- * When it's written (to non-zero) for the first time, pass
2540 +- * it through.
2541 +- *
2542 +- * For nested:
2543 +- * The handling of the MSR bitmap for L2 guests is done in
2544 +- * nested_vmx_prepare_msr_bitmap. We should not touch the
2545 +- * vmcs02.msr_bitmap here since it gets completely overwritten
2546 +- * in the merging.
2547 +- */
2548 +- vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2549 +- MSR_TYPE_W);
2550 +- break;
2551 +- case MSR_IA32_CR_PAT:
2552 +- if (!kvm_pat_valid(data))
2553 +- return 1;
2554 +-
2555 +- if (is_guest_mode(vcpu) &&
2556 +- get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2557 +- get_vmcs12(vcpu)->guest_ia32_pat = data;
2558 +-
2559 +- if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2560 +- vmcs_write64(GUEST_IA32_PAT, data);
2561 +- vcpu->arch.pat = data;
2562 +- break;
2563 +- }
2564 +- ret = kvm_set_msr_common(vcpu, msr_info);
2565 +- break;
2566 +- case MSR_IA32_TSC_ADJUST:
2567 +- ret = kvm_set_msr_common(vcpu, msr_info);
2568 +- break;
2569 +- case MSR_IA32_MCG_EXT_CTL:
2570 +- if ((!msr_info->host_initiated &&
2571 +- !(to_vmx(vcpu)->msr_ia32_feature_control &
2572 +- FEATURE_CONTROL_LMCE)) ||
2573 +- (data & ~MCG_EXT_CTL_LMCE_EN))
2574 +- return 1;
2575 +- vcpu->arch.mcg_ext_ctl = data;
2576 +- break;
2577 +- case MSR_IA32_FEATURE_CONTROL:
2578 +- if (!vmx_feature_control_msr_valid(vcpu, data) ||
2579 +- (to_vmx(vcpu)->msr_ia32_feature_control &
2580 +- FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2581 +- return 1;
2582 +- vmx->msr_ia32_feature_control = data;
2583 +- if (msr_info->host_initiated && data == 0)
2584 +- vmx_leave_nested(vcpu);
2585 +- break;
2586 +- case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2587 +- if (!msr_info->host_initiated)
2588 +- return 1; /* they are read-only */
2589 +- if (!nested_vmx_allowed(vcpu))
2590 +- return 1;
2591 +- return vmx_set_vmx_msr(vcpu, msr_index, data);
2592 +- case MSR_IA32_RTIT_CTL:
2593 +- if ((pt_mode != PT_MODE_HOST_GUEST) ||
2594 +- vmx_rtit_ctl_check(vcpu, data) ||
2595 +- vmx->nested.vmxon)
2596 +- return 1;
2597 +- vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2598 +- vmx->pt_desc.guest.ctl = data;
2599 +- pt_update_intercept_for_msr(vmx);
2600 +- break;
2601 +- case MSR_IA32_RTIT_STATUS:
2602 +- if ((pt_mode != PT_MODE_HOST_GUEST) ||
2603 +- (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2604 +- (data & MSR_IA32_RTIT_STATUS_MASK))
2605 +- return 1;
2606 +- vmx->pt_desc.guest.status = data;
2607 +- break;
2608 +- case MSR_IA32_RTIT_CR3_MATCH:
2609 +- if ((pt_mode != PT_MODE_HOST_GUEST) ||
2610 +- (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2611 +- !intel_pt_validate_cap(vmx->pt_desc.caps,
2612 +- PT_CAP_cr3_filtering))
2613 +- return 1;
2614 +- vmx->pt_desc.guest.cr3_match = data;
2615 +- break;
2616 +- case MSR_IA32_RTIT_OUTPUT_BASE:
2617 +- if ((pt_mode != PT_MODE_HOST_GUEST) ||
2618 +- (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2619 +- (!intel_pt_validate_cap(vmx->pt_desc.caps,
2620 +- PT_CAP_topa_output) &&
2621 +- !intel_pt_validate_cap(vmx->pt_desc.caps,
2622 +- PT_CAP_single_range_output)) ||
2623 +- (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
2624 +- return 1;
2625 +- vmx->pt_desc.guest.output_base = data;
2626 +- break;
2627 +- case MSR_IA32_RTIT_OUTPUT_MASK:
2628 +- if ((pt_mode != PT_MODE_HOST_GUEST) ||
2629 +- (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2630 +- (!intel_pt_validate_cap(vmx->pt_desc.caps,
2631 +- PT_CAP_topa_output) &&
2632 +- !intel_pt_validate_cap(vmx->pt_desc.caps,
2633 +- PT_CAP_single_range_output)))
2634 +- return 1;
2635 +- vmx->pt_desc.guest.output_mask = data;
2636 +- break;
2637 +- case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2638 +- index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2639 +- if ((pt_mode != PT_MODE_HOST_GUEST) ||
2640 +- (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2641 +- (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2642 +- PT_CAP_num_address_ranges)))
2643 +- return 1;
2644 +- if (is_noncanonical_address(data, vcpu))
2645 +- return 1;
2646 +- if (index % 2)
2647 +- vmx->pt_desc.guest.addr_b[index / 2] = data;
2648 +- else
2649 +- vmx->pt_desc.guest.addr_a[index / 2] = data;
2650 +- break;
2651 +- case MSR_TSC_AUX:
2652 +- if (!msr_info->host_initiated &&
2653 +- !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2654 +- return 1;
2655 +- /* Check reserved bit, higher 32 bits should be zero */
2656 +- if ((data >> 32) != 0)
2657 +- return 1;
2658 +- goto find_shared_msr;
2659 +-
2660 +- default:
2661 +- find_shared_msr:
2662 +- msr = find_msr_entry(vmx, msr_index);
2663 +- if (msr)
2664 +- ret = vmx_set_guest_msr(vmx, msr, data);
2665 +- else
2666 +- ret = kvm_set_msr_common(vcpu, msr_info);
2667 +- }
2668 +-
2669 +- return ret;
2670 +-}
2671 +-
2672 +-static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2673 +-{
2674 +- kvm_register_mark_available(vcpu, reg);
2675 +-
2676 +- switch (reg) {
2677 +- case VCPU_REGS_RSP:
2678 +- vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2679 +- break;
2680 +- case VCPU_REGS_RIP:
2681 +- vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2682 +- break;
2683 +- case VCPU_EXREG_PDPTR:
2684 +- if (enable_ept)
2685 +- ept_save_pdptrs(vcpu);
2686 +- break;
2687 +- case VCPU_EXREG_CR3:
2688 +- if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2689 +- vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2690 +- break;
2691 +- default:
2692 +- WARN_ON_ONCE(1);
2693 +- break;
2694 +- }
2695 +-}
2696 +-
2697 +-static __init int cpu_has_kvm_support(void)
2698 +-{
2699 +- return cpu_has_vmx();
2700 +-}
2701 +-
2702 +-static __init int vmx_disabled_by_bios(void)
2703 +-{
2704 +- u64 msr;
2705 +-
2706 +- rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2707 +- if (msr & FEATURE_CONTROL_LOCKED) {
2708 +- /* launched w/ TXT and VMX disabled */
2709 +- if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2710 +- && tboot_enabled())
2711 +- return 1;
2712 +- /* launched w/o TXT and VMX only enabled w/ TXT */
2713 +- if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2714 +- && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2715 +- && !tboot_enabled()) {
2716 +- printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2717 +- "activate TXT before enabling KVM\n");
2718 +- return 1;
2719 +- }
2720 +- /* launched w/o TXT and VMX disabled */
2721 +- if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2722 +- && !tboot_enabled())
2723 +- return 1;
2724 +- }
2725 +-
2726 +- return 0;
2727 +-}
2728 +-
2729 +-static void kvm_cpu_vmxon(u64 addr)
2730 +-{
2731 +- cr4_set_bits(X86_CR4_VMXE);
2732 +- intel_pt_handle_vmx(1);
2733 +-
2734 +- asm volatile ("vmxon %0" : : "m"(addr));
2735 +-}
2736 +-
2737 +-static int hardware_enable(void)
2738 +-{
2739 +- int cpu = raw_smp_processor_id();
2740 +- u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2741 +- u64 old, test_bits;
2742 +-
2743 +- if (cr4_read_shadow() & X86_CR4_VMXE)
2744 +- return -EBUSY;
2745 +-
2746 +- /*
2747 +- * This can happen if we hot-added a CPU but failed to allocate
2748 +- * VP assist page for it.
2749 +- */
2750 +- if (static_branch_unlikely(&enable_evmcs) &&
2751 +- !hv_get_vp_assist_page(cpu))
2752 +- return -EFAULT;
2753 +-
2754 +- INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2755 +- INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2756 +- spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
2757 +-
2758 +- /*
2759 +- * Now we can enable the vmclear operation in kdump
2760 +- * since the loaded_vmcss_on_cpu list on this cpu
2761 +- * has been initialized.
2762 +- *
2763 +- * Though the cpu is not in VMX operation now, there
2764 +- * is no problem to enable the vmclear operation
2765 +- * for the loaded_vmcss_on_cpu list is empty!
2766 +- */
2767 +- crash_enable_local_vmclear(cpu);
2768 +-
2769 +- rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2770 +-
2771 +- test_bits = FEATURE_CONTROL_LOCKED;
2772 +- test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2773 +- if (tboot_enabled())
2774 +- test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2775 +-
2776 +- if ((old & test_bits) != test_bits) {
2777 +- /* enable and lock */
2778 +- wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2779 +- }
2780 +- kvm_cpu_vmxon(phys_addr);
2781 +- if (enable_ept)
2782 +- ept_sync_global();
2783 +-
2784 +- return 0;
2785 +-}
2786 +-
2787 +-static void vmclear_local_loaded_vmcss(void)
2788 +-{
2789 +- int cpu = raw_smp_processor_id();
2790 +- struct loaded_vmcs *v, *n;
2791 +-
2792 +- list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2793 +- loaded_vmcss_on_cpu_link)
2794 +- __loaded_vmcs_clear(v);
2795 +-}
2796 +-
2797 +-
2798 +-/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2799 +- * tricks.
2800 +- */
2801 +-static void kvm_cpu_vmxoff(void)
2802 +-{
2803 +- asm volatile (__ex("vmxoff"));
2804 +-
2805 +- intel_pt_handle_vmx(0);
2806 +- cr4_clear_bits(X86_CR4_VMXE);
2807 +-}
2808 +-
2809 +-static void hardware_disable(void)
2810 +-{
2811 +- vmclear_local_loaded_vmcss();
2812 +- kvm_cpu_vmxoff();
2813 +-}
2814 +-
2815 +-static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2816 +- u32 msr, u32 *result)
2817 +-{
2818 +- u32 vmx_msr_low, vmx_msr_high;
2819 +- u32 ctl = ctl_min | ctl_opt;
2820 +-
2821 +- rdmsr(msr, vmx_msr_low, vmx_msr_high);
2822 +-
2823 +- ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2824 +- ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2825 +-
2826 +- /* Ensure minimum (required) set of control bits are supported. */
2827 +- if (ctl_min & ~ctl)
2828 +- return -EIO;
2829 +-
2830 +- *result = ctl;
2831 +- return 0;
2832 +-}
2833 +-
2834 +-static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2835 +- struct vmx_capability *vmx_cap)
2836 +-{
2837 +- u32 vmx_msr_low, vmx_msr_high;
2838 +- u32 min, opt, min2, opt2;
2839 +- u32 _pin_based_exec_control = 0;
2840 +- u32 _cpu_based_exec_control = 0;
2841 +- u32 _cpu_based_2nd_exec_control = 0;
2842 +- u32 _vmexit_control = 0;
2843 +- u32 _vmentry_control = 0;
2844 +-
2845 +- memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2846 +- min = CPU_BASED_HLT_EXITING |
2847 +-#ifdef CONFIG_X86_64
2848 +- CPU_BASED_CR8_LOAD_EXITING |
2849 +- CPU_BASED_CR8_STORE_EXITING |
2850 +-#endif
2851 +- CPU_BASED_CR3_LOAD_EXITING |
2852 +- CPU_BASED_CR3_STORE_EXITING |
2853 +- CPU_BASED_UNCOND_IO_EXITING |
2854 +- CPU_BASED_MOV_DR_EXITING |
2855 +- CPU_BASED_USE_TSC_OFFSETTING |
2856 +- CPU_BASED_MWAIT_EXITING |
2857 +- CPU_BASED_MONITOR_EXITING |
2858 +- CPU_BASED_INVLPG_EXITING |
2859 +- CPU_BASED_RDPMC_EXITING;
2860 +-
2861 +- opt = CPU_BASED_TPR_SHADOW |
2862 +- CPU_BASED_USE_MSR_BITMAPS |
2863 +- CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2864 +- if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2865 +- &_cpu_based_exec_control) < 0)
2866 +- return -EIO;
2867 +-#ifdef CONFIG_X86_64
2868 +- if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2869 +- _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2870 +- ~CPU_BASED_CR8_STORE_EXITING;
2871 +-#endif
2872 +- if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2873 +- min2 = 0;
2874 +- opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2875 +- SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2876 +- SECONDARY_EXEC_WBINVD_EXITING |
2877 +- SECONDARY_EXEC_ENABLE_VPID |
2878 +- SECONDARY_EXEC_ENABLE_EPT |
2879 +- SECONDARY_EXEC_UNRESTRICTED_GUEST |
2880 +- SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2881 +- SECONDARY_EXEC_DESC |
2882 +- SECONDARY_EXEC_RDTSCP |
2883 +- SECONDARY_EXEC_ENABLE_INVPCID |
2884 +- SECONDARY_EXEC_APIC_REGISTER_VIRT |
2885 +- SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2886 +- SECONDARY_EXEC_SHADOW_VMCS |
2887 +- SECONDARY_EXEC_XSAVES |
2888 +- SECONDARY_EXEC_RDSEED_EXITING |
2889 +- SECONDARY_EXEC_RDRAND_EXITING |
2890 +- SECONDARY_EXEC_ENABLE_PML |
2891 +- SECONDARY_EXEC_TSC_SCALING |
2892 +- SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2893 +- SECONDARY_EXEC_PT_USE_GPA |
2894 +- SECONDARY_EXEC_PT_CONCEAL_VMX |
2895 +- SECONDARY_EXEC_ENABLE_VMFUNC |
2896 +- SECONDARY_EXEC_ENCLS_EXITING;
2897 +- if (adjust_vmx_controls(min2, opt2,
2898 +- MSR_IA32_VMX_PROCBASED_CTLS2,
2899 +- &_cpu_based_2nd_exec_control) < 0)
2900 +- return -EIO;
2901 +- }
2902 +-#ifndef CONFIG_X86_64
2903 +- if (!(_cpu_based_2nd_exec_control &
2904 +- SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2905 +- _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2906 +-#endif
2907 +-
2908 +- if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2909 +- _cpu_based_2nd_exec_control &= ~(
2910 +- SECONDARY_EXEC_APIC_REGISTER_VIRT |
2911 +- SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2912 +- SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2913 +-
2914 +- rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2915 +- &vmx_cap->ept, &vmx_cap->vpid);
2916 +-
2917 +- if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2918 +- /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2919 +- enabled */
2920 +- _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2921 +- CPU_BASED_CR3_STORE_EXITING |
2922 +- CPU_BASED_INVLPG_EXITING);
2923 +- } else if (vmx_cap->ept) {
2924 +- vmx_cap->ept = 0;
2925 +- pr_warn_once("EPT CAP should not exist if not support "
2926 +- "1-setting enable EPT VM-execution control\n");
2927 +- }
2928 +- if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2929 +- vmx_cap->vpid) {
2930 +- vmx_cap->vpid = 0;
2931 +- pr_warn_once("VPID CAP should not exist if not support "
2932 +- "1-setting enable VPID VM-execution control\n");
2933 +- }
2934 +-
2935 +- min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2936 +-#ifdef CONFIG_X86_64
2937 +- min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2938 +-#endif
2939 +- opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2940 +- VM_EXIT_LOAD_IA32_PAT |
2941 +- VM_EXIT_LOAD_IA32_EFER |
2942 +- VM_EXIT_CLEAR_BNDCFGS |
2943 +- VM_EXIT_PT_CONCEAL_PIP |
2944 +- VM_EXIT_CLEAR_IA32_RTIT_CTL;
2945 +- if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2946 +- &_vmexit_control) < 0)
2947 +- return -EIO;
2948 +-
2949 +- min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2950 +- opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2951 +- PIN_BASED_VMX_PREEMPTION_TIMER;
2952 +- if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2953 +- &_pin_based_exec_control) < 0)
2954 +- return -EIO;
2955 +-
2956 +- if (cpu_has_broken_vmx_preemption_timer())
2957 +- _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2958 +- if (!(_cpu_based_2nd_exec_control &
2959 +- SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2960 +- _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2961 +-
2962 +- min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2963 +- opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2964 +- VM_ENTRY_LOAD_IA32_PAT |
2965 +- VM_ENTRY_LOAD_IA32_EFER |
2966 +- VM_ENTRY_LOAD_BNDCFGS |
2967 +- VM_ENTRY_PT_CONCEAL_PIP |
2968 +- VM_ENTRY_LOAD_IA32_RTIT_CTL;
2969 +- if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2970 +- &_vmentry_control) < 0)
2971 +- return -EIO;
2972 +-
2973 +- /*
2974 +- * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2975 +- * can't be used due to an errata where VM Exit may incorrectly clear
2976 +- * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2977 +- * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2978 +- */
2979 +- if (boot_cpu_data.x86 == 0x6) {
2980 +- switch (boot_cpu_data.x86_model) {
2981 +- case 26: /* AAK155 */
2982 +- case 30: /* AAP115 */
2983 +- case 37: /* AAT100 */
2984 +- case 44: /* BC86,AAY89,BD102 */
2985 +- case 46: /* BA97 */
2986 +- _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2987 +- _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2988 +- pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2989 +- "does not work properly. Using workaround\n");
2990 +- break;
2991 +- default:
2992 +- break;
2993 +- }
2994 +- }
2995 +-
2996 +-
2997 +- rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2998 +-
2999 +- /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3000 +- if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3001 +- return -EIO;
3002 +-
3003 +-#ifdef CONFIG_X86_64
3004 +- /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3005 +- if (vmx_msr_high & (1u<<16))
3006 +- return -EIO;
3007 +-#endif
3008 +-
3009 +- /* Require Write-Back (WB) memory type for VMCS accesses. */
3010 +- if (((vmx_msr_high >> 18) & 15) != 6)
3011 +- return -EIO;
3012 +-
3013 +- vmcs_conf->size = vmx_msr_high & 0x1fff;
3014 +- vmcs_conf->order = get_order(vmcs_conf->size);
3015 +- vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3016 +-
3017 +- vmcs_conf->revision_id = vmx_msr_low;
3018 +-
3019 +- vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3020 +- vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3021 +- vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3022 +- vmcs_conf->vmexit_ctrl = _vmexit_control;
3023 +- vmcs_conf->vmentry_ctrl = _vmentry_control;
3024 +-
3025 +- if (static_branch_unlikely(&enable_evmcs))
3026 +- evmcs_sanitize_exec_ctrls(vmcs_conf);
3027 +-
3028 +- return 0;
3029 +-}
3030 +-
3031 +-struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
3032 +-{
3033 +- int node = cpu_to_node(cpu);
3034 +- struct page *pages;
3035 +- struct vmcs *vmcs;
3036 +-
3037 +- pages = __alloc_pages_node(node, flags, vmcs_config.order);
3038 +- if (!pages)
3039 +- return NULL;
3040 +- vmcs = page_address(pages);
3041 +- memset(vmcs, 0, vmcs_config.size);
3042 +-
3043 +- /* KVM supports Enlightened VMCS v1 only */
3044 +- if (static_branch_unlikely(&enable_evmcs))
3045 +- vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
3046 +- else
3047 +- vmcs->hdr.revision_id = vmcs_config.revision_id;
3048 +-
3049 +- if (shadow)
3050 +- vmcs->hdr.shadow_vmcs = 1;
3051 +- return vmcs;
3052 +-}
3053 +-
3054 +-void free_vmcs(struct vmcs *vmcs)
3055 +-{
3056 +- free_pages((unsigned long)vmcs, vmcs_config.order);
3057 +-}
3058 +-
3059 +-/*
3060 +- * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3061 +- */
3062 +-void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3063 +-{
3064 +- if (!loaded_vmcs->vmcs)
3065 +- return;
3066 +- loaded_vmcs_clear(loaded_vmcs);
3067 +- free_vmcs(loaded_vmcs->vmcs);
3068 +- loaded_vmcs->vmcs = NULL;
3069 +- if (loaded_vmcs->msr_bitmap)
3070 +- free_page((unsigned long)loaded_vmcs->msr_bitmap);
3071 +- WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3072 +-}
3073 +-
3074 +-int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3075 +-{
3076 +- loaded_vmcs->vmcs = alloc_vmcs(false);
3077 +- if (!loaded_vmcs->vmcs)
3078 +- return -ENOMEM;
3079 +-
3080 +- loaded_vmcs->shadow_vmcs = NULL;
3081 +- loaded_vmcs->hv_timer_soft_disabled = false;
3082 +- loaded_vmcs_init(loaded_vmcs);
3083 +-
3084 +- if (cpu_has_vmx_msr_bitmap()) {
3085 +- loaded_vmcs->msr_bitmap = (unsigned long *)
3086 +- __get_free_page(GFP_KERNEL_ACCOUNT);
3087 +- if (!loaded_vmcs->msr_bitmap)
3088 +- goto out_vmcs;
3089 +- memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
3090 +-
3091 +- if (IS_ENABLED(CONFIG_HYPERV) &&
3092 +- static_branch_unlikely(&enable_evmcs) &&
3093 +- (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
3094 +- struct hv_enlightened_vmcs *evmcs =
3095 +- (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
3096 +-
3097 +- evmcs->hv_enlightenments_control.msr_bitmap = 1;
3098 +- }
3099 +- }
3100 +-
3101 +- memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
3102 +- memset(&loaded_vmcs->controls_shadow, 0,
3103 +- sizeof(struct vmcs_controls_shadow));
3104 +-
3105 +- return 0;
3106 +-
3107 +-out_vmcs:
3108 +- free_loaded_vmcs(loaded_vmcs);
3109 +- return -ENOMEM;
3110 +-}
3111 +-
3112 +-static void free_kvm_area(void)
3113 +-{
3114 +- int cpu;
3115 +-
3116 +- for_each_possible_cpu(cpu) {
3117 +- free_vmcs(per_cpu(vmxarea, cpu));
3118 +- per_cpu(vmxarea, cpu) = NULL;
3119 +- }
3120 +-}
3121 +-
3122 +-static __init int alloc_kvm_area(void)
3123 +-{
3124 +- int cpu;
3125 +-
3126 +- for_each_possible_cpu(cpu) {
3127 +- struct vmcs *vmcs;
3128 +-
3129 +- vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
3130 +- if (!vmcs) {
3131 +- free_kvm_area();
3132 +- return -ENOMEM;
3133 +- }
3134 +-
3135 +- /*
3136 +- * When eVMCS is enabled, alloc_vmcs_cpu() sets
3137 +- * vmcs->revision_id to KVM_EVMCS_VERSION instead of
3138 +- * revision_id reported by MSR_IA32_VMX_BASIC.
3139 +- *
3140 +- * However, even though not explicitly documented by
3141 +- * TLFS, VMXArea passed as VMXON argument should
3142 +- * still be marked with revision_id reported by
3143 +- * physical CPU.
3144 +- */
3145 +- if (static_branch_unlikely(&enable_evmcs))
3146 +- vmcs->hdr.revision_id = vmcs_config.revision_id;
3147 +-
3148 +- per_cpu(vmxarea, cpu) = vmcs;
3149 +- }
3150 +- return 0;
3151 +-}
3152 +-
3153 +-static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3154 +- struct kvm_segment *save)
3155 +-{
3156 +- if (!emulate_invalid_guest_state) {
3157 +- /*
3158 +- * CS and SS RPL should be equal during guest entry according
3159 +- * to VMX spec, but in reality it is not always so. Since vcpu
3160 +- * is in the middle of the transition from real mode to
3161 +- * protected mode it is safe to assume that RPL 0 is a good
3162 +- * default value.
3163 +- */
3164 +- if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3165 +- save->selector &= ~SEGMENT_RPL_MASK;
3166 +- save->dpl = save->selector & SEGMENT_RPL_MASK;
3167 +- save->s = 1;
3168 +- }
3169 +- vmx_set_segment(vcpu, save, seg);
3170 +-}
3171 +-
3172 +-static void enter_pmode(struct kvm_vcpu *vcpu)
3173 +-{
3174 +- unsigned long flags;
3175 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
3176 +-
3177 +- /*
3178 +- * Update real mode segment cache. It may be not up-to-date if sement
3179 +- * register was written while vcpu was in a guest mode.
3180 +- */
3181 +- vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3182 +- vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3183 +- vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3184 +- vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3185 +- vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3186 +- vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3187 +-
3188 +- vmx->rmode.vm86_active = 0;
3189 +-
3190 +- vmx_segment_cache_clear(vmx);
3191 +-
3192 +- vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3193 +-
3194 +- flags = vmcs_readl(GUEST_RFLAGS);
3195 +- flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3196 +- flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3197 +- vmcs_writel(GUEST_RFLAGS, flags);
3198 +-
3199 +- vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3200 +- (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3201 +-
3202 +- update_exception_bitmap(vcpu);
3203 +-
3204 +- fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3205 +- fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3206 +- fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3207 +- fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3208 +- fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3209 +- fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3210 +-}
3211 +-
3212 +-static void fix_rmode_seg(int seg, struct kvm_segment *save)
3213 +-{
3214 +- const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3215 +- struct kvm_segment var = *save;
3216 +-
3217 +- var.dpl = 0x3;
3218 +- if (seg == VCPU_SREG_CS)
3219 +- var.type = 0x3;
3220 +-
3221 +- if (!emulate_invalid_guest_state) {
3222 +- var.selector = var.base >> 4;
3223 +- var.base = var.base & 0xffff0;
3224 +- var.limit = 0xffff;
3225 +- var.g = 0;
3226 +- var.db = 0;
3227 +- var.present = 1;
3228 +- var.s = 1;
3229 +- var.l = 0;
3230 +- var.unusable = 0;
3231 +- var.type = 0x3;
3232 +- var.avl = 0;
3233 +- if (save->base & 0xf)
3234 +- printk_once(KERN_WARNING "kvm: segment base is not "
3235 +- "paragraph aligned when entering "
3236 +- "protected mode (seg=%d)", seg);
3237 +- }
3238 +-
3239 +- vmcs_write16(sf->selector, var.selector);
3240 +- vmcs_writel(sf->base, var.base);
3241 +- vmcs_write32(sf->limit, var.limit);
3242 +- vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3243 +-}
3244 +-
3245 +-static void enter_rmode(struct kvm_vcpu *vcpu)
3246 +-{
3247 +- unsigned long flags;
3248 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
3249 +- struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
3250 +-
3251 +- vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3252 +- vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3253 +- vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3254 +- vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3255 +- vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3256 +- vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3257 +- vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3258 +-
3259 +- vmx->rmode.vm86_active = 1;
3260 +-
3261 +- /*
3262 +- * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3263 +- * vcpu. Warn the user that an update is overdue.
3264 +- */
3265 +- if (!kvm_vmx->tss_addr)
3266 +- printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3267 +- "called before entering vcpu\n");
3268 +-
3269 +- vmx_segment_cache_clear(vmx);
3270 +-
3271 +- vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
3272 +- vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3273 +- vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3274 +-
3275 +- flags = vmcs_readl(GUEST_RFLAGS);
3276 +- vmx->rmode.save_rflags = flags;
3277 +-
3278 +- flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3279 +-
3280 +- vmcs_writel(GUEST_RFLAGS, flags);
3281 +- vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3282 +- update_exception_bitmap(vcpu);
3283 +-
3284 +- fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3285 +- fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3286 +- fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3287 +- fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3288 +- fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3289 +- fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3290 +-
3291 +- kvm_mmu_reset_context(vcpu);
3292 +-}
3293 +-
3294 +-void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3295 +-{
3296 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
3297 +- struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3298 +-
3299 +- if (!msr)
3300 +- return;
3301 +-
3302 +- vcpu->arch.efer = efer;
3303 +- if (efer & EFER_LMA) {
3304 +- vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3305 +- msr->data = efer;
3306 +- } else {
3307 +- vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3308 +-
3309 +- msr->data = efer & ~EFER_LME;
3310 +- }
3311 +- setup_msrs(vmx);
3312 +-}
3313 +-
3314 +-#ifdef CONFIG_X86_64
3315 +-
3316 +-static void enter_lmode(struct kvm_vcpu *vcpu)
3317 +-{
3318 +- u32 guest_tr_ar;
3319 +-
3320 +- vmx_segment_cache_clear(to_vmx(vcpu));
3321 +-
3322 +- guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3323 +- if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3324 +- pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3325 +- __func__);
3326 +- vmcs_write32(GUEST_TR_AR_BYTES,
3327 +- (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3328 +- | VMX_AR_TYPE_BUSY_64_TSS);
3329 +- }
3330 +- vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3331 +-}
3332 +-
3333 +-static void exit_lmode(struct kvm_vcpu *vcpu)
3334 +-{
3335 +- vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3336 +- vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3337 +-}
3338 +-
3339 +-#endif
3340 +-
3341 +-static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
3342 +-{
3343 +- int vpid = to_vmx(vcpu)->vpid;
3344 +-
3345 +- if (!vpid_sync_vcpu_addr(vpid, addr))
3346 +- vpid_sync_context(vpid);
3347 +-
3348 +- /*
3349 +- * If VPIDs are not supported or enabled, then the above is a no-op.
3350 +- * But we don't really need a TLB flush in that case anyway, because
3351 +- * each VM entry/exit includes an implicit flush when VPID is 0.
3352 +- */
3353 +-}
3354 +-
3355 +-static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3356 +-{
3357 +- ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3358 +-
3359 +- vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3360 +- vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3361 +-}
3362 +-
3363 +-static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3364 +-{
3365 +- ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3366 +-
3367 +- vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3368 +- vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3369 +-}
3370 +-
3371 +-static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3372 +-{
3373 +- struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3374 +-
3375 +- if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
3376 +- return;
3377 +-
3378 +- if (is_pae_paging(vcpu)) {
3379 +- vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3380 +- vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3381 +- vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3382 +- vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3383 +- }
3384 +-}
3385 +-
3386 +-void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3387 +-{
3388 +- struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3389 +-
3390 +- if (is_pae_paging(vcpu)) {
3391 +- mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3392 +- mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3393 +- mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3394 +- mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3395 +- }
3396 +-
3397 +- kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
3398 +-}
3399 +-
3400 +-static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3401 +- unsigned long cr0,
3402 +- struct kvm_vcpu *vcpu)
3403 +-{
3404 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
3405 +-
3406 +- if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
3407 +- vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
3408 +- if (!(cr0 & X86_CR0_PG)) {
3409 +- /* From paging/starting to nonpaging */
3410 +- exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
3411 +- CPU_BASED_CR3_STORE_EXITING);
3412 +- vcpu->arch.cr0 = cr0;
3413 +- vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3414 +- } else if (!is_paging(vcpu)) {
3415 +- /* From nonpaging to paging */
3416 +- exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
3417 +- CPU_BASED_CR3_STORE_EXITING);
3418 +- vcpu->arch.cr0 = cr0;
3419 +- vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3420 +- }
3421 +-
3422 +- if (!(cr0 & X86_CR0_WP))
3423 +- *hw_cr0 &= ~X86_CR0_WP;
3424 +-}
3425 +-
3426 +-void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3427 +-{
3428 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
3429 +- unsigned long hw_cr0;
3430 +-
3431 +- hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3432 +- if (enable_unrestricted_guest)
3433 +- hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3434 +- else {
3435 +- hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3436 +-
3437 +- if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3438 +- enter_pmode(vcpu);
3439 +-
3440 +- if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3441 +- enter_rmode(vcpu);
3442 +- }
3443 +-
3444 +-#ifdef CONFIG_X86_64
3445 +- if (vcpu->arch.efer & EFER_LME) {
3446 +- if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3447 +- enter_lmode(vcpu);
3448 +- if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3449 +- exit_lmode(vcpu);
3450 +- }
3451 +-#endif
3452 +-
3453 +- if (enable_ept && !enable_unrestricted_guest)
3454 +- ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3455 +-
3456 +- vmcs_writel(CR0_READ_SHADOW, cr0);
3457 +- vmcs_writel(GUEST_CR0, hw_cr0);
3458 +- vcpu->arch.cr0 = cr0;
3459 +-
3460 +- /* depends on vcpu->arch.cr0 to be set to a new value */
3461 +- vmx->emulation_required = emulation_required(vcpu);
3462 +-}
3463 +-
3464 +-static int get_ept_level(struct kvm_vcpu *vcpu)
3465 +-{
3466 +- if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
3467 +- return 5;
3468 +- return 4;
3469 +-}
3470 +-
3471 +-u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
3472 +-{
3473 +- u64 eptp = VMX_EPTP_MT_WB;
3474 +-
3475 +- eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3476 +-
3477 +- if (enable_ept_ad_bits &&
3478 +- (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3479 +- eptp |= VMX_EPTP_AD_ENABLE_BIT;
3480 +- eptp |= (root_hpa & PAGE_MASK);
3481 +-
3482 +- return eptp;
3483 +-}
3484 +-
3485 +-void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3486 +-{
3487 +- struct kvm *kvm = vcpu->kvm;
3488 +- bool update_guest_cr3 = true;
3489 +- unsigned long guest_cr3;
3490 +- u64 eptp;
3491 +-
3492 +- guest_cr3 = cr3;
3493 +- if (enable_ept) {
3494 +- eptp = construct_eptp(vcpu, cr3);
3495 +- vmcs_write64(EPT_POINTER, eptp);
3496 +-
3497 +- if (kvm_x86_ops->tlb_remote_flush) {
3498 +- spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3499 +- to_vmx(vcpu)->ept_pointer = eptp;
3500 +- to_kvm_vmx(kvm)->ept_pointers_match
3501 +- = EPT_POINTERS_CHECK;
3502 +- spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3503 +- }
3504 +-
3505 +- /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
3506 +- if (is_guest_mode(vcpu))
3507 +- update_guest_cr3 = false;
3508 +- else if (!enable_unrestricted_guest && !is_paging(vcpu))
3509 +- guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3510 +- else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3511 +- guest_cr3 = vcpu->arch.cr3;
3512 +- else /* vmcs01.GUEST_CR3 is already up-to-date. */
3513 +- update_guest_cr3 = false;
3514 +- ept_load_pdptrs(vcpu);
3515 +- }
3516 +-
3517 +- if (update_guest_cr3)
3518 +- vmcs_writel(GUEST_CR3, guest_cr3);
3519 +-}
3520 +-
3521 +-int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3522 +-{
3523 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
3524 +- /*
3525 +- * Pass through host's Machine Check Enable value to hw_cr4, which
3526 +- * is in force while we are in guest mode. Do not let guests control
3527 +- * this bit, even if host CR4.MCE == 0.
3528 +- */
3529 +- unsigned long hw_cr4;
3530 +-
3531 +- hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3532 +- if (enable_unrestricted_guest)
3533 +- hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3534 +- else if (vmx->rmode.vm86_active)
3535 +- hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3536 +- else
3537 +- hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3538 +-
3539 +- if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3540 +- if (cr4 & X86_CR4_UMIP) {
3541 +- secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3542 +- hw_cr4 &= ~X86_CR4_UMIP;
3543 +- } else if (!is_guest_mode(vcpu) ||
3544 +- !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3545 +- secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3546 +- }
3547 +- }
3548 +-
3549 +- if (cr4 & X86_CR4_VMXE) {
3550 +- /*
3551 +- * To use VMXON (and later other VMX instructions), a guest
3552 +- * must first be able to turn on cr4.VMXE (see handle_vmon()).
3553 +- * So basically the check on whether to allow nested VMX
3554 +- * is here. We operate under the default treatment of SMM,
3555 +- * so VMX cannot be enabled under SMM.
3556 +- */
3557 +- if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3558 +- return 1;
3559 +- }
3560 +-
3561 +- if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3562 +- return 1;
3563 +-
3564 +- vcpu->arch.cr4 = cr4;
3565 +-
3566 +- if (!enable_unrestricted_guest) {
3567 +- if (enable_ept) {
3568 +- if (!is_paging(vcpu)) {
3569 +- hw_cr4 &= ~X86_CR4_PAE;
3570 +- hw_cr4 |= X86_CR4_PSE;
3571 +- } else if (!(cr4 & X86_CR4_PAE)) {
3572 +- hw_cr4 &= ~X86_CR4_PAE;
3573 +- }
3574 +- }
3575 +-
3576 +- /*
3577 +- * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3578 +- * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3579 +- * to be manually disabled when guest switches to non-paging
3580 +- * mode.
3581 +- *
3582 +- * If !enable_unrestricted_guest, the CPU is always running
3583 +- * with CR0.PG=1 and CR4 needs to be modified.
3584 +- * If enable_unrestricted_guest, the CPU automatically
3585 +- * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3586 +- */
3587 +- if (!is_paging(vcpu))
3588 +- hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3589 +- }
3590 +-
3591 +- vmcs_writel(CR4_READ_SHADOW, cr4);
3592 +- vmcs_writel(GUEST_CR4, hw_cr4);
3593 +- return 0;
3594 +-}
3595 +-
3596 +-void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3597 +-{
3598 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
3599 +- u32 ar;
3600 +-
3601 +- if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3602 +- *var = vmx->rmode.segs[seg];
3603 +- if (seg == VCPU_SREG_TR
3604 +- || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3605 +- return;
3606 +- var->base = vmx_read_guest_seg_base(vmx, seg);
3607 +- var->selector = vmx_read_guest_seg_selector(vmx, seg);
3608 +- return;
3609 +- }
3610 +- var->base = vmx_read_guest_seg_base(vmx, seg);
3611 +- var->limit = vmx_read_guest_seg_limit(vmx, seg);
3612 +- var->selector = vmx_read_guest_seg_selector(vmx, seg);
3613 +- ar = vmx_read_guest_seg_ar(vmx, seg);
3614 +- var->unusable = (ar >> 16) & 1;
3615 +- var->type = ar & 15;
3616 +- var->s = (ar >> 4) & 1;
3617 +- var->dpl = (ar >> 5) & 3;
3618 +- /*
3619 +- * Some userspaces do not preserve unusable property. Since usable
3620 +- * segment has to be present according to VMX spec we can use present
3621 +- * property to amend userspace bug by making unusable segment always
3622 +- * nonpresent. vmx_segment_access_rights() already marks nonpresent
3623 +- * segment as unusable.
3624 +- */
3625 +- var->present = !var->unusable;
3626 +- var->avl = (ar >> 12) & 1;
3627 +- var->l = (ar >> 13) & 1;
3628 +- var->db = (ar >> 14) & 1;
3629 +- var->g = (ar >> 15) & 1;
3630 +-}
3631 +-
3632 +-static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3633 +-{
3634 +- struct kvm_segment s;
3635 +-
3636 +- if (to_vmx(vcpu)->rmode.vm86_active) {
3637 +- vmx_get_segment(vcpu, &s, seg);
3638 +- return s.base;
3639 +- }
3640 +- return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3641 +-}
3642 +-
3643 +-int vmx_get_cpl(struct kvm_vcpu *vcpu)
3644 +-{
3645 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
3646 +-
3647 +- if (unlikely(vmx->rmode.vm86_active))
3648 +- return 0;
3649 +- else {
3650 +- int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3651 +- return VMX_AR_DPL(ar);
3652 +- }
3653 +-}
3654 +-
3655 +-static u32 vmx_segment_access_rights(struct kvm_segment *var)
3656 +-{
3657 +- u32 ar;
3658 +-
3659 +- if (var->unusable || !var->present)
3660 +- ar = 1 << 16;
3661 +- else {
3662 +- ar = var->type & 15;
3663 +- ar |= (var->s & 1) << 4;
3664 +- ar |= (var->dpl & 3) << 5;
3665 +- ar |= (var->present & 1) << 7;
3666 +- ar |= (var->avl & 1) << 12;
3667 +- ar |= (var->l & 1) << 13;
3668 +- ar |= (var->db & 1) << 14;
3669 +- ar |= (var->g & 1) << 15;
3670 +- }
3671 +-
3672 +- return ar;
3673 +-}
3674 +-
3675 +-void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3676 +-{
3677 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
3678 +- const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3679 +-
3680 +- vmx_segment_cache_clear(vmx);
3681 +-
3682 +- if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3683 +- vmx->rmode.segs[seg] = *var;
3684 +- if (seg == VCPU_SREG_TR)
3685 +- vmcs_write16(sf->selector, var->selector);
3686 +- else if (var->s)
3687 +- fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3688 +- goto out;
3689 +- }
3690 +-
3691 +- vmcs_writel(sf->base, var->base);
3692 +- vmcs_write32(sf->limit, var->limit);
3693 +- vmcs_write16(sf->selector, var->selector);
3694 +-
3695 +- /*
3696 +- * Fix the "Accessed" bit in AR field of segment registers for older
3697 +- * qemu binaries.
3698 +- * IA32 arch specifies that at the time of processor reset the
3699 +- * "Accessed" bit in the AR field of segment registers is 1. And qemu
3700 +- * is setting it to 0 in the userland code. This causes invalid guest
3701 +- * state vmexit when "unrestricted guest" mode is turned on.
3702 +- * Fix for this setup issue in cpu_reset is being pushed in the qemu
3703 +- * tree. Newer qemu binaries with that qemu fix would not need this
3704 +- * kvm hack.
3705 +- */
3706 +- if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3707 +- var->type |= 0x1; /* Accessed */
3708 +-
3709 +- vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3710 +-
3711 +-out:
3712 +- vmx->emulation_required = emulation_required(vcpu);
3713 +-}
3714 +-
3715 +-static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3716 +-{
3717 +- u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3718 +-
3719 +- *db = (ar >> 14) & 1;
3720 +- *l = (ar >> 13) & 1;
3721 +-}
3722 +-
3723 +-static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3724 +-{
3725 +- dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3726 +- dt->address = vmcs_readl(GUEST_IDTR_BASE);
3727 +-}
3728 +-
3729 +-static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3730 +-{
3731 +- vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3732 +- vmcs_writel(GUEST_IDTR_BASE, dt->address);
3733 +-}
3734 +-
3735 +-static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3736 +-{
3737 +- dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3738 +- dt->address = vmcs_readl(GUEST_GDTR_BASE);
3739 +-}
3740 +-
3741 +-static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3742 +-{
3743 +- vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3744 +- vmcs_writel(GUEST_GDTR_BASE, dt->address);
3745 +-}
3746 +-
3747 +-static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3748 +-{
3749 +- struct kvm_segment var;
3750 +- u32 ar;
3751 +-
3752 +- vmx_get_segment(vcpu, &var, seg);
3753 +- var.dpl = 0x3;
3754 +- if (seg == VCPU_SREG_CS)
3755 +- var.type = 0x3;
3756 +- ar = vmx_segment_access_rights(&var);
3757 +-
3758 +- if (var.base != (var.selector << 4))
3759 +- return false;
3760 +- if (var.limit != 0xffff)
3761 +- return false;
3762 +- if (ar != 0xf3)
3763 +- return false;
3764 +-
3765 +- return true;
3766 +-}
3767 +-
3768 +-static bool code_segment_valid(struct kvm_vcpu *vcpu)
3769 +-{
3770 +- struct kvm_segment cs;
3771 +- unsigned int cs_rpl;
3772 +-
3773 +- vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3774 +- cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3775 +-
3776 +- if (cs.unusable)
3777 +- return false;
3778 +- if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3779 +- return false;
3780 +- if (!cs.s)
3781 +- return false;
3782 +- if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3783 +- if (cs.dpl > cs_rpl)
3784 +- return false;
3785 +- } else {
3786 +- if (cs.dpl != cs_rpl)
3787 +- return false;
3788 +- }
3789 +- if (!cs.present)
3790 +- return false;
3791 +-
3792 +- /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3793 +- return true;
3794 +-}
3795 +-
3796 +-static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3797 +-{
3798 +- struct kvm_segment ss;
3799 +- unsigned int ss_rpl;
3800 +-
3801 +- vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3802 +- ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3803 +-
3804 +- if (ss.unusable)
3805 +- return true;
3806 +- if (ss.type != 3 && ss.type != 7)
3807 +- return false;
3808 +- if (!ss.s)
3809 +- return false;
3810 +- if (ss.dpl != ss_rpl) /* DPL != RPL */
3811 +- return false;
3812 +- if (!ss.present)
3813 +- return false;
3814 +-
3815 +- return true;
3816 +-}
3817 +-
3818 +-static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3819 +-{
3820 +- struct kvm_segment var;
3821 +- unsigned int rpl;
3822 +-
3823 +- vmx_get_segment(vcpu, &var, seg);
3824 +- rpl = var.selector & SEGMENT_RPL_MASK;
3825 +-
3826 +- if (var.unusable)
3827 +- return true;
3828 +- if (!var.s)
3829 +- return false;
3830 +- if (!var.present)
3831 +- return false;
3832 +- if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3833 +- if (var.dpl < rpl) /* DPL < RPL */
3834 +- return false;
3835 +- }
3836 +-
3837 +- /* TODO: Add other members to kvm_segment_field to allow checking for other access
3838 +- * rights flags
3839 +- */
3840 +- return true;
3841 +-}
3842 +-
3843 +-static bool tr_valid(struct kvm_vcpu *vcpu)
3844 +-{
3845 +- struct kvm_segment tr;
3846 +-
3847 +- vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3848 +-
3849 +- if (tr.unusable)
3850 +- return false;
3851 +- if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3852 +- return false;
3853 +- if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3854 +- return false;
3855 +- if (!tr.present)
3856 +- return false;
3857 +-
3858 +- return true;
3859 +-}
3860 +-
3861 +-static bool ldtr_valid(struct kvm_vcpu *vcpu)
3862 +-{
3863 +- struct kvm_segment ldtr;
3864 +-
3865 +- vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3866 +-
3867 +- if (ldtr.unusable)
3868 +- return true;
3869 +- if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3870 +- return false;
3871 +- if (ldtr.type != 2)
3872 +- return false;
3873 +- if (!ldtr.present)
3874 +- return false;
3875 +-
3876 +- return true;
3877 +-}
3878 +-
3879 +-static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3880 +-{
3881 +- struct kvm_segment cs, ss;
3882 +-
3883 +- vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3884 +- vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3885 +-
3886 +- return ((cs.selector & SEGMENT_RPL_MASK) ==
3887 +- (ss.selector & SEGMENT_RPL_MASK));
3888 +-}
3889 +-
3890 +-/*
3891 +- * Check if guest state is valid. Returns true if valid, false if
3892 +- * not.
3893 +- * We assume that registers are always usable
3894 +- */
3895 +-static bool guest_state_valid(struct kvm_vcpu *vcpu)
3896 +-{
3897 +- if (enable_unrestricted_guest)
3898 +- return true;
3899 +-
3900 +- /* real mode guest state checks */
3901 +- if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3902 +- if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3903 +- return false;
3904 +- if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3905 +- return false;
3906 +- if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3907 +- return false;
3908 +- if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3909 +- return false;
3910 +- if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3911 +- return false;
3912 +- if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3913 +- return false;
3914 +- } else {
3915 +- /* protected mode guest state checks */
3916 +- if (!cs_ss_rpl_check(vcpu))
3917 +- return false;
3918 +- if (!code_segment_valid(vcpu))
3919 +- return false;
3920 +- if (!stack_segment_valid(vcpu))
3921 +- return false;
3922 +- if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3923 +- return false;
3924 +- if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3925 +- return false;
3926 +- if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3927 +- return false;
3928 +- if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3929 +- return false;
3930 +- if (!tr_valid(vcpu))
3931 +- return false;
3932 +- if (!ldtr_valid(vcpu))
3933 +- return false;
3934 +- }
3935 +- /* TODO:
3936 +- * - Add checks on RIP
3937 +- * - Add checks on RFLAGS
3938 +- */
3939 +-
3940 +- return true;
3941 +-}
3942 +-
3943 +-static int init_rmode_tss(struct kvm *kvm)
3944 +-{
3945 +- gfn_t fn;
3946 +- u16 data = 0;
3947 +- int idx, r;
3948 +-
3949 +- idx = srcu_read_lock(&kvm->srcu);
3950 +- fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3951 +- r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3952 +- if (r < 0)
3953 +- goto out;
3954 +- data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3955 +- r = kvm_write_guest_page(kvm, fn++, &data,
3956 +- TSS_IOPB_BASE_OFFSET, sizeof(u16));
3957 +- if (r < 0)
3958 +- goto out;
3959 +- r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3960 +- if (r < 0)
3961 +- goto out;
3962 +- r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3963 +- if (r < 0)
3964 +- goto out;
3965 +- data = ~0;
3966 +- r = kvm_write_guest_page(kvm, fn, &data,
3967 +- RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3968 +- sizeof(u8));
3969 +-out:
3970 +- srcu_read_unlock(&kvm->srcu, idx);
3971 +- return r;
3972 +-}
3973 +-
3974 +-static int init_rmode_identity_map(struct kvm *kvm)
3975 +-{
3976 +- struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3977 +- int i, idx, r = 0;
3978 +- kvm_pfn_t identity_map_pfn;
3979 +- u32 tmp;
3980 +-
3981 +- /* Protect kvm_vmx->ept_identity_pagetable_done. */
3982 +- mutex_lock(&kvm->slots_lock);
3983 +-
3984 +- if (likely(kvm_vmx->ept_identity_pagetable_done))
3985 +- goto out2;
3986 +-
3987 +- if (!kvm_vmx->ept_identity_map_addr)
3988 +- kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3989 +- identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3990 +-
3991 +- r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3992 +- kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3993 +- if (r < 0)
3994 +- goto out2;
3995 +-
3996 +- idx = srcu_read_lock(&kvm->srcu);
3997 +- r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3998 +- if (r < 0)
3999 +- goto out;
4000 +- /* Set up identity-mapping pagetable for EPT in real mode */
4001 +- for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4002 +- tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4003 +- _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4004 +- r = kvm_write_guest_page(kvm, identity_map_pfn,
4005 +- &tmp, i * sizeof(tmp), sizeof(tmp));
4006 +- if (r < 0)
4007 +- goto out;
4008 +- }
4009 +- kvm_vmx->ept_identity_pagetable_done = true;
4010 +-
4011 +-out:
4012 +- srcu_read_unlock(&kvm->srcu, idx);
4013 +-
4014 +-out2:
4015 +- mutex_unlock(&kvm->slots_lock);
4016 +- return r;
4017 +-}
4018 +-
4019 +-static void seg_setup(int seg)
4020 +-{
4021 +- const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4022 +- unsigned int ar;
4023 +-
4024 +- vmcs_write16(sf->selector, 0);
4025 +- vmcs_writel(sf->base, 0);
4026 +- vmcs_write32(sf->limit, 0xffff);
4027 +- ar = 0x93;
4028 +- if (seg == VCPU_SREG_CS)
4029 +- ar |= 0x08; /* code segment */
4030 +-
4031 +- vmcs_write32(sf->ar_bytes, ar);
4032 +-}
4033 +-
4034 +-static int alloc_apic_access_page(struct kvm *kvm)
4035 +-{
4036 +- struct page *page;
4037 +- int r = 0;
4038 +-
4039 +- mutex_lock(&kvm->slots_lock);
4040 +- if (kvm->arch.apic_access_page_done)
4041 +- goto out;
4042 +- r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4043 +- APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4044 +- if (r)
4045 +- goto out;
4046 +-
4047 +- page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4048 +- if (is_error_page(page)) {
4049 +- r = -EFAULT;
4050 +- goto out;
4051 +- }
4052 +-
4053 +- /*
4054 +- * Do not pin the page in memory, so that memory hot-unplug
4055 +- * is able to migrate it.
4056 +- */
4057 +- put_page(page);
4058 +- kvm->arch.apic_access_page_done = true;
4059 +-out:
4060 +- mutex_unlock(&kvm->slots_lock);
4061 +- return r;
4062 +-}
4063 +-
4064 +-int allocate_vpid(void)
4065 +-{
4066 +- int vpid;
4067 +-
4068 +- if (!enable_vpid)
4069 +- return 0;
4070 +- spin_lock(&vmx_vpid_lock);
4071 +- vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4072 +- if (vpid < VMX_NR_VPIDS)
4073 +- __set_bit(vpid, vmx_vpid_bitmap);
4074 +- else
4075 +- vpid = 0;
4076 +- spin_unlock(&vmx_vpid_lock);
4077 +- return vpid;
4078 +-}
4079 +-
4080 +-void free_vpid(int vpid)
4081 +-{
4082 +- if (!enable_vpid || vpid == 0)
4083 +- return;
4084 +- spin_lock(&vmx_vpid_lock);
4085 +- __clear_bit(vpid, vmx_vpid_bitmap);
4086 +- spin_unlock(&vmx_vpid_lock);
4087 +-}
4088 +-
4089 +-static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4090 +- u32 msr, int type)
4091 +-{
4092 +- int f = sizeof(unsigned long);
4093 +-
4094 +- if (!cpu_has_vmx_msr_bitmap())
4095 +- return;
4096 +-
4097 +- if (static_branch_unlikely(&enable_evmcs))
4098 +- evmcs_touch_msr_bitmap();
4099 +-
4100 +- /*
4101 +- * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4102 +- * have the write-low and read-high bitmap offsets the wrong way round.
4103 +- * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4104 +- */
4105 +- if (msr <= 0x1fff) {
4106 +- if (type & MSR_TYPE_R)
4107 +- /* read-low */
4108 +- __clear_bit(msr, msr_bitmap + 0x000 / f);
4109 +-
4110 +- if (type & MSR_TYPE_W)
4111 +- /* write-low */
4112 +- __clear_bit(msr, msr_bitmap + 0x800 / f);
4113 +-
4114 +- } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4115 +- msr &= 0x1fff;
4116 +- if (type & MSR_TYPE_R)
4117 +- /* read-high */
4118 +- __clear_bit(msr, msr_bitmap + 0x400 / f);
4119 +-
4120 +- if (type & MSR_TYPE_W)
4121 +- /* write-high */
4122 +- __clear_bit(msr, msr_bitmap + 0xc00 / f);
4123 +-
4124 +- }
4125 +-}
4126 +-
4127 +-static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4128 +- u32 msr, int type)
4129 +-{
4130 +- int f = sizeof(unsigned long);
4131 +-
4132 +- if (!cpu_has_vmx_msr_bitmap())
4133 +- return;
4134 +-
4135 +- if (static_branch_unlikely(&enable_evmcs))
4136 +- evmcs_touch_msr_bitmap();
4137 +-
4138 +- /*
4139 +- * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4140 +- * have the write-low and read-high bitmap offsets the wrong way round.
4141 +- * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4142 +- */
4143 +- if (msr <= 0x1fff) {
4144 +- if (type & MSR_TYPE_R)
4145 +- /* read-low */
4146 +- __set_bit(msr, msr_bitmap + 0x000 / f);
4147 +-
4148 +- if (type & MSR_TYPE_W)
4149 +- /* write-low */
4150 +- __set_bit(msr, msr_bitmap + 0x800 / f);
4151 +-
4152 +- } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4153 +- msr &= 0x1fff;
4154 +- if (type & MSR_TYPE_R)
4155 +- /* read-high */
4156 +- __set_bit(msr, msr_bitmap + 0x400 / f);
4157 +-
4158 +- if (type & MSR_TYPE_W)
4159 +- /* write-high */
4160 +- __set_bit(msr, msr_bitmap + 0xc00 / f);
4161 +-
4162 +- }
4163 +-}
4164 +-
4165 +-static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
4166 +- u32 msr, int type, bool value)
4167 +-{
4168 +- if (value)
4169 +- vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
4170 +- else
4171 +- vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
4172 +-}
4173 +-
4174 +-static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
4175 +-{
4176 +- u8 mode = 0;
4177 +-
4178 +- if (cpu_has_secondary_exec_ctrls() &&
4179 +- (secondary_exec_controls_get(to_vmx(vcpu)) &
4180 +- SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
4181 +- mode |= MSR_BITMAP_MODE_X2APIC;
4182 +- if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
4183 +- mode |= MSR_BITMAP_MODE_X2APIC_APICV;
4184 +- }
4185 +-
4186 +- return mode;
4187 +-}
4188 +-
4189 +-static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
4190 +- u8 mode)
4191 +-{
4192 +- int msr;
4193 +-
4194 +- for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
4195 +- unsigned word = msr / BITS_PER_LONG;
4196 +- msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
4197 +- msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
4198 +- }
4199 +-
4200 +- if (mode & MSR_BITMAP_MODE_X2APIC) {
4201 +- /*
4202 +- * TPR reads and writes can be virtualized even if virtual interrupt
4203 +- * delivery is not in use.
4204 +- */
4205 +- vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
4206 +- if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
4207 +- vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
4208 +- vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
4209 +- vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
4210 +- }
4211 +- }
4212 +-}
4213 +-
4214 +-void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
4215 +-{
4216 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
4217 +- unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
4218 +- u8 mode = vmx_msr_bitmap_mode(vcpu);
4219 +- u8 changed = mode ^ vmx->msr_bitmap_mode;
4220 +-
4221 +- if (!changed)
4222 +- return;
4223 +-
4224 +- if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
4225 +- vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
4226 +-
4227 +- vmx->msr_bitmap_mode = mode;
4228 +-}
4229 +-
4230 +-void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
4231 +-{
4232 +- unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
4233 +- bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
4234 +- u32 i;
4235 +-
4236 +- vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
4237 +- MSR_TYPE_RW, flag);
4238 +- vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
4239 +- MSR_TYPE_RW, flag);
4240 +- vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
4241 +- MSR_TYPE_RW, flag);
4242 +- vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
4243 +- MSR_TYPE_RW, flag);
4244 +- for (i = 0; i < vmx->pt_desc.addr_range; i++) {
4245 +- vmx_set_intercept_for_msr(msr_bitmap,
4246 +- MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
4247 +- vmx_set_intercept_for_msr(msr_bitmap,
4248 +- MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
4249 +- }
4250 +-}
4251 +-
4252 +-static bool vmx_get_enable_apicv(struct kvm *kvm)
4253 +-{
4254 +- return enable_apicv;
4255 +-}
4256 +-
4257 +-static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
4258 +-{
4259 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
4260 +- void *vapic_page;
4261 +- u32 vppr;
4262 +- int rvi;
4263 +-
4264 +- if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
4265 +- !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
4266 +- WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
4267 +- return false;
4268 +-
4269 +- rvi = vmx_get_rvi();
4270 +-
4271 +- vapic_page = vmx->nested.virtual_apic_map.hva;
4272 +- vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
4273 +-
4274 +- return ((rvi & 0xf0) > (vppr & 0xf0));
4275 +-}
4276 +-
4277 +-static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
4278 +- bool nested)
4279 +-{
4280 +-#ifdef CONFIG_SMP
4281 +- int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
4282 +-
4283 +- if (vcpu->mode == IN_GUEST_MODE) {
4284 +- /*
4285 +- * The vector of interrupt to be delivered to vcpu had
4286 +- * been set in PIR before this function.
4287 +- *
4288 +- * Following cases will be reached in this block, and
4289 +- * we always send a notification event in all cases as
4290 +- * explained below.
4291 +- *
4292 +- * Case 1: vcpu keeps in non-root mode. Sending a
4293 +- * notification event posts the interrupt to vcpu.
4294 +- *
4295 +- * Case 2: vcpu exits to root mode and is still
4296 +- * runnable. PIR will be synced to vIRR before the
4297 +- * next vcpu entry. Sending a notification event in
4298 +- * this case has no effect, as vcpu is not in root
4299 +- * mode.
4300 +- *
4301 +- * Case 3: vcpu exits to root mode and is blocked.
4302 +- * vcpu_block() has already synced PIR to vIRR and
4303 +- * never blocks vcpu if vIRR is not cleared. Therefore,
4304 +- * a blocked vcpu here does not wait for any requested
4305 +- * interrupts in PIR, and sending a notification event
4306 +- * which has no effect is safe here.
4307 +- */
4308 +-
4309 +- apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
4310 +- return true;
4311 +- }
4312 +-#endif
4313 +- return false;
4314 +-}
4315 +-
4316 +-static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4317 +- int vector)
4318 +-{
4319 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
4320 +-
4321 +- if (is_guest_mode(vcpu) &&
4322 +- vector == vmx->nested.posted_intr_nv) {
4323 +- /*
4324 +- * If a posted intr is not recognized by hardware,
4325 +- * we will accomplish it in the next vmentry.
4326 +- */
4327 +- vmx->nested.pi_pending = true;
4328 +- kvm_make_request(KVM_REQ_EVENT, vcpu);
4329 +- /* the PIR and ON have been set by L1. */
4330 +- if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
4331 +- kvm_vcpu_kick(vcpu);
4332 +- return 0;
4333 +- }
4334 +- return -1;
4335 +-}
4336 +-/*
4337 +- * Send interrupt to vcpu via posted interrupt way.
4338 +- * 1. If target vcpu is running(non-root mode), send posted interrupt
4339 +- * notification to vcpu and hardware will sync PIR to vIRR atomically.
4340 +- * 2. If target vcpu isn't running(root mode), kick it to pick up the
4341 +- * interrupt from PIR in next vmentry.
4342 +- */
4343 +-static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4344 +-{
4345 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
4346 +- int r;
4347 +-
4348 +- r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4349 +- if (!r)
4350 +- return;
4351 +-
4352 +- if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4353 +- return;
4354 +-
4355 +- /* If a previous notification has sent the IPI, nothing to do. */
4356 +- if (pi_test_and_set_on(&vmx->pi_desc))
4357 +- return;
4358 +-
4359 +- if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
4360 +- kvm_vcpu_kick(vcpu);
4361 +-}
4362 +-
4363 +-/*
4364 +- * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4365 +- * will not change in the lifetime of the guest.
4366 +- * Note that host-state that does change is set elsewhere. E.g., host-state
4367 +- * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4368 +- */
4369 +-void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4370 +-{
4371 +- u32 low32, high32;
4372 +- unsigned long tmpl;
4373 +- unsigned long cr0, cr3, cr4;
4374 +-
4375 +- cr0 = read_cr0();
4376 +- WARN_ON(cr0 & X86_CR0_TS);
4377 +- vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
4378 +-
4379 +- /*
4380 +- * Save the most likely value for this task's CR3 in the VMCS.
4381 +- * We can't use __get_current_cr3_fast() because we're not atomic.
4382 +- */
4383 +- cr3 = __read_cr3();
4384 +- vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
4385 +- vmx->loaded_vmcs->host_state.cr3 = cr3;
4386 +-
4387 +- /* Save the most likely value for this task's CR4 in the VMCS. */
4388 +- cr4 = cr4_read_shadow();
4389 +- vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4390 +- vmx->loaded_vmcs->host_state.cr4 = cr4;
4391 +-
4392 +- vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4393 +-#ifdef CONFIG_X86_64
4394 +- /*
4395 +- * Load null selectors, so we can avoid reloading them in
4396 +- * vmx_prepare_switch_to_host(), in case userspace uses
4397 +- * the null selectors too (the expected case).
4398 +- */
4399 +- vmcs_write16(HOST_DS_SELECTOR, 0);
4400 +- vmcs_write16(HOST_ES_SELECTOR, 0);
4401 +-#else
4402 +- vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4403 +- vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4404 +-#endif
4405 +- vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4406 +- vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4407 +-
4408 +- vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
4409 +-
4410 +- vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
4411 +-
4412 +- rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4413 +- vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4414 +- rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4415 +- vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4416 +-
4417 +- if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4418 +- rdmsr(MSR_IA32_CR_PAT, low32, high32);
4419 +- vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4420 +- }
4421 +-
4422 +- if (cpu_has_load_ia32_efer())
4423 +- vmcs_write64(HOST_IA32_EFER, host_efer);
4424 +-}
4425 +-
4426 +-void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4427 +-{
4428 +- vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4429 +- if (enable_ept)
4430 +- vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4431 +- if (is_guest_mode(&vmx->vcpu))
4432 +- vmx->vcpu.arch.cr4_guest_owned_bits &=
4433 +- ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4434 +- vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4435 +-}
4436 +-
4437 +-u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4438 +-{
4439 +- u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4440 +-
4441 +- if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4442 +- pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4443 +-
4444 +- if (!enable_vnmi)
4445 +- pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
4446 +-
4447 +- if (!enable_preemption_timer)
4448 +- pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4449 +-
4450 +- return pin_based_exec_ctrl;
4451 +-}
4452 +-
4453 +-static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4454 +-{
4455 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
4456 +-
4457 +- pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4458 +- if (cpu_has_secondary_exec_ctrls()) {
4459 +- if (kvm_vcpu_apicv_active(vcpu))
4460 +- secondary_exec_controls_setbit(vmx,
4461 +- SECONDARY_EXEC_APIC_REGISTER_VIRT |
4462 +- SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4463 +- else
4464 +- secondary_exec_controls_clearbit(vmx,
4465 +- SECONDARY_EXEC_APIC_REGISTER_VIRT |
4466 +- SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4467 +- }
4468 +-
4469 +- if (cpu_has_vmx_msr_bitmap())
4470 +- vmx_update_msr_bitmap(vcpu);
4471 +-}
4472 +-
4473 +-u32 vmx_exec_control(struct vcpu_vmx *vmx)
4474 +-{
4475 +- u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4476 +-
4477 +- if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4478 +- exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4479 +-
4480 +- if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4481 +- exec_control &= ~CPU_BASED_TPR_SHADOW;
4482 +-#ifdef CONFIG_X86_64
4483 +- exec_control |= CPU_BASED_CR8_STORE_EXITING |
4484 +- CPU_BASED_CR8_LOAD_EXITING;
4485 +-#endif
4486 +- }
4487 +- if (!enable_ept)
4488 +- exec_control |= CPU_BASED_CR3_STORE_EXITING |
4489 +- CPU_BASED_CR3_LOAD_EXITING |
4490 +- CPU_BASED_INVLPG_EXITING;
4491 +- if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4492 +- exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4493 +- CPU_BASED_MONITOR_EXITING);
4494 +- if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4495 +- exec_control &= ~CPU_BASED_HLT_EXITING;
4496 +- return exec_control;
4497 +-}
4498 +-
4499 +-
4500 +-static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
4501 +-{
4502 +- struct kvm_vcpu *vcpu = &vmx->vcpu;
4503 +-
4504 +- u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4505 +-
4506 +- if (pt_mode == PT_MODE_SYSTEM)
4507 +- exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4508 +- if (!cpu_need_virtualize_apic_accesses(vcpu))
4509 +- exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4510 +- if (vmx->vpid == 0)
4511 +- exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4512 +- if (!enable_ept) {
4513 +- exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4514 +- enable_unrestricted_guest = 0;
4515 +- }
4516 +- if (!enable_unrestricted_guest)
4517 +- exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4518 +- if (kvm_pause_in_guest(vmx->vcpu.kvm))
4519 +- exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4520 +- if (!kvm_vcpu_apicv_active(vcpu))
4521 +- exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4522 +- SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4523 +- exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4524 +-
4525 +- /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4526 +- * in vmx_set_cr4. */
4527 +- exec_control &= ~SECONDARY_EXEC_DESC;
4528 +-
4529 +- /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4530 +- (handle_vmptrld).
4531 +- We can NOT enable shadow_vmcs here because we don't have yet
4532 +- a current VMCS12
4533 +- */
4534 +- exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4535 +-
4536 +- if (!enable_pml)
4537 +- exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4538 +-
4539 +- if (vmx_xsaves_supported()) {
4540 +- /* Exposing XSAVES only when XSAVE is exposed */
4541 +- bool xsaves_enabled =
4542 +- guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4543 +- guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4544 +-
4545 +- vcpu->arch.xsaves_enabled = xsaves_enabled;
4546 +-
4547 +- if (!xsaves_enabled)
4548 +- exec_control &= ~SECONDARY_EXEC_XSAVES;
4549 +-
4550 +- if (nested) {
4551 +- if (xsaves_enabled)
4552 +- vmx->nested.msrs.secondary_ctls_high |=
4553 +- SECONDARY_EXEC_XSAVES;
4554 +- else
4555 +- vmx->nested.msrs.secondary_ctls_high &=
4556 +- ~SECONDARY_EXEC_XSAVES;
4557 +- }
4558 +- }
4559 +-
4560 +- if (vmx_rdtscp_supported()) {
4561 +- bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4562 +- if (!rdtscp_enabled)
4563 +- exec_control &= ~SECONDARY_EXEC_RDTSCP;
4564 +-
4565 +- if (nested) {
4566 +- if (rdtscp_enabled)
4567 +- vmx->nested.msrs.secondary_ctls_high |=
4568 +- SECONDARY_EXEC_RDTSCP;
4569 +- else
4570 +- vmx->nested.msrs.secondary_ctls_high &=
4571 +- ~SECONDARY_EXEC_RDTSCP;
4572 +- }
4573 +- }
4574 +-
4575 +- if (vmx_invpcid_supported()) {
4576 +- /* Exposing INVPCID only when PCID is exposed */
4577 +- bool invpcid_enabled =
4578 +- guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4579 +- guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4580 +-
4581 +- if (!invpcid_enabled) {
4582 +- exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4583 +- guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4584 +- }
4585 +-
4586 +- if (nested) {
4587 +- if (invpcid_enabled)
4588 +- vmx->nested.msrs.secondary_ctls_high |=
4589 +- SECONDARY_EXEC_ENABLE_INVPCID;
4590 +- else
4591 +- vmx->nested.msrs.secondary_ctls_high &=
4592 +- ~SECONDARY_EXEC_ENABLE_INVPCID;
4593 +- }
4594 +- }
4595 +-
4596 +- if (vmx_rdrand_supported()) {
4597 +- bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4598 +- if (rdrand_enabled)
4599 +- exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4600 +-
4601 +- if (nested) {
4602 +- if (rdrand_enabled)
4603 +- vmx->nested.msrs.secondary_ctls_high |=
4604 +- SECONDARY_EXEC_RDRAND_EXITING;
4605 +- else
4606 +- vmx->nested.msrs.secondary_ctls_high &=
4607 +- ~SECONDARY_EXEC_RDRAND_EXITING;
4608 +- }
4609 +- }
4610 +-
4611 +- if (vmx_rdseed_supported()) {
4612 +- bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4613 +- if (rdseed_enabled)
4614 +- exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4615 +-
4616 +- if (nested) {
4617 +- if (rdseed_enabled)
4618 +- vmx->nested.msrs.secondary_ctls_high |=
4619 +- SECONDARY_EXEC_RDSEED_EXITING;
4620 +- else
4621 +- vmx->nested.msrs.secondary_ctls_high &=
4622 +- ~SECONDARY_EXEC_RDSEED_EXITING;
4623 +- }
4624 +- }
4625 +-
4626 +- if (vmx_waitpkg_supported()) {
4627 +- bool waitpkg_enabled =
4628 +- guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4629 +-
4630 +- if (!waitpkg_enabled)
4631 +- exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4632 +-
4633 +- if (nested) {
4634 +- if (waitpkg_enabled)
4635 +- vmx->nested.msrs.secondary_ctls_high |=
4636 +- SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4637 +- else
4638 +- vmx->nested.msrs.secondary_ctls_high &=
4639 +- ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4640 +- }
4641 +- }
4642 +-
4643 +- vmx->secondary_exec_control = exec_control;
4644 +-}
4645 +-
4646 +-static void ept_set_mmio_spte_mask(void)
4647 +-{
4648 +- /*
4649 +- * EPT Misconfigurations can be generated if the value of bits 2:0
4650 +- * of an EPT paging-structure entry is 110b (write/execute).
4651 +- */
4652 +- kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4653 +- VMX_EPT_MISCONFIG_WX_VALUE, 0);
4654 +-}
4655 +-
4656 +-#define VMX_XSS_EXIT_BITMAP 0
4657 +-
4658 +-/*
4659 +- * Noting that the initialization of Guest-state Area of VMCS is in
4660 +- * vmx_vcpu_reset().
4661 +- */
4662 +-static void init_vmcs(struct vcpu_vmx *vmx)
4663 +-{
4664 +- if (nested)
4665 +- nested_vmx_set_vmcs_shadowing_bitmap();
4666 +-
4667 +- if (cpu_has_vmx_msr_bitmap())
4668 +- vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4669 +-
4670 +- vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4671 +-
4672 +- /* Control */
4673 +- pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4674 +-
4675 +- exec_controls_set(vmx, vmx_exec_control(vmx));
4676 +-
4677 +- if (cpu_has_secondary_exec_ctrls()) {
4678 +- vmx_compute_secondary_exec_control(vmx);
4679 +- secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4680 +- }
4681 +-
4682 +- if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4683 +- vmcs_write64(EOI_EXIT_BITMAP0, 0);
4684 +- vmcs_write64(EOI_EXIT_BITMAP1, 0);
4685 +- vmcs_write64(EOI_EXIT_BITMAP2, 0);
4686 +- vmcs_write64(EOI_EXIT_BITMAP3, 0);
4687 +-
4688 +- vmcs_write16(GUEST_INTR_STATUS, 0);
4689 +-
4690 +- vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4691 +- vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4692 +- }
4693 +-
4694 +- if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4695 +- vmcs_write32(PLE_GAP, ple_gap);
4696 +- vmx->ple_window = ple_window;
4697 +- vmx->ple_window_dirty = true;
4698 +- }
4699 +-
4700 +- vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4701 +- vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4702 +- vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4703 +-
4704 +- vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4705 +- vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4706 +- vmx_set_constant_host_state(vmx);
4707 +- vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4708 +- vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4709 +-
4710 +- if (cpu_has_vmx_vmfunc())
4711 +- vmcs_write64(VM_FUNCTION_CONTROL, 0);
4712 +-
4713 +- vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4714 +- vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4715 +- vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4716 +- vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4717 +- vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4718 +-
4719 +- if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4720 +- vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4721 +-
4722 +- vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4723 +-
4724 +- /* 22.2.1, 20.8.1 */
4725 +- vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4726 +-
4727 +- vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4728 +- vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4729 +-
4730 +- set_cr4_guest_host_mask(vmx);
4731 +-
4732 +- if (vmx->vpid != 0)
4733 +- vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4734 +-
4735 +- if (vmx_xsaves_supported())
4736 +- vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4737 +-
4738 +- if (enable_pml) {
4739 +- vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4740 +- vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4741 +- }
4742 +-
4743 +- if (cpu_has_vmx_encls_vmexit())
4744 +- vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4745 +-
4746 +- if (pt_mode == PT_MODE_HOST_GUEST) {
4747 +- memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4748 +- /* Bit[6~0] are forced to 1, writes are ignored. */
4749 +- vmx->pt_desc.guest.output_mask = 0x7F;
4750 +- vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4751 +- }
4752 +-}
4753 +-
4754 +-static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4755 +-{
4756 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
4757 +- struct msr_data apic_base_msr;
4758 +- u64 cr0;
4759 +-
4760 +- vmx->rmode.vm86_active = 0;
4761 +- vmx->spec_ctrl = 0;
4762 +-
4763 +- vmx->msr_ia32_umwait_control = 0;
4764 +-
4765 +- vcpu->arch.microcode_version = 0x100000000ULL;
4766 +- vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4767 +- vmx->hv_deadline_tsc = -1;
4768 +- kvm_set_cr8(vcpu, 0);
4769 +-
4770 +- if (!init_event) {
4771 +- apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4772 +- MSR_IA32_APICBASE_ENABLE;
4773 +- if (kvm_vcpu_is_reset_bsp(vcpu))
4774 +- apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4775 +- apic_base_msr.host_initiated = true;
4776 +- kvm_set_apic_base(vcpu, &apic_base_msr);
4777 +- }
4778 +-
4779 +- vmx_segment_cache_clear(vmx);
4780 +-
4781 +- seg_setup(VCPU_SREG_CS);
4782 +- vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4783 +- vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4784 +-
4785 +- seg_setup(VCPU_SREG_DS);
4786 +- seg_setup(VCPU_SREG_ES);
4787 +- seg_setup(VCPU_SREG_FS);
4788 +- seg_setup(VCPU_SREG_GS);
4789 +- seg_setup(VCPU_SREG_SS);
4790 +-
4791 +- vmcs_write16(GUEST_TR_SELECTOR, 0);
4792 +- vmcs_writel(GUEST_TR_BASE, 0);
4793 +- vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4794 +- vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4795 +-
4796 +- vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4797 +- vmcs_writel(GUEST_LDTR_BASE, 0);
4798 +- vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4799 +- vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4800 +-
4801 +- if (!init_event) {
4802 +- vmcs_write32(GUEST_SYSENTER_CS, 0);
4803 +- vmcs_writel(GUEST_SYSENTER_ESP, 0);
4804 +- vmcs_writel(GUEST_SYSENTER_EIP, 0);
4805 +- vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4806 +- }
4807 +-
4808 +- kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4809 +- kvm_rip_write(vcpu, 0xfff0);
4810 +-
4811 +- vmcs_writel(GUEST_GDTR_BASE, 0);
4812 +- vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4813 +-
4814 +- vmcs_writel(GUEST_IDTR_BASE, 0);
4815 +- vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4816 +-
4817 +- vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4818 +- vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4819 +- vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4820 +- if (kvm_mpx_supported())
4821 +- vmcs_write64(GUEST_BNDCFGS, 0);
4822 +-
4823 +- setup_msrs(vmx);
4824 +-
4825 +- vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4826 +-
4827 +- if (cpu_has_vmx_tpr_shadow() && !init_event) {
4828 +- vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4829 +- if (cpu_need_tpr_shadow(vcpu))
4830 +- vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4831 +- __pa(vcpu->arch.apic->regs));
4832 +- vmcs_write32(TPR_THRESHOLD, 0);
4833 +- }
4834 +-
4835 +- kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4836 +-
4837 +- cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4838 +- vmx->vcpu.arch.cr0 = cr0;
4839 +- vmx_set_cr0(vcpu, cr0); /* enter rmode */
4840 +- vmx_set_cr4(vcpu, 0);
4841 +- vmx_set_efer(vcpu, 0);
4842 +-
4843 +- update_exception_bitmap(vcpu);
4844 +-
4845 +- vpid_sync_context(vmx->vpid);
4846 +- if (init_event)
4847 +- vmx_clear_hlt(vcpu);
4848 +-}
4849 +-
4850 +-static void enable_irq_window(struct kvm_vcpu *vcpu)
4851 +-{
4852 +- exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4853 +-}
4854 +-
4855 +-static void enable_nmi_window(struct kvm_vcpu *vcpu)
4856 +-{
4857 +- if (!enable_vnmi ||
4858 +- vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4859 +- enable_irq_window(vcpu);
4860 +- return;
4861 +- }
4862 +-
4863 +- exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4864 +-}
4865 +-
4866 +-static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4867 +-{
4868 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
4869 +- uint32_t intr;
4870 +- int irq = vcpu->arch.interrupt.nr;
4871 +-
4872 +- trace_kvm_inj_virq(irq);
4873 +-
4874 +- ++vcpu->stat.irq_injections;
4875 +- if (vmx->rmode.vm86_active) {
4876 +- int inc_eip = 0;
4877 +- if (vcpu->arch.interrupt.soft)
4878 +- inc_eip = vcpu->arch.event_exit_inst_len;
4879 +- kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4880 +- return;
4881 +- }
4882 +- intr = irq | INTR_INFO_VALID_MASK;
4883 +- if (vcpu->arch.interrupt.soft) {
4884 +- intr |= INTR_TYPE_SOFT_INTR;
4885 +- vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4886 +- vmx->vcpu.arch.event_exit_inst_len);
4887 +- } else
4888 +- intr |= INTR_TYPE_EXT_INTR;
4889 +- vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4890 +-
4891 +- vmx_clear_hlt(vcpu);
4892 +-}
4893 +-
4894 +-static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4895 +-{
4896 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
4897 +-
4898 +- if (!enable_vnmi) {
4899 +- /*
4900 +- * Tracking the NMI-blocked state in software is built upon
4901 +- * finding the next open IRQ window. This, in turn, depends on
4902 +- * well-behaving guests: They have to keep IRQs disabled at
4903 +- * least as long as the NMI handler runs. Otherwise we may
4904 +- * cause NMI nesting, maybe breaking the guest. But as this is
4905 +- * highly unlikely, we can live with the residual risk.
4906 +- */
4907 +- vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4908 +- vmx->loaded_vmcs->vnmi_blocked_time = 0;
4909 +- }
4910 +-
4911 +- ++vcpu->stat.nmi_injections;
4912 +- vmx->loaded_vmcs->nmi_known_unmasked = false;
4913 +-
4914 +- if (vmx->rmode.vm86_active) {
4915 +- kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4916 +- return;
4917 +- }
4918 +-
4919 +- vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4920 +- INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4921 +-
4922 +- vmx_clear_hlt(vcpu);
4923 +-}
4924 +-
4925 +-bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4926 +-{
4927 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
4928 +- bool masked;
4929 +-
4930 +- if (!enable_vnmi)
4931 +- return vmx->loaded_vmcs->soft_vnmi_blocked;
4932 +- if (vmx->loaded_vmcs->nmi_known_unmasked)
4933 +- return false;
4934 +- masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4935 +- vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4936 +- return masked;
4937 +-}
4938 +-
4939 +-void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4940 +-{
4941 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
4942 +-
4943 +- if (!enable_vnmi) {
4944 +- if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4945 +- vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4946 +- vmx->loaded_vmcs->vnmi_blocked_time = 0;
4947 +- }
4948 +- } else {
4949 +- vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4950 +- if (masked)
4951 +- vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4952 +- GUEST_INTR_STATE_NMI);
4953 +- else
4954 +- vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4955 +- GUEST_INTR_STATE_NMI);
4956 +- }
4957 +-}
4958 +-
4959 +-static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4960 +-{
4961 +- if (to_vmx(vcpu)->nested.nested_run_pending)
4962 +- return 0;
4963 +-
4964 +- if (!enable_vnmi &&
4965 +- to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4966 +- return 0;
4967 +-
4968 +- return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4969 +- (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4970 +- | GUEST_INTR_STATE_NMI));
4971 +-}
4972 +-
4973 +-static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4974 +-{
4975 +- return (!to_vmx(vcpu)->nested.nested_run_pending &&
4976 +- vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4977 +- !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4978 +- (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4979 +-}
4980 +-
4981 +-static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4982 +-{
4983 +- int ret;
4984 +-
4985 +- if (enable_unrestricted_guest)
4986 +- return 0;
4987 +-
4988 +- ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4989 +- PAGE_SIZE * 3);
4990 +- if (ret)
4991 +- return ret;
4992 +- to_kvm_vmx(kvm)->tss_addr = addr;
4993 +- return init_rmode_tss(kvm);
4994 +-}
4995 +-
4996 +-static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4997 +-{
4998 +- to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4999 +- return 0;
5000 +-}
5001 +-
5002 +-static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5003 +-{
5004 +- switch (vec) {
5005 +- case BP_VECTOR:
5006 +- /*
5007 +- * Update instruction length as we may reinject the exception
5008 +- * from user space while in guest debugging mode.
5009 +- */
5010 +- to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5011 +- vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5012 +- if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5013 +- return false;
5014 +- /* fall through */
5015 +- case DB_VECTOR:
5016 +- if (vcpu->guest_debug &
5017 +- (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5018 +- return false;
5019 +- /* fall through */
5020 +- case DE_VECTOR:
5021 +- case OF_VECTOR:
5022 +- case BR_VECTOR:
5023 +- case UD_VECTOR:
5024 +- case DF_VECTOR:
5025 +- case SS_VECTOR:
5026 +- case GP_VECTOR:
5027 +- case MF_VECTOR:
5028 +- return true;
5029 +- break;
5030 +- }
5031 +- return false;
5032 +-}
5033 +-
5034 +-static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5035 +- int vec, u32 err_code)
5036 +-{
5037 +- /*
5038 +- * Instruction with address size override prefix opcode 0x67
5039 +- * Cause the #SS fault with 0 error code in VM86 mode.
5040 +- */
5041 +- if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5042 +- if (kvm_emulate_instruction(vcpu, 0)) {
5043 +- if (vcpu->arch.halt_request) {
5044 +- vcpu->arch.halt_request = 0;
5045 +- return kvm_vcpu_halt(vcpu);
5046 +- }
5047 +- return 1;
5048 +- }
5049 +- return 0;
5050 +- }
5051 +-
5052 +- /*
5053 +- * Forward all other exceptions that are valid in real mode.
5054 +- * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5055 +- * the required debugging infrastructure rework.
5056 +- */
5057 +- kvm_queue_exception(vcpu, vec);
5058 +- return 1;
5059 +-}
5060 +-
5061 +-/*
5062 +- * Trigger machine check on the host. We assume all the MSRs are already set up
5063 +- * by the CPU and that we still run on the same CPU as the MCE occurred on.
5064 +- * We pass a fake environment to the machine check handler because we want
5065 +- * the guest to be always treated like user space, no matter what context
5066 +- * it used internally.
5067 +- */
5068 +-static void kvm_machine_check(void)
5069 +-{
5070 +-#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5071 +- struct pt_regs regs = {
5072 +- .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5073 +- .flags = X86_EFLAGS_IF,
5074 +- };
5075 +-
5076 +- do_machine_check(&regs, 0);
5077 +-#endif
5078 +-}
5079 +-
5080 +-static int handle_machine_check(struct kvm_vcpu *vcpu)
5081 +-{
5082 +- /* handled by vmx_vcpu_run() */
5083 +- return 1;
5084 +-}
5085 +-
5086 +-static int handle_exception_nmi(struct kvm_vcpu *vcpu)
5087 +-{
5088 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
5089 +- struct kvm_run *kvm_run = vcpu->run;
5090 +- u32 intr_info, ex_no, error_code;
5091 +- unsigned long cr2, rip, dr6;
5092 +- u32 vect_info;
5093 +-
5094 +- vect_info = vmx->idt_vectoring_info;
5095 +- intr_info = vmx->exit_intr_info;
5096 +-
5097 +- if (is_machine_check(intr_info) || is_nmi(intr_info))
5098 +- return 1; /* handled by handle_exception_nmi_irqoff() */
5099 +-
5100 +- if (is_invalid_opcode(intr_info))
5101 +- return handle_ud(vcpu);
5102 +-
5103 +- error_code = 0;
5104 +- if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5105 +- error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5106 +-
5107 +- if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
5108 +- WARN_ON_ONCE(!enable_vmware_backdoor);
5109 +-
5110 +- /*
5111 +- * VMware backdoor emulation on #GP interception only handles
5112 +- * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
5113 +- * error code on #GP.
5114 +- */
5115 +- if (error_code) {
5116 +- kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
5117 +- return 1;
5118 +- }
5119 +- return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
5120 +- }
5121 +-
5122 +- /*
5123 +- * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5124 +- * MMIO, it is better to report an internal error.
5125 +- * See the comments in vmx_handle_exit.
5126 +- */
5127 +- if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5128 +- !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5129 +- vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5130 +- vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5131 +- vcpu->run->internal.ndata = 3;
5132 +- vcpu->run->internal.data[0] = vect_info;
5133 +- vcpu->run->internal.data[1] = intr_info;
5134 +- vcpu->run->internal.data[2] = error_code;
5135 +- return 0;
5136 +- }
5137 +-
5138 +- if (is_page_fault(intr_info)) {
5139 +- cr2 = vmcs_readl(EXIT_QUALIFICATION);
5140 +- /* EPT won't cause page fault directly */
5141 +- WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
5142 +- return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
5143 +- }
5144 +-
5145 +- ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5146 +-
5147 +- if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5148 +- return handle_rmode_exception(vcpu, ex_no, error_code);
5149 +-
5150 +- switch (ex_no) {
5151 +- case AC_VECTOR:
5152 +- kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5153 +- return 1;
5154 +- case DB_VECTOR:
5155 +- dr6 = vmcs_readl(EXIT_QUALIFICATION);
5156 +- if (!(vcpu->guest_debug &
5157 +- (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5158 +- vcpu->arch.dr6 &= ~DR_TRAP_BITS;
5159 +- vcpu->arch.dr6 |= dr6 | DR6_RTM;
5160 +- if (is_icebp(intr_info))
5161 +- WARN_ON(!skip_emulated_instruction(vcpu));
5162 +-
5163 +- kvm_queue_exception(vcpu, DB_VECTOR);
5164 +- return 1;
5165 +- }
5166 +- kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5167 +- kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5168 +- /* fall through */
5169 +- case BP_VECTOR:
5170 +- /*
5171 +- * Update instruction length as we may reinject #BP from
5172 +- * user space while in guest debugging mode. Reading it for
5173 +- * #DB as well causes no harm, it is not used in that case.
5174 +- */
5175 +- vmx->vcpu.arch.event_exit_inst_len =
5176 +- vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5177 +- kvm_run->exit_reason = KVM_EXIT_DEBUG;
5178 +- rip = kvm_rip_read(vcpu);
5179 +- kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5180 +- kvm_run->debug.arch.exception = ex_no;
5181 +- break;
5182 +- default:
5183 +- kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5184 +- kvm_run->ex.exception = ex_no;
5185 +- kvm_run->ex.error_code = error_code;
5186 +- break;
5187 +- }
5188 +- return 0;
5189 +-}
5190 +-
5191 +-static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
5192 +-{
5193 +- ++vcpu->stat.irq_exits;
5194 +- return 1;
5195 +-}
5196 +-
5197 +-static int handle_triple_fault(struct kvm_vcpu *vcpu)
5198 +-{
5199 +- vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5200 +- vcpu->mmio_needed = 0;
5201 +- return 0;
5202 +-}
5203 +-
5204 +-static int handle_io(struct kvm_vcpu *vcpu)
5205 +-{
5206 +- unsigned long exit_qualification;
5207 +- int size, in, string;
5208 +- unsigned port;
5209 +-
5210 +- exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5211 +- string = (exit_qualification & 16) != 0;
5212 +-
5213 +- ++vcpu->stat.io_exits;
5214 +-
5215 +- if (string)
5216 +- return kvm_emulate_instruction(vcpu, 0);
5217 +-
5218 +- port = exit_qualification >> 16;
5219 +- size = (exit_qualification & 7) + 1;
5220 +- in = (exit_qualification & 8) != 0;
5221 +-
5222 +- return kvm_fast_pio(vcpu, size, port, in);
5223 +-}
5224 +-
5225 +-static void
5226 +-vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5227 +-{
5228 +- /*
5229 +- * Patch in the VMCALL instruction:
5230 +- */
5231 +- hypercall[0] = 0x0f;
5232 +- hypercall[1] = 0x01;
5233 +- hypercall[2] = 0xc1;
5234 +-}
5235 +-
5236 +-/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5237 +-static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5238 +-{
5239 +- if (is_guest_mode(vcpu)) {
5240 +- struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5241 +- unsigned long orig_val = val;
5242 +-
5243 +- /*
5244 +- * We get here when L2 changed cr0 in a way that did not change
5245 +- * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5246 +- * but did change L0 shadowed bits. So we first calculate the
5247 +- * effective cr0 value that L1 would like to write into the
5248 +- * hardware. It consists of the L2-owned bits from the new
5249 +- * value combined with the L1-owned bits from L1's guest_cr0.
5250 +- */
5251 +- val = (val & ~vmcs12->cr0_guest_host_mask) |
5252 +- (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5253 +-
5254 +- if (!nested_guest_cr0_valid(vcpu, val))
5255 +- return 1;
5256 +-
5257 +- if (kvm_set_cr0(vcpu, val))
5258 +- return 1;
5259 +- vmcs_writel(CR0_READ_SHADOW, orig_val);
5260 +- return 0;
5261 +- } else {
5262 +- if (to_vmx(vcpu)->nested.vmxon &&
5263 +- !nested_host_cr0_valid(vcpu, val))
5264 +- return 1;
5265 +-
5266 +- return kvm_set_cr0(vcpu, val);
5267 +- }
5268 +-}
5269 +-
5270 +-static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5271 +-{
5272 +- if (is_guest_mode(vcpu)) {
5273 +- struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5274 +- unsigned long orig_val = val;
5275 +-
5276 +- /* analogously to handle_set_cr0 */
5277 +- val = (val & ~vmcs12->cr4_guest_host_mask) |
5278 +- (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5279 +- if (kvm_set_cr4(vcpu, val))
5280 +- return 1;
5281 +- vmcs_writel(CR4_READ_SHADOW, orig_val);
5282 +- return 0;
5283 +- } else
5284 +- return kvm_set_cr4(vcpu, val);
5285 +-}
5286 +-
5287 +-static int handle_desc(struct kvm_vcpu *vcpu)
5288 +-{
5289 +- WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
5290 +- return kvm_emulate_instruction(vcpu, 0);
5291 +-}
5292 +-
5293 +-static int handle_cr(struct kvm_vcpu *vcpu)
5294 +-{
5295 +- unsigned long exit_qualification, val;
5296 +- int cr;
5297 +- int reg;
5298 +- int err;
5299 +- int ret;
5300 +-
5301 +- exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5302 +- cr = exit_qualification & 15;
5303 +- reg = (exit_qualification >> 8) & 15;
5304 +- switch ((exit_qualification >> 4) & 3) {
5305 +- case 0: /* mov to cr */
5306 +- val = kvm_register_readl(vcpu, reg);
5307 +- trace_kvm_cr_write(cr, val);
5308 +- switch (cr) {
5309 +- case 0:
5310 +- err = handle_set_cr0(vcpu, val);
5311 +- return kvm_complete_insn_gp(vcpu, err);
5312 +- case 3:
5313 +- WARN_ON_ONCE(enable_unrestricted_guest);
5314 +- err = kvm_set_cr3(vcpu, val);
5315 +- return kvm_complete_insn_gp(vcpu, err);
5316 +- case 4:
5317 +- err = handle_set_cr4(vcpu, val);
5318 +- return kvm_complete_insn_gp(vcpu, err);
5319 +- case 8: {
5320 +- u8 cr8_prev = kvm_get_cr8(vcpu);
5321 +- u8 cr8 = (u8)val;
5322 +- err = kvm_set_cr8(vcpu, cr8);
5323 +- ret = kvm_complete_insn_gp(vcpu, err);
5324 +- if (lapic_in_kernel(vcpu))
5325 +- return ret;
5326 +- if (cr8_prev <= cr8)
5327 +- return ret;
5328 +- /*
5329 +- * TODO: we might be squashing a
5330 +- * KVM_GUESTDBG_SINGLESTEP-triggered
5331 +- * KVM_EXIT_DEBUG here.
5332 +- */
5333 +- vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5334 +- return 0;
5335 +- }
5336 +- }
5337 +- break;
5338 +- case 2: /* clts */
5339 +- WARN_ONCE(1, "Guest should always own CR0.TS");
5340 +- vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5341 +- trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5342 +- return kvm_skip_emulated_instruction(vcpu);
5343 +- case 1: /*mov from cr*/
5344 +- switch (cr) {
5345 +- case 3:
5346 +- WARN_ON_ONCE(enable_unrestricted_guest);
5347 +- val = kvm_read_cr3(vcpu);
5348 +- kvm_register_write(vcpu, reg, val);
5349 +- trace_kvm_cr_read(cr, val);
5350 +- return kvm_skip_emulated_instruction(vcpu);
5351 +- case 8:
5352 +- val = kvm_get_cr8(vcpu);
5353 +- kvm_register_write(vcpu, reg, val);
5354 +- trace_kvm_cr_read(cr, val);
5355 +- return kvm_skip_emulated_instruction(vcpu);
5356 +- }
5357 +- break;
5358 +- case 3: /* lmsw */
5359 +- val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5360 +- trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5361 +- kvm_lmsw(vcpu, val);
5362 +-
5363 +- return kvm_skip_emulated_instruction(vcpu);
5364 +- default:
5365 +- break;
5366 +- }
5367 +- vcpu->run->exit_reason = 0;
5368 +- vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5369 +- (int)(exit_qualification >> 4) & 3, cr);
5370 +- return 0;
5371 +-}
5372 +-
5373 +-static int handle_dr(struct kvm_vcpu *vcpu)
5374 +-{
5375 +- unsigned long exit_qualification;
5376 +- int dr, dr7, reg;
5377 +-
5378 +- exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5379 +- dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5380 +-
5381 +- /* First, if DR does not exist, trigger UD */
5382 +- if (!kvm_require_dr(vcpu, dr))
5383 +- return 1;
5384 +-
5385 +- /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5386 +- if (!kvm_require_cpl(vcpu, 0))
5387 +- return 1;
5388 +- dr7 = vmcs_readl(GUEST_DR7);
5389 +- if (dr7 & DR7_GD) {
5390 +- /*
5391 +- * As the vm-exit takes precedence over the debug trap, we
5392 +- * need to emulate the latter, either for the host or the
5393 +- * guest debugging itself.
5394 +- */
5395 +- if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5396 +- vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5397 +- vcpu->run->debug.arch.dr7 = dr7;
5398 +- vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5399 +- vcpu->run->debug.arch.exception = DB_VECTOR;
5400 +- vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5401 +- return 0;
5402 +- } else {
5403 +- vcpu->arch.dr6 &= ~DR_TRAP_BITS;
5404 +- vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5405 +- kvm_queue_exception(vcpu, DB_VECTOR);
5406 +- return 1;
5407 +- }
5408 +- }
5409 +-
5410 +- if (vcpu->guest_debug == 0) {
5411 +- exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5412 +-
5413 +- /*
5414 +- * No more DR vmexits; force a reload of the debug registers
5415 +- * and reenter on this instruction. The next vmexit will
5416 +- * retrieve the full state of the debug registers.
5417 +- */
5418 +- vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5419 +- return 1;
5420 +- }
5421 +-
5422 +- reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5423 +- if (exit_qualification & TYPE_MOV_FROM_DR) {
5424 +- unsigned long val;
5425 +-
5426 +- if (kvm_get_dr(vcpu, dr, &val))
5427 +- return 1;
5428 +- kvm_register_write(vcpu, reg, val);
5429 +- } else
5430 +- if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5431 +- return 1;
5432 +-
5433 +- return kvm_skip_emulated_instruction(vcpu);
5434 +-}
5435 +-
5436 +-static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5437 +-{
5438 +- return vcpu->arch.dr6;
5439 +-}
5440 +-
5441 +-static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5442 +-{
5443 +-}
5444 +-
5445 +-static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5446 +-{
5447 +- get_debugreg(vcpu->arch.db[0], 0);
5448 +- get_debugreg(vcpu->arch.db[1], 1);
5449 +- get_debugreg(vcpu->arch.db[2], 2);
5450 +- get_debugreg(vcpu->arch.db[3], 3);
5451 +- get_debugreg(vcpu->arch.dr6, 6);
5452 +- vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5453 +-
5454 +- vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5455 +- exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5456 +-}
5457 +-
5458 +-static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5459 +-{
5460 +- vmcs_writel(GUEST_DR7, val);
5461 +-}
5462 +-
5463 +-static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5464 +-{
5465 +- kvm_apic_update_ppr(vcpu);
5466 +- return 1;
5467 +-}
5468 +-
5469 +-static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5470 +-{
5471 +- exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5472 +-
5473 +- kvm_make_request(KVM_REQ_EVENT, vcpu);
5474 +-
5475 +- ++vcpu->stat.irq_window_exits;
5476 +- return 1;
5477 +-}
5478 +-
5479 +-static int handle_vmcall(struct kvm_vcpu *vcpu)
5480 +-{
5481 +- return kvm_emulate_hypercall(vcpu);
5482 +-}
5483 +-
5484 +-static int handle_invd(struct kvm_vcpu *vcpu)
5485 +-{
5486 +- return kvm_emulate_instruction(vcpu, 0);
5487 +-}
5488 +-
5489 +-static int handle_invlpg(struct kvm_vcpu *vcpu)
5490 +-{
5491 +- unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5492 +-
5493 +- kvm_mmu_invlpg(vcpu, exit_qualification);
5494 +- return kvm_skip_emulated_instruction(vcpu);
5495 +-}
5496 +-
5497 +-static int handle_rdpmc(struct kvm_vcpu *vcpu)
5498 +-{
5499 +- int err;
5500 +-
5501 +- err = kvm_rdpmc(vcpu);
5502 +- return kvm_complete_insn_gp(vcpu, err);
5503 +-}
5504 +-
5505 +-static int handle_wbinvd(struct kvm_vcpu *vcpu)
5506 +-{
5507 +- return kvm_emulate_wbinvd(vcpu);
5508 +-}
5509 +-
5510 +-static int handle_xsetbv(struct kvm_vcpu *vcpu)
5511 +-{
5512 +- u64 new_bv = kvm_read_edx_eax(vcpu);
5513 +- u32 index = kvm_rcx_read(vcpu);
5514 +-
5515 +- if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5516 +- return kvm_skip_emulated_instruction(vcpu);
5517 +- return 1;
5518 +-}
5519 +-
5520 +-static int handle_apic_access(struct kvm_vcpu *vcpu)
5521 +-{
5522 +- if (likely(fasteoi)) {
5523 +- unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5524 +- int access_type, offset;
5525 +-
5526 +- access_type = exit_qualification & APIC_ACCESS_TYPE;
5527 +- offset = exit_qualification & APIC_ACCESS_OFFSET;
5528 +- /*
5529 +- * Sane guest uses MOV to write EOI, with written value
5530 +- * not cared. So make a short-circuit here by avoiding
5531 +- * heavy instruction emulation.
5532 +- */
5533 +- if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5534 +- (offset == APIC_EOI)) {
5535 +- kvm_lapic_set_eoi(vcpu);
5536 +- return kvm_skip_emulated_instruction(vcpu);
5537 +- }
5538 +- }
5539 +- return kvm_emulate_instruction(vcpu, 0);
5540 +-}
5541 +-
5542 +-static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5543 +-{
5544 +- unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5545 +- int vector = exit_qualification & 0xff;
5546 +-
5547 +- /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5548 +- kvm_apic_set_eoi_accelerated(vcpu, vector);
5549 +- return 1;
5550 +-}
5551 +-
5552 +-static int handle_apic_write(struct kvm_vcpu *vcpu)
5553 +-{
5554 +- unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5555 +- u32 offset = exit_qualification & 0xfff;
5556 +-
5557 +- /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5558 +- kvm_apic_write_nodecode(vcpu, offset);
5559 +- return 1;
5560 +-}
5561 +-
5562 +-static int handle_task_switch(struct kvm_vcpu *vcpu)
5563 +-{
5564 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
5565 +- unsigned long exit_qualification;
5566 +- bool has_error_code = false;
5567 +- u32 error_code = 0;
5568 +- u16 tss_selector;
5569 +- int reason, type, idt_v, idt_index;
5570 +-
5571 +- idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5572 +- idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5573 +- type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5574 +-
5575 +- exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5576 +-
5577 +- reason = (u32)exit_qualification >> 30;
5578 +- if (reason == TASK_SWITCH_GATE && idt_v) {
5579 +- switch (type) {
5580 +- case INTR_TYPE_NMI_INTR:
5581 +- vcpu->arch.nmi_injected = false;
5582 +- vmx_set_nmi_mask(vcpu, true);
5583 +- break;
5584 +- case INTR_TYPE_EXT_INTR:
5585 +- case INTR_TYPE_SOFT_INTR:
5586 +- kvm_clear_interrupt_queue(vcpu);
5587 +- break;
5588 +- case INTR_TYPE_HARD_EXCEPTION:
5589 +- if (vmx->idt_vectoring_info &
5590 +- VECTORING_INFO_DELIVER_CODE_MASK) {
5591 +- has_error_code = true;
5592 +- error_code =
5593 +- vmcs_read32(IDT_VECTORING_ERROR_CODE);
5594 +- }
5595 +- /* fall through */
5596 +- case INTR_TYPE_SOFT_EXCEPTION:
5597 +- kvm_clear_exception_queue(vcpu);
5598 +- break;
5599 +- default:
5600 +- break;
5601 +- }
5602 +- }
5603 +- tss_selector = exit_qualification;
5604 +-
5605 +- if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5606 +- type != INTR_TYPE_EXT_INTR &&
5607 +- type != INTR_TYPE_NMI_INTR))
5608 +- WARN_ON(!skip_emulated_instruction(vcpu));
5609 +-
5610 +- /*
5611 +- * TODO: What about debug traps on tss switch?
5612 +- * Are we supposed to inject them and update dr6?
5613 +- */
5614 +- return kvm_task_switch(vcpu, tss_selector,
5615 +- type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5616 +- reason, has_error_code, error_code);
5617 +-}
5618 +-
5619 +-static int handle_ept_violation(struct kvm_vcpu *vcpu)
5620 +-{
5621 +- unsigned long exit_qualification;
5622 +- gpa_t gpa;
5623 +- u64 error_code;
5624 +-
5625 +- exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5626 +-
5627 +- /*
5628 +- * EPT violation happened while executing iret from NMI,
5629 +- * "blocked by NMI" bit has to be set before next VM entry.
5630 +- * There are errata that may cause this bit to not be set:
5631 +- * AAK134, BY25.
5632 +- */
5633 +- if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5634 +- enable_vnmi &&
5635 +- (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5636 +- vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5637 +-
5638 +- gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5639 +- trace_kvm_page_fault(gpa, exit_qualification);
5640 +-
5641 +- /* Is it a read fault? */
5642 +- error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5643 +- ? PFERR_USER_MASK : 0;
5644 +- /* Is it a write fault? */
5645 +- error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5646 +- ? PFERR_WRITE_MASK : 0;
5647 +- /* Is it a fetch fault? */
5648 +- error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5649 +- ? PFERR_FETCH_MASK : 0;
5650 +- /* ept page table entry is present? */
5651 +- error_code |= (exit_qualification &
5652 +- (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5653 +- EPT_VIOLATION_EXECUTABLE))
5654 +- ? PFERR_PRESENT_MASK : 0;
5655 +-
5656 +- error_code |= (exit_qualification & 0x100) != 0 ?
5657 +- PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5658 +-
5659 +- vcpu->arch.exit_qualification = exit_qualification;
5660 +- return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5661 +-}
5662 +-
5663 +-static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5664 +-{
5665 +- gpa_t gpa;
5666 +-
5667 +- /*
5668 +- * A nested guest cannot optimize MMIO vmexits, because we have an
5669 +- * nGPA here instead of the required GPA.
5670 +- */
5671 +- gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5672 +- if (!is_guest_mode(vcpu) &&
5673 +- !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5674 +- trace_kvm_fast_mmio(gpa);
5675 +- return kvm_skip_emulated_instruction(vcpu);
5676 +- }
5677 +-
5678 +- return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5679 +-}
5680 +-
5681 +-static int handle_nmi_window(struct kvm_vcpu *vcpu)
5682 +-{
5683 +- WARN_ON_ONCE(!enable_vnmi);
5684 +- exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5685 +- ++vcpu->stat.nmi_window_exits;
5686 +- kvm_make_request(KVM_REQ_EVENT, vcpu);
5687 +-
5688 +- return 1;
5689 +-}
5690 +-
5691 +-static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5692 +-{
5693 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
5694 +- bool intr_window_requested;
5695 +- unsigned count = 130;
5696 +-
5697 +- /*
5698 +- * We should never reach the point where we are emulating L2
5699 +- * due to invalid guest state as that means we incorrectly
5700 +- * allowed a nested VMEntry with an invalid vmcs12.
5701 +- */
5702 +- WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5703 +-
5704 +- intr_window_requested = exec_controls_get(vmx) &
5705 +- CPU_BASED_INTR_WINDOW_EXITING;
5706 +-
5707 +- while (vmx->emulation_required && count-- != 0) {
5708 +- if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5709 +- return handle_interrupt_window(&vmx->vcpu);
5710 +-
5711 +- if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5712 +- return 1;
5713 +-
5714 +- if (!kvm_emulate_instruction(vcpu, 0))
5715 +- return 0;
5716 +-
5717 +- if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5718 +- vcpu->arch.exception.pending) {
5719 +- vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5720 +- vcpu->run->internal.suberror =
5721 +- KVM_INTERNAL_ERROR_EMULATION;
5722 +- vcpu->run->internal.ndata = 0;
5723 +- return 0;
5724 +- }
5725 +-
5726 +- if (vcpu->arch.halt_request) {
5727 +- vcpu->arch.halt_request = 0;
5728 +- return kvm_vcpu_halt(vcpu);
5729 +- }
5730 +-
5731 +- /*
5732 +- * Note, return 1 and not 0, vcpu_run() is responsible for
5733 +- * morphing the pending signal into the proper return code.
5734 +- */
5735 +- if (signal_pending(current))
5736 +- return 1;
5737 +-
5738 +- if (need_resched())
5739 +- schedule();
5740 +- }
5741 +-
5742 +- return 1;
5743 +-}
5744 +-
5745 +-static void grow_ple_window(struct kvm_vcpu *vcpu)
5746 +-{
5747 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
5748 +- unsigned int old = vmx->ple_window;
5749 +-
5750 +- vmx->ple_window = __grow_ple_window(old, ple_window,
5751 +- ple_window_grow,
5752 +- ple_window_max);
5753 +-
5754 +- if (vmx->ple_window != old) {
5755 +- vmx->ple_window_dirty = true;
5756 +- trace_kvm_ple_window_update(vcpu->vcpu_id,
5757 +- vmx->ple_window, old);
5758 +- }
5759 +-}
5760 +-
5761 +-static void shrink_ple_window(struct kvm_vcpu *vcpu)
5762 +-{
5763 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
5764 +- unsigned int old = vmx->ple_window;
5765 +-
5766 +- vmx->ple_window = __shrink_ple_window(old, ple_window,
5767 +- ple_window_shrink,
5768 +- ple_window);
5769 +-
5770 +- if (vmx->ple_window != old) {
5771 +- vmx->ple_window_dirty = true;
5772 +- trace_kvm_ple_window_update(vcpu->vcpu_id,
5773 +- vmx->ple_window, old);
5774 +- }
5775 +-}
5776 +-
5777 +-/*
5778 +- * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5779 +- */
5780 +-static void wakeup_handler(void)
5781 +-{
5782 +- struct kvm_vcpu *vcpu;
5783 +- int cpu = smp_processor_id();
5784 +-
5785 +- spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5786 +- list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5787 +- blocked_vcpu_list) {
5788 +- struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5789 +-
5790 +- if (pi_test_on(pi_desc) == 1)
5791 +- kvm_vcpu_kick(vcpu);
5792 +- }
5793 +- spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5794 +-}
5795 +-
5796 +-static void vmx_enable_tdp(void)
5797 +-{
5798 +- kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5799 +- enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5800 +- enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5801 +- 0ull, VMX_EPT_EXECUTABLE_MASK,
5802 +- cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5803 +- VMX_EPT_RWX_MASK, 0ull);
5804 +-
5805 +- ept_set_mmio_spte_mask();
5806 +- kvm_enable_tdp();
5807 +-}
5808 +-
5809 +-/*
5810 +- * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5811 +- * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5812 +- */
5813 +-static int handle_pause(struct kvm_vcpu *vcpu)
5814 +-{
5815 +- if (!kvm_pause_in_guest(vcpu->kvm))
5816 +- grow_ple_window(vcpu);
5817 +-
5818 +- /*
5819 +- * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5820 +- * VM-execution control is ignored if CPL > 0. OTOH, KVM
5821 +- * never set PAUSE_EXITING and just set PLE if supported,
5822 +- * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5823 +- */
5824 +- kvm_vcpu_on_spin(vcpu, true);
5825 +- return kvm_skip_emulated_instruction(vcpu);
5826 +-}
5827 +-
5828 +-static int handle_nop(struct kvm_vcpu *vcpu)
5829 +-{
5830 +- return kvm_skip_emulated_instruction(vcpu);
5831 +-}
5832 +-
5833 +-static int handle_mwait(struct kvm_vcpu *vcpu)
5834 +-{
5835 +- printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5836 +- return handle_nop(vcpu);
5837 +-}
5838 +-
5839 +-static int handle_invalid_op(struct kvm_vcpu *vcpu)
5840 +-{
5841 +- kvm_queue_exception(vcpu, UD_VECTOR);
5842 +- return 1;
5843 +-}
5844 +-
5845 +-static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5846 +-{
5847 +- return 1;
5848 +-}
5849 +-
5850 +-static int handle_monitor(struct kvm_vcpu *vcpu)
5851 +-{
5852 +- printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5853 +- return handle_nop(vcpu);
5854 +-}
5855 +-
5856 +-static int handle_invpcid(struct kvm_vcpu *vcpu)
5857 +-{
5858 +- u32 vmx_instruction_info;
5859 +- unsigned long type;
5860 +- bool pcid_enabled;
5861 +- gva_t gva;
5862 +- struct x86_exception e;
5863 +- unsigned i;
5864 +- unsigned long roots_to_free = 0;
5865 +- struct {
5866 +- u64 pcid;
5867 +- u64 gla;
5868 +- } operand;
5869 +-
5870 +- if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5871 +- kvm_queue_exception(vcpu, UD_VECTOR);
5872 +- return 1;
5873 +- }
5874 +-
5875 +- vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5876 +- type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5877 +-
5878 +- if (type > 3) {
5879 +- kvm_inject_gp(vcpu, 0);
5880 +- return 1;
5881 +- }
5882 +-
5883 +- /* According to the Intel instruction reference, the memory operand
5884 +- * is read even if it isn't needed (e.g., for type==all)
5885 +- */
5886 +- if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5887 +- vmx_instruction_info, false,
5888 +- sizeof(operand), &gva))
5889 +- return 1;
5890 +-
5891 +- if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5892 +- kvm_inject_page_fault(vcpu, &e);
5893 +- return 1;
5894 +- }
5895 +-
5896 +- if (operand.pcid >> 12 != 0) {
5897 +- kvm_inject_gp(vcpu, 0);
5898 +- return 1;
5899 +- }
5900 +-
5901 +- pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5902 +-
5903 +- switch (type) {
5904 +- case INVPCID_TYPE_INDIV_ADDR:
5905 +- if ((!pcid_enabled && (operand.pcid != 0)) ||
5906 +- is_noncanonical_address(operand.gla, vcpu)) {
5907 +- kvm_inject_gp(vcpu, 0);
5908 +- return 1;
5909 +- }
5910 +- kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5911 +- return kvm_skip_emulated_instruction(vcpu);
5912 +-
5913 +- case INVPCID_TYPE_SINGLE_CTXT:
5914 +- if (!pcid_enabled && (operand.pcid != 0)) {
5915 +- kvm_inject_gp(vcpu, 0);
5916 +- return 1;
5917 +- }
5918 +-
5919 +- if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5920 +- kvm_mmu_sync_roots(vcpu);
5921 +- kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5922 +- }
5923 +-
5924 +- for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5925 +- if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5926 +- == operand.pcid)
5927 +- roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5928 +-
5929 +- kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5930 +- /*
5931 +- * If neither the current cr3 nor any of the prev_roots use the
5932 +- * given PCID, then nothing needs to be done here because a
5933 +- * resync will happen anyway before switching to any other CR3.
5934 +- */
5935 +-
5936 +- return kvm_skip_emulated_instruction(vcpu);
5937 +-
5938 +- case INVPCID_TYPE_ALL_NON_GLOBAL:
5939 +- /*
5940 +- * Currently, KVM doesn't mark global entries in the shadow
5941 +- * page tables, so a non-global flush just degenerates to a
5942 +- * global flush. If needed, we could optimize this later by
5943 +- * keeping track of global entries in shadow page tables.
5944 +- */
5945 +-
5946 +- /* fall-through */
5947 +- case INVPCID_TYPE_ALL_INCL_GLOBAL:
5948 +- kvm_mmu_unload(vcpu);
5949 +- return kvm_skip_emulated_instruction(vcpu);
5950 +-
5951 +- default:
5952 +- BUG(); /* We have already checked above that type <= 3 */
5953 +- }
5954 +-}
5955 +-
5956 +-static int handle_pml_full(struct kvm_vcpu *vcpu)
5957 +-{
5958 +- unsigned long exit_qualification;
5959 +-
5960 +- trace_kvm_pml_full(vcpu->vcpu_id);
5961 +-
5962 +- exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5963 +-
5964 +- /*
5965 +- * PML buffer FULL happened while executing iret from NMI,
5966 +- * "blocked by NMI" bit has to be set before next VM entry.
5967 +- */
5968 +- if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5969 +- enable_vnmi &&
5970 +- (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5971 +- vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5972 +- GUEST_INTR_STATE_NMI);
5973 +-
5974 +- /*
5975 +- * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5976 +- * here.., and there's no userspace involvement needed for PML.
5977 +- */
5978 +- return 1;
5979 +-}
5980 +-
5981 +-static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5982 +-{
5983 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
5984 +-
5985 +- if (!vmx->req_immediate_exit &&
5986 +- !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5987 +- kvm_lapic_expired_hv_timer(vcpu);
5988 +-
5989 +- return 1;
5990 +-}
5991 +-
5992 +-/*
5993 +- * When nested=0, all VMX instruction VM Exits filter here. The handlers
5994 +- * are overwritten by nested_vmx_setup() when nested=1.
5995 +- */
5996 +-static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5997 +-{
5998 +- kvm_queue_exception(vcpu, UD_VECTOR);
5999 +- return 1;
6000 +-}
6001 +-
6002 +-static int handle_encls(struct kvm_vcpu *vcpu)
6003 +-{
6004 +- /*
6005 +- * SGX virtualization is not yet supported. There is no software
6006 +- * enable bit for SGX, so we have to trap ENCLS and inject a #UD
6007 +- * to prevent the guest from executing ENCLS.
6008 +- */
6009 +- kvm_queue_exception(vcpu, UD_VECTOR);
6010 +- return 1;
6011 +-}
6012 +-
6013 +-/*
6014 +- * The exit handlers return 1 if the exit was handled fully and guest execution
6015 +- * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6016 +- * to be done to userspace and return 0.
6017 +- */
6018 +-static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6019 +- [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
6020 +- [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
6021 +- [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6022 +- [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6023 +- [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6024 +- [EXIT_REASON_CR_ACCESS] = handle_cr,
6025 +- [EXIT_REASON_DR_ACCESS] = handle_dr,
6026 +- [EXIT_REASON_CPUID] = kvm_emulate_cpuid,
6027 +- [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr,
6028 +- [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr,
6029 +- [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window,
6030 +- [EXIT_REASON_HLT] = kvm_emulate_halt,
6031 +- [EXIT_REASON_INVD] = handle_invd,
6032 +- [EXIT_REASON_INVLPG] = handle_invlpg,
6033 +- [EXIT_REASON_RDPMC] = handle_rdpmc,
6034 +- [EXIT_REASON_VMCALL] = handle_vmcall,
6035 +- [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
6036 +- [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
6037 +- [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
6038 +- [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
6039 +- [EXIT_REASON_VMREAD] = handle_vmx_instruction,
6040 +- [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
6041 +- [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
6042 +- [EXIT_REASON_VMOFF] = handle_vmx_instruction,
6043 +- [EXIT_REASON_VMON] = handle_vmx_instruction,
6044 +- [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6045 +- [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
6046 +- [EXIT_REASON_APIC_WRITE] = handle_apic_write,
6047 +- [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
6048 +- [EXIT_REASON_WBINVD] = handle_wbinvd,
6049 +- [EXIT_REASON_XSETBV] = handle_xsetbv,
6050 +- [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
6051 +- [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
6052 +- [EXIT_REASON_GDTR_IDTR] = handle_desc,
6053 +- [EXIT_REASON_LDTR_TR] = handle_desc,
6054 +- [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6055 +- [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
6056 +- [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
6057 +- [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
6058 +- [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
6059 +- [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
6060 +- [EXIT_REASON_INVEPT] = handle_vmx_instruction,
6061 +- [EXIT_REASON_INVVPID] = handle_vmx_instruction,
6062 +- [EXIT_REASON_RDRAND] = handle_invalid_op,
6063 +- [EXIT_REASON_RDSEED] = handle_invalid_op,
6064 +- [EXIT_REASON_PML_FULL] = handle_pml_full,
6065 +- [EXIT_REASON_INVPCID] = handle_invpcid,
6066 +- [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
6067 +- [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
6068 +- [EXIT_REASON_ENCLS] = handle_encls,
6069 +-};
6070 +-
6071 +-static const int kvm_vmx_max_exit_handlers =
6072 +- ARRAY_SIZE(kvm_vmx_exit_handlers);
6073 +-
6074 +-static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6075 +-{
6076 +- *info1 = vmcs_readl(EXIT_QUALIFICATION);
6077 +- *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6078 +-}
6079 +-
6080 +-static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
6081 +-{
6082 +- if (vmx->pml_pg) {
6083 +- __free_page(vmx->pml_pg);
6084 +- vmx->pml_pg = NULL;
6085 +- }
6086 +-}
6087 +-
6088 +-static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
6089 +-{
6090 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
6091 +- u64 *pml_buf;
6092 +- u16 pml_idx;
6093 +-
6094 +- pml_idx = vmcs_read16(GUEST_PML_INDEX);
6095 +-
6096 +- /* Do nothing if PML buffer is empty */
6097 +- if (pml_idx == (PML_ENTITY_NUM - 1))
6098 +- return;
6099 +-
6100 +- /* PML index always points to next available PML buffer entity */
6101 +- if (pml_idx >= PML_ENTITY_NUM)
6102 +- pml_idx = 0;
6103 +- else
6104 +- pml_idx++;
6105 +-
6106 +- pml_buf = page_address(vmx->pml_pg);
6107 +- for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
6108 +- u64 gpa;
6109 +-
6110 +- gpa = pml_buf[pml_idx];
6111 +- WARN_ON(gpa & (PAGE_SIZE - 1));
6112 +- kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
6113 +- }
6114 +-
6115 +- /* reset PML index */
6116 +- vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
6117 +-}
6118 +-
6119 +-/*
6120 +- * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
6121 +- * Called before reporting dirty_bitmap to userspace.
6122 +- */
6123 +-static void kvm_flush_pml_buffers(struct kvm *kvm)
6124 +-{
6125 +- int i;
6126 +- struct kvm_vcpu *vcpu;
6127 +- /*
6128 +- * We only need to kick vcpu out of guest mode here, as PML buffer
6129 +- * is flushed at beginning of all VMEXITs, and it's obvious that only
6130 +- * vcpus running in guest are possible to have unflushed GPAs in PML
6131 +- * buffer.
6132 +- */
6133 +- kvm_for_each_vcpu(i, vcpu, kvm)
6134 +- kvm_vcpu_kick(vcpu);
6135 +-}
6136 +-
6137 +-static void vmx_dump_sel(char *name, uint32_t sel)
6138 +-{
6139 +- pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
6140 +- name, vmcs_read16(sel),
6141 +- vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
6142 +- vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
6143 +- vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
6144 +-}
6145 +-
6146 +-static void vmx_dump_dtsel(char *name, uint32_t limit)
6147 +-{
6148 +- pr_err("%s limit=0x%08x, base=0x%016lx\n",
6149 +- name, vmcs_read32(limit),
6150 +- vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
6151 +-}
6152 +-
6153 +-void dump_vmcs(void)
6154 +-{
6155 +- u32 vmentry_ctl, vmexit_ctl;
6156 +- u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
6157 +- unsigned long cr4;
6158 +- u64 efer;
6159 +- int i, n;
6160 +-
6161 +- if (!dump_invalid_vmcs) {
6162 +- pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
6163 +- return;
6164 +- }
6165 +-
6166 +- vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
6167 +- vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
6168 +- cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6169 +- pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
6170 +- cr4 = vmcs_readl(GUEST_CR4);
6171 +- efer = vmcs_read64(GUEST_IA32_EFER);
6172 +- secondary_exec_control = 0;
6173 +- if (cpu_has_secondary_exec_ctrls())
6174 +- secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6175 +-
6176 +- pr_err("*** Guest State ***\n");
6177 +- pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
6178 +- vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
6179 +- vmcs_readl(CR0_GUEST_HOST_MASK));
6180 +- pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
6181 +- cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
6182 +- pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
6183 +- if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
6184 +- (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
6185 +- {
6186 +- pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
6187 +- vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
6188 +- pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
6189 +- vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
6190 +- }
6191 +- pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
6192 +- vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
6193 +- pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
6194 +- vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
6195 +- pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
6196 +- vmcs_readl(GUEST_SYSENTER_ESP),
6197 +- vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
6198 +- vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
6199 +- vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
6200 +- vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
6201 +- vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
6202 +- vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
6203 +- vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
6204 +- vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
6205 +- vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
6206 +- vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
6207 +- vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
6208 +- if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
6209 +- (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
6210 +- pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
6211 +- efer, vmcs_read64(GUEST_IA32_PAT));
6212 +- pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
6213 +- vmcs_read64(GUEST_IA32_DEBUGCTL),
6214 +- vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
6215 +- if (cpu_has_load_perf_global_ctrl() &&
6216 +- vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
6217 +- pr_err("PerfGlobCtl = 0x%016llx\n",
6218 +- vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
6219 +- if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
6220 +- pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
6221 +- pr_err("Interruptibility = %08x ActivityState = %08x\n",
6222 +- vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
6223 +- vmcs_read32(GUEST_ACTIVITY_STATE));
6224 +- if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
6225 +- pr_err("InterruptStatus = %04x\n",
6226 +- vmcs_read16(GUEST_INTR_STATUS));
6227 +-
6228 +- pr_err("*** Host State ***\n");
6229 +- pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
6230 +- vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
6231 +- pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
6232 +- vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
6233 +- vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
6234 +- vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
6235 +- vmcs_read16(HOST_TR_SELECTOR));
6236 +- pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
6237 +- vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
6238 +- vmcs_readl(HOST_TR_BASE));
6239 +- pr_err("GDTBase=%016lx IDTBase=%016lx\n",
6240 +- vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
6241 +- pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
6242 +- vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
6243 +- vmcs_readl(HOST_CR4));
6244 +- pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
6245 +- vmcs_readl(HOST_IA32_SYSENTER_ESP),
6246 +- vmcs_read32(HOST_IA32_SYSENTER_CS),
6247 +- vmcs_readl(HOST_IA32_SYSENTER_EIP));
6248 +- if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
6249 +- pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
6250 +- vmcs_read64(HOST_IA32_EFER),
6251 +- vmcs_read64(HOST_IA32_PAT));
6252 +- if (cpu_has_load_perf_global_ctrl() &&
6253 +- vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
6254 +- pr_err("PerfGlobCtl = 0x%016llx\n",
6255 +- vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
6256 +-
6257 +- pr_err("*** Control State ***\n");
6258 +- pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
6259 +- pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
6260 +- pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
6261 +- pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
6262 +- vmcs_read32(EXCEPTION_BITMAP),
6263 +- vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
6264 +- vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
6265 +- pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
6266 +- vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6267 +- vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
6268 +- vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
6269 +- pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
6270 +- vmcs_read32(VM_EXIT_INTR_INFO),
6271 +- vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6272 +- vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
6273 +- pr_err(" reason=%08x qualification=%016lx\n",
6274 +- vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
6275 +- pr_err("IDTVectoring: info=%08x errcode=%08x\n",
6276 +- vmcs_read32(IDT_VECTORING_INFO_FIELD),
6277 +- vmcs_read32(IDT_VECTORING_ERROR_CODE));
6278 +- pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
6279 +- if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
6280 +- pr_err("TSC Multiplier = 0x%016llx\n",
6281 +- vmcs_read64(TSC_MULTIPLIER));
6282 +- if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
6283 +- if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
6284 +- u16 status = vmcs_read16(GUEST_INTR_STATUS);
6285 +- pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
6286 +- }
6287 +- pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
6288 +- if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
6289 +- pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
6290 +- pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
6291 +- }
6292 +- if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
6293 +- pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
6294 +- if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
6295 +- pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
6296 +- n = vmcs_read32(CR3_TARGET_COUNT);
6297 +- for (i = 0; i + 1 < n; i += 4)
6298 +- pr_err("CR3 target%u=%016lx target%u=%016lx\n",
6299 +- i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
6300 +- i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
6301 +- if (i < n)
6302 +- pr_err("CR3 target%u=%016lx\n",
6303 +- i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
6304 +- if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
6305 +- pr_err("PLE Gap=%08x Window=%08x\n",
6306 +- vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
6307 +- if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
6308 +- pr_err("Virtual processor ID = 0x%04x\n",
6309 +- vmcs_read16(VIRTUAL_PROCESSOR_ID));
6310 +-}
6311 +-
6312 +-/*
6313 +- * The guest has exited. See if we can fix it or if we need userspace
6314 +- * assistance.
6315 +- */
6316 +-static int vmx_handle_exit(struct kvm_vcpu *vcpu,
6317 +- enum exit_fastpath_completion exit_fastpath)
6318 +-{
6319 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
6320 +- u32 exit_reason = vmx->exit_reason;
6321 +- u32 vectoring_info = vmx->idt_vectoring_info;
6322 +-
6323 +- trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
6324 +-
6325 +- /*
6326 +- * Flush logged GPAs PML buffer, this will make dirty_bitmap more
6327 +- * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
6328 +- * querying dirty_bitmap, we only need to kick all vcpus out of guest
6329 +- * mode as if vcpus is in root mode, the PML buffer must has been
6330 +- * flushed already.
6331 +- */
6332 +- if (enable_pml)
6333 +- vmx_flush_pml_buffer(vcpu);
6334 +-
6335 +- /* If guest state is invalid, start emulating */
6336 +- if (vmx->emulation_required)
6337 +- return handle_invalid_guest_state(vcpu);
6338 +-
6339 +- if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
6340 +- return nested_vmx_reflect_vmexit(vcpu, exit_reason);
6341 +-
6342 +- if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6343 +- dump_vmcs();
6344 +- vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6345 +- vcpu->run->fail_entry.hardware_entry_failure_reason
6346 +- = exit_reason;
6347 +- return 0;
6348 +- }
6349 +-
6350 +- if (unlikely(vmx->fail)) {
6351 +- dump_vmcs();
6352 +- vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6353 +- vcpu->run->fail_entry.hardware_entry_failure_reason
6354 +- = vmcs_read32(VM_INSTRUCTION_ERROR);
6355 +- return 0;
6356 +- }
6357 +-
6358 +- /*
6359 +- * Note:
6360 +- * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6361 +- * delivery event since it indicates guest is accessing MMIO.
6362 +- * The vm-exit can be triggered again after return to guest that
6363 +- * will cause infinite loop.
6364 +- */
6365 +- if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6366 +- (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6367 +- exit_reason != EXIT_REASON_EPT_VIOLATION &&
6368 +- exit_reason != EXIT_REASON_PML_FULL &&
6369 +- exit_reason != EXIT_REASON_TASK_SWITCH)) {
6370 +- vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6371 +- vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6372 +- vcpu->run->internal.ndata = 3;
6373 +- vcpu->run->internal.data[0] = vectoring_info;
6374 +- vcpu->run->internal.data[1] = exit_reason;
6375 +- vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
6376 +- if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
6377 +- vcpu->run->internal.ndata++;
6378 +- vcpu->run->internal.data[3] =
6379 +- vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6380 +- }
6381 +- return 0;
6382 +- }
6383 +-
6384 +- if (unlikely(!enable_vnmi &&
6385 +- vmx->loaded_vmcs->soft_vnmi_blocked)) {
6386 +- if (vmx_interrupt_allowed(vcpu)) {
6387 +- vmx->loaded_vmcs->soft_vnmi_blocked = 0;
6388 +- } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
6389 +- vcpu->arch.nmi_pending) {
6390 +- /*
6391 +- * This CPU don't support us in finding the end of an
6392 +- * NMI-blocked window if the guest runs with IRQs
6393 +- * disabled. So we pull the trigger after 1 s of
6394 +- * futile waiting, but inform the user about this.
6395 +- */
6396 +- printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6397 +- "state on VCPU %d after 1 s timeout\n",
6398 +- __func__, vcpu->vcpu_id);
6399 +- vmx->loaded_vmcs->soft_vnmi_blocked = 0;
6400 +- }
6401 +- }
6402 +-
6403 +- if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
6404 +- kvm_skip_emulated_instruction(vcpu);
6405 +- return 1;
6406 +- } else if (exit_reason < kvm_vmx_max_exit_handlers
6407 +- && kvm_vmx_exit_handlers[exit_reason]) {
6408 +-#ifdef CONFIG_RETPOLINE
6409 +- if (exit_reason == EXIT_REASON_MSR_WRITE)
6410 +- return kvm_emulate_wrmsr(vcpu);
6411 +- else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
6412 +- return handle_preemption_timer(vcpu);
6413 +- else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
6414 +- return handle_interrupt_window(vcpu);
6415 +- else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6416 +- return handle_external_interrupt(vcpu);
6417 +- else if (exit_reason == EXIT_REASON_HLT)
6418 +- return kvm_emulate_halt(vcpu);
6419 +- else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
6420 +- return handle_ept_misconfig(vcpu);
6421 +-#endif
6422 +- return kvm_vmx_exit_handlers[exit_reason](vcpu);
6423 +- } else {
6424 +- vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
6425 +- exit_reason);
6426 +- dump_vmcs();
6427 +- vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6428 +- vcpu->run->internal.suberror =
6429 +- KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6430 +- vcpu->run->internal.ndata = 1;
6431 +- vcpu->run->internal.data[0] = exit_reason;
6432 +- return 0;
6433 +- }
6434 +-}
6435 +-
6436 +-/*
6437 +- * Software based L1D cache flush which is used when microcode providing
6438 +- * the cache control MSR is not loaded.
6439 +- *
6440 +- * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6441 +- * flush it is required to read in 64 KiB because the replacement algorithm
6442 +- * is not exactly LRU. This could be sized at runtime via topology
6443 +- * information but as all relevant affected CPUs have 32KiB L1D cache size
6444 +- * there is no point in doing so.
6445 +- */
6446 +-static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6447 +-{
6448 +- int size = PAGE_SIZE << L1D_CACHE_ORDER;
6449 +-
6450 +- /*
6451 +- * This code is only executed when the the flush mode is 'cond' or
6452 +- * 'always'
6453 +- */
6454 +- if (static_branch_likely(&vmx_l1d_flush_cond)) {
6455 +- bool flush_l1d;
6456 +-
6457 +- /*
6458 +- * Clear the per-vcpu flush bit, it gets set again
6459 +- * either from vcpu_run() or from one of the unsafe
6460 +- * VMEXIT handlers.
6461 +- */
6462 +- flush_l1d = vcpu->arch.l1tf_flush_l1d;
6463 +- vcpu->arch.l1tf_flush_l1d = false;
6464 +-
6465 +- /*
6466 +- * Clear the per-cpu flush bit, it gets set again from
6467 +- * the interrupt handlers.
6468 +- */
6469 +- flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6470 +- kvm_clear_cpu_l1tf_flush_l1d();
6471 +-
6472 +- if (!flush_l1d)
6473 +- return;
6474 +- }
6475 +-
6476 +- vcpu->stat.l1d_flush++;
6477 +-
6478 +- if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6479 +- wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6480 +- return;
6481 +- }
6482 +-
6483 +- asm volatile(
6484 +- /* First ensure the pages are in the TLB */
6485 +- "xorl %%eax, %%eax\n"
6486 +- ".Lpopulate_tlb:\n\t"
6487 +- "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6488 +- "addl $4096, %%eax\n\t"
6489 +- "cmpl %%eax, %[size]\n\t"
6490 +- "jne .Lpopulate_tlb\n\t"
6491 +- "xorl %%eax, %%eax\n\t"
6492 +- "cpuid\n\t"
6493 +- /* Now fill the cache */
6494 +- "xorl %%eax, %%eax\n"
6495 +- ".Lfill_cache:\n"
6496 +- "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6497 +- "addl $64, %%eax\n\t"
6498 +- "cmpl %%eax, %[size]\n\t"
6499 +- "jne .Lfill_cache\n\t"
6500 +- "lfence\n"
6501 +- :: [flush_pages] "r" (vmx_l1d_flush_pages),
6502 +- [size] "r" (size)
6503 +- : "eax", "ebx", "ecx", "edx");
6504 +-}
6505 +-
6506 +-static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6507 +-{
6508 +- struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6509 +- int tpr_threshold;
6510 +-
6511 +- if (is_guest_mode(vcpu) &&
6512 +- nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6513 +- return;
6514 +-
6515 +- tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6516 +- if (is_guest_mode(vcpu))
6517 +- to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6518 +- else
6519 +- vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6520 +-}
6521 +-
6522 +-void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6523 +-{
6524 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
6525 +- u32 sec_exec_control;
6526 +-
6527 +- if (!lapic_in_kernel(vcpu))
6528 +- return;
6529 +-
6530 +- if (!flexpriority_enabled &&
6531 +- !cpu_has_vmx_virtualize_x2apic_mode())
6532 +- return;
6533 +-
6534 +- /* Postpone execution until vmcs01 is the current VMCS. */
6535 +- if (is_guest_mode(vcpu)) {
6536 +- vmx->nested.change_vmcs01_virtual_apic_mode = true;
6537 +- return;
6538 +- }
6539 +-
6540 +- sec_exec_control = secondary_exec_controls_get(vmx);
6541 +- sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6542 +- SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6543 +-
6544 +- switch (kvm_get_apic_mode(vcpu)) {
6545 +- case LAPIC_MODE_INVALID:
6546 +- WARN_ONCE(true, "Invalid local APIC state");
6547 +- case LAPIC_MODE_DISABLED:
6548 +- break;
6549 +- case LAPIC_MODE_XAPIC:
6550 +- if (flexpriority_enabled) {
6551 +- sec_exec_control |=
6552 +- SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6553 +- vmx_flush_tlb(vcpu, true);
6554 +- }
6555 +- break;
6556 +- case LAPIC_MODE_X2APIC:
6557 +- if (cpu_has_vmx_virtualize_x2apic_mode())
6558 +- sec_exec_control |=
6559 +- SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6560 +- break;
6561 +- }
6562 +- secondary_exec_controls_set(vmx, sec_exec_control);
6563 +-
6564 +- vmx_update_msr_bitmap(vcpu);
6565 +-}
6566 +-
6567 +-static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6568 +-{
6569 +- if (!is_guest_mode(vcpu)) {
6570 +- vmcs_write64(APIC_ACCESS_ADDR, hpa);
6571 +- vmx_flush_tlb(vcpu, true);
6572 +- }
6573 +-}
6574 +-
6575 +-static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6576 +-{
6577 +- u16 status;
6578 +- u8 old;
6579 +-
6580 +- if (max_isr == -1)
6581 +- max_isr = 0;
6582 +-
6583 +- status = vmcs_read16(GUEST_INTR_STATUS);
6584 +- old = status >> 8;
6585 +- if (max_isr != old) {
6586 +- status &= 0xff;
6587 +- status |= max_isr << 8;
6588 +- vmcs_write16(GUEST_INTR_STATUS, status);
6589 +- }
6590 +-}
6591 +-
6592 +-static void vmx_set_rvi(int vector)
6593 +-{
6594 +- u16 status;
6595 +- u8 old;
6596 +-
6597 +- if (vector == -1)
6598 +- vector = 0;
6599 +-
6600 +- status = vmcs_read16(GUEST_INTR_STATUS);
6601 +- old = (u8)status & 0xff;
6602 +- if ((u8)vector != old) {
6603 +- status &= ~0xff;
6604 +- status |= (u8)vector;
6605 +- vmcs_write16(GUEST_INTR_STATUS, status);
6606 +- }
6607 +-}
6608 +-
6609 +-static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6610 +-{
6611 +- /*
6612 +- * When running L2, updating RVI is only relevant when
6613 +- * vmcs12 virtual-interrupt-delivery enabled.
6614 +- * However, it can be enabled only when L1 also
6615 +- * intercepts external-interrupts and in that case
6616 +- * we should not update vmcs02 RVI but instead intercept
6617 +- * interrupt. Therefore, do nothing when running L2.
6618 +- */
6619 +- if (!is_guest_mode(vcpu))
6620 +- vmx_set_rvi(max_irr);
6621 +-}
6622 +-
6623 +-static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6624 +-{
6625 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
6626 +- int max_irr;
6627 +- bool max_irr_updated;
6628 +-
6629 +- WARN_ON(!vcpu->arch.apicv_active);
6630 +- if (pi_test_on(&vmx->pi_desc)) {
6631 +- pi_clear_on(&vmx->pi_desc);
6632 +- /*
6633 +- * IOMMU can write to PID.ON, so the barrier matters even on UP.
6634 +- * But on x86 this is just a compiler barrier anyway.
6635 +- */
6636 +- smp_mb__after_atomic();
6637 +- max_irr_updated =
6638 +- kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6639 +-
6640 +- /*
6641 +- * If we are running L2 and L1 has a new pending interrupt
6642 +- * which can be injected, we should re-evaluate
6643 +- * what should be done with this new L1 interrupt.
6644 +- * If L1 intercepts external-interrupts, we should
6645 +- * exit from L2 to L1. Otherwise, interrupt should be
6646 +- * delivered directly to L2.
6647 +- */
6648 +- if (is_guest_mode(vcpu) && max_irr_updated) {
6649 +- if (nested_exit_on_intr(vcpu))
6650 +- kvm_vcpu_exiting_guest_mode(vcpu);
6651 +- else
6652 +- kvm_make_request(KVM_REQ_EVENT, vcpu);
6653 +- }
6654 +- } else {
6655 +- max_irr = kvm_lapic_find_highest_irr(vcpu);
6656 +- }
6657 +- vmx_hwapic_irr_update(vcpu, max_irr);
6658 +- return max_irr;
6659 +-}
6660 +-
6661 +-static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6662 +-{
6663 +- struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6664 +-
6665 +- return pi_test_on(pi_desc) ||
6666 +- (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
6667 +-}
6668 +-
6669 +-static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6670 +-{
6671 +- if (!kvm_vcpu_apicv_active(vcpu))
6672 +- return;
6673 +-
6674 +- vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6675 +- vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6676 +- vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6677 +- vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6678 +-}
6679 +-
6680 +-static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6681 +-{
6682 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
6683 +-
6684 +- pi_clear_on(&vmx->pi_desc);
6685 +- memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6686 +-}
6687 +-
6688 +-static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6689 +-{
6690 +- vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6691 +-
6692 +- /* if exit due to PF check for async PF */
6693 +- if (is_page_fault(vmx->exit_intr_info))
6694 +- vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6695 +-
6696 +- /* Handle machine checks before interrupts are enabled */
6697 +- if (is_machine_check(vmx->exit_intr_info))
6698 +- kvm_machine_check();
6699 +-
6700 +- /* We need to handle NMIs before interrupts are enabled */
6701 +- if (is_nmi(vmx->exit_intr_info)) {
6702 +- kvm_before_interrupt(&vmx->vcpu);
6703 +- asm("int $2");
6704 +- kvm_after_interrupt(&vmx->vcpu);
6705 +- }
6706 +-}
6707 +-
6708 +-static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6709 +-{
6710 +- unsigned int vector;
6711 +- unsigned long entry;
6712 +-#ifdef CONFIG_X86_64
6713 +- unsigned long tmp;
6714 +-#endif
6715 +- gate_desc *desc;
6716 +- u32 intr_info;
6717 +-
6718 +- intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6719 +- if (WARN_ONCE(!is_external_intr(intr_info),
6720 +- "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6721 +- return;
6722 +-
6723 +- vector = intr_info & INTR_INFO_VECTOR_MASK;
6724 +- desc = (gate_desc *)host_idt_base + vector;
6725 +- entry = gate_offset(desc);
6726 +-
6727 +- kvm_before_interrupt(vcpu);
6728 +-
6729 +- asm volatile(
6730 +-#ifdef CONFIG_X86_64
6731 +- "mov %%" _ASM_SP ", %[sp]\n\t"
6732 +- "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6733 +- "push $%c[ss]\n\t"
6734 +- "push %[sp]\n\t"
6735 +-#endif
6736 +- "pushf\n\t"
6737 +- __ASM_SIZE(push) " $%c[cs]\n\t"
6738 +- CALL_NOSPEC
6739 +- :
6740 +-#ifdef CONFIG_X86_64
6741 +- [sp]"=&r"(tmp),
6742 +-#endif
6743 +- ASM_CALL_CONSTRAINT
6744 +- :
6745 +- THUNK_TARGET(entry),
6746 +- [ss]"i"(__KERNEL_DS),
6747 +- [cs]"i"(__KERNEL_CS)
6748 +- );
6749 +-
6750 +- kvm_after_interrupt(vcpu);
6751 +-}
6752 +-STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6753 +-
6754 +-static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu,
6755 +- enum exit_fastpath_completion *exit_fastpath)
6756 +-{
6757 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
6758 +-
6759 +- if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6760 +- handle_external_interrupt_irqoff(vcpu);
6761 +- else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6762 +- handle_exception_nmi_irqoff(vmx);
6763 +- else if (!is_guest_mode(vcpu) &&
6764 +- vmx->exit_reason == EXIT_REASON_MSR_WRITE)
6765 +- *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
6766 +-}
6767 +-
6768 +-static bool vmx_has_emulated_msr(int index)
6769 +-{
6770 +- switch (index) {
6771 +- case MSR_IA32_SMBASE:
6772 +- /*
6773 +- * We cannot do SMM unless we can run the guest in big
6774 +- * real mode.
6775 +- */
6776 +- return enable_unrestricted_guest || emulate_invalid_guest_state;
6777 +- case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6778 +- return nested;
6779 +- case MSR_AMD64_VIRT_SPEC_CTRL:
6780 +- /* This is AMD only. */
6781 +- return false;
6782 +- default:
6783 +- return true;
6784 +- }
6785 +-}
6786 +-
6787 +-static bool vmx_pt_supported(void)
6788 +-{
6789 +- return pt_mode == PT_MODE_HOST_GUEST;
6790 +-}
6791 +-
6792 +-static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6793 +-{
6794 +- u32 exit_intr_info;
6795 +- bool unblock_nmi;
6796 +- u8 vector;
6797 +- bool idtv_info_valid;
6798 +-
6799 +- idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6800 +-
6801 +- if (enable_vnmi) {
6802 +- if (vmx->loaded_vmcs->nmi_known_unmasked)
6803 +- return;
6804 +- /*
6805 +- * Can't use vmx->exit_intr_info since we're not sure what
6806 +- * the exit reason is.
6807 +- */
6808 +- exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6809 +- unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6810 +- vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6811 +- /*
6812 +- * SDM 3: 27.7.1.2 (September 2008)
6813 +- * Re-set bit "block by NMI" before VM entry if vmexit caused by
6814 +- * a guest IRET fault.
6815 +- * SDM 3: 23.2.2 (September 2008)
6816 +- * Bit 12 is undefined in any of the following cases:
6817 +- * If the VM exit sets the valid bit in the IDT-vectoring
6818 +- * information field.
6819 +- * If the VM exit is due to a double fault.
6820 +- */
6821 +- if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6822 +- vector != DF_VECTOR && !idtv_info_valid)
6823 +- vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6824 +- GUEST_INTR_STATE_NMI);
6825 +- else
6826 +- vmx->loaded_vmcs->nmi_known_unmasked =
6827 +- !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6828 +- & GUEST_INTR_STATE_NMI);
6829 +- } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6830 +- vmx->loaded_vmcs->vnmi_blocked_time +=
6831 +- ktime_to_ns(ktime_sub(ktime_get(),
6832 +- vmx->loaded_vmcs->entry_time));
6833 +-}
6834 +-
6835 +-static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6836 +- u32 idt_vectoring_info,
6837 +- int instr_len_field,
6838 +- int error_code_field)
6839 +-{
6840 +- u8 vector;
6841 +- int type;
6842 +- bool idtv_info_valid;
6843 +-
6844 +- idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6845 +-
6846 +- vcpu->arch.nmi_injected = false;
6847 +- kvm_clear_exception_queue(vcpu);
6848 +- kvm_clear_interrupt_queue(vcpu);
6849 +-
6850 +- if (!idtv_info_valid)
6851 +- return;
6852 +-
6853 +- kvm_make_request(KVM_REQ_EVENT, vcpu);
6854 +-
6855 +- vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6856 +- type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6857 +-
6858 +- switch (type) {
6859 +- case INTR_TYPE_NMI_INTR:
6860 +- vcpu->arch.nmi_injected = true;
6861 +- /*
6862 +- * SDM 3: 27.7.1.2 (September 2008)
6863 +- * Clear bit "block by NMI" before VM entry if a NMI
6864 +- * delivery faulted.
6865 +- */
6866 +- vmx_set_nmi_mask(vcpu, false);
6867 +- break;
6868 +- case INTR_TYPE_SOFT_EXCEPTION:
6869 +- vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6870 +- /* fall through */
6871 +- case INTR_TYPE_HARD_EXCEPTION:
6872 +- if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6873 +- u32 err = vmcs_read32(error_code_field);
6874 +- kvm_requeue_exception_e(vcpu, vector, err);
6875 +- } else
6876 +- kvm_requeue_exception(vcpu, vector);
6877 +- break;
6878 +- case INTR_TYPE_SOFT_INTR:
6879 +- vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6880 +- /* fall through */
6881 +- case INTR_TYPE_EXT_INTR:
6882 +- kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6883 +- break;
6884 +- default:
6885 +- break;
6886 +- }
6887 +-}
6888 +-
6889 +-static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6890 +-{
6891 +- __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6892 +- VM_EXIT_INSTRUCTION_LEN,
6893 +- IDT_VECTORING_ERROR_CODE);
6894 +-}
6895 +-
6896 +-static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6897 +-{
6898 +- __vmx_complete_interrupts(vcpu,
6899 +- vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6900 +- VM_ENTRY_INSTRUCTION_LEN,
6901 +- VM_ENTRY_EXCEPTION_ERROR_CODE);
6902 +-
6903 +- vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6904 +-}
6905 +-
6906 +-static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6907 +-{
6908 +- int i, nr_msrs;
6909 +- struct perf_guest_switch_msr *msrs;
6910 +-
6911 +- msrs = perf_guest_get_msrs(&nr_msrs);
6912 +-
6913 +- if (!msrs)
6914 +- return;
6915 +-
6916 +- for (i = 0; i < nr_msrs; i++)
6917 +- if (msrs[i].host == msrs[i].guest)
6918 +- clear_atomic_switch_msr(vmx, msrs[i].msr);
6919 +- else
6920 +- add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6921 +- msrs[i].host, false);
6922 +-}
6923 +-
6924 +-static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6925 +-{
6926 +- u32 host_umwait_control;
6927 +-
6928 +- if (!vmx_has_waitpkg(vmx))
6929 +- return;
6930 +-
6931 +- host_umwait_control = get_umwait_control_msr();
6932 +-
6933 +- if (vmx->msr_ia32_umwait_control != host_umwait_control)
6934 +- add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6935 +- vmx->msr_ia32_umwait_control,
6936 +- host_umwait_control, false);
6937 +- else
6938 +- clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6939 +-}
6940 +-
6941 +-static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6942 +-{
6943 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
6944 +- u64 tscl;
6945 +- u32 delta_tsc;
6946 +-
6947 +- if (vmx->req_immediate_exit) {
6948 +- vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6949 +- vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6950 +- } else if (vmx->hv_deadline_tsc != -1) {
6951 +- tscl = rdtsc();
6952 +- if (vmx->hv_deadline_tsc > tscl)
6953 +- /* set_hv_timer ensures the delta fits in 32-bits */
6954 +- delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6955 +- cpu_preemption_timer_multi);
6956 +- else
6957 +- delta_tsc = 0;
6958 +-
6959 +- vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6960 +- vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6961 +- } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6962 +- vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6963 +- vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6964 +- }
6965 +-}
6966 +-
6967 +-void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6968 +-{
6969 +- if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6970 +- vmx->loaded_vmcs->host_state.rsp = host_rsp;
6971 +- vmcs_writel(HOST_RSP, host_rsp);
6972 +- }
6973 +-}
6974 +-
6975 +-bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6976 +-
6977 +-static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6978 +-{
6979 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
6980 +- unsigned long cr3, cr4;
6981 +-
6982 +- /* Record the guest's net vcpu time for enforced NMI injections. */
6983 +- if (unlikely(!enable_vnmi &&
6984 +- vmx->loaded_vmcs->soft_vnmi_blocked))
6985 +- vmx->loaded_vmcs->entry_time = ktime_get();
6986 +-
6987 +- /* Don't enter VMX if guest state is invalid, let the exit handler
6988 +- start emulation until we arrive back to a valid state */
6989 +- if (vmx->emulation_required)
6990 +- return;
6991 +-
6992 +- if (vmx->ple_window_dirty) {
6993 +- vmx->ple_window_dirty = false;
6994 +- vmcs_write32(PLE_WINDOW, vmx->ple_window);
6995 +- }
6996 +-
6997 +- if (vmx->nested.need_vmcs12_to_shadow_sync)
6998 +- nested_sync_vmcs12_to_shadow(vcpu);
6999 +-
7000 +- if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
7001 +- vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7002 +- if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
7003 +- vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7004 +-
7005 +- cr3 = __get_current_cr3_fast();
7006 +- if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
7007 +- vmcs_writel(HOST_CR3, cr3);
7008 +- vmx->loaded_vmcs->host_state.cr3 = cr3;
7009 +- }
7010 +-
7011 +- cr4 = cr4_read_shadow();
7012 +- if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
7013 +- vmcs_writel(HOST_CR4, cr4);
7014 +- vmx->loaded_vmcs->host_state.cr4 = cr4;
7015 +- }
7016 +-
7017 +- /* When single-stepping over STI and MOV SS, we must clear the
7018 +- * corresponding interruptibility bits in the guest state. Otherwise
7019 +- * vmentry fails as it then expects bit 14 (BS) in pending debug
7020 +- * exceptions being set, but that's not correct for the guest debugging
7021 +- * case. */
7022 +- if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7023 +- vmx_set_interrupt_shadow(vcpu, 0);
7024 +-
7025 +- kvm_load_guest_xsave_state(vcpu);
7026 +-
7027 +- if (static_cpu_has(X86_FEATURE_PKU) &&
7028 +- kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
7029 +- vcpu->arch.pkru != vmx->host_pkru)
7030 +- __write_pkru(vcpu->arch.pkru);
7031 +-
7032 +- pt_guest_enter(vmx);
7033 +-
7034 +- atomic_switch_perf_msrs(vmx);
7035 +- atomic_switch_umwait_control_msr(vmx);
7036 +-
7037 +- if (enable_preemption_timer)
7038 +- vmx_update_hv_timer(vcpu);
7039 +-
7040 +- if (lapic_in_kernel(vcpu) &&
7041 +- vcpu->arch.apic->lapic_timer.timer_advance_ns)
7042 +- kvm_wait_lapic_expire(vcpu);
7043 +-
7044 +- /*
7045 +- * If this vCPU has touched SPEC_CTRL, restore the guest's value if
7046 +- * it's non-zero. Since vmentry is serialising on affected CPUs, there
7047 +- * is no need to worry about the conditional branch over the wrmsr
7048 +- * being speculatively taken.
7049 +- */
7050 +- x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
7051 +-
7052 +- /* L1D Flush includes CPU buffer clear to mitigate MDS */
7053 +- if (static_branch_unlikely(&vmx_l1d_should_flush))
7054 +- vmx_l1d_flush(vcpu);
7055 +- else if (static_branch_unlikely(&mds_user_clear))
7056 +- mds_clear_cpu_buffers();
7057 +-
7058 +- if (vcpu->arch.cr2 != read_cr2())
7059 +- write_cr2(vcpu->arch.cr2);
7060 +-
7061 +- vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
7062 +- vmx->loaded_vmcs->launched);
7063 +-
7064 +- vcpu->arch.cr2 = read_cr2();
7065 +-
7066 +- /*
7067 +- * We do not use IBRS in the kernel. If this vCPU has used the
7068 +- * SPEC_CTRL MSR it may have left it on; save the value and
7069 +- * turn it off. This is much more efficient than blindly adding
7070 +- * it to the atomic save/restore list. Especially as the former
7071 +- * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
7072 +- *
7073 +- * For non-nested case:
7074 +- * If the L01 MSR bitmap does not intercept the MSR, then we need to
7075 +- * save it.
7076 +- *
7077 +- * For nested case:
7078 +- * If the L02 MSR bitmap does not intercept the MSR, then we need to
7079 +- * save it.
7080 +- */
7081 +- if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
7082 +- vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
7083 +-
7084 +- x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
7085 +-
7086 +- /* All fields are clean at this point */
7087 +- if (static_branch_unlikely(&enable_evmcs))
7088 +- current_evmcs->hv_clean_fields |=
7089 +- HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
7090 +-
7091 +- if (static_branch_unlikely(&enable_evmcs))
7092 +- current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
7093 +-
7094 +- /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7095 +- if (vmx->host_debugctlmsr)
7096 +- update_debugctlmsr(vmx->host_debugctlmsr);
7097 +-
7098 +-#ifndef CONFIG_X86_64
7099 +- /*
7100 +- * The sysexit path does not restore ds/es, so we must set them to
7101 +- * a reasonable value ourselves.
7102 +- *
7103 +- * We can't defer this to vmx_prepare_switch_to_host() since that
7104 +- * function may be executed in interrupt context, which saves and
7105 +- * restore segments around it, nullifying its effect.
7106 +- */
7107 +- loadsegment(ds, __USER_DS);
7108 +- loadsegment(es, __USER_DS);
7109 +-#endif
7110 +-
7111 +- vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7112 +- | (1 << VCPU_EXREG_RFLAGS)
7113 +- | (1 << VCPU_EXREG_PDPTR)
7114 +- | (1 << VCPU_EXREG_SEGMENTS)
7115 +- | (1 << VCPU_EXREG_CR3));
7116 +- vcpu->arch.regs_dirty = 0;
7117 +-
7118 +- pt_guest_exit(vmx);
7119 +-
7120 +- /*
7121 +- * eager fpu is enabled if PKEY is supported and CR4 is switched
7122 +- * back on host, so it is safe to read guest PKRU from current
7123 +- * XSAVE.
7124 +- */
7125 +- if (static_cpu_has(X86_FEATURE_PKU) &&
7126 +- kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
7127 +- vcpu->arch.pkru = rdpkru();
7128 +- if (vcpu->arch.pkru != vmx->host_pkru)
7129 +- __write_pkru(vmx->host_pkru);
7130 +- }
7131 +-
7132 +- kvm_load_host_xsave_state(vcpu);
7133 +-
7134 +- vmx->nested.nested_run_pending = 0;
7135 +- vmx->idt_vectoring_info = 0;
7136 +-
7137 +- vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
7138 +- if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
7139 +- kvm_machine_check();
7140 +-
7141 +- if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7142 +- return;
7143 +-
7144 +- vmx->loaded_vmcs->launched = 1;
7145 +- vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7146 +-
7147 +- vmx_recover_nmi_blocking(vmx);
7148 +- vmx_complete_interrupts(vmx);
7149 +-}
7150 +-
7151 +-static struct kvm *vmx_vm_alloc(void)
7152 +-{
7153 +- struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
7154 +- GFP_KERNEL_ACCOUNT | __GFP_ZERO,
7155 +- PAGE_KERNEL);
7156 +- return &kvm_vmx->kvm;
7157 +-}
7158 +-
7159 +-static void vmx_vm_free(struct kvm *kvm)
7160 +-{
7161 +- kfree(kvm->arch.hyperv.hv_pa_pg);
7162 +- vfree(to_kvm_vmx(kvm));
7163 +-}
7164 +-
7165 +-static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7166 +-{
7167 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
7168 +-
7169 +- if (enable_pml)
7170 +- vmx_destroy_pml_buffer(vmx);
7171 +- free_vpid(vmx->vpid);
7172 +- nested_vmx_free_vcpu(vcpu);
7173 +- free_loaded_vmcs(vmx->loaded_vmcs);
7174 +- kvm_vcpu_uninit(vcpu);
7175 +- kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
7176 +- kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
7177 +- kmem_cache_free(kvm_vcpu_cache, vmx);
7178 +-}
7179 +-
7180 +-static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7181 +-{
7182 +- int err;
7183 +- struct vcpu_vmx *vmx;
7184 +- unsigned long *msr_bitmap;
7185 +- int i, cpu;
7186 +-
7187 +- BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0,
7188 +- "struct kvm_vcpu must be at offset 0 for arch usercopy region");
7189 +-
7190 +- vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
7191 +- if (!vmx)
7192 +- return ERR_PTR(-ENOMEM);
7193 +-
7194 +- vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
7195 +- GFP_KERNEL_ACCOUNT);
7196 +- if (!vmx->vcpu.arch.user_fpu) {
7197 +- printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
7198 +- err = -ENOMEM;
7199 +- goto free_partial_vcpu;
7200 +- }
7201 +-
7202 +- vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
7203 +- GFP_KERNEL_ACCOUNT);
7204 +- if (!vmx->vcpu.arch.guest_fpu) {
7205 +- printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
7206 +- err = -ENOMEM;
7207 +- goto free_user_fpu;
7208 +- }
7209 +-
7210 +- vmx->vpid = allocate_vpid();
7211 +-
7212 +- err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7213 +- if (err)
7214 +- goto free_vcpu;
7215 +-
7216 +- err = -ENOMEM;
7217 +-
7218 +- /*
7219 +- * If PML is turned on, failure on enabling PML just results in failure
7220 +- * of creating the vcpu, therefore we can simplify PML logic (by
7221 +- * avoiding dealing with cases, such as enabling PML partially on vcpus
7222 +- * for the guest), etc.
7223 +- */
7224 +- if (enable_pml) {
7225 +- vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
7226 +- if (!vmx->pml_pg)
7227 +- goto uninit_vcpu;
7228 +- }
7229 +-
7230 +- BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS);
7231 +-
7232 +- for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
7233 +- u32 index = vmx_msr_index[i];
7234 +- u32 data_low, data_high;
7235 +- int j = vmx->nmsrs;
7236 +-
7237 +- if (rdmsr_safe(index, &data_low, &data_high) < 0)
7238 +- continue;
7239 +- if (wrmsr_safe(index, data_low, data_high) < 0)
7240 +- continue;
7241 +-
7242 +- vmx->guest_msrs[j].index = i;
7243 +- vmx->guest_msrs[j].data = 0;
7244 +- switch (index) {
7245 +- case MSR_IA32_TSX_CTRL:
7246 +- /*
7247 +- * No need to pass TSX_CTRL_CPUID_CLEAR through, so
7248 +- * let's avoid changing CPUID bits under the host
7249 +- * kernel's feet.
7250 +- */
7251 +- vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
7252 +- break;
7253 +- default:
7254 +- vmx->guest_msrs[j].mask = -1ull;
7255 +- break;
7256 +- }
7257 +- ++vmx->nmsrs;
7258 +- }
7259 +-
7260 +- err = alloc_loaded_vmcs(&vmx->vmcs01);
7261 +- if (err < 0)
7262 +- goto free_pml;
7263 +-
7264 +- msr_bitmap = vmx->vmcs01.msr_bitmap;
7265 +- vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
7266 +- vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
7267 +- vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
7268 +- vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
7269 +- vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
7270 +- vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
7271 +- vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
7272 +- if (kvm_cstate_in_guest(kvm)) {
7273 +- vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
7274 +- vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
7275 +- vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
7276 +- vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
7277 +- }
7278 +- vmx->msr_bitmap_mode = 0;
7279 +-
7280 +- vmx->loaded_vmcs = &vmx->vmcs01;
7281 +- cpu = get_cpu();
7282 +- vmx_vcpu_load(&vmx->vcpu, cpu);
7283 +- vmx->vcpu.cpu = cpu;
7284 +- init_vmcs(vmx);
7285 +- vmx_vcpu_put(&vmx->vcpu);
7286 +- put_cpu();
7287 +- if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
7288 +- err = alloc_apic_access_page(kvm);
7289 +- if (err)
7290 +- goto free_vmcs;
7291 +- }
7292 +-
7293 +- if (enable_ept && !enable_unrestricted_guest) {
7294 +- err = init_rmode_identity_map(kvm);
7295 +- if (err)
7296 +- goto free_vmcs;
7297 +- }
7298 +-
7299 +- if (nested)
7300 +- nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
7301 +- vmx_capability.ept,
7302 +- kvm_vcpu_apicv_active(&vmx->vcpu));
7303 +- else
7304 +- memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
7305 +-
7306 +- vmx->nested.posted_intr_nv = -1;
7307 +- vmx->nested.current_vmptr = -1ull;
7308 +-
7309 +- vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
7310 +-
7311 +- /*
7312 +- * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
7313 +- * or POSTED_INTR_WAKEUP_VECTOR.
7314 +- */
7315 +- vmx->pi_desc.nv = POSTED_INTR_VECTOR;
7316 +- vmx->pi_desc.sn = 1;
7317 +-
7318 +- vmx->ept_pointer = INVALID_PAGE;
7319 +-
7320 +- return &vmx->vcpu;
7321 +-
7322 +-free_vmcs:
7323 +- free_loaded_vmcs(vmx->loaded_vmcs);
7324 +-free_pml:
7325 +- vmx_destroy_pml_buffer(vmx);
7326 +-uninit_vcpu:
7327 +- kvm_vcpu_uninit(&vmx->vcpu);
7328 +-free_vcpu:
7329 +- free_vpid(vmx->vpid);
7330 +- kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
7331 +-free_user_fpu:
7332 +- kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
7333 +-free_partial_vcpu:
7334 +- kmem_cache_free(kvm_vcpu_cache, vmx);
7335 +- return ERR_PTR(err);
7336 +-}
7337 +-
7338 +-#define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
7339 +-#define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
7340 +-
7341 +-static int vmx_vm_init(struct kvm *kvm)
7342 +-{
7343 +- spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
7344 +-
7345 +- if (!ple_gap)
7346 +- kvm->arch.pause_in_guest = true;
7347 +-
7348 +- if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
7349 +- switch (l1tf_mitigation) {
7350 +- case L1TF_MITIGATION_OFF:
7351 +- case L1TF_MITIGATION_FLUSH_NOWARN:
7352 +- /* 'I explicitly don't care' is set */
7353 +- break;
7354 +- case L1TF_MITIGATION_FLUSH:
7355 +- case L1TF_MITIGATION_FLUSH_NOSMT:
7356 +- case L1TF_MITIGATION_FULL:
7357 +- /*
7358 +- * Warn upon starting the first VM in a potentially
7359 +- * insecure environment.
7360 +- */
7361 +- if (sched_smt_active())
7362 +- pr_warn_once(L1TF_MSG_SMT);
7363 +- if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
7364 +- pr_warn_once(L1TF_MSG_L1D);
7365 +- break;
7366 +- case L1TF_MITIGATION_FULL_FORCE:
7367 +- /* Flush is enforced */
7368 +- break;
7369 +- }
7370 +- }
7371 +- return 0;
7372 +-}
7373 +-
7374 +-static int __init vmx_check_processor_compat(void)
7375 +-{
7376 +- struct vmcs_config vmcs_conf;
7377 +- struct vmx_capability vmx_cap;
7378 +-
7379 +- if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
7380 +- return -EIO;
7381 +- if (nested)
7382 +- nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
7383 +- enable_apicv);
7384 +- if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7385 +- printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7386 +- smp_processor_id());
7387 +- return -EIO;
7388 +- }
7389 +- return 0;
7390 +-}
7391 +-
7392 +-static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7393 +-{
7394 +- u8 cache;
7395 +- u64 ipat = 0;
7396 +-
7397 +- /* For VT-d and EPT combination
7398 +- * 1. MMIO: always map as UC
7399 +- * 2. EPT with VT-d:
7400 +- * a. VT-d without snooping control feature: can't guarantee the
7401 +- * result, try to trust guest.
7402 +- * b. VT-d with snooping control feature: snooping control feature of
7403 +- * VT-d engine can guarantee the cache correctness. Just set it
7404 +- * to WB to keep consistent with host. So the same as item 3.
7405 +- * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7406 +- * consistent with host MTRR
7407 +- */
7408 +- if (is_mmio) {
7409 +- cache = MTRR_TYPE_UNCACHABLE;
7410 +- goto exit;
7411 +- }
7412 +-
7413 +- if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
7414 +- ipat = VMX_EPT_IPAT_BIT;
7415 +- cache = MTRR_TYPE_WRBACK;
7416 +- goto exit;
7417 +- }
7418 +-
7419 +- if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
7420 +- ipat = VMX_EPT_IPAT_BIT;
7421 +- if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
7422 +- cache = MTRR_TYPE_WRBACK;
7423 +- else
7424 +- cache = MTRR_TYPE_UNCACHABLE;
7425 +- goto exit;
7426 +- }
7427 +-
7428 +- cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
7429 +-
7430 +-exit:
7431 +- return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
7432 +-}
7433 +-
7434 +-static int vmx_get_lpage_level(void)
7435 +-{
7436 +- if (enable_ept && !cpu_has_vmx_ept_1g_page())
7437 +- return PT_DIRECTORY_LEVEL;
7438 +- else
7439 +- /* For shadow and EPT supported 1GB page */
7440 +- return PT_PDPE_LEVEL;
7441 +-}
7442 +-
7443 +-static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
7444 +-{
7445 +- /*
7446 +- * These bits in the secondary execution controls field
7447 +- * are dynamic, the others are mostly based on the hypervisor
7448 +- * architecture and the guest's CPUID. Do not touch the
7449 +- * dynamic bits.
7450 +- */
7451 +- u32 mask =
7452 +- SECONDARY_EXEC_SHADOW_VMCS |
7453 +- SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
7454 +- SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7455 +- SECONDARY_EXEC_DESC;
7456 +-
7457 +- u32 new_ctl = vmx->secondary_exec_control;
7458 +- u32 cur_ctl = secondary_exec_controls_get(vmx);
7459 +-
7460 +- secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
7461 +-}
7462 +-
7463 +-/*
7464 +- * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7465 +- * (indicating "allowed-1") if they are supported in the guest's CPUID.
7466 +- */
7467 +-static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7468 +-{
7469 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
7470 +- struct kvm_cpuid_entry2 *entry;
7471 +-
7472 +- vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7473 +- vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7474 +-
7475 +-#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
7476 +- if (entry && (entry->_reg & (_cpuid_mask))) \
7477 +- vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
7478 +-} while (0)
7479 +-
7480 +- entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7481 +- cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
7482 +- cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
7483 +- cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
7484 +- cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
7485 +- cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
7486 +- cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
7487 +- cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
7488 +- cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
7489 +- cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
7490 +- cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
7491 +- cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
7492 +- cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
7493 +- cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
7494 +- cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
7495 +-
7496 +- entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7497 +- cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
7498 +- cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
7499 +- cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
7500 +- cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
7501 +- cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
7502 +- cr4_fixed1_update(X86_CR4_LA57, ecx, bit(X86_FEATURE_LA57));
7503 +-
7504 +-#undef cr4_fixed1_update
7505 +-}
7506 +-
7507 +-static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7508 +-{
7509 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
7510 +-
7511 +- if (kvm_mpx_supported()) {
7512 +- bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7513 +-
7514 +- if (mpx_enabled) {
7515 +- vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7516 +- vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7517 +- } else {
7518 +- vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7519 +- vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7520 +- }
7521 +- }
7522 +-}
7523 +-
7524 +-static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7525 +-{
7526 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
7527 +- struct kvm_cpuid_entry2 *best = NULL;
7528 +- int i;
7529 +-
7530 +- for (i = 0; i < PT_CPUID_LEAVES; i++) {
7531 +- best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7532 +- if (!best)
7533 +- return;
7534 +- vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7535 +- vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7536 +- vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7537 +- vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7538 +- }
7539 +-
7540 +- /* Get the number of configurable Address Ranges for filtering */
7541 +- vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7542 +- PT_CAP_num_address_ranges);
7543 +-
7544 +- /* Initialize and clear the no dependency bits */
7545 +- vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7546 +- RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7547 +-
7548 +- /*
7549 +- * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7550 +- * will inject an #GP
7551 +- */
7552 +- if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7553 +- vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7554 +-
7555 +- /*
7556 +- * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7557 +- * PSBFreq can be set
7558 +- */
7559 +- if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7560 +- vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7561 +- RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7562 +-
7563 +- /*
7564 +- * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7565 +- * MTCFreq can be set
7566 +- */
7567 +- if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7568 +- vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7569 +- RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7570 +-
7571 +- /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7572 +- if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7573 +- vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7574 +- RTIT_CTL_PTW_EN);
7575 +-
7576 +- /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7577 +- if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7578 +- vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7579 +-
7580 +- /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7581 +- if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7582 +- vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7583 +-
7584 +- /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7585 +- if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7586 +- vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7587 +-
7588 +- /* unmask address range configure area */
7589 +- for (i = 0; i < vmx->pt_desc.addr_range; i++)
7590 +- vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7591 +-}
7592 +-
7593 +-static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7594 +-{
7595 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
7596 +-
7597 +- /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7598 +- vcpu->arch.xsaves_enabled = false;
7599 +-
7600 +- if (cpu_has_secondary_exec_ctrls()) {
7601 +- vmx_compute_secondary_exec_control(vmx);
7602 +- vmcs_set_secondary_exec_control(vmx);
7603 +- }
7604 +-
7605 +- if (nested_vmx_allowed(vcpu))
7606 +- to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7607 +- FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX |
7608 +- FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7609 +- else
7610 +- to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7611 +- ~(FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX |
7612 +- FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX);
7613 +-
7614 +- if (nested_vmx_allowed(vcpu)) {
7615 +- nested_vmx_cr_fixed1_bits_update(vcpu);
7616 +- nested_vmx_entry_exit_ctls_update(vcpu);
7617 +- }
7618 +-
7619 +- if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7620 +- guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7621 +- update_intel_pt_cfg(vcpu);
7622 +-
7623 +- if (boot_cpu_has(X86_FEATURE_RTM)) {
7624 +- struct shared_msr_entry *msr;
7625 +- msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
7626 +- if (msr) {
7627 +- bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7628 +- vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7629 +- }
7630 +- }
7631 +-}
7632 +-
7633 +-static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7634 +-{
7635 +- if (func == 1 && nested)
7636 +- entry->ecx |= bit(X86_FEATURE_VMX);
7637 +-}
7638 +-
7639 +-static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7640 +-{
7641 +- to_vmx(vcpu)->req_immediate_exit = true;
7642 +-}
7643 +-
7644 +-static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7645 +- struct x86_instruction_info *info,
7646 +- enum x86_intercept_stage stage)
7647 +-{
7648 +- struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7649 +- struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7650 +-
7651 +- /*
7652 +- * RDPID causes #UD if disabled through secondary execution controls.
7653 +- * Because it is marked as EmulateOnUD, we need to intercept it here.
7654 +- */
7655 +- if (info->intercept == x86_intercept_rdtscp &&
7656 +- !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7657 +- ctxt->exception.vector = UD_VECTOR;
7658 +- ctxt->exception.error_code_valid = false;
7659 +- return X86EMUL_PROPAGATE_FAULT;
7660 +- }
7661 +-
7662 +- /* TODO: check more intercepts... */
7663 +- return X86EMUL_CONTINUE;
7664 +-}
7665 +-
7666 +-#ifdef CONFIG_X86_64
7667 +-/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7668 +-static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7669 +- u64 divisor, u64 *result)
7670 +-{
7671 +- u64 low = a << shift, high = a >> (64 - shift);
7672 +-
7673 +- /* To avoid the overflow on divq */
7674 +- if (high >= divisor)
7675 +- return 1;
7676 +-
7677 +- /* Low hold the result, high hold rem which is discarded */
7678 +- asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7679 +- "rm" (divisor), "0" (low), "1" (high));
7680 +- *result = low;
7681 +-
7682 +- return 0;
7683 +-}
7684 +-
7685 +-static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7686 +- bool *expired)
7687 +-{
7688 +- struct vcpu_vmx *vmx;
7689 +- u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7690 +- struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7691 +-
7692 +- if (kvm_mwait_in_guest(vcpu->kvm) ||
7693 +- kvm_can_post_timer_interrupt(vcpu))
7694 +- return -EOPNOTSUPP;
7695 +-
7696 +- vmx = to_vmx(vcpu);
7697 +- tscl = rdtsc();
7698 +- guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7699 +- delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7700 +- lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7701 +- ktimer->timer_advance_ns);
7702 +-
7703 +- if (delta_tsc > lapic_timer_advance_cycles)
7704 +- delta_tsc -= lapic_timer_advance_cycles;
7705 +- else
7706 +- delta_tsc = 0;
7707 +-
7708 +- /* Convert to host delta tsc if tsc scaling is enabled */
7709 +- if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7710 +- delta_tsc && u64_shl_div_u64(delta_tsc,
7711 +- kvm_tsc_scaling_ratio_frac_bits,
7712 +- vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7713 +- return -ERANGE;
7714 +-
7715 +- /*
7716 +- * If the delta tsc can't fit in the 32 bit after the multi shift,
7717 +- * we can't use the preemption timer.
7718 +- * It's possible that it fits on later vmentries, but checking
7719 +- * on every vmentry is costly so we just use an hrtimer.
7720 +- */
7721 +- if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7722 +- return -ERANGE;
7723 +-
7724 +- vmx->hv_deadline_tsc = tscl + delta_tsc;
7725 +- *expired = !delta_tsc;
7726 +- return 0;
7727 +-}
7728 +-
7729 +-static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7730 +-{
7731 +- to_vmx(vcpu)->hv_deadline_tsc = -1;
7732 +-}
7733 +-#endif
7734 +-
7735 +-static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7736 +-{
7737 +- if (!kvm_pause_in_guest(vcpu->kvm))
7738 +- shrink_ple_window(vcpu);
7739 +-}
7740 +-
7741 +-static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7742 +- struct kvm_memory_slot *slot)
7743 +-{
7744 +- kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7745 +- kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7746 +-}
7747 +-
7748 +-static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7749 +- struct kvm_memory_slot *slot)
7750 +-{
7751 +- kvm_mmu_slot_set_dirty(kvm, slot);
7752 +-}
7753 +-
7754 +-static void vmx_flush_log_dirty(struct kvm *kvm)
7755 +-{
7756 +- kvm_flush_pml_buffers(kvm);
7757 +-}
7758 +-
7759 +-static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7760 +-{
7761 +- struct vmcs12 *vmcs12;
7762 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
7763 +- gpa_t gpa, dst;
7764 +-
7765 +- if (is_guest_mode(vcpu)) {
7766 +- WARN_ON_ONCE(vmx->nested.pml_full);
7767 +-
7768 +- /*
7769 +- * Check if PML is enabled for the nested guest.
7770 +- * Whether eptp bit 6 is set is already checked
7771 +- * as part of A/D emulation.
7772 +- */
7773 +- vmcs12 = get_vmcs12(vcpu);
7774 +- if (!nested_cpu_has_pml(vmcs12))
7775 +- return 0;
7776 +-
7777 +- if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7778 +- vmx->nested.pml_full = true;
7779 +- return 1;
7780 +- }
7781 +-
7782 +- gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7783 +- dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7784 +-
7785 +- if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7786 +- offset_in_page(dst), sizeof(gpa)))
7787 +- return 0;
7788 +-
7789 +- vmcs12->guest_pml_index--;
7790 +- }
7791 +-
7792 +- return 0;
7793 +-}
7794 +-
7795 +-static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7796 +- struct kvm_memory_slot *memslot,
7797 +- gfn_t offset, unsigned long mask)
7798 +-{
7799 +- kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7800 +-}
7801 +-
7802 +-static void __pi_post_block(struct kvm_vcpu *vcpu)
7803 +-{
7804 +- struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7805 +- struct pi_desc old, new;
7806 +- unsigned int dest;
7807 +-
7808 +- do {
7809 +- old.control = new.control = pi_desc->control;
7810 +- WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7811 +- "Wakeup handler not enabled while the VCPU is blocked\n");
7812 +-
7813 +- dest = cpu_physical_id(vcpu->cpu);
7814 +-
7815 +- if (x2apic_enabled())
7816 +- new.ndst = dest;
7817 +- else
7818 +- new.ndst = (dest << 8) & 0xFF00;
7819 +-
7820 +- /* set 'NV' to 'notification vector' */
7821 +- new.nv = POSTED_INTR_VECTOR;
7822 +- } while (cmpxchg64(&pi_desc->control, old.control,
7823 +- new.control) != old.control);
7824 +-
7825 +- if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7826 +- spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7827 +- list_del(&vcpu->blocked_vcpu_list);
7828 +- spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7829 +- vcpu->pre_pcpu = -1;
7830 +- }
7831 +-}
7832 +-
7833 +-/*
7834 +- * This routine does the following things for vCPU which is going
7835 +- * to be blocked if VT-d PI is enabled.
7836 +- * - Store the vCPU to the wakeup list, so when interrupts happen
7837 +- * we can find the right vCPU to wake up.
7838 +- * - Change the Posted-interrupt descriptor as below:
7839 +- * 'NDST' <-- vcpu->pre_pcpu
7840 +- * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7841 +- * - If 'ON' is set during this process, which means at least one
7842 +- * interrupt is posted for this vCPU, we cannot block it, in
7843 +- * this case, return 1, otherwise, return 0.
7844 +- *
7845 +- */
7846 +-static int pi_pre_block(struct kvm_vcpu *vcpu)
7847 +-{
7848 +- unsigned int dest;
7849 +- struct pi_desc old, new;
7850 +- struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7851 +-
7852 +- if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7853 +- !irq_remapping_cap(IRQ_POSTING_CAP) ||
7854 +- !kvm_vcpu_apicv_active(vcpu))
7855 +- return 0;
7856 +-
7857 +- WARN_ON(irqs_disabled());
7858 +- local_irq_disable();
7859 +- if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7860 +- vcpu->pre_pcpu = vcpu->cpu;
7861 +- spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7862 +- list_add_tail(&vcpu->blocked_vcpu_list,
7863 +- &per_cpu(blocked_vcpu_on_cpu,
7864 +- vcpu->pre_pcpu));
7865 +- spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7866 +- }
7867 +-
7868 +- do {
7869 +- old.control = new.control = pi_desc->control;
7870 +-
7871 +- WARN((pi_desc->sn == 1),
7872 +- "Warning: SN field of posted-interrupts "
7873 +- "is set before blocking\n");
7874 +-
7875 +- /*
7876 +- * Since vCPU can be preempted during this process,
7877 +- * vcpu->cpu could be different with pre_pcpu, we
7878 +- * need to set pre_pcpu as the destination of wakeup
7879 +- * notification event, then we can find the right vCPU
7880 +- * to wakeup in wakeup handler if interrupts happen
7881 +- * when the vCPU is in blocked state.
7882 +- */
7883 +- dest = cpu_physical_id(vcpu->pre_pcpu);
7884 +-
7885 +- if (x2apic_enabled())
7886 +- new.ndst = dest;
7887 +- else
7888 +- new.ndst = (dest << 8) & 0xFF00;
7889 +-
7890 +- /* set 'NV' to 'wakeup vector' */
7891 +- new.nv = POSTED_INTR_WAKEUP_VECTOR;
7892 +- } while (cmpxchg64(&pi_desc->control, old.control,
7893 +- new.control) != old.control);
7894 +-
7895 +- /* We should not block the vCPU if an interrupt is posted for it. */
7896 +- if (pi_test_on(pi_desc) == 1)
7897 +- __pi_post_block(vcpu);
7898 +-
7899 +- local_irq_enable();
7900 +- return (vcpu->pre_pcpu == -1);
7901 +-}
7902 +-
7903 +-static int vmx_pre_block(struct kvm_vcpu *vcpu)
7904 +-{
7905 +- if (pi_pre_block(vcpu))
7906 +- return 1;
7907 +-
7908 +- if (kvm_lapic_hv_timer_in_use(vcpu))
7909 +- kvm_lapic_switch_to_sw_timer(vcpu);
7910 +-
7911 +- return 0;
7912 +-}
7913 +-
7914 +-static void pi_post_block(struct kvm_vcpu *vcpu)
7915 +-{
7916 +- if (vcpu->pre_pcpu == -1)
7917 +- return;
7918 +-
7919 +- WARN_ON(irqs_disabled());
7920 +- local_irq_disable();
7921 +- __pi_post_block(vcpu);
7922 +- local_irq_enable();
7923 +-}
7924 +-
7925 +-static void vmx_post_block(struct kvm_vcpu *vcpu)
7926 +-{
7927 +- if (kvm_x86_ops->set_hv_timer)
7928 +- kvm_lapic_switch_to_hv_timer(vcpu);
7929 +-
7930 +- pi_post_block(vcpu);
7931 +-}
7932 +-
7933 +-/*
7934 +- * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7935 +- *
7936 +- * @kvm: kvm
7937 +- * @host_irq: host irq of the interrupt
7938 +- * @guest_irq: gsi of the interrupt
7939 +- * @set: set or unset PI
7940 +- * returns 0 on success, < 0 on failure
7941 +- */
7942 +-static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7943 +- uint32_t guest_irq, bool set)
7944 +-{
7945 +- struct kvm_kernel_irq_routing_entry *e;
7946 +- struct kvm_irq_routing_table *irq_rt;
7947 +- struct kvm_lapic_irq irq;
7948 +- struct kvm_vcpu *vcpu;
7949 +- struct vcpu_data vcpu_info;
7950 +- int idx, ret = 0;
7951 +-
7952 +- if (!kvm_arch_has_assigned_device(kvm) ||
7953 +- !irq_remapping_cap(IRQ_POSTING_CAP) ||
7954 +- !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7955 +- return 0;
7956 +-
7957 +- idx = srcu_read_lock(&kvm->irq_srcu);
7958 +- irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7959 +- if (guest_irq >= irq_rt->nr_rt_entries ||
7960 +- hlist_empty(&irq_rt->map[guest_irq])) {
7961 +- pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7962 +- guest_irq, irq_rt->nr_rt_entries);
7963 +- goto out;
7964 +- }
7965 +-
7966 +- hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7967 +- if (e->type != KVM_IRQ_ROUTING_MSI)
7968 +- continue;
7969 +- /*
7970 +- * VT-d PI cannot support posting multicast/broadcast
7971 +- * interrupts to a vCPU, we still use interrupt remapping
7972 +- * for these kind of interrupts.
7973 +- *
7974 +- * For lowest-priority interrupts, we only support
7975 +- * those with single CPU as the destination, e.g. user
7976 +- * configures the interrupts via /proc/irq or uses
7977 +- * irqbalance to make the interrupts single-CPU.
7978 +- *
7979 +- * We will support full lowest-priority interrupt later.
7980 +- *
7981 +- * In addition, we can only inject generic interrupts using
7982 +- * the PI mechanism, refuse to route others through it.
7983 +- */
7984 +-
7985 +- kvm_set_msi_irq(kvm, e, &irq);
7986 +- if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7987 +- !kvm_irq_is_postable(&irq)) {
7988 +- /*
7989 +- * Make sure the IRTE is in remapped mode if
7990 +- * we don't handle it in posted mode.
7991 +- */
7992 +- ret = irq_set_vcpu_affinity(host_irq, NULL);
7993 +- if (ret < 0) {
7994 +- printk(KERN_INFO
7995 +- "failed to back to remapped mode, irq: %u\n",
7996 +- host_irq);
7997 +- goto out;
7998 +- }
7999 +-
8000 +- continue;
8001 +- }
8002 +-
8003 +- vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
8004 +- vcpu_info.vector = irq.vector;
8005 +-
8006 +- trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
8007 +- vcpu_info.vector, vcpu_info.pi_desc_addr, set);
8008 +-
8009 +- if (set)
8010 +- ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
8011 +- else
8012 +- ret = irq_set_vcpu_affinity(host_irq, NULL);
8013 +-
8014 +- if (ret < 0) {
8015 +- printk(KERN_INFO "%s: failed to update PI IRTE\n",
8016 +- __func__);
8017 +- goto out;
8018 +- }
8019 +- }
8020 +-
8021 +- ret = 0;
8022 +-out:
8023 +- srcu_read_unlock(&kvm->irq_srcu, idx);
8024 +- return ret;
8025 +-}
8026 +-
8027 +-static void vmx_setup_mce(struct kvm_vcpu *vcpu)
8028 +-{
8029 +- if (vcpu->arch.mcg_cap & MCG_LMCE_P)
8030 +- to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
8031 +- FEATURE_CONTROL_LMCE;
8032 +- else
8033 +- to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
8034 +- ~FEATURE_CONTROL_LMCE;
8035 +-}
8036 +-
8037 +-static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
8038 +-{
8039 +- /* we need a nested vmexit to enter SMM, postpone if run is pending */
8040 +- if (to_vmx(vcpu)->nested.nested_run_pending)
8041 +- return 0;
8042 +- return 1;
8043 +-}
8044 +-
8045 +-static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
8046 +-{
8047 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
8048 +-
8049 +- vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
8050 +- if (vmx->nested.smm.guest_mode)
8051 +- nested_vmx_vmexit(vcpu, -1, 0, 0);
8052 +-
8053 +- vmx->nested.smm.vmxon = vmx->nested.vmxon;
8054 +- vmx->nested.vmxon = false;
8055 +- vmx_clear_hlt(vcpu);
8056 +- return 0;
8057 +-}
8058 +-
8059 +-static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
8060 +-{
8061 +- struct vcpu_vmx *vmx = to_vmx(vcpu);
8062 +- int ret;
8063 +-
8064 +- if (vmx->nested.smm.vmxon) {
8065 +- vmx->nested.vmxon = true;
8066 +- vmx->nested.smm.vmxon = false;
8067 +- }
8068 +-
8069 +- if (vmx->nested.smm.guest_mode) {
8070 +- ret = nested_vmx_enter_non_root_mode(vcpu, false);
8071 +- if (ret)
8072 +- return ret;
8073 +-
8074 +- vmx->nested.smm.guest_mode = false;
8075 +- }
8076 +- return 0;
8077 +-}
8078 +-
8079 +-static int enable_smi_window(struct kvm_vcpu *vcpu)
8080 +-{
8081 +- return 0;
8082 +-}
8083 +-
8084 +-static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
8085 +-{
8086 +- return false;
8087 +-}
8088 +-
8089 +-static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
8090 +-{
8091 +- return to_vmx(vcpu)->nested.vmxon;
8092 +-}
8093 +-
8094 +-static __init int hardware_setup(void)
8095 +-{
8096 +- unsigned long host_bndcfgs;
8097 +- struct desc_ptr dt;
8098 +- int r, i;
8099 +-
8100 +- rdmsrl_safe(MSR_EFER, &host_efer);
8101 +-
8102 +- store_idt(&dt);
8103 +- host_idt_base = dt.address;
8104 +-
8105 +- for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
8106 +- kvm_define_shared_msr(i, vmx_msr_index[i]);
8107 +-
8108 +- if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
8109 +- return -EIO;
8110 +-
8111 +- if (boot_cpu_has(X86_FEATURE_NX))
8112 +- kvm_enable_efer_bits(EFER_NX);
8113 +-
8114 +- if (boot_cpu_has(X86_FEATURE_MPX)) {
8115 +- rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
8116 +- WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
8117 +- }
8118 +-
8119 +- if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
8120 +- !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
8121 +- enable_vpid = 0;
8122 +-
8123 +- if (!cpu_has_vmx_ept() ||
8124 +- !cpu_has_vmx_ept_4levels() ||
8125 +- !cpu_has_vmx_ept_mt_wb() ||
8126 +- !cpu_has_vmx_invept_global())
8127 +- enable_ept = 0;
8128 +-
8129 +- if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
8130 +- enable_ept_ad_bits = 0;
8131 +-
8132 +- if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
8133 +- enable_unrestricted_guest = 0;
8134 +-
8135 +- if (!cpu_has_vmx_flexpriority())
8136 +- flexpriority_enabled = 0;
8137 +-
8138 +- if (!cpu_has_virtual_nmis())
8139 +- enable_vnmi = 0;
8140 +-
8141 +- /*
8142 +- * set_apic_access_page_addr() is used to reload apic access
8143 +- * page upon invalidation. No need to do anything if not
8144 +- * using the APIC_ACCESS_ADDR VMCS field.
8145 +- */
8146 +- if (!flexpriority_enabled)
8147 +- kvm_x86_ops->set_apic_access_page_addr = NULL;
8148 +-
8149 +- if (!cpu_has_vmx_tpr_shadow())
8150 +- kvm_x86_ops->update_cr8_intercept = NULL;
8151 +-
8152 +- if (enable_ept && !cpu_has_vmx_ept_2m_page())
8153 +- kvm_disable_largepages();
8154 +-
8155 +-#if IS_ENABLED(CONFIG_HYPERV)
8156 +- if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
8157 +- && enable_ept) {
8158 +- kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
8159 +- kvm_x86_ops->tlb_remote_flush_with_range =
8160 +- hv_remote_flush_tlb_with_range;
8161 +- }
8162 +-#endif
8163 +-
8164 +- if (!cpu_has_vmx_ple()) {
8165 +- ple_gap = 0;
8166 +- ple_window = 0;
8167 +- ple_window_grow = 0;
8168 +- ple_window_max = 0;
8169 +- ple_window_shrink = 0;
8170 +- }
8171 +-
8172 +- if (!cpu_has_vmx_apicv()) {
8173 +- enable_apicv = 0;
8174 +- kvm_x86_ops->sync_pir_to_irr = NULL;
8175 +- }
8176 +-
8177 +- if (cpu_has_vmx_tsc_scaling()) {
8178 +- kvm_has_tsc_control = true;
8179 +- kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
8180 +- kvm_tsc_scaling_ratio_frac_bits = 48;
8181 +- }
8182 +-
8183 +- set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8184 +-
8185 +- if (enable_ept)
8186 +- vmx_enable_tdp();
8187 +- else
8188 +- kvm_disable_tdp();
8189 +-
8190 +- /*
8191 +- * Only enable PML when hardware supports PML feature, and both EPT
8192 +- * and EPT A/D bit features are enabled -- PML depends on them to work.
8193 +- */
8194 +- if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
8195 +- enable_pml = 0;
8196 +-
8197 +- if (!enable_pml) {
8198 +- kvm_x86_ops->slot_enable_log_dirty = NULL;
8199 +- kvm_x86_ops->slot_disable_log_dirty = NULL;
8200 +- kvm_x86_ops->flush_log_dirty = NULL;
8201 +- kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
8202 +- }
8203 +-
8204 +- if (!cpu_has_vmx_preemption_timer())
8205 +- enable_preemption_timer = false;
8206 +-
8207 +- if (enable_preemption_timer) {
8208 +- u64 use_timer_freq = 5000ULL * 1000 * 1000;
8209 +- u64 vmx_msr;
8210 +-
8211 +- rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
8212 +- cpu_preemption_timer_multi =
8213 +- vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
8214 +-
8215 +- if (tsc_khz)
8216 +- use_timer_freq = (u64)tsc_khz * 1000;
8217 +- use_timer_freq >>= cpu_preemption_timer_multi;
8218 +-
8219 +- /*
8220 +- * KVM "disables" the preemption timer by setting it to its max
8221 +- * value. Don't use the timer if it might cause spurious exits
8222 +- * at a rate faster than 0.1 Hz (of uninterrupted guest time).
8223 +- */
8224 +- if (use_timer_freq > 0xffffffffu / 10)
8225 +- enable_preemption_timer = false;
8226 +- }
8227 +-
8228 +- if (!enable_preemption_timer) {
8229 +- kvm_x86_ops->set_hv_timer = NULL;
8230 +- kvm_x86_ops->cancel_hv_timer = NULL;
8231 +- kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
8232 +- }
8233 +-
8234 +- kvm_set_posted_intr_wakeup_handler(wakeup_handler);
8235 +-
8236 +- kvm_mce_cap_supported |= MCG_LMCE_P;
8237 +-
8238 +- if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
8239 +- return -EINVAL;
8240 +- if (!enable_ept || !cpu_has_vmx_intel_pt())
8241 +- pt_mode = PT_MODE_SYSTEM;
8242 +-
8243 +- if (nested) {
8244 +- nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
8245 +- vmx_capability.ept, enable_apicv);
8246 +-
8247 +- r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
8248 +- if (r)
8249 +- return r;
8250 +- }
8251 +-
8252 +- r = alloc_kvm_area();
8253 +- if (r)
8254 +- nested_vmx_hardware_unsetup();
8255 +- return r;
8256 +-}
8257 +-
8258 +-static __exit void hardware_unsetup(void)
8259 +-{
8260 +- if (nested)
8261 +- nested_vmx_hardware_unsetup();
8262 +-
8263 +- free_kvm_area();
8264 +-}
8265 +-
8266 +-static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
8267 +- .cpu_has_kvm_support = cpu_has_kvm_support,
8268 +- .disabled_by_bios = vmx_disabled_by_bios,
8269 +- .hardware_setup = hardware_setup,
8270 +- .hardware_unsetup = hardware_unsetup,
8271 +- .check_processor_compatibility = vmx_check_processor_compat,
8272 +- .hardware_enable = hardware_enable,
8273 +- .hardware_disable = hardware_disable,
8274 +- .cpu_has_accelerated_tpr = report_flexpriority,
8275 +- .has_emulated_msr = vmx_has_emulated_msr,
8276 +-
8277 +- .vm_init = vmx_vm_init,
8278 +- .vm_alloc = vmx_vm_alloc,
8279 +- .vm_free = vmx_vm_free,
8280 +-
8281 +- .vcpu_create = vmx_create_vcpu,
8282 +- .vcpu_free = vmx_free_vcpu,
8283 +- .vcpu_reset = vmx_vcpu_reset,
8284 +-
8285 +- .prepare_guest_switch = vmx_prepare_switch_to_guest,
8286 +- .vcpu_load = vmx_vcpu_load,
8287 +- .vcpu_put = vmx_vcpu_put,
8288 +-
8289 +- .update_bp_intercept = update_exception_bitmap,
8290 +- .get_msr_feature = vmx_get_msr_feature,
8291 +- .get_msr = vmx_get_msr,
8292 +- .set_msr = vmx_set_msr,
8293 +- .get_segment_base = vmx_get_segment_base,
8294 +- .get_segment = vmx_get_segment,
8295 +- .set_segment = vmx_set_segment,
8296 +- .get_cpl = vmx_get_cpl,
8297 +- .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8298 +- .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8299 +- .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8300 +- .set_cr0 = vmx_set_cr0,
8301 +- .set_cr3 = vmx_set_cr3,
8302 +- .set_cr4 = vmx_set_cr4,
8303 +- .set_efer = vmx_set_efer,
8304 +- .get_idt = vmx_get_idt,
8305 +- .set_idt = vmx_set_idt,
8306 +- .get_gdt = vmx_get_gdt,
8307 +- .set_gdt = vmx_set_gdt,
8308 +- .get_dr6 = vmx_get_dr6,
8309 +- .set_dr6 = vmx_set_dr6,
8310 +- .set_dr7 = vmx_set_dr7,
8311 +- .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
8312 +- .cache_reg = vmx_cache_reg,
8313 +- .get_rflags = vmx_get_rflags,
8314 +- .set_rflags = vmx_set_rflags,
8315 +-
8316 +- .tlb_flush = vmx_flush_tlb,
8317 +- .tlb_flush_gva = vmx_flush_tlb_gva,
8318 +-
8319 +- .run = vmx_vcpu_run,
8320 +- .handle_exit = vmx_handle_exit,
8321 +- .skip_emulated_instruction = skip_emulated_instruction,
8322 +- .set_interrupt_shadow = vmx_set_interrupt_shadow,
8323 +- .get_interrupt_shadow = vmx_get_interrupt_shadow,
8324 +- .patch_hypercall = vmx_patch_hypercall,
8325 +- .set_irq = vmx_inject_irq,
8326 +- .set_nmi = vmx_inject_nmi,
8327 +- .queue_exception = vmx_queue_exception,
8328 +- .cancel_injection = vmx_cancel_injection,
8329 +- .interrupt_allowed = vmx_interrupt_allowed,
8330 +- .nmi_allowed = vmx_nmi_allowed,
8331 +- .get_nmi_mask = vmx_get_nmi_mask,
8332 +- .set_nmi_mask = vmx_set_nmi_mask,
8333 +- .enable_nmi_window = enable_nmi_window,
8334 +- .enable_irq_window = enable_irq_window,
8335 +- .update_cr8_intercept = update_cr8_intercept,
8336 +- .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
8337 +- .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
8338 +- .get_enable_apicv = vmx_get_enable_apicv,
8339 +- .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
8340 +- .load_eoi_exitmap = vmx_load_eoi_exitmap,
8341 +- .apicv_post_state_restore = vmx_apicv_post_state_restore,
8342 +- .hwapic_irr_update = vmx_hwapic_irr_update,
8343 +- .hwapic_isr_update = vmx_hwapic_isr_update,
8344 +- .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
8345 +- .sync_pir_to_irr = vmx_sync_pir_to_irr,
8346 +- .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8347 +- .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
8348 +-
8349 +- .set_tss_addr = vmx_set_tss_addr,
8350 +- .set_identity_map_addr = vmx_set_identity_map_addr,
8351 +- .get_tdp_level = get_ept_level,
8352 +- .get_mt_mask = vmx_get_mt_mask,
8353 +-
8354 +- .get_exit_info = vmx_get_exit_info,
8355 +-
8356 +- .get_lpage_level = vmx_get_lpage_level,
8357 +-
8358 +- .cpuid_update = vmx_cpuid_update,
8359 +-
8360 +- .rdtscp_supported = vmx_rdtscp_supported,
8361 +- .invpcid_supported = vmx_invpcid_supported,
8362 +-
8363 +- .set_supported_cpuid = vmx_set_supported_cpuid,
8364 +-
8365 +- .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8366 +-
8367 +- .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
8368 +- .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
8369 +-
8370 +- .set_tdp_cr3 = vmx_set_cr3,
8371 +-
8372 +- .check_intercept = vmx_check_intercept,
8373 +- .handle_exit_irqoff = vmx_handle_exit_irqoff,
8374 +- .mpx_supported = vmx_mpx_supported,
8375 +- .xsaves_supported = vmx_xsaves_supported,
8376 +- .umip_emulated = vmx_umip_emulated,
8377 +- .pt_supported = vmx_pt_supported,
8378 +-
8379 +- .request_immediate_exit = vmx_request_immediate_exit,
8380 +-
8381 +- .sched_in = vmx_sched_in,
8382 +-
8383 +- .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
8384 +- .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
8385 +- .flush_log_dirty = vmx_flush_log_dirty,
8386 +- .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
8387 +- .write_log_dirty = vmx_write_pml_buffer,
8388 +-
8389 +- .pre_block = vmx_pre_block,
8390 +- .post_block = vmx_post_block,
8391 +-
8392 +- .pmu_ops = &intel_pmu_ops,
8393 +-
8394 +- .update_pi_irte = vmx_update_pi_irte,
8395 +-
8396 +-#ifdef CONFIG_X86_64
8397 +- .set_hv_timer = vmx_set_hv_timer,
8398 +- .cancel_hv_timer = vmx_cancel_hv_timer,
8399 +-#endif
8400 +-
8401 +- .setup_mce = vmx_setup_mce,
8402 +-
8403 +- .smi_allowed = vmx_smi_allowed,
8404 +- .pre_enter_smm = vmx_pre_enter_smm,
8405 +- .pre_leave_smm = vmx_pre_leave_smm,
8406 +- .enable_smi_window = enable_smi_window,
8407 +-
8408 +- .check_nested_events = NULL,
8409 +- .get_nested_state = NULL,
8410 +- .set_nested_state = NULL,
8411 +- .get_vmcs12_pages = NULL,
8412 +- .nested_enable_evmcs = NULL,
8413 +- .nested_get_evmcs_version = NULL,
8414 +- .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
8415 +- .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
8416 +-};
8417 +-
8418 +-static void vmx_cleanup_l1d_flush(void)
8419 +-{
8420 +- if (vmx_l1d_flush_pages) {
8421 +- free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
8422 +- vmx_l1d_flush_pages = NULL;
8423 +- }
8424 +- /* Restore state so sysfs ignores VMX */
8425 +- l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
8426 +-}
8427 +-
8428 +-static void vmx_exit(void)
8429 +-{
8430 +-#ifdef CONFIG_KEXEC_CORE
8431 +- RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8432 +- synchronize_rcu();
8433 +-#endif
8434 +-
8435 +- kvm_exit();
8436 +-
8437 +-#if IS_ENABLED(CONFIG_HYPERV)
8438 +- if (static_branch_unlikely(&enable_evmcs)) {
8439 +- int cpu;
8440 +- struct hv_vp_assist_page *vp_ap;
8441 +- /*
8442 +- * Reset everything to support using non-enlightened VMCS
8443 +- * access later (e.g. when we reload the module with
8444 +- * enlightened_vmcs=0)
8445 +- */
8446 +- for_each_online_cpu(cpu) {
8447 +- vp_ap = hv_get_vp_assist_page(cpu);
8448 +-
8449 +- if (!vp_ap)
8450 +- continue;
8451 +-
8452 +- vp_ap->nested_control.features.directhypercall = 0;
8453 +- vp_ap->current_nested_vmcs = 0;
8454 +- vp_ap->enlighten_vmentry = 0;
8455 +- }
8456 +-
8457 +- static_branch_disable(&enable_evmcs);
8458 +- }
8459 +-#endif
8460 +- vmx_cleanup_l1d_flush();
8461 +-}
8462 +-module_exit(vmx_exit);
8463 +-
8464 +-static int __init vmx_init(void)
8465 +-{
8466 +- int r;
8467 +-
8468 +-#if IS_ENABLED(CONFIG_HYPERV)
8469 +- /*
8470 +- * Enlightened VMCS usage should be recommended and the host needs
8471 +- * to support eVMCS v1 or above. We can also disable eVMCS support
8472 +- * with module parameter.
8473 +- */
8474 +- if (enlightened_vmcs &&
8475 +- ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
8476 +- (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
8477 +- KVM_EVMCS_VERSION) {
8478 +- int cpu;
8479 +-
8480 +- /* Check that we have assist pages on all online CPUs */
8481 +- for_each_online_cpu(cpu) {
8482 +- if (!hv_get_vp_assist_page(cpu)) {
8483 +- enlightened_vmcs = false;
8484 +- break;
8485 +- }
8486 +- }
8487 +-
8488 +- if (enlightened_vmcs) {
8489 +- pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
8490 +- static_branch_enable(&enable_evmcs);
8491 +- }
8492 +-
8493 +- if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
8494 +- vmx_x86_ops.enable_direct_tlbflush
8495 +- = hv_enable_direct_tlbflush;
8496 +-
8497 +- } else {
8498 +- enlightened_vmcs = false;
8499 +- }
8500 +-#endif
8501 +-
8502 +- r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8503 +- __alignof__(struct vcpu_vmx), THIS_MODULE);
8504 +- if (r)
8505 +- return r;
8506 +-
8507 +- /*
8508 +- * Must be called after kvm_init() so enable_ept is properly set
8509 +- * up. Hand the parameter mitigation value in which was stored in
8510 +- * the pre module init parser. If no parameter was given, it will
8511 +- * contain 'auto' which will be turned into the default 'cond'
8512 +- * mitigation mode.
8513 +- */
8514 +- r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8515 +- if (r) {
8516 +- vmx_exit();
8517 +- return r;
8518 +- }
8519 +-
8520 +-#ifdef CONFIG_KEXEC_CORE
8521 +- rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8522 +- crash_vmclear_local_loaded_vmcss);
8523 +-#endif
8524 +- vmx_check_vmcs12_offsets();
8525 +-
8526 +- return 0;
8527 +-}
8528 +-module_init(vmx_init);
8529 +diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c
8530 +index 4bc352fc08f1..105872617be0 100644
8531 +--- a/arch/x86/platform/efi/efi.c
8532 ++++ b/arch/x86/platform/efi/efi.c
8533 +@@ -465,7 +465,6 @@ void __init efi_init(void)
8534 + efi_char16_t *c16;
8535 + char vendor[100] = "unknown";
8536 + int i = 0;
8537 +- void *tmp;
8538 +
8539 + #ifdef CONFIG_X86_32
8540 + if (boot_params.efi_info.efi_systab_hi ||
8541 +@@ -490,14 +489,16 @@ void __init efi_init(void)
8542 + /*
8543 + * Show what we know for posterity
8544 + */
8545 +- c16 = tmp = early_memremap(efi.systab->fw_vendor, 2);
8546 ++ c16 = early_memremap_ro(efi.systab->fw_vendor,
8547 ++ sizeof(vendor) * sizeof(efi_char16_t));
8548 + if (c16) {
8549 +- for (i = 0; i < sizeof(vendor) - 1 && *c16; ++i)
8550 +- vendor[i] = *c16++;
8551 ++ for (i = 0; i < sizeof(vendor) - 1 && c16[i]; ++i)
8552 ++ vendor[i] = c16[i];
8553 + vendor[i] = '\0';
8554 +- } else
8555 ++ early_memunmap(c16, sizeof(vendor) * sizeof(efi_char16_t));
8556 ++ } else {
8557 + pr_err("Could not map the firmware vendor!\n");
8558 +- early_memunmap(tmp, 2);
8559 ++ }
8560 +
8561 + pr_info("EFI v%u.%.02u by %s\n",
8562 + efi.systab->hdr.revision >> 16,
8563 +diff --git a/drivers/acpi/acpica/dsfield.c b/drivers/acpi/acpica/dsfield.c
8564 +index 20de148594fd..d56cbcda37c1 100644
8565 +--- a/drivers/acpi/acpica/dsfield.c
8566 ++++ b/drivers/acpi/acpica/dsfield.c
8567 +@@ -272,7 +272,7 @@ cleanup:
8568 + * FUNCTION: acpi_ds_get_field_names
8569 + *
8570 + * PARAMETERS: info - create_field info structure
8571 +- * ` walk_state - Current method state
8572 ++ * walk_state - Current method state
8573 + * arg - First parser arg for the field name list
8574 + *
8575 + * RETURN: Status
8576 +diff --git a/drivers/acpi/acpica/dswload.c b/drivers/acpi/acpica/dswload.c
8577 +index 097188a6b1c1..35f1d7657927 100644
8578 +--- a/drivers/acpi/acpica/dswload.c
8579 ++++ b/drivers/acpi/acpica/dswload.c
8580 +@@ -440,6 +440,27 @@ acpi_status acpi_ds_load1_end_op(struct acpi_walk_state *walk_state)
8581 + ACPI_DEBUG_PRINT((ACPI_DB_DISPATCH, "Op=%p State=%p\n", op,
8582 + walk_state));
8583 +
8584 ++ /*
8585 ++ * Disassembler: handle create field operators here.
8586 ++ *
8587 ++ * create_buffer_field is a deferred op that is typically processed in load
8588 ++ * pass 2. However, disassembly of control method contents walk the parse
8589 ++ * tree with ACPI_PARSE_LOAD_PASS1 and AML_CREATE operators are processed
8590 ++ * in a later walk. This is a problem when there is a control method that
8591 ++ * has the same name as the AML_CREATE object. In this case, any use of the
8592 ++ * name segment will be detected as a method call rather than a reference
8593 ++ * to a buffer field.
8594 ++ *
8595 ++ * This earlier creation during disassembly solves this issue by inserting
8596 ++ * the named object in the ACPI namespace so that references to this name
8597 ++ * would be a name string rather than a method call.
8598 ++ */
8599 ++ if ((walk_state->parse_flags & ACPI_PARSE_DISASSEMBLE) &&
8600 ++ (walk_state->op_info->flags & AML_CREATE)) {
8601 ++ status = acpi_ds_create_buffer_field(op, walk_state);
8602 ++ return_ACPI_STATUS(status);
8603 ++ }
8604 ++
8605 + /* We are only interested in opcodes that have an associated name */
8606 +
8607 + if (!(walk_state->op_info->flags & (AML_NAMED | AML_FIELD))) {
8608 +diff --git a/drivers/base/dd.c b/drivers/base/dd.c
8609 +index 1dffb018a7fe..04a923186081 100644
8610 +--- a/drivers/base/dd.c
8611 ++++ b/drivers/base/dd.c
8612 +@@ -283,7 +283,10 @@ static int really_probe(struct device *dev, struct device_driver *drv)
8613 + atomic_inc(&probe_count);
8614 + pr_debug("bus: '%s': %s: probing driver %s with device %s\n",
8615 + drv->bus->name, __func__, drv->name, dev_name(dev));
8616 +- WARN_ON(!list_empty(&dev->devres_head));
8617 ++ if (!list_empty(&dev->devres_head)) {
8618 ++ dev_crit(dev, "Resources present before probing\n");
8619 ++ return -EBUSY;
8620 ++ }
8621 +
8622 + dev->driver = drv;
8623 +
8624 +diff --git a/drivers/block/brd.c b/drivers/block/brd.c
8625 +index 1914c63ca8b1..58c1138ad5e1 100644
8626 +--- a/drivers/block/brd.c
8627 ++++ b/drivers/block/brd.c
8628 +@@ -581,6 +581,25 @@ static struct kobject *brd_probe(dev_t dev, int *part, void *data)
8629 + return kobj;
8630 + }
8631 +
8632 ++static inline void brd_check_and_reset_par(void)
8633 ++{
8634 ++ if (unlikely(!max_part))
8635 ++ max_part = 1;
8636 ++
8637 ++ /*
8638 ++ * make sure 'max_part' can be divided exactly by (1U << MINORBITS),
8639 ++ * otherwise, it is possiable to get same dev_t when adding partitions.
8640 ++ */
8641 ++ if ((1U << MINORBITS) % max_part != 0)
8642 ++ max_part = 1UL << fls(max_part);
8643 ++
8644 ++ if (max_part > DISK_MAX_PARTS) {
8645 ++ pr_info("brd: max_part can't be larger than %d, reset max_part = %d.\n",
8646 ++ DISK_MAX_PARTS, DISK_MAX_PARTS);
8647 ++ max_part = DISK_MAX_PARTS;
8648 ++ }
8649 ++}
8650 ++
8651 + static int __init brd_init(void)
8652 + {
8653 + struct brd_device *brd, *next;
8654 +@@ -604,8 +623,7 @@ static int __init brd_init(void)
8655 + if (register_blkdev(RAMDISK_MAJOR, "ramdisk"))
8656 + return -EIO;
8657 +
8658 +- if (unlikely(!max_part))
8659 +- max_part = 1;
8660 ++ brd_check_and_reset_par();
8661 +
8662 + for (i = 0; i < rd_nr; i++) {
8663 + brd = brd_alloc(i);
8664 +diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c
8665 +index a12a163c6e6d..58ce577ba6d7 100644
8666 +--- a/drivers/block/floppy.c
8667 ++++ b/drivers/block/floppy.c
8668 +@@ -848,14 +848,17 @@ static void reset_fdc_info(int mode)
8669 + /* selects the fdc and drive, and enables the fdc's input/dma. */
8670 + static void set_fdc(int drive)
8671 + {
8672 ++ unsigned int new_fdc = fdc;
8673 ++
8674 + if (drive >= 0 && drive < N_DRIVE) {
8675 +- fdc = FDC(drive);
8676 ++ new_fdc = FDC(drive);
8677 + current_drive = drive;
8678 + }
8679 +- if (fdc != 1 && fdc != 0) {
8680 ++ if (new_fdc >= N_FDC) {
8681 + pr_info("bad fdc value\n");
8682 + return;
8683 + }
8684 ++ fdc = new_fdc;
8685 + set_dor(fdc, ~0, 8);
8686 + #if N_FDC > 1
8687 + set_dor(1 - fdc, ~8, 0);
8688 +diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
8689 +index 350a01f74870..8b549ece9f13 100644
8690 +--- a/drivers/clk/qcom/clk-rcg2.c
8691 ++++ b/drivers/clk/qcom/clk-rcg2.c
8692 +@@ -194,6 +194,9 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw,
8693 +
8694 + clk_flags = clk_hw_get_flags(hw);
8695 + p = clk_hw_get_parent_by_index(hw, index);
8696 ++ if (!p)
8697 ++ return -EINVAL;
8698 ++
8699 + if (clk_flags & CLK_SET_RATE_PARENT) {
8700 + if (f->pre_div) {
8701 + if (!rate)
8702 +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
8703 +index 3e90ddcbb24a..d799927d3a5d 100644
8704 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
8705 ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
8706 +@@ -319,17 +319,9 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *
8707 + path_size += le16_to_cpu(path->usSize);
8708 +
8709 + if (device_support & le16_to_cpu(path->usDeviceTag)) {
8710 +- uint8_t con_obj_id, con_obj_num, con_obj_type;
8711 +-
8712 +- con_obj_id =
8713 ++ uint8_t con_obj_id =
8714 + (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
8715 + >> OBJECT_ID_SHIFT;
8716 +- con_obj_num =
8717 +- (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
8718 +- >> ENUM_ID_SHIFT;
8719 +- con_obj_type =
8720 +- (le16_to_cpu(path->usConnObjectId) &
8721 +- OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
8722 +
8723 + /* Skip TV/CV support */
8724 + if ((le16_to_cpu(path->usDeviceTag) ==
8725 +@@ -354,14 +346,7 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *
8726 + router.ddc_valid = false;
8727 + router.cd_valid = false;
8728 + for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
8729 +- uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
8730 +-
8731 +- grph_obj_id =
8732 +- (le16_to_cpu(path->usGraphicObjIds[j]) &
8733 +- OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
8734 +- grph_obj_num =
8735 +- (le16_to_cpu(path->usGraphicObjIds[j]) &
8736 +- ENUM_ID_MASK) >> ENUM_ID_SHIFT;
8737 ++ uint8_t grph_obj_type=
8738 + grph_obj_type =
8739 + (le16_to_cpu(path->usGraphicObjIds[j]) &
8740 + OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
8741 +diff --git a/drivers/gpu/drm/gma500/framebuffer.c b/drivers/gpu/drm/gma500/framebuffer.c
8742 +index 2eaf1b31c7bd..ef60bb197195 100644
8743 +--- a/drivers/gpu/drm/gma500/framebuffer.c
8744 ++++ b/drivers/gpu/drm/gma500/framebuffer.c
8745 +@@ -533,6 +533,7 @@ static int psbfb_probe(struct drm_fb_helper *helper,
8746 + container_of(helper, struct psb_fbdev, psb_fb_helper);
8747 + struct drm_device *dev = psb_fbdev->psb_fb_helper.dev;
8748 + struct drm_psb_private *dev_priv = dev->dev_private;
8749 ++ unsigned int fb_size;
8750 + int bytespp;
8751 +
8752 + bytespp = sizes->surface_bpp / 8;
8753 +@@ -542,8 +543,11 @@ static int psbfb_probe(struct drm_fb_helper *helper,
8754 + /* If the mode will not fit in 32bit then switch to 16bit to get
8755 + a console on full resolution. The X mode setting server will
8756 + allocate its own 32bit GEM framebuffer */
8757 +- if (ALIGN(sizes->fb_width * bytespp, 64) * sizes->fb_height >
8758 +- dev_priv->vram_stolen_size) {
8759 ++ fb_size = ALIGN(sizes->surface_width * bytespp, 64) *
8760 ++ sizes->surface_height;
8761 ++ fb_size = ALIGN(fb_size, PAGE_SIZE);
8762 ++
8763 ++ if (fb_size > dev_priv->vram_stolen_size) {
8764 + sizes->surface_bpp = 16;
8765 + sizes->surface_depth = 16;
8766 + }
8767 +diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c
8768 +index 574c36b492ee..fccec23731e2 100644
8769 +--- a/drivers/gpu/drm/nouveau/nouveau_fence.c
8770 ++++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
8771 +@@ -157,7 +157,7 @@ nouveau_fence_wait_uevent_handler(struct nvif_notify *notify)
8772 +
8773 + fence = list_entry(fctx->pending.next, typeof(*fence), head);
8774 + chan = rcu_dereference_protected(fence->channel, lockdep_is_held(&fctx->lock));
8775 +- if (nouveau_fence_update(fence->channel, fctx))
8776 ++ if (nouveau_fence_update(chan, fctx))
8777 + ret = NVIF_NOTIFY_DROP;
8778 + }
8779 + spin_unlock_irqrestore(&fctx->lock, flags);
8780 +diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c
8781 +index 01803c0679b6..d012df9fb9df 100644
8782 +--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c
8783 ++++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c
8784 +@@ -72,6 +72,8 @@ nv50_disp_chan_mthd(struct nv50_disp_chan *chan, int debug)
8785 +
8786 + if (debug > subdev->debug)
8787 + return;
8788 ++ if (!mthd)
8789 ++ return;
8790 +
8791 + for (i = 0; (list = mthd->data[i].mthd) != NULL; i++) {
8792 + u32 base = chan->head * mthd->addr;
8793 +diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
8794 +index 446d99062306..4572bfba017c 100644
8795 +--- a/drivers/gpu/drm/radeon/radeon_display.c
8796 ++++ b/drivers/gpu/drm/radeon/radeon_display.c
8797 +@@ -110,6 +110,8 @@ static void dce5_crtc_load_lut(struct drm_crtc *crtc)
8798 +
8799 + DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
8800 +
8801 ++ msleep(10);
8802 ++
8803 + WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
8804 + (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
8805 + NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
8806 +diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf_res.c b/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf_res.c
8807 +index 1f013d45c9e9..0c7c3005594c 100644
8808 +--- a/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf_res.c
8809 ++++ b/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf_res.c
8810 +@@ -210,8 +210,10 @@ int vmw_cmdbuf_res_add(struct vmw_cmdbuf_res_manager *man,
8811 +
8812 + cres->hash.key = user_key | (res_type << 24);
8813 + ret = drm_ht_insert_item(&man->resources, &cres->hash);
8814 +- if (unlikely(ret != 0))
8815 ++ if (unlikely(ret != 0)) {
8816 ++ kfree(cres);
8817 + goto out_invalid_key;
8818 ++ }
8819 +
8820 + cres->state = VMW_CMDBUF_RES_ADD;
8821 + cres->res = vmw_resource_reference(res);
8822 +diff --git a/drivers/hwmon/pmbus/ltc2978.c b/drivers/hwmon/pmbus/ltc2978.c
8823 +index 58b789c28b48..94eea2ac6251 100644
8824 +--- a/drivers/hwmon/pmbus/ltc2978.c
8825 ++++ b/drivers/hwmon/pmbus/ltc2978.c
8826 +@@ -89,8 +89,8 @@ enum chips { ltc2974, ltc2975, ltc2977, ltc2978, ltc2980, ltc3880, ltc3882,
8827 +
8828 + #define LTC_POLL_TIMEOUT 100 /* in milli-seconds */
8829 +
8830 +-#define LTC_NOT_BUSY BIT(5)
8831 +-#define LTC_NOT_PENDING BIT(4)
8832 ++#define LTC_NOT_BUSY BIT(6)
8833 ++#define LTC_NOT_PENDING BIT(5)
8834 +
8835 + /*
8836 + * LTC2978 clears peak data whenever the CLEAR_FAULTS command is executed, which
8837 +diff --git a/drivers/ide/cmd64x.c b/drivers/ide/cmd64x.c
8838 +index b127ed60c733..9dde8390da09 100644
8839 +--- a/drivers/ide/cmd64x.c
8840 ++++ b/drivers/ide/cmd64x.c
8841 +@@ -65,6 +65,9 @@ static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)
8842 + struct ide_timing t;
8843 + u8 arttim = 0;
8844 +
8845 ++ if (drive->dn >= ARRAY_SIZE(drwtim_regs))
8846 ++ return;
8847 ++
8848 + ide_timing_compute(drive, mode, &t, T, 0);
8849 +
8850 + /*
8851 +diff --git a/drivers/ide/serverworks.c b/drivers/ide/serverworks.c
8852 +index a97affca18ab..0f57d45484d1 100644
8853 +--- a/drivers/ide/serverworks.c
8854 ++++ b/drivers/ide/serverworks.c
8855 +@@ -114,6 +114,9 @@ static void svwks_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
8856 + struct pci_dev *dev = to_pci_dev(hwif->dev);
8857 + const u8 pio = drive->pio_mode - XFER_PIO_0;
8858 +
8859 ++ if (drive->dn >= ARRAY_SIZE(drive_pci))
8860 ++ return;
8861 ++
8862 + pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
8863 +
8864 + if (svwks_csb_check(dev)) {
8865 +@@ -140,6 +143,9 @@ static void svwks_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
8866 +
8867 + u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0;
8868 +
8869 ++ if (drive->dn >= ARRAY_SIZE(drive_pci2))
8870 ++ return;
8871 ++
8872 + pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
8873 + pci_read_config_byte(dev, 0x54, &ultra_enable);
8874 +
8875 +diff --git a/drivers/infiniband/ulp/isert/ib_isert.c b/drivers/infiniband/ulp/isert/ib_isert.c
8876 +index 32ef17e1aef8..d8adb586362c 100644
8877 +--- a/drivers/infiniband/ulp/isert/ib_isert.c
8878 ++++ b/drivers/infiniband/ulp/isert/ib_isert.c
8879 +@@ -3295,6 +3295,17 @@ isert_wait4flush(struct isert_conn *isert_conn)
8880 + wait_for_completion(&isert_conn->wait_comp_err);
8881 + }
8882 +
8883 ++static void
8884 ++isert_wait4cmds(struct iscsi_conn *conn)
8885 ++{
8886 ++ isert_info("iscsi_conn %p\n", conn);
8887 ++
8888 ++ if (conn->sess) {
8889 ++ target_sess_cmd_list_set_waiting(conn->sess->se_sess);
8890 ++ target_wait_for_sess_cmds(conn->sess->se_sess);
8891 ++ }
8892 ++}
8893 ++
8894 + /**
8895 + * isert_put_unsol_pending_cmds() - Drop commands waiting for
8896 + * unsolicitate dataout
8897 +@@ -3350,6 +3361,7 @@ static void isert_wait_conn(struct iscsi_conn *conn)
8898 +
8899 + isert_wait4flush(isert_conn);
8900 + isert_put_unsol_pending_cmds(conn);
8901 ++ isert_wait4cmds(conn);
8902 + isert_wait4logout(isert_conn);
8903 +
8904 + queue_work(isert_release_wq, &isert_conn->release_work);
8905 +diff --git a/drivers/input/touchscreen/edt-ft5x06.c b/drivers/input/touchscreen/edt-ft5x06.c
8906 +index 0b0f8c17f3f7..a9d97d577a7e 100644
8907 +--- a/drivers/input/touchscreen/edt-ft5x06.c
8908 ++++ b/drivers/input/touchscreen/edt-ft5x06.c
8909 +@@ -880,6 +880,7 @@ static int edt_ft5x06_ts_probe(struct i2c_client *client,
8910 + {
8911 + const struct edt_i2c_chip_data *chip_data;
8912 + struct edt_ft5x06_ts_data *tsdata;
8913 ++ u8 buf[2] = { 0xfc, 0x00 };
8914 + struct input_dev *input;
8915 + unsigned long irq_flags;
8916 + int error;
8917 +@@ -949,6 +950,12 @@ static int edt_ft5x06_ts_probe(struct i2c_client *client,
8918 + return error;
8919 + }
8920 +
8921 ++ /*
8922 ++ * Dummy read access. EP0700MLP1 returns bogus data on the first
8923 ++ * register read access and ignores writes.
8924 ++ */
8925 ++ edt_ft5x06_ts_readwrite(tsdata->client, 2, buf, 2, buf);
8926 ++
8927 + edt_ft5x06_ts_set_regs(tsdata);
8928 + edt_ft5x06_ts_get_defaults(&client->dev, tsdata);
8929 + edt_ft5x06_ts_get_parameters(tsdata);
8930 +diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
8931 +index eb9937225d64..6c10f307a1c9 100644
8932 +--- a/drivers/iommu/arm-smmu-v3.c
8933 ++++ b/drivers/iommu/arm-smmu-v3.c
8934 +@@ -1090,7 +1090,8 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
8935 + }
8936 +
8937 + arm_smmu_sync_ste_for_sid(smmu, sid);
8938 +- dst[0] = cpu_to_le64(val);
8939 ++ /* See comment in arm_smmu_write_ctx_desc() */
8940 ++ WRITE_ONCE(dst[0], cpu_to_le64(val));
8941 + arm_smmu_sync_ste_for_sid(smmu, sid);
8942 +
8943 + /* It's likely that we'll want to use the new STE soon */
8944 +diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
8945 +index cf11d43ce241..d4ae43f71e72 100644
8946 +--- a/drivers/irqchip/irq-gic-v3-its.c
8947 ++++ b/drivers/irqchip/irq-gic-v3-its.c
8948 +@@ -352,7 +352,7 @@ static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd,
8949 + struct its_cmd_desc *desc)
8950 + {
8951 + its_encode_cmd(cmd, GITS_CMD_INVALL);
8952 +- its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
8953 ++ its_encode_collection(cmd, desc->its_invall_cmd.col->col_id);
8954 +
8955 + its_fixup_cmd(cmd);
8956 +
8957 +diff --git a/drivers/md/bcache/bset.h b/drivers/md/bcache/bset.h
8958 +index b935839ab79c..f483041eed98 100644
8959 +--- a/drivers/md/bcache/bset.h
8960 ++++ b/drivers/md/bcache/bset.h
8961 +@@ -380,7 +380,8 @@ void bch_btree_keys_stats(struct btree_keys *, struct bset_stats *);
8962 +
8963 + /* Bkey utility code */
8964 +
8965 +-#define bset_bkey_last(i) bkey_idx((struct bkey *) (i)->d, (i)->keys)
8966 ++#define bset_bkey_last(i) bkey_idx((struct bkey *) (i)->d, \
8967 ++ (unsigned int)(i)->keys)
8968 +
8969 + static inline struct bkey *bset_bkey_idx(struct bset *i, unsigned idx)
8970 + {
8971 +diff --git a/drivers/media/i2c/mt9v032.c b/drivers/media/i2c/mt9v032.c
8972 +index a68ce94ee097..cacdab30fece 100644
8973 +--- a/drivers/media/i2c/mt9v032.c
8974 ++++ b/drivers/media/i2c/mt9v032.c
8975 +@@ -454,10 +454,12 @@ static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev,
8976 + struct v4l2_subdev_pad_config *cfg,
8977 + struct v4l2_subdev_mbus_code_enum *code)
8978 + {
8979 ++ struct mt9v032 *mt9v032 = to_mt9v032(subdev);
8980 ++
8981 + if (code->index > 0)
8982 + return -EINVAL;
8983 +
8984 +- code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
8985 ++ code->code = mt9v032->format.code;
8986 + return 0;
8987 + }
8988 +
8989 +@@ -465,7 +467,11 @@ static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev,
8990 + struct v4l2_subdev_pad_config *cfg,
8991 + struct v4l2_subdev_frame_size_enum *fse)
8992 + {
8993 +- if (fse->index >= 3 || fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
8994 ++ struct mt9v032 *mt9v032 = to_mt9v032(subdev);
8995 ++
8996 ++ if (fse->index >= 3)
8997 ++ return -EINVAL;
8998 ++ if (mt9v032->format.code != fse->code)
8999 + return -EINVAL;
9000 +
9001 + fse->min_width = MT9V032_WINDOW_WIDTH_DEF / (1 << fse->index);
9002 +diff --git a/drivers/media/platform/sti/bdisp/bdisp-hw.c b/drivers/media/platform/sti/bdisp/bdisp-hw.c
9003 +index 052c932ac942..0792db43ce9d 100644
9004 +--- a/drivers/media/platform/sti/bdisp/bdisp-hw.c
9005 ++++ b/drivers/media/platform/sti/bdisp/bdisp-hw.c
9006 +@@ -14,8 +14,8 @@
9007 + #define MAX_SRC_WIDTH 2048
9008 +
9009 + /* Reset & boot poll config */
9010 +-#define POLL_RST_MAX 50
9011 +-#define POLL_RST_DELAY_MS 20
9012 ++#define POLL_RST_MAX 500
9013 ++#define POLL_RST_DELAY_MS 2
9014 +
9015 + enum bdisp_target_plan {
9016 + BDISP_RGB,
9017 +@@ -77,7 +77,7 @@ int bdisp_hw_reset(struct bdisp_dev *bdisp)
9018 + for (i = 0; i < POLL_RST_MAX; i++) {
9019 + if (readl(bdisp->regs + BLT_STA1) & BLT_STA1_IDLE)
9020 + break;
9021 +- msleep(POLL_RST_DELAY_MS);
9022 ++ udelay(POLL_RST_DELAY_MS * 1000);
9023 + }
9024 + if (i == POLL_RST_MAX)
9025 + dev_err(bdisp->dev, "Reset timeout\n");
9026 +diff --git a/drivers/net/ethernet/cisco/enic/enic_main.c b/drivers/net/ethernet/cisco/enic/enic_main.c
9027 +index 3c20d0dc9256..9b9793333816 100644
9028 +--- a/drivers/net/ethernet/cisco/enic/enic_main.c
9029 ++++ b/drivers/net/ethernet/cisco/enic/enic_main.c
9030 +@@ -1807,10 +1807,10 @@ static int enic_stop(struct net_device *netdev)
9031 + }
9032 +
9033 + netif_carrier_off(netdev);
9034 +- netif_tx_disable(netdev);
9035 + if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
9036 + for (i = 0; i < enic->wq_count; i++)
9037 + napi_disable(&enic->napi[enic_cq_wq(enic, i)]);
9038 ++ netif_tx_disable(netdev);
9039 +
9040 + if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
9041 + enic_dev_del_station_addr(enic);
9042 +diff --git a/drivers/net/ethernet/freescale/gianfar.c b/drivers/net/ethernet/freescale/gianfar.c
9043 +index 2d61369f586f..37cc1f838dd8 100644
9044 +--- a/drivers/net/ethernet/freescale/gianfar.c
9045 ++++ b/drivers/net/ethernet/freescale/gianfar.c
9046 +@@ -2679,13 +2679,17 @@ static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
9047 + skb_dirtytx = tx_queue->skb_dirtytx;
9048 +
9049 + while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
9050 ++ bool do_tstamp;
9051 ++
9052 ++ do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
9053 ++ priv->hwts_tx_en;
9054 +
9055 + frags = skb_shinfo(skb)->nr_frags;
9056 +
9057 + /* When time stamping, one additional TxBD must be freed.
9058 + * Also, we need to dma_unmap_single() the TxPAL.
9059 + */
9060 +- if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
9061 ++ if (unlikely(do_tstamp))
9062 + nr_txbds = frags + 2;
9063 + else
9064 + nr_txbds = frags + 1;
9065 +@@ -2699,7 +2703,7 @@ static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
9066 + (lstatus & BD_LENGTH_MASK))
9067 + break;
9068 +
9069 +- if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
9070 ++ if (unlikely(do_tstamp)) {
9071 + next = next_txbd(bdp, base, tx_ring_size);
9072 + buflen = be16_to_cpu(next->length) +
9073 + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
9074 +@@ -2709,7 +2713,7 @@ static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
9075 + dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
9076 + buflen, DMA_TO_DEVICE);
9077 +
9078 +- if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
9079 ++ if (unlikely(do_tstamp)) {
9080 + struct skb_shared_hwtstamps shhwtstamps;
9081 + u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
9082 + ~0x7UL);
9083 +diff --git a/drivers/net/wan/ixp4xx_hss.c b/drivers/net/wan/ixp4xx_hss.c
9084 +index e7bbdb7af53a..97968e6a6a4e 100644
9085 +--- a/drivers/net/wan/ixp4xx_hss.c
9086 ++++ b/drivers/net/wan/ixp4xx_hss.c
9087 +@@ -261,7 +261,7 @@ struct port {
9088 + struct hss_plat_info *plat;
9089 + buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
9090 + struct desc *desc_tab; /* coherent */
9091 +- u32 desc_tab_phys;
9092 ++ dma_addr_t desc_tab_phys;
9093 + unsigned int id;
9094 + unsigned int clock_type, clock_rate, loopback;
9095 + unsigned int initialized, carrier;
9096 +@@ -861,7 +861,7 @@ static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
9097 + dev->stats.tx_dropped++;
9098 + return NETDEV_TX_OK;
9099 + }
9100 +- memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
9101 ++ memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4);
9102 + dev_kfree_skb(skb);
9103 + #endif
9104 +
9105 +diff --git a/drivers/net/wireless/b43legacy/main.c b/drivers/net/wireless/b43legacy/main.c
9106 +index afc1fb3e38df..bd35a702382f 100644
9107 +--- a/drivers/net/wireless/b43legacy/main.c
9108 ++++ b/drivers/net/wireless/b43legacy/main.c
9109 +@@ -1304,8 +1304,9 @@ static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
9110 + }
9111 +
9112 + /* Interrupt handler bottom-half */
9113 +-static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
9114 ++static void b43legacy_interrupt_tasklet(unsigned long data)
9115 + {
9116 ++ struct b43legacy_wldev *dev = (struct b43legacy_wldev *)data;
9117 + u32 reason;
9118 + u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
9119 + u32 merged_dma_reason = 0;
9120 +@@ -3775,7 +3776,7 @@ static int b43legacy_one_core_attach(struct ssb_device *dev,
9121 + b43legacy_set_status(wldev, B43legacy_STAT_UNINIT);
9122 + wldev->bad_frames_preempt = modparam_bad_frames_preempt;
9123 + tasklet_init(&wldev->isr_tasklet,
9124 +- (void (*)(unsigned long))b43legacy_interrupt_tasklet,
9125 ++ b43legacy_interrupt_tasklet,
9126 + (unsigned long)wldev);
9127 + if (modparam_pio)
9128 + wldev->__using_pio = true;
9129 +diff --git a/drivers/net/wireless/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/brcm80211/brcmfmac/sdio.c
9130 +index 9954e641c943..8bb028f740fd 100644
9131 +--- a/drivers/net/wireless/brcm80211/brcmfmac/sdio.c
9132 ++++ b/drivers/net/wireless/brcm80211/brcmfmac/sdio.c
9133 +@@ -2027,6 +2027,7 @@ static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
9134 + BRCMF_SDIO_FT_NORMAL)) {
9135 + rd->len = 0;
9136 + brcmu_pkt_buf_free_skb(pkt);
9137 ++ continue;
9138 + }
9139 + bus->sdcnt.rx_readahead_cnt++;
9140 + if (rd->len != roundup(rd_new.len, 16)) {
9141 +diff --git a/drivers/net/wireless/hostap/hostap_ap.c b/drivers/net/wireless/hostap/hostap_ap.c
9142 +index c995ace153ee..30171d4c4718 100644
9143 +--- a/drivers/net/wireless/hostap/hostap_ap.c
9144 ++++ b/drivers/net/wireless/hostap/hostap_ap.c
9145 +@@ -2570,7 +2570,7 @@ static int prism2_hostapd_add_sta(struct ap_data *ap,
9146 + sta->supported_rates[0] = 2;
9147 + if (sta->tx_supp_rates & WLAN_RATE_2M)
9148 + sta->supported_rates[1] = 4;
9149 +- if (sta->tx_supp_rates & WLAN_RATE_5M5)
9150 ++ if (sta->tx_supp_rates & WLAN_RATE_5M5)
9151 + sta->supported_rates[2] = 11;
9152 + if (sta->tx_supp_rates & WLAN_RATE_11M)
9153 + sta->supported_rates[3] = 22;
9154 +diff --git a/drivers/net/wireless/ipw2x00/ipw2100.c b/drivers/net/wireless/ipw2x00/ipw2100.c
9155 +index 36818c7f30b9..11cfc5822eb0 100644
9156 +--- a/drivers/net/wireless/ipw2x00/ipw2100.c
9157 ++++ b/drivers/net/wireless/ipw2x00/ipw2100.c
9158 +@@ -3213,8 +3213,9 @@ static void ipw2100_tx_send_data(struct ipw2100_priv *priv)
9159 + }
9160 + }
9161 +
9162 +-static void ipw2100_irq_tasklet(struct ipw2100_priv *priv)
9163 ++static void ipw2100_irq_tasklet(unsigned long data)
9164 + {
9165 ++ struct ipw2100_priv *priv = (struct ipw2100_priv *)data;
9166 + struct net_device *dev = priv->net_dev;
9167 + unsigned long flags;
9168 + u32 inta, tmp;
9169 +@@ -6022,7 +6023,7 @@ static void ipw2100_rf_kill(struct work_struct *work)
9170 + spin_unlock_irqrestore(&priv->low_lock, flags);
9171 + }
9172 +
9173 +-static void ipw2100_irq_tasklet(struct ipw2100_priv *priv);
9174 ++static void ipw2100_irq_tasklet(unsigned long data);
9175 +
9176 + static const struct net_device_ops ipw2100_netdev_ops = {
9177 + .ndo_open = ipw2100_open,
9178 +@@ -6151,7 +6152,7 @@ static struct net_device *ipw2100_alloc_device(struct pci_dev *pci_dev,
9179 + INIT_DELAYED_WORK(&priv->rf_kill, ipw2100_rf_kill);
9180 + INIT_DELAYED_WORK(&priv->scan_event, ipw2100_scan_event);
9181 +
9182 +- tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
9183 ++ tasklet_init(&priv->irq_tasklet,
9184 + ipw2100_irq_tasklet, (unsigned long)priv);
9185 +
9186 + /* NOTE: We do not start the deferred work for status checks yet */
9187 +diff --git a/drivers/net/wireless/ipw2x00/ipw2200.c b/drivers/net/wireless/ipw2x00/ipw2200.c
9188 +index ed0adaf1eec4..1e08f94dc4da 100644
9189 +--- a/drivers/net/wireless/ipw2x00/ipw2200.c
9190 ++++ b/drivers/net/wireless/ipw2x00/ipw2200.c
9191 +@@ -1968,8 +1968,9 @@ static void notify_wx_assoc_event(struct ipw_priv *priv)
9192 + wireless_send_event(priv->net_dev, SIOCGIWAP, &wrqu, NULL);
9193 + }
9194 +
9195 +-static void ipw_irq_tasklet(struct ipw_priv *priv)
9196 ++static void ipw_irq_tasklet(unsigned long data)
9197 + {
9198 ++ struct ipw_priv *priv = (struct ipw_priv *)data;
9199 + u32 inta, inta_mask, handled = 0;
9200 + unsigned long flags;
9201 + int rc = 0;
9202 +@@ -10705,7 +10706,7 @@ static int ipw_setup_deferred_work(struct ipw_priv *priv)
9203 + INIT_WORK(&priv->qos_activate, ipw_bg_qos_activate);
9204 + #endif /* CONFIG_IPW2200_QOS */
9205 +
9206 +- tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
9207 ++ tasklet_init(&priv->irq_tasklet,
9208 + ipw_irq_tasklet, (unsigned long)priv);
9209 +
9210 + return ret;
9211 +diff --git a/drivers/net/wireless/iwlegacy/3945-mac.c b/drivers/net/wireless/iwlegacy/3945-mac.c
9212 +index af1b3e6839fa..775f5e7791d4 100644
9213 +--- a/drivers/net/wireless/iwlegacy/3945-mac.c
9214 ++++ b/drivers/net/wireless/iwlegacy/3945-mac.c
9215 +@@ -1399,8 +1399,9 @@ il3945_dump_nic_error_log(struct il_priv *il)
9216 + }
9217 +
9218 + static void
9219 +-il3945_irq_tasklet(struct il_priv *il)
9220 ++il3945_irq_tasklet(unsigned long data)
9221 + {
9222 ++ struct il_priv *il = (struct il_priv *)data;
9223 + u32 inta, handled = 0;
9224 + u32 inta_fh;
9225 + unsigned long flags;
9226 +@@ -3432,7 +3433,7 @@ il3945_setup_deferred_work(struct il_priv *il)
9227 + setup_timer(&il->watchdog, il_bg_watchdog, (unsigned long)il);
9228 +
9229 + tasklet_init(&il->irq_tasklet,
9230 +- (void (*)(unsigned long))il3945_irq_tasklet,
9231 ++ il3945_irq_tasklet,
9232 + (unsigned long)il);
9233 + }
9234 +
9235 +diff --git a/drivers/net/wireless/iwlegacy/4965-mac.c b/drivers/net/wireless/iwlegacy/4965-mac.c
9236 +index 04b0349a6ad9..b1925bdb1171 100644
9237 +--- a/drivers/net/wireless/iwlegacy/4965-mac.c
9238 ++++ b/drivers/net/wireless/iwlegacy/4965-mac.c
9239 +@@ -4361,8 +4361,9 @@ il4965_synchronize_irq(struct il_priv *il)
9240 + }
9241 +
9242 + static void
9243 +-il4965_irq_tasklet(struct il_priv *il)
9244 ++il4965_irq_tasklet(unsigned long data)
9245 + {
9246 ++ struct il_priv *il = (struct il_priv *)data;
9247 + u32 inta, handled = 0;
9248 + u32 inta_fh;
9249 + unsigned long flags;
9250 +@@ -6257,7 +6258,7 @@ il4965_setup_deferred_work(struct il_priv *il)
9251 + setup_timer(&il->watchdog, il_bg_watchdog, (unsigned long)il);
9252 +
9253 + tasklet_init(&il->irq_tasklet,
9254 +- (void (*)(unsigned long))il4965_irq_tasklet,
9255 ++ il4965_irq_tasklet,
9256 + (unsigned long)il);
9257 + }
9258 +
9259 +diff --git a/drivers/net/wireless/iwlegacy/common.c b/drivers/net/wireless/iwlegacy/common.c
9260 +index 887114582583..544ab3750ea6 100644
9261 +--- a/drivers/net/wireless/iwlegacy/common.c
9262 ++++ b/drivers/net/wireless/iwlegacy/common.c
9263 +@@ -717,7 +717,7 @@ il_eeprom_init(struct il_priv *il)
9264 + u32 gp = _il_rd(il, CSR_EEPROM_GP);
9265 + int sz;
9266 + int ret;
9267 +- u16 addr;
9268 ++ int addr;
9269 +
9270 + /* allocate eeprom */
9271 + sz = il->cfg->eeprom_size;
9272 +diff --git a/drivers/net/wireless/orinoco/orinoco_usb.c b/drivers/net/wireless/orinoco/orinoco_usb.c
9273 +index e434f7ca8ff3..3c5baccd6792 100644
9274 +--- a/drivers/net/wireless/orinoco/orinoco_usb.c
9275 ++++ b/drivers/net/wireless/orinoco/orinoco_usb.c
9276 +@@ -1351,7 +1351,8 @@ static int ezusb_init(struct hermes *hw)
9277 + int retval;
9278 +
9279 + BUG_ON(in_interrupt());
9280 +- BUG_ON(!upriv);
9281 ++ if (!upriv)
9282 ++ return -EINVAL;
9283 +
9284 + upriv->reply_count = 0;
9285 + /* Write the MAGIC number on the simulated registers to keep
9286 +diff --git a/drivers/net/wireless/realtek/rtlwifi/pci.c b/drivers/net/wireless/realtek/rtlwifi/pci.c
9287 +index b51815eccdb3..17a07d6b961c 100644
9288 +--- a/drivers/net/wireless/realtek/rtlwifi/pci.c
9289 ++++ b/drivers/net/wireless/realtek/rtlwifi/pci.c
9290 +@@ -1096,13 +1096,15 @@ done:
9291 + return ret;
9292 + }
9293 +
9294 +-static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
9295 ++static void _rtl_pci_irq_tasklet(unsigned long data)
9296 + {
9297 ++ struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
9298 + _rtl_pci_tx_chk_waitq(hw);
9299 + }
9300 +
9301 +-static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
9302 ++static void _rtl_pci_prepare_bcn_tasklet(unsigned long data)
9303 + {
9304 ++ struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
9305 + struct rtl_priv *rtlpriv = rtl_priv(hw);
9306 + struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
9307 + struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
9308 +@@ -1223,10 +1225,10 @@ static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
9309 +
9310 + /*task */
9311 + tasklet_init(&rtlpriv->works.irq_tasklet,
9312 +- (void (*)(unsigned long))_rtl_pci_irq_tasklet,
9313 ++ _rtl_pci_irq_tasklet,
9314 + (unsigned long)hw);
9315 + tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
9316 +- (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
9317 ++ _rtl_pci_prepare_bcn_tasklet,
9318 + (unsigned long)hw);
9319 + INIT_WORK(&rtlpriv->works.lps_change_work,
9320 + rtl_lps_change_work_callback);
9321 +diff --git a/drivers/nfc/port100.c b/drivers/nfc/port100.c
9322 +index 87d509996704..3ffbed72adf7 100644
9323 +--- a/drivers/nfc/port100.c
9324 ++++ b/drivers/nfc/port100.c
9325 +@@ -545,7 +545,7 @@ static void port100_tx_update_payload_len(void *_frame, int len)
9326 + {
9327 + struct port100_frame *frame = _frame;
9328 +
9329 +- frame->datalen = cpu_to_le16(le16_to_cpu(frame->datalen) + len);
9330 ++ le16_add_cpu(&frame->datalen, len);
9331 + }
9332 +
9333 + static bool port100_rx_frame_is_valid(void *_frame)
9334 +diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
9335 +index 1723ac1b30e1..fe2865a0da39 100644
9336 +--- a/drivers/pci/setup-bus.c
9337 ++++ b/drivers/pci/setup-bus.c
9338 +@@ -1760,12 +1760,18 @@ again:
9339 + /* restore size and flags */
9340 + list_for_each_entry(fail_res, &fail_head, list) {
9341 + struct resource *res = fail_res->res;
9342 ++ int idx;
9343 +
9344 + res->start = fail_res->start;
9345 + res->end = fail_res->end;
9346 + res->flags = fail_res->flags;
9347 +- if (fail_res->dev->subordinate)
9348 +- res->flags = 0;
9349 ++
9350 ++ if (pci_is_bridge(fail_res->dev)) {
9351 ++ idx = res - &fail_res->dev->resource[0];
9352 ++ if (idx >= PCI_BRIDGE_RESOURCES &&
9353 ++ idx <= PCI_BRIDGE_RESOURCE_END)
9354 ++ res->flags = 0;
9355 ++ }
9356 + }
9357 + free_list(&fail_head);
9358 +
9359 +@@ -1826,12 +1832,18 @@ again:
9360 + /* restore size and flags */
9361 + list_for_each_entry(fail_res, &fail_head, list) {
9362 + struct resource *res = fail_res->res;
9363 ++ int idx;
9364 +
9365 + res->start = fail_res->start;
9366 + res->end = fail_res->end;
9367 + res->flags = fail_res->flags;
9368 +- if (fail_res->dev->subordinate)
9369 +- res->flags = 0;
9370 ++
9371 ++ if (pci_is_bridge(fail_res->dev)) {
9372 ++ idx = res - &fail_res->dev->resource[0];
9373 ++ if (idx >= PCI_BRIDGE_RESOURCES &&
9374 ++ idx <= PCI_BRIDGE_RESOURCE_END)
9375 ++ res->flags = 0;
9376 ++ }
9377 + }
9378 + free_list(&fail_head);
9379 +
9380 +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
9381 +index e1c34e19222e..3ddb9565ed80 100644
9382 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c
9383 ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
9384 +@@ -500,17 +500,15 @@ enum {
9385 + SD_WP_MARK, SD_CLK_MARK, SD_CMD_MARK,
9386 + CRX0_MARK, CRX1_MARK,
9387 + CTX0_MARK, CTX1_MARK,
9388 ++ CRX0_CRX1_MARK, CTX0_CTX1_MARK,
9389 +
9390 + PWM1A_MARK, PWM1B_MARK, PWM1C_MARK, PWM1D_MARK,
9391 + PWM1E_MARK, PWM1F_MARK, PWM1G_MARK, PWM1H_MARK,
9392 + PWM2A_MARK, PWM2B_MARK, PWM2C_MARK, PWM2D_MARK,
9393 + PWM2E_MARK, PWM2F_MARK, PWM2G_MARK, PWM2H_MARK,
9394 + IERXD_MARK, IETXD_MARK,
9395 +- CRX0_CRX1_MARK,
9396 + WDTOVF_MARK,
9397 +
9398 +- CRX0X1_MARK,
9399 +-
9400 + /* DMAC */
9401 + TEND0_MARK, DACK0_MARK, DREQ0_MARK,
9402 + TEND1_MARK, DACK1_MARK, DREQ1_MARK,
9403 +@@ -998,12 +996,12 @@ static const u16 pinmux_data[] = {
9404 +
9405 + PINMUX_DATA(PJ3_DATA, PJ3MD_00),
9406 + PINMUX_DATA(CRX1_MARK, PJ3MD_01),
9407 +- PINMUX_DATA(CRX0X1_MARK, PJ3MD_10),
9408 ++ PINMUX_DATA(CRX0_CRX1_MARK, PJ3MD_10),
9409 + PINMUX_DATA(IRQ1_PJ_MARK, PJ3MD_11),
9410 +
9411 + PINMUX_DATA(PJ2_DATA, PJ2MD_000),
9412 + PINMUX_DATA(CTX1_MARK, PJ2MD_001),
9413 +- PINMUX_DATA(CRX0_CRX1_MARK, PJ2MD_010),
9414 ++ PINMUX_DATA(CTX0_CTX1_MARK, PJ2MD_010),
9415 + PINMUX_DATA(CS2_MARK, PJ2MD_011),
9416 + PINMUX_DATA(SCK0_MARK, PJ2MD_100),
9417 + PINMUX_DATA(LCD_M_DISP_MARK, PJ2MD_101),
9418 +@@ -1248,6 +1246,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
9419 + GPIO_FN(CTX1),
9420 + GPIO_FN(CRX1),
9421 + GPIO_FN(CTX0),
9422 ++ GPIO_FN(CTX0_CTX1),
9423 + GPIO_FN(CRX0),
9424 + GPIO_FN(CRX0_CRX1),
9425 +
9426 +diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
9427 +index cfdb4fc177c3..3df0c0d139d0 100644
9428 +--- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c
9429 ++++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
9430 +@@ -740,13 +740,12 @@ enum {
9431 + CRX0_MARK, CTX0_MARK,
9432 + CRX1_MARK, CTX1_MARK,
9433 + CRX2_MARK, CTX2_MARK,
9434 +- CRX0_CRX1_MARK,
9435 +- CRX0_CRX1_CRX2_MARK,
9436 +- CTX0CTX1CTX2_MARK,
9437 ++ CRX0_CRX1_MARK, CTX0_CTX1_MARK,
9438 ++ CRX0_CRX1_CRX2_MARK, CTX0_CTX1_CTX2_MARK,
9439 + CRX1_PJ22_MARK, CTX1_PJ23_MARK,
9440 + CRX2_PJ20_MARK, CTX2_PJ21_MARK,
9441 +- CRX0CRX1_PJ22_MARK,
9442 +- CRX0CRX1CRX2_PJ20_MARK,
9443 ++ CRX0_CRX1_PJ22_MARK, CTX0_CTX1_PJ23_MARK,
9444 ++ CRX0_CRX1_CRX2_PJ20_MARK, CTX0_CTX1_CTX2_PJ21_MARK,
9445 +
9446 + /* VDC */
9447 + DV_CLK_MARK,
9448 +@@ -824,6 +823,7 @@ static const u16 pinmux_data[] = {
9449 + PINMUX_DATA(CS3_MARK, PC8MD_001),
9450 + PINMUX_DATA(TXD7_MARK, PC8MD_010),
9451 + PINMUX_DATA(CTX1_MARK, PC8MD_011),
9452 ++ PINMUX_DATA(CTX0_CTX1_MARK, PC8MD_100),
9453 +
9454 + PINMUX_DATA(PC7_DATA, PC7MD_000),
9455 + PINMUX_DATA(CKE_MARK, PC7MD_001),
9456 +@@ -836,11 +836,12 @@ static const u16 pinmux_data[] = {
9457 + PINMUX_DATA(CAS_MARK, PC6MD_001),
9458 + PINMUX_DATA(SCK7_MARK, PC6MD_010),
9459 + PINMUX_DATA(CTX0_MARK, PC6MD_011),
9460 ++ PINMUX_DATA(CTX0_CTX1_CTX2_MARK, PC6MD_100),
9461 +
9462 + PINMUX_DATA(PC5_DATA, PC5MD_000),
9463 + PINMUX_DATA(RAS_MARK, PC5MD_001),
9464 + PINMUX_DATA(CRX0_MARK, PC5MD_011),
9465 +- PINMUX_DATA(CTX0CTX1CTX2_MARK, PC5MD_100),
9466 ++ PINMUX_DATA(CTX0_CTX1_CTX2_MARK, PC5MD_100),
9467 + PINMUX_DATA(IRQ0_PC_MARK, PC5MD_101),
9468 +
9469 + PINMUX_DATA(PC4_DATA, PC4MD_00),
9470 +@@ -1292,30 +1293,32 @@ static const u16 pinmux_data[] = {
9471 + PINMUX_DATA(LCD_DATA23_PJ23_MARK, PJ23MD_010),
9472 + PINMUX_DATA(LCD_TCON6_MARK, PJ23MD_011),
9473 + PINMUX_DATA(IRQ3_PJ_MARK, PJ23MD_100),
9474 +- PINMUX_DATA(CTX1_MARK, PJ23MD_101),
9475 ++ PINMUX_DATA(CTX1_PJ23_MARK, PJ23MD_101),
9476 ++ PINMUX_DATA(CTX0_CTX1_PJ23_MARK, PJ23MD_110),
9477 +
9478 + PINMUX_DATA(PJ22_DATA, PJ22MD_000),
9479 + PINMUX_DATA(DV_DATA22_MARK, PJ22MD_001),
9480 + PINMUX_DATA(LCD_DATA22_PJ22_MARK, PJ22MD_010),
9481 + PINMUX_DATA(LCD_TCON5_MARK, PJ22MD_011),
9482 + PINMUX_DATA(IRQ2_PJ_MARK, PJ22MD_100),
9483 +- PINMUX_DATA(CRX1_MARK, PJ22MD_101),
9484 +- PINMUX_DATA(CRX0_CRX1_MARK, PJ22MD_110),
9485 ++ PINMUX_DATA(CRX1_PJ22_MARK, PJ22MD_101),
9486 ++ PINMUX_DATA(CRX0_CRX1_PJ22_MARK, PJ22MD_110),
9487 +
9488 + PINMUX_DATA(PJ21_DATA, PJ21MD_000),
9489 + PINMUX_DATA(DV_DATA21_MARK, PJ21MD_001),
9490 + PINMUX_DATA(LCD_DATA21_PJ21_MARK, PJ21MD_010),
9491 + PINMUX_DATA(LCD_TCON4_MARK, PJ21MD_011),
9492 + PINMUX_DATA(IRQ1_PJ_MARK, PJ21MD_100),
9493 +- PINMUX_DATA(CTX2_MARK, PJ21MD_101),
9494 ++ PINMUX_DATA(CTX2_PJ21_MARK, PJ21MD_101),
9495 ++ PINMUX_DATA(CTX0_CTX1_CTX2_PJ21_MARK, PJ21MD_110),
9496 +
9497 + PINMUX_DATA(PJ20_DATA, PJ20MD_000),
9498 + PINMUX_DATA(DV_DATA20_MARK, PJ20MD_001),
9499 + PINMUX_DATA(LCD_DATA20_PJ20_MARK, PJ20MD_010),
9500 + PINMUX_DATA(LCD_TCON3_MARK, PJ20MD_011),
9501 + PINMUX_DATA(IRQ0_PJ_MARK, PJ20MD_100),
9502 +- PINMUX_DATA(CRX2_MARK, PJ20MD_101),
9503 +- PINMUX_DATA(CRX0CRX1CRX2_PJ20_MARK, PJ20MD_110),
9504 ++ PINMUX_DATA(CRX2_PJ20_MARK, PJ20MD_101),
9505 ++ PINMUX_DATA(CRX0_CRX1_CRX2_PJ20_MARK, PJ20MD_110),
9506 +
9507 + PINMUX_DATA(PJ19_DATA, PJ19MD_000),
9508 + PINMUX_DATA(DV_DATA19_MARK, PJ19MD_001),
9509 +@@ -1666,12 +1669,24 @@ static const struct pinmux_func pinmux_func_gpios[] = {
9510 + GPIO_FN(WDTOVF),
9511 +
9512 + /* CAN */
9513 ++ GPIO_FN(CTX2),
9514 ++ GPIO_FN(CRX2),
9515 + GPIO_FN(CTX1),
9516 + GPIO_FN(CRX1),
9517 + GPIO_FN(CTX0),
9518 + GPIO_FN(CRX0),
9519 ++ GPIO_FN(CTX0_CTX1),
9520 + GPIO_FN(CRX0_CRX1),
9521 ++ GPIO_FN(CTX0_CTX1_CTX2),
9522 + GPIO_FN(CRX0_CRX1_CRX2),
9523 ++ GPIO_FN(CTX2_PJ21),
9524 ++ GPIO_FN(CRX2_PJ20),
9525 ++ GPIO_FN(CTX1_PJ23),
9526 ++ GPIO_FN(CRX1_PJ22),
9527 ++ GPIO_FN(CTX0_CTX1_PJ23),
9528 ++ GPIO_FN(CRX0_CRX1_PJ22),
9529 ++ GPIO_FN(CTX0_CTX1_CTX2_PJ21),
9530 ++ GPIO_FN(CRX0_CRX1_CRX2_PJ20),
9531 +
9532 + /* DMAC */
9533 + GPIO_FN(TEND0),
9534 +diff --git a/drivers/regulator/rk808-regulator.c b/drivers/regulator/rk808-regulator.c
9535 +index d86a3dcd61e2..b96d50a03022 100644
9536 +--- a/drivers/regulator/rk808-regulator.c
9537 ++++ b/drivers/regulator/rk808-regulator.c
9538 +@@ -551,7 +551,7 @@ static int rk808_regulator_dt_parse_pdata(struct device *dev,
9539 + }
9540 +
9541 + if (!pdata->dvs_gpio[i]) {
9542 +- dev_warn(dev, "there is no dvs%d gpio\n", i);
9543 ++ dev_info(dev, "there is no dvs%d gpio\n", i);
9544 + continue;
9545 + }
9546 +
9547 +diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
9548 +index 4f7ce0097191..b76ef5244b65 100644
9549 +--- a/drivers/remoteproc/remoteproc_core.c
9550 ++++ b/drivers/remoteproc/remoteproc_core.c
9551 +@@ -1477,7 +1477,7 @@ static int __init remoteproc_init(void)
9552 +
9553 + return 0;
9554 + }
9555 +-module_init(remoteproc_init);
9556 ++subsys_initcall(remoteproc_init);
9557 +
9558 + static void __exit remoteproc_exit(void)
9559 + {
9560 +diff --git a/drivers/scsi/aic7xxx/aic7xxx_core.c b/drivers/scsi/aic7xxx/aic7xxx_core.c
9561 +index 64ab9eaec428..def3208dd290 100644
9562 +--- a/drivers/scsi/aic7xxx/aic7xxx_core.c
9563 ++++ b/drivers/scsi/aic7xxx/aic7xxx_core.c
9564 +@@ -2321,7 +2321,7 @@ ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
9565 + * At some speeds, we only support
9566 + * ST transfers.
9567 + */
9568 +- if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
9569 ++ if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
9570 + *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
9571 + break;
9572 + }
9573 +diff --git a/drivers/scsi/iscsi_tcp.c b/drivers/scsi/iscsi_tcp.c
9574 +index fccb8991bd5b..64a49dccb0b6 100644
9575 +--- a/drivers/scsi/iscsi_tcp.c
9576 ++++ b/drivers/scsi/iscsi_tcp.c
9577 +@@ -872,6 +872,10 @@ free_host:
9578 + static void iscsi_sw_tcp_session_destroy(struct iscsi_cls_session *cls_session)
9579 + {
9580 + struct Scsi_Host *shost = iscsi_session_to_shost(cls_session);
9581 ++ struct iscsi_session *session = cls_session->dd_data;
9582 ++
9583 ++ if (WARN_ON_ONCE(session->leadconn))
9584 ++ return;
9585 +
9586 + iscsi_tcp_r2tpool_free(cls_session->dd_data);
9587 + iscsi_session_teardown(cls_session);
9588 +diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c
9589 +index 8975baab73e5..daafb60fa13e 100644
9590 +--- a/drivers/scsi/qla2xxx/qla_os.c
9591 ++++ b/drivers/scsi/qla2xxx/qla_os.c
9592 +@@ -429,6 +429,12 @@ static int qla25xx_setup_mode(struct scsi_qla_host *vha)
9593 + goto fail;
9594 + }
9595 + if (ql2xmultique_tag) {
9596 ++ ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
9597 ++ if (unlikely(!ha->wq)) {
9598 ++ ql_log(ql_log_warn, vha, 0x01e0,
9599 ++ "Failed to alloc workqueue.\n");
9600 ++ goto fail;
9601 ++ }
9602 + /* create a request queue for IO */
9603 + options |= BIT_7;
9604 + req = qla25xx_create_req_que(ha, options, 0, 0, -1,
9605 +@@ -436,9 +442,8 @@ static int qla25xx_setup_mode(struct scsi_qla_host *vha)
9606 + if (!req) {
9607 + ql_log(ql_log_warn, vha, 0x00e0,
9608 + "Failed to create request queue.\n");
9609 +- goto fail;
9610 ++ goto fail2;
9611 + }
9612 +- ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
9613 + vha->req = ha->req_q_map[req];
9614 + options |= BIT_1;
9615 + for (ques = 1; ques < ha->max_rsp_queues; ques++) {
9616 +@@ -446,7 +451,7 @@ static int qla25xx_setup_mode(struct scsi_qla_host *vha)
9617 + if (!ret) {
9618 + ql_log(ql_log_warn, vha, 0x00e8,
9619 + "Failed to create response queue.\n");
9620 +- goto fail2;
9621 ++ goto fail3;
9622 + }
9623 + }
9624 + ha->flags.cpu_affinity_enabled = 1;
9625 +@@ -460,11 +465,13 @@ static int qla25xx_setup_mode(struct scsi_qla_host *vha)
9626 + ha->max_rsp_queues, ha->max_req_queues);
9627 + }
9628 + return 0;
9629 +-fail2:
9630 ++
9631 ++fail3:
9632 + qla25xx_delete_queues(vha);
9633 +- destroy_workqueue(ha->wq);
9634 +- ha->wq = NULL;
9635 + vha->req = ha->req_q_map[0];
9636 ++fail2:
9637 ++ destroy_workqueue(ha->wq);
9638 ++ ha->wq = NULL;
9639 + fail:
9640 + ha->mqenable = 0;
9641 + kfree(ha->req_q_map);
9642 +diff --git a/drivers/scsi/scsi_transport_iscsi.c b/drivers/scsi/scsi_transport_iscsi.c
9643 +index ab32e6073642..20cf01d6ded7 100644
9644 +--- a/drivers/scsi/scsi_transport_iscsi.c
9645 ++++ b/drivers/scsi/scsi_transport_iscsi.c
9646 +@@ -2965,6 +2965,24 @@ iscsi_set_path(struct iscsi_transport *transport, struct iscsi_uevent *ev)
9647 + return err;
9648 + }
9649 +
9650 ++static int iscsi_session_has_conns(int sid)
9651 ++{
9652 ++ struct iscsi_cls_conn *conn;
9653 ++ unsigned long flags;
9654 ++ int found = 0;
9655 ++
9656 ++ spin_lock_irqsave(&connlock, flags);
9657 ++ list_for_each_entry(conn, &connlist, conn_list) {
9658 ++ if (iscsi_conn_get_sid(conn) == sid) {
9659 ++ found = 1;
9660 ++ break;
9661 ++ }
9662 ++ }
9663 ++ spin_unlock_irqrestore(&connlock, flags);
9664 ++
9665 ++ return found;
9666 ++}
9667 ++
9668 + static int
9669 + iscsi_set_iface_params(struct iscsi_transport *transport,
9670 + struct iscsi_uevent *ev, uint32_t len)
9671 +@@ -3539,10 +3557,12 @@ iscsi_if_recv_msg(struct sk_buff *skb, struct nlmsghdr *nlh, uint32_t *group)
9672 + break;
9673 + case ISCSI_UEVENT_DESTROY_SESSION:
9674 + session = iscsi_session_lookup(ev->u.d_session.sid);
9675 +- if (session)
9676 +- transport->destroy_session(session);
9677 +- else
9678 ++ if (!session)
9679 + err = -EINVAL;
9680 ++ else if (iscsi_session_has_conns(ev->u.d_session.sid))
9681 ++ err = -EBUSY;
9682 ++ else
9683 ++ transport->destroy_session(session);
9684 + break;
9685 + case ISCSI_UEVENT_UNBIND_SESSION:
9686 + session = iscsi_session_lookup(ev->u.d_session.sid);
9687 +diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c
9688 +index 5b18f6ffa45c..cd61c883c19f 100644
9689 +--- a/drivers/soc/tegra/fuse/tegra-apbmisc.c
9690 ++++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c
9691 +@@ -134,7 +134,7 @@ void __init tegra_init_apbmisc(void)
9692 + apbmisc.flags = IORESOURCE_MEM;
9693 +
9694 + /* strapping options */
9695 +- if (tegra_get_chip_id() == TEGRA124) {
9696 ++ if (of_machine_is_compatible("nvidia,tegra124")) {
9697 + straps.start = 0x7000e864;
9698 + straps.end = 0x7000e867;
9699 + } else {
9700 +diff --git a/drivers/staging/android/ashmem.c b/drivers/staging/android/ashmem.c
9701 +index b4c425383f99..d6efd07146ce 100644
9702 +--- a/drivers/staging/android/ashmem.c
9703 ++++ b/drivers/staging/android/ashmem.c
9704 +@@ -357,8 +357,23 @@ static inline vm_flags_t calc_vm_may_flags(unsigned long prot)
9705 + _calc_vm_trans(prot, PROT_EXEC, VM_MAYEXEC);
9706 + }
9707 +
9708 ++static int ashmem_vmfile_mmap(struct file *file, struct vm_area_struct *vma)
9709 ++{
9710 ++ /* do not allow to mmap ashmem backing shmem file directly */
9711 ++ return -EPERM;
9712 ++}
9713 ++
9714 ++static unsigned long
9715 ++ashmem_vmfile_get_unmapped_area(struct file *file, unsigned long addr,
9716 ++ unsigned long len, unsigned long pgoff,
9717 ++ unsigned long flags)
9718 ++{
9719 ++ return current->mm->get_unmapped_area(file, addr, len, pgoff, flags);
9720 ++}
9721 ++
9722 + static int ashmem_mmap(struct file *file, struct vm_area_struct *vma)
9723 + {
9724 ++ static struct file_operations vmfile_fops;
9725 + struct ashmem_area *asma = file->private_data;
9726 + int ret = 0;
9727 +
9728 +@@ -399,6 +414,19 @@ static int ashmem_mmap(struct file *file, struct vm_area_struct *vma)
9729 + }
9730 + vmfile->f_mode |= FMODE_LSEEK;
9731 + asma->file = vmfile;
9732 ++ /*
9733 ++ * override mmap operation of the vmfile so that it can't be
9734 ++ * remapped which would lead to creation of a new vma with no
9735 ++ * asma permission checks. Have to override get_unmapped_area
9736 ++ * as well to prevent VM_BUG_ON check for f_ops modification.
9737 ++ */
9738 ++ if (!vmfile_fops.mmap) {
9739 ++ vmfile_fops = *vmfile->f_op;
9740 ++ vmfile_fops.mmap = ashmem_vmfile_mmap;
9741 ++ vmfile_fops.get_unmapped_area =
9742 ++ ashmem_vmfile_get_unmapped_area;
9743 ++ }
9744 ++ vmfile->f_op = &vmfile_fops;
9745 + }
9746 + get_file(asma->file);
9747 +
9748 +diff --git a/drivers/staging/rtl8188eu/os_dep/ioctl_linux.c b/drivers/staging/rtl8188eu/os_dep/ioctl_linux.c
9749 +index ec90f2781085..2a6192e08b75 100644
9750 +--- a/drivers/staging/rtl8188eu/os_dep/ioctl_linux.c
9751 ++++ b/drivers/staging/rtl8188eu/os_dep/ioctl_linux.c
9752 +@@ -2054,7 +2054,7 @@ static int wpa_supplicant_ioctl(struct net_device *dev, struct iw_point *p)
9753 + struct ieee_param *param;
9754 + uint ret = 0;
9755 +
9756 +- if (p->length < sizeof(struct ieee_param) || !p->pointer) {
9757 ++ if (!p->pointer || p->length != sizeof(struct ieee_param)) {
9758 + ret = -EINVAL;
9759 + goto out;
9760 + }
9761 +@@ -2859,7 +2859,7 @@ static int rtw_hostapd_ioctl(struct net_device *dev, struct iw_point *p)
9762 + goto out;
9763 + }
9764 +
9765 +- if (!p->pointer) {
9766 ++ if (!p->pointer || p->length != sizeof(struct ieee_param)) {
9767 + ret = -EINVAL;
9768 + goto out;
9769 + }
9770 +diff --git a/drivers/staging/vt6656/dpc.c b/drivers/staging/vt6656/dpc.c
9771 +index e6367ed3b0bb..4fc6f00666ca 100644
9772 +--- a/drivers/staging/vt6656/dpc.c
9773 ++++ b/drivers/staging/vt6656/dpc.c
9774 +@@ -144,7 +144,7 @@ int vnt_rx_data(struct vnt_private *priv, struct vnt_rcb *ptr_rcb,
9775 +
9776 + vnt_rf_rssi_to_dbm(priv, *rssi, &rx_dbm);
9777 +
9778 +- priv->bb_pre_ed_rssi = (u8)rx_dbm + 1;
9779 ++ priv->bb_pre_ed_rssi = (u8)-rx_dbm + 1;
9780 + priv->current_rssi = priv->bb_pre_ed_rssi;
9781 +
9782 + frame = skb_data + 8;
9783 +diff --git a/drivers/target/iscsi/iscsi_target.c b/drivers/target/iscsi/iscsi_target.c
9784 +index 07d9384bce94..cbb4414edd71 100644
9785 +--- a/drivers/target/iscsi/iscsi_target.c
9786 ++++ b/drivers/target/iscsi/iscsi_target.c
9787 +@@ -993,9 +993,7 @@ int iscsit_setup_scsi_cmd(struct iscsi_conn *conn, struct iscsi_cmd *cmd,
9788 + hdr->cmdsn, be32_to_cpu(hdr->data_length), payload_length,
9789 + conn->cid);
9790 +
9791 +- if (target_get_sess_cmd(&cmd->se_cmd, true) < 0)
9792 +- return iscsit_add_reject_cmd(cmd,
9793 +- ISCSI_REASON_WAITING_FOR_LOGOUT, buf);
9794 ++ target_get_sess_cmd(&cmd->se_cmd, true);
9795 +
9796 + cmd->sense_reason = transport_lookup_cmd_lun(&cmd->se_cmd,
9797 + scsilun_to_int(&hdr->lun));
9798 +@@ -1806,9 +1804,7 @@ iscsit_handle_task_mgt_cmd(struct iscsi_conn *conn, struct iscsi_cmd *cmd,
9799 + conn->sess->se_sess, 0, DMA_NONE,
9800 + TCM_SIMPLE_TAG, cmd->sense_buffer + 2);
9801 +
9802 +- if (target_get_sess_cmd(&cmd->se_cmd, true) < 0)
9803 +- return iscsit_add_reject_cmd(cmd,
9804 +- ISCSI_REASON_WAITING_FOR_LOGOUT, buf);
9805 ++ target_get_sess_cmd(&cmd->se_cmd, true);
9806 +
9807 + /*
9808 + * TASK_REASSIGN for ERL=2 / connection stays inside of
9809 +@@ -4309,6 +4305,9 @@ int iscsit_close_connection(
9810 + iscsit_stop_nopin_response_timer(conn);
9811 + iscsit_stop_nopin_timer(conn);
9812 +
9813 ++ if (conn->conn_transport->iscsit_wait_conn)
9814 ++ conn->conn_transport->iscsit_wait_conn(conn);
9815 ++
9816 + /*
9817 + * During Connection recovery drop unacknowledged out of order
9818 + * commands for this connection, and prepare the other commands
9819 +@@ -4391,11 +4390,6 @@ int iscsit_close_connection(
9820 + * must wait until they have completed.
9821 + */
9822 + iscsit_check_conn_usage_count(conn);
9823 +- target_sess_cmd_list_set_waiting(sess->se_sess);
9824 +- target_wait_for_sess_cmds(sess->se_sess);
9825 +-
9826 +- if (conn->conn_transport->iscsit_wait_conn)
9827 +- conn->conn_transport->iscsit_wait_conn(conn);
9828 +
9829 + if (conn->conn_rx_hash.tfm)
9830 + crypto_free_hash(conn->conn_rx_hash.tfm);
9831 +diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
9832 +index b59d0dafefab..ca69e2ca6b56 100644
9833 +--- a/drivers/tty/serial/imx.c
9834 ++++ b/drivers/tty/serial/imx.c
9835 +@@ -529,7 +529,7 @@ static void imx_dma_tx(struct imx_port *sport)
9836 +
9837 + sport->tx_bytes = uart_circ_chars_pending(xmit);
9838 +
9839 +- if (xmit->tail < xmit->head) {
9840 ++ if (xmit->tail < xmit->head || xmit->head == 0) {
9841 + sport->dma_tx_nents = 1;
9842 + sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
9843 + } else {
9844 +diff --git a/drivers/tty/vt/vt_ioctl.c b/drivers/tty/vt/vt_ioctl.c
9845 +index a86bc7afb3b2..e9d9f9f3dc88 100644
9846 +--- a/drivers/tty/vt/vt_ioctl.c
9847 ++++ b/drivers/tty/vt/vt_ioctl.c
9848 +@@ -850,58 +850,49 @@ int vt_ioctl(struct tty_struct *tty,
9849 +
9850 + case VT_RESIZEX:
9851 + {
9852 +- struct vt_consize __user *vtconsize = up;
9853 +- ushort ll,cc,vlin,clin,vcol,ccol;
9854 ++ struct vt_consize v;
9855 + if (!perm)
9856 + return -EPERM;
9857 +- if (!access_ok(VERIFY_READ, vtconsize,
9858 +- sizeof(struct vt_consize))) {
9859 +- ret = -EFAULT;
9860 +- break;
9861 +- }
9862 ++ if (copy_from_user(&v, up, sizeof(struct vt_consize)))
9863 ++ return -EFAULT;
9864 + /* FIXME: Should check the copies properly */
9865 +- __get_user(ll, &vtconsize->v_rows);
9866 +- __get_user(cc, &vtconsize->v_cols);
9867 +- __get_user(vlin, &vtconsize->v_vlin);
9868 +- __get_user(clin, &vtconsize->v_clin);
9869 +- __get_user(vcol, &vtconsize->v_vcol);
9870 +- __get_user(ccol, &vtconsize->v_ccol);
9871 +- vlin = vlin ? vlin : vc->vc_scan_lines;
9872 +- if (clin) {
9873 +- if (ll) {
9874 +- if (ll != vlin/clin) {
9875 +- /* Parameters don't add up */
9876 +- ret = -EINVAL;
9877 +- break;
9878 +- }
9879 +- } else
9880 +- ll = vlin/clin;
9881 ++ if (!v.v_vlin)
9882 ++ v.v_vlin = vc->vc_scan_lines;
9883 ++ if (v.v_clin) {
9884 ++ int rows = v.v_vlin/v.v_clin;
9885 ++ if (v.v_rows != rows) {
9886 ++ if (v.v_rows) /* Parameters don't add up */
9887 ++ return -EINVAL;
9888 ++ v.v_rows = rows;
9889 ++ }
9890 + }
9891 +- if (vcol && ccol) {
9892 +- if (cc) {
9893 +- if (cc != vcol/ccol) {
9894 +- ret = -EINVAL;
9895 +- break;
9896 +- }
9897 +- } else
9898 +- cc = vcol/ccol;
9899 ++ if (v.v_vcol && v.v_ccol) {
9900 ++ int cols = v.v_vcol/v.v_ccol;
9901 ++ if (v.v_cols != cols) {
9902 ++ if (v.v_cols)
9903 ++ return -EINVAL;
9904 ++ v.v_cols = cols;
9905 ++ }
9906 + }
9907 +
9908 +- if (clin > 32) {
9909 +- ret = -EINVAL;
9910 +- break;
9911 +- }
9912 +-
9913 ++ if (v.v_clin > 32)
9914 ++ return -EINVAL;
9915 ++
9916 + for (i = 0; i < MAX_NR_CONSOLES; i++) {
9917 ++ struct vc_data *vcp;
9918 ++
9919 + if (!vc_cons[i].d)
9920 + continue;
9921 + console_lock();
9922 +- if (vlin)
9923 +- vc_cons[i].d->vc_scan_lines = vlin;
9924 +- if (clin)
9925 +- vc_cons[i].d->vc_font.height = clin;
9926 +- vc_cons[i].d->vc_resize_user = 1;
9927 +- vc_resize(vc_cons[i].d, cc, ll);
9928 ++ vcp = vc_cons[i].d;
9929 ++ if (vcp) {
9930 ++ if (v.v_vlin)
9931 ++ vcp->vc_scan_lines = v.v_vlin;
9932 ++ if (v.v_clin)
9933 ++ vcp->vc_font.height = v.v_clin;
9934 ++ vcp->vc_resize_user = 1;
9935 ++ vc_resize(vcp, v.v_cols, v.v_rows);
9936 ++ }
9937 + console_unlock();
9938 + }
9939 + break;
9940 +diff --git a/drivers/uio/uio_dmem_genirq.c b/drivers/uio/uio_dmem_genirq.c
9941 +index e1134a4d97f3..a00b4aee6c79 100644
9942 +--- a/drivers/uio/uio_dmem_genirq.c
9943 ++++ b/drivers/uio/uio_dmem_genirq.c
9944 +@@ -135,11 +135,13 @@ static int uio_dmem_genirq_irqcontrol(struct uio_info *dev_info, s32 irq_on)
9945 + if (irq_on) {
9946 + if (test_and_clear_bit(0, &priv->flags))
9947 + enable_irq(dev_info->irq);
9948 ++ spin_unlock_irqrestore(&priv->lock, flags);
9949 + } else {
9950 +- if (!test_and_set_bit(0, &priv->flags))
9951 ++ if (!test_and_set_bit(0, &priv->flags)) {
9952 ++ spin_unlock_irqrestore(&priv->lock, flags);
9953 + disable_irq(dev_info->irq);
9954 ++ }
9955 + }
9956 +- spin_unlock_irqrestore(&priv->lock, flags);
9957 +
9958 + return 0;
9959 + }
9960 +diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
9961 +index 75a07b73a82b..4c302424c97a 100644
9962 +--- a/drivers/usb/core/hub.c
9963 ++++ b/drivers/usb/core/hub.c
9964 +@@ -1171,11 +1171,6 @@ static void hub_activate(struct usb_hub *hub, enum hub_activation_type type)
9965 + #ifdef CONFIG_PM
9966 + udev->reset_resume = 1;
9967 + #endif
9968 +- /* Don't set the change_bits when the device
9969 +- * was powered off.
9970 +- */
9971 +- if (test_bit(port1, hub->power_bits))
9972 +- set_bit(port1, hub->change_bits);
9973 +
9974 + } else {
9975 + /* The power session is gone; tell hub_wq */
9976 +diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c
9977 +index 19e819aa2419..ad8307140df8 100644
9978 +--- a/drivers/usb/core/quirks.c
9979 ++++ b/drivers/usb/core/quirks.c
9980 +@@ -291,6 +291,9 @@ static const struct usb_device_id usb_quirk_list[] = {
9981 + /* INTEL VALUE SSD */
9982 + { USB_DEVICE(0x8086, 0xf1a5), .driver_info = USB_QUIRK_RESET_RESUME },
9983 +
9984 ++ /* novation SoundControl XL */
9985 ++ { USB_DEVICE(0x1235, 0x0061), .driver_info = USB_QUIRK_RESET_RESUME },
9986 ++
9987 + { } /* terminating entry must be last */
9988 + };
9989 +
9990 +diff --git a/drivers/usb/gadget/udc/gr_udc.c b/drivers/usb/gadget/udc/gr_udc.c
9991 +index b9429bc42511..594639e5cbf8 100644
9992 +--- a/drivers/usb/gadget/udc/gr_udc.c
9993 ++++ b/drivers/usb/gadget/udc/gr_udc.c
9994 +@@ -2201,8 +2201,6 @@ static int gr_probe(struct platform_device *pdev)
9995 + return -ENOMEM;
9996 + }
9997 +
9998 +- spin_lock(&dev->lock);
9999 +-
10000 + /* Inside lock so that no gadget can use this udc until probe is done */
10001 + retval = usb_add_gadget_udc(dev->dev, &dev->gadget);
10002 + if (retval) {
10003 +@@ -2211,15 +2209,21 @@ static int gr_probe(struct platform_device *pdev)
10004 + }
10005 + dev->added = 1;
10006 +
10007 ++ spin_lock(&dev->lock);
10008 ++
10009 + retval = gr_udc_init(dev);
10010 +- if (retval)
10011 ++ if (retval) {
10012 ++ spin_unlock(&dev->lock);
10013 + goto out;
10014 +-
10015 +- gr_dfs_create(dev);
10016 ++ }
10017 +
10018 + /* Clear all interrupt enables that might be left on since last boot */
10019 + gr_disable_interrupts_and_pullup(dev);
10020 +
10021 ++ spin_unlock(&dev->lock);
10022 ++
10023 ++ gr_dfs_create(dev);
10024 ++
10025 + retval = gr_request_irq(dev, dev->irq);
10026 + if (retval) {
10027 + dev_err(dev->dev, "Failed to request irq %d\n", dev->irq);
10028 +@@ -2248,8 +2252,6 @@ static int gr_probe(struct platform_device *pdev)
10029 + dev_info(dev->dev, "regs: %p, irq %d\n", dev->regs, dev->irq);
10030 +
10031 + out:
10032 +- spin_unlock(&dev->lock);
10033 +-
10034 + if (retval)
10035 + gr_remove(pdev);
10036 +
10037 +diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
10038 +index df86ea308415..5af57afb4e56 100644
10039 +--- a/drivers/usb/host/xhci-pci.c
10040 ++++ b/drivers/usb/host/xhci-pci.c
10041 +@@ -53,6 +53,7 @@
10042 + #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
10043 + #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
10044 + #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
10045 ++#define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
10046 +
10047 + static const char hcd_name[] = "xhci_hcd";
10048 +
10049 +@@ -169,7 +170,8 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
10050 + pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
10051 + pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
10052 + pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
10053 +- pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
10054 ++ pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
10055 ++ pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
10056 + xhci->quirks |= XHCI_PME_STUCK_QUIRK;
10057 + }
10058 + if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
10059 +diff --git a/drivers/usb/storage/uas.c b/drivers/usb/storage/uas.c
10060 +index a7cc0bc68deb..b38d9f162123 100644
10061 +--- a/drivers/usb/storage/uas.c
10062 ++++ b/drivers/usb/storage/uas.c
10063 +@@ -46,6 +46,7 @@ struct uas_dev_info {
10064 + struct scsi_cmnd *cmnd[MAX_CMNDS];
10065 + spinlock_t lock;
10066 + struct work_struct work;
10067 ++ struct work_struct scan_work; /* for async scanning */
10068 + };
10069 +
10070 + enum {
10071 +@@ -115,6 +116,17 @@ out:
10072 + spin_unlock_irqrestore(&devinfo->lock, flags);
10073 + }
10074 +
10075 ++static void uas_scan_work(struct work_struct *work)
10076 ++{
10077 ++ struct uas_dev_info *devinfo =
10078 ++ container_of(work, struct uas_dev_info, scan_work);
10079 ++ struct Scsi_Host *shost = usb_get_intfdata(devinfo->intf);
10080 ++
10081 ++ dev_dbg(&devinfo->intf->dev, "starting scan\n");
10082 ++ scsi_scan_host(shost);
10083 ++ dev_dbg(&devinfo->intf->dev, "scan complete\n");
10084 ++}
10085 ++
10086 + static void uas_add_work(struct uas_cmd_info *cmdinfo)
10087 + {
10088 + struct scsi_pointer *scp = (void *)cmdinfo;
10089 +@@ -929,6 +941,7 @@ static int uas_probe(struct usb_interface *intf, const struct usb_device_id *id)
10090 + init_usb_anchor(&devinfo->data_urbs);
10091 + spin_lock_init(&devinfo->lock);
10092 + INIT_WORK(&devinfo->work, uas_do_work);
10093 ++ INIT_WORK(&devinfo->scan_work, uas_scan_work);
10094 +
10095 + result = uas_configure_endpoints(devinfo);
10096 + if (result)
10097 +@@ -945,7 +958,9 @@ static int uas_probe(struct usb_interface *intf, const struct usb_device_id *id)
10098 + if (result)
10099 + goto free_streams;
10100 +
10101 +- scsi_scan_host(shost);
10102 ++ /* Submit the delayed_work for SCSI-device scanning */
10103 ++ schedule_work(&devinfo->scan_work);
10104 ++
10105 + return result;
10106 +
10107 + free_streams:
10108 +@@ -1113,6 +1128,12 @@ static void uas_disconnect(struct usb_interface *intf)
10109 + usb_kill_anchored_urbs(&devinfo->data_urbs);
10110 + uas_zap_pending(devinfo, DID_NO_CONNECT);
10111 +
10112 ++ /*
10113 ++ * Prevent SCSI scanning (if it hasn't started yet)
10114 ++ * or wait for the SCSI-scanning routine to stop.
10115 ++ */
10116 ++ cancel_work_sync(&devinfo->scan_work);
10117 ++
10118 + scsi_remove_host(shost);
10119 + uas_free_streams(devinfo);
10120 + scsi_host_put(shost);
10121 +diff --git a/drivers/xen/preempt.c b/drivers/xen/preempt.c
10122 +index 08cb419eb4e6..5f6b77ea34fb 100644
10123 +--- a/drivers/xen/preempt.c
10124 ++++ b/drivers/xen/preempt.c
10125 +@@ -37,7 +37,9 @@ asmlinkage __visible void xen_maybe_preempt_hcall(void)
10126 + * cpu.
10127 + */
10128 + __this_cpu_write(xen_in_preemptible_hcall, false);
10129 +- _cond_resched();
10130 ++ local_irq_enable();
10131 ++ cond_resched();
10132 ++ local_irq_disable();
10133 + __this_cpu_write(xen_in_preemptible_hcall, true);
10134 + }
10135 + }
10136 +diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c
10137 +index 2fb533233e8e..656f0b768185 100644
10138 +--- a/fs/btrfs/disk-io.c
10139 ++++ b/fs/btrfs/disk-io.c
10140 +@@ -2972,6 +2972,7 @@ retry_root_backup:
10141 +
10142 + /* do not make disk changes in broken FS */
10143 + if (btrfs_super_log_root(disk_super) != 0) {
10144 ++ btrfs_info(fs_info, "start tree-log replay");
10145 + ret = btrfs_replay_log(fs_info, fs_devices);
10146 + if (ret) {
10147 + err = ret;
10148 +diff --git a/fs/btrfs/extent_map.c b/fs/btrfs/extent_map.c
10149 +index 84fb56d5c018..3818b65b0682 100644
10150 +--- a/fs/btrfs/extent_map.c
10151 ++++ b/fs/btrfs/extent_map.c
10152 +@@ -227,6 +227,17 @@ static void try_merge_map(struct extent_map_tree *tree, struct extent_map *em)
10153 + struct extent_map *merge = NULL;
10154 + struct rb_node *rb;
10155 +
10156 ++ /*
10157 ++ * We can't modify an extent map that is in the tree and that is being
10158 ++ * used by another task, as it can cause that other task to see it in
10159 ++ * inconsistent state during the merging. We always have 1 reference for
10160 ++ * the tree and 1 for this task (which is unpinning the extent map or
10161 ++ * clearing the logging flag), so anything > 2 means it's being used by
10162 ++ * other tasks too.
10163 ++ */
10164 ++ if (atomic_read(&em->refs) > 2)
10165 ++ return;
10166 ++
10167 + if (em->start != 0) {
10168 + rb = rb_prev(&em->rb_node);
10169 + if (rb)
10170 +diff --git a/fs/btrfs/ordered-data.c b/fs/btrfs/ordered-data.c
10171 +index 8c27292ea9ea..2eadc8f8c9ef 100644
10172 +--- a/fs/btrfs/ordered-data.c
10173 ++++ b/fs/btrfs/ordered-data.c
10174 +@@ -820,10 +820,15 @@ int btrfs_wait_ordered_range(struct inode *inode, u64 start, u64 len)
10175 + }
10176 + btrfs_start_ordered_extent(inode, ordered, 1);
10177 + end = ordered->file_offset;
10178 ++ /*
10179 ++ * If the ordered extent had an error save the error but don't
10180 ++ * exit without waiting first for all other ordered extents in
10181 ++ * the range to complete.
10182 ++ */
10183 + if (test_bit(BTRFS_ORDERED_IOERR, &ordered->flags))
10184 + ret = -EIO;
10185 + btrfs_put_ordered_extent(ordered);
10186 +- if (ret || end == 0 || end == start)
10187 ++ if (end == 0 || end == start)
10188 + break;
10189 + end--;
10190 + }
10191 +diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c
10192 +index df211bad255c..404051bf5cba 100644
10193 +--- a/fs/btrfs/super.c
10194 ++++ b/fs/btrfs/super.c
10195 +@@ -1702,6 +1702,8 @@ static int btrfs_remount(struct super_block *sb, int *flags, char *data)
10196 + }
10197 +
10198 + if (btrfs_super_log_root(fs_info->super_copy) != 0) {
10199 ++ btrfs_warn(fs_info,
10200 ++ "mount required to replay tree-log, cannot remount read-write");
10201 + ret = -EINVAL;
10202 + goto restore;
10203 + }
10204 +diff --git a/fs/ecryptfs/crypto.c b/fs/ecryptfs/crypto.c
10205 +index f246f1760ba2..83e9f6272bfb 100644
10206 +--- a/fs/ecryptfs/crypto.c
10207 ++++ b/fs/ecryptfs/crypto.c
10208 +@@ -346,8 +346,10 @@ static int crypt_scatterlist(struct ecryptfs_crypt_stat *crypt_stat,
10209 + struct extent_crypt_result ecr;
10210 + int rc = 0;
10211 +
10212 +- BUG_ON(!crypt_stat || !crypt_stat->tfm
10213 +- || !(crypt_stat->flags & ECRYPTFS_STRUCT_INITIALIZED));
10214 ++ if (!crypt_stat || !crypt_stat->tfm
10215 ++ || !(crypt_stat->flags & ECRYPTFS_STRUCT_INITIALIZED))
10216 ++ return -EINVAL;
10217 ++
10218 + if (unlikely(ecryptfs_verbosity > 0)) {
10219 + ecryptfs_printk(KERN_DEBUG, "Key size [%zd]; key:\n",
10220 + crypt_stat->key_size);
10221 +diff --git a/fs/ecryptfs/keystore.c b/fs/ecryptfs/keystore.c
10222 +index 20632ee51ae5..b272b778aa85 100644
10223 +--- a/fs/ecryptfs/keystore.c
10224 ++++ b/fs/ecryptfs/keystore.c
10225 +@@ -1280,7 +1280,7 @@ parse_tag_1_packet(struct ecryptfs_crypt_stat *crypt_stat,
10226 + printk(KERN_ERR "Enter w/ first byte != 0x%.2x\n",
10227 + ECRYPTFS_TAG_1_PACKET_TYPE);
10228 + rc = -EINVAL;
10229 +- goto out;
10230 ++ goto out_free;
10231 + }
10232 + /* Released: wipe_auth_tok_list called in ecryptfs_parse_packet_set or
10233 + * at end of function upon failure */
10234 +diff --git a/fs/ecryptfs/messaging.c b/fs/ecryptfs/messaging.c
10235 +index 4f457d5c4933..26464f9d9b76 100644
10236 +--- a/fs/ecryptfs/messaging.c
10237 ++++ b/fs/ecryptfs/messaging.c
10238 +@@ -397,6 +397,7 @@ int __init ecryptfs_init_messaging(void)
10239 + * ecryptfs_message_buf_len),
10240 + GFP_KERNEL);
10241 + if (!ecryptfs_msg_ctx_arr) {
10242 ++ kfree(ecryptfs_daemon_hash);
10243 + rc = -ENOMEM;
10244 + printk(KERN_ERR "%s: Failed to allocate memory\n", __func__);
10245 + goto out;
10246 +diff --git a/fs/ext4/dir.c b/fs/ext4/dir.c
10247 +index 209018f08dfd..7b626e942987 100644
10248 +--- a/fs/ext4/dir.c
10249 ++++ b/fs/ext4/dir.c
10250 +@@ -125,12 +125,14 @@ static int ext4_readdir(struct file *file, struct dir_context *ctx)
10251 + if (err != ERR_BAD_DX_DIR) {
10252 + return err;
10253 + }
10254 +- /*
10255 +- * We don't set the inode dirty flag since it's not
10256 +- * critical that it get flushed back to the disk.
10257 +- */
10258 +- ext4_clear_inode_flag(file_inode(file),
10259 +- EXT4_INODE_INDEX);
10260 ++ /* Can we just clear INDEX flag to ignore htree information? */
10261 ++ if (!ext4_has_metadata_csum(sb)) {
10262 ++ /*
10263 ++ * We don't set the inode dirty flag since it's not
10264 ++ * critical that it gets flushed back to the disk.
10265 ++ */
10266 ++ ext4_clear_inode_flag(inode, EXT4_INODE_INDEX);
10267 ++ }
10268 + }
10269 +
10270 + if (ext4_has_inline_data(inode)) {
10271 +diff --git a/fs/ext4/ext4.h b/fs/ext4/ext4.h
10272 +index b6e25d771eea..00ab96311487 100644
10273 +--- a/fs/ext4/ext4.h
10274 ++++ b/fs/ext4/ext4.h
10275 +@@ -2381,8 +2381,11 @@ int ext4_insert_dentry(struct inode *dir,
10276 + struct ext4_filename *fname);
10277 + static inline void ext4_update_dx_flag(struct inode *inode)
10278 + {
10279 +- if (!ext4_has_feature_dir_index(inode->i_sb))
10280 ++ if (!ext4_has_feature_dir_index(inode->i_sb)) {
10281 ++ /* ext4_iget() should have caught this... */
10282 ++ WARN_ON_ONCE(ext4_has_feature_metadata_csum(inode->i_sb));
10283 + ext4_clear_inode_flag(inode, EXT4_INODE_INDEX);
10284 ++ }
10285 + }
10286 + static unsigned char ext4_filetype_table[] = {
10287 + DT_UNKNOWN, DT_REG, DT_DIR, DT_CHR, DT_BLK, DT_FIFO, DT_SOCK, DT_LNK
10288 +@@ -2848,7 +2851,7 @@ static inline void ext4_update_i_disksize(struct inode *inode, loff_t newsize)
10289 + !mutex_is_locked(&inode->i_mutex));
10290 + down_write(&EXT4_I(inode)->i_data_sem);
10291 + if (newsize > EXT4_I(inode)->i_disksize)
10292 +- EXT4_I(inode)->i_disksize = newsize;
10293 ++ WRITE_ONCE(EXT4_I(inode)->i_disksize, newsize);
10294 + up_write(&EXT4_I(inode)->i_data_sem);
10295 + }
10296 +
10297 +diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c
10298 +index 271d8d9d0598..d1daac8d81f3 100644
10299 +--- a/fs/ext4/inode.c
10300 ++++ b/fs/ext4/inode.c
10301 +@@ -2320,7 +2320,7 @@ update_disksize:
10302 + * truncate are avoided by checking i_size under i_data_sem.
10303 + */
10304 + disksize = ((loff_t)mpd->first_page) << PAGE_CACHE_SHIFT;
10305 +- if (disksize > EXT4_I(inode)->i_disksize) {
10306 ++ if (disksize > READ_ONCE(EXT4_I(inode)->i_disksize)) {
10307 + int err2;
10308 + loff_t i_size;
10309 +
10310 +@@ -4325,6 +4325,18 @@ struct inode *ext4_iget(struct super_block *sb, unsigned long ino)
10311 + ret = -EFSCORRUPTED;
10312 + goto bad_inode;
10313 + }
10314 ++ /*
10315 ++ * If dir_index is not enabled but there's dir with INDEX flag set,
10316 ++ * we'd normally treat htree data as empty space. But with metadata
10317 ++ * checksumming that corrupts checksums so forbid that.
10318 ++ */
10319 ++ if (!ext4_has_feature_dir_index(sb) && ext4_has_metadata_csum(sb) &&
10320 ++ ext4_test_inode_flag(inode, EXT4_INODE_INDEX)) {
10321 ++ EXT4_ERROR_INODE(inode,
10322 ++ "iget: Dir with htree data on filesystem without dir_index feature.");
10323 ++ ret = -EFSCORRUPTED;
10324 ++ goto bad_inode;
10325 ++ }
10326 + ei->i_disksize = inode->i_size;
10327 + #ifdef CONFIG_QUOTA
10328 + ei->i_reserved_quota = 0;
10329 +diff --git a/fs/ext4/namei.c b/fs/ext4/namei.c
10330 +index 712bf332e394..49e0d97b2ee7 100644
10331 +--- a/fs/ext4/namei.c
10332 ++++ b/fs/ext4/namei.c
10333 +@@ -1418,6 +1418,7 @@ restart:
10334 + /*
10335 + * We deal with the read-ahead logic here.
10336 + */
10337 ++ cond_resched();
10338 + if (ra_ptr >= ra_max) {
10339 + /* Refill the readahead buffer */
10340 + ra_ptr = 0;
10341 +@@ -2121,6 +2122,13 @@ static int ext4_add_entry(handle_t *handle, struct dentry *dentry,
10342 + retval = ext4_dx_add_entry(handle, &fname, dentry, inode);
10343 + if (!retval || (retval != ERR_BAD_DX_DIR))
10344 + goto out;
10345 ++ /* Can we just ignore htree data? */
10346 ++ if (ext4_has_metadata_csum(sb)) {
10347 ++ EXT4_ERROR_INODE(dir,
10348 ++ "Directory has corrupted htree index.");
10349 ++ retval = -EFSCORRUPTED;
10350 ++ goto out;
10351 ++ }
10352 + ext4_clear_inode_flag(dir, EXT4_INODE_INDEX);
10353 + dx_fallback++;
10354 + ext4_mark_inode_dirty(handle, dir);
10355 +diff --git a/fs/jbd2/checkpoint.c b/fs/jbd2/checkpoint.c
10356 +index 4d5a5a4cc017..addb0784dd1c 100644
10357 +--- a/fs/jbd2/checkpoint.c
10358 ++++ b/fs/jbd2/checkpoint.c
10359 +@@ -168,7 +168,7 @@ void __jbd2_log_wait_for_space(journal_t *journal)
10360 + "journal space in %s\n", __func__,
10361 + journal->j_devname);
10362 + WARN_ON(1);
10363 +- jbd2_journal_abort(journal, 0);
10364 ++ jbd2_journal_abort(journal, -EIO);
10365 + }
10366 + write_lock(&journal->j_state_lock);
10367 + } else {
10368 +diff --git a/fs/jbd2/commit.c b/fs/jbd2/commit.c
10369 +index ebbd7d054cab..a7d12dd6d56e 100644
10370 +--- a/fs/jbd2/commit.c
10371 ++++ b/fs/jbd2/commit.c
10372 +@@ -797,7 +797,7 @@ start_journal_io:
10373 + err = journal_submit_commit_record(journal, commit_transaction,
10374 + &cbh, crc32_sum);
10375 + if (err)
10376 +- __jbd2_journal_abort_hard(journal);
10377 ++ jbd2_journal_abort(journal, err);
10378 + }
10379 +
10380 + blk_finish_plug(&plug);
10381 +@@ -890,7 +890,7 @@ start_journal_io:
10382 + err = journal_submit_commit_record(journal, commit_transaction,
10383 + &cbh, crc32_sum);
10384 + if (err)
10385 +- __jbd2_journal_abort_hard(journal);
10386 ++ jbd2_journal_abort(journal, err);
10387 + }
10388 + if (cbh)
10389 + err = journal_wait_on_commit_record(journal, cbh);
10390 +@@ -987,29 +987,33 @@ restart_loop:
10391 + * it. */
10392 +
10393 + /*
10394 +- * A buffer which has been freed while still being journaled by
10395 +- * a previous transaction.
10396 +- */
10397 +- if (buffer_freed(bh)) {
10398 ++ * A buffer which has been freed while still being journaled
10399 ++ * by a previous transaction, refile the buffer to BJ_Forget of
10400 ++ * the running transaction. If the just committed transaction
10401 ++ * contains "add to orphan" operation, we can completely
10402 ++ * invalidate the buffer now. We are rather through in that
10403 ++ * since the buffer may be still accessible when blocksize <
10404 ++ * pagesize and it is attached to the last partial page.
10405 ++ */
10406 ++ if (buffer_freed(bh) && !jh->b_next_transaction) {
10407 ++ struct address_space *mapping;
10408 ++
10409 ++ clear_buffer_freed(bh);
10410 ++ clear_buffer_jbddirty(bh);
10411 ++
10412 + /*
10413 +- * If the running transaction is the one containing
10414 +- * "add to orphan" operation (b_next_transaction !=
10415 +- * NULL), we have to wait for that transaction to
10416 +- * commit before we can really get rid of the buffer.
10417 +- * So just clear b_modified to not confuse transaction
10418 +- * credit accounting and refile the buffer to
10419 +- * BJ_Forget of the running transaction. If the just
10420 +- * committed transaction contains "add to orphan"
10421 +- * operation, we can completely invalidate the buffer
10422 +- * now. We are rather through in that since the
10423 +- * buffer may be still accessible when blocksize <
10424 +- * pagesize and it is attached to the last partial
10425 +- * page.
10426 ++ * Block device buffers need to stay mapped all the
10427 ++ * time, so it is enough to clear buffer_jbddirty and
10428 ++ * buffer_freed bits. For the file mapping buffers (i.e.
10429 ++ * journalled data) we need to unmap buffer and clear
10430 ++ * more bits. We also need to be careful about the check
10431 ++ * because the data page mapping can get cleared under
10432 ++ * out hands, which alse need not to clear more bits
10433 ++ * because the page and buffers will be freed and can
10434 ++ * never be reused once we are done with them.
10435 + */
10436 +- jh->b_modified = 0;
10437 +- if (!jh->b_next_transaction) {
10438 +- clear_buffer_freed(bh);
10439 +- clear_buffer_jbddirty(bh);
10440 ++ mapping = READ_ONCE(bh->b_page->mapping);
10441 ++ if (mapping && !sb_is_blkdev_sb(mapping->host->i_sb)) {
10442 + clear_buffer_mapped(bh);
10443 + clear_buffer_new(bh);
10444 + clear_buffer_req(bh);
10445 +diff --git a/fs/jbd2/journal.c b/fs/jbd2/journal.c
10446 +index 9398d1b70545..d62435897d0d 100644
10447 +--- a/fs/jbd2/journal.c
10448 ++++ b/fs/jbd2/journal.c
10449 +@@ -1656,6 +1656,11 @@ int jbd2_journal_load(journal_t *journal)
10450 + journal->j_devname);
10451 + return -EFSCORRUPTED;
10452 + }
10453 ++ /*
10454 ++ * clear JBD2_ABORT flag initialized in journal_init_common
10455 ++ * here to update log tail information with the newest seq.
10456 ++ */
10457 ++ journal->j_flags &= ~JBD2_ABORT;
10458 +
10459 + /* OK, we've finished with the dynamic journal bits:
10460 + * reinitialise the dynamic contents of the superblock in memory
10461 +@@ -1663,7 +1668,6 @@ int jbd2_journal_load(journal_t *journal)
10462 + if (journal_reset(journal))
10463 + goto recovery_error;
10464 +
10465 +- journal->j_flags &= ~JBD2_ABORT;
10466 + journal->j_flags |= JBD2_LOADED;
10467 + return 0;
10468 +
10469 +@@ -2082,12 +2086,10 @@ static void __journal_abort_soft (journal_t *journal, int errno)
10470 +
10471 + __jbd2_journal_abort_hard(journal);
10472 +
10473 +- if (errno) {
10474 +- jbd2_journal_update_sb_errno(journal);
10475 +- write_lock(&journal->j_state_lock);
10476 +- journal->j_flags |= JBD2_REC_ERR;
10477 +- write_unlock(&journal->j_state_lock);
10478 +- }
10479 ++ jbd2_journal_update_sb_errno(journal);
10480 ++ write_lock(&journal->j_state_lock);
10481 ++ journal->j_flags |= JBD2_REC_ERR;
10482 ++ write_unlock(&journal->j_state_lock);
10483 + }
10484 +
10485 + /**
10486 +@@ -2129,11 +2131,6 @@ static void __journal_abort_soft (journal_t *journal, int errno)
10487 + * failure to disk. ext3_error, for example, now uses this
10488 + * functionality.
10489 + *
10490 +- * Errors which originate from within the journaling layer will NOT
10491 +- * supply an errno; a null errno implies that absolutely no further
10492 +- * writes are done to the journal (unless there are any already in
10493 +- * progress).
10494 +- *
10495 + */
10496 +
10497 + void jbd2_journal_abort(journal_t *journal, int errno)
10498 +diff --git a/fs/jbd2/transaction.c b/fs/jbd2/transaction.c
10499 +index c34433432d47..6457023d8fac 100644
10500 +--- a/fs/jbd2/transaction.c
10501 ++++ b/fs/jbd2/transaction.c
10502 +@@ -2223,14 +2223,16 @@ static int journal_unmap_buffer(journal_t *journal, struct buffer_head *bh,
10503 + return -EBUSY;
10504 + }
10505 + /*
10506 +- * OK, buffer won't be reachable after truncate. We just set
10507 +- * j_next_transaction to the running transaction (if there is
10508 +- * one) and mark buffer as freed so that commit code knows it
10509 +- * should clear dirty bits when it is done with the buffer.
10510 ++ * OK, buffer won't be reachable after truncate. We just clear
10511 ++ * b_modified to not confuse transaction credit accounting, and
10512 ++ * set j_next_transaction to the running transaction (if there
10513 ++ * is one) and mark buffer as freed so that commit code knows
10514 ++ * it should clear dirty bits when it is done with the buffer.
10515 + */
10516 + set_buffer_freed(bh);
10517 + if (journal->j_running_transaction && buffer_jbddirty(bh))
10518 + jh->b_next_transaction = journal->j_running_transaction;
10519 ++ jh->b_modified = 0;
10520 + jbd2_journal_put_journal_head(jh);
10521 + spin_unlock(&journal->j_list_lock);
10522 + jbd_unlock_bh_state(bh);
10523 +diff --git a/fs/nfs/Kconfig b/fs/nfs/Kconfig
10524 +index b1daeafbea92..c3428767332c 100644
10525 +--- a/fs/nfs/Kconfig
10526 ++++ b/fs/nfs/Kconfig
10527 +@@ -89,7 +89,7 @@ config NFS_V4
10528 + config NFS_SWAP
10529 + bool "Provide swap over NFS support"
10530 + default n
10531 +- depends on NFS_FS
10532 ++ depends on NFS_FS && SWAP
10533 + select SUNRPC_SWAP
10534 + help
10535 + This option enables swapon to work on files located on NFS mounts.
10536 +diff --git a/fs/ocfs2/journal.h b/fs/ocfs2/journal.h
10537 +index f4cd3c3e9fb7..0a4d2cbf512f 100644
10538 +--- a/fs/ocfs2/journal.h
10539 ++++ b/fs/ocfs2/journal.h
10540 +@@ -637,9 +637,11 @@ static inline void ocfs2_update_inode_fsync_trans(handle_t *handle,
10541 + {
10542 + struct ocfs2_inode_info *oi = OCFS2_I(inode);
10543 +
10544 +- oi->i_sync_tid = handle->h_transaction->t_tid;
10545 +- if (datasync)
10546 +- oi->i_datasync_tid = handle->h_transaction->t_tid;
10547 ++ if (!is_handle_aborted(handle)) {
10548 ++ oi->i_sync_tid = handle->h_transaction->t_tid;
10549 ++ if (datasync)
10550 ++ oi->i_datasync_tid = handle->h_transaction->t_tid;
10551 ++ }
10552 + }
10553 +
10554 + #endif /* OCFS2_JOURNAL_H */
10555 +diff --git a/fs/reiserfs/stree.c b/fs/reiserfs/stree.c
10556 +index 24cbe013240f..e3a4cbad9620 100644
10557 +--- a/fs/reiserfs/stree.c
10558 ++++ b/fs/reiserfs/stree.c
10559 +@@ -2249,7 +2249,8 @@ error_out:
10560 + /* also releases the path */
10561 + unfix_nodes(&s_ins_balance);
10562 + #ifdef REISERQUOTA_DEBUG
10563 +- reiserfs_debug(th->t_super, REISERFS_DEBUG_CODE,
10564 ++ if (inode)
10565 ++ reiserfs_debug(th->t_super, REISERFS_DEBUG_CODE,
10566 + "reiserquota insert_item(): freeing %u id=%u type=%c",
10567 + quota_bytes, inode->i_uid, head2type(ih));
10568 + #endif
10569 +diff --git a/fs/reiserfs/super.c b/fs/reiserfs/super.c
10570 +index 519bf410e65b..f9796fd51531 100644
10571 +--- a/fs/reiserfs/super.c
10572 ++++ b/fs/reiserfs/super.c
10573 +@@ -1921,7 +1921,7 @@ static int reiserfs_fill_super(struct super_block *s, void *data, int silent)
10574 + if (!sbi->s_jdev) {
10575 + SWARN(silent, s, "", "Cannot allocate memory for "
10576 + "journal device name");
10577 +- goto error;
10578 ++ goto error_unlocked;
10579 + }
10580 + }
10581 + #ifdef CONFIG_QUOTA
10582 +diff --git a/fs/ubifs/file.c b/fs/ubifs/file.c
10583 +index b895af7d8d80..e6d0a7df341d 100644
10584 +--- a/fs/ubifs/file.c
10585 ++++ b/fs/ubifs/file.c
10586 +@@ -782,8 +782,9 @@ static int ubifs_do_bulk_read(struct ubifs_info *c, struct bu_info *bu,
10587 +
10588 + if (page_offset > end_index)
10589 + break;
10590 +- page = find_or_create_page(mapping, page_offset,
10591 +- GFP_NOFS | __GFP_COLD);
10592 ++ page = pagecache_get_page(mapping, page_offset,
10593 ++ FGP_LOCK|FGP_ACCESSED|FGP_CREAT|FGP_NOWAIT,
10594 ++ GFP_NOFS | __GFP_COLD);
10595 + if (!page)
10596 + break;
10597 + if (!PageUptodate(page))
10598 +diff --git a/include/linux/list_nulls.h b/include/linux/list_nulls.h
10599 +index 444d2b1313bd..703928e4fd42 100644
10600 +--- a/include/linux/list_nulls.h
10601 ++++ b/include/linux/list_nulls.h
10602 +@@ -66,10 +66,10 @@ static inline void hlist_nulls_add_head(struct hlist_nulls_node *n,
10603 + struct hlist_nulls_node *first = h->first;
10604 +
10605 + n->next = first;
10606 +- n->pprev = &h->first;
10607 ++ WRITE_ONCE(n->pprev, &h->first);
10608 + h->first = n;
10609 + if (!is_a_nulls(first))
10610 +- first->pprev = &n->next;
10611 ++ WRITE_ONCE(first->pprev, &n->next);
10612 + }
10613 +
10614 + static inline void __hlist_nulls_del(struct hlist_nulls_node *n)
10615 +@@ -79,13 +79,13 @@ static inline void __hlist_nulls_del(struct hlist_nulls_node *n)
10616 +
10617 + WRITE_ONCE(*pprev, next);
10618 + if (!is_a_nulls(next))
10619 +- next->pprev = pprev;
10620 ++ WRITE_ONCE(next->pprev, pprev);
10621 + }
10622 +
10623 + static inline void hlist_nulls_del(struct hlist_nulls_node *n)
10624 + {
10625 + __hlist_nulls_del(n);
10626 +- n->pprev = LIST_POISON2;
10627 ++ WRITE_ONCE(n->pprev, LIST_POISON2);
10628 + }
10629 +
10630 + /**
10631 +diff --git a/include/linux/rculist_nulls.h b/include/linux/rculist_nulls.h
10632 +index 1c33dd7da4a7..f35dc0a1d6eb 100644
10633 +--- a/include/linux/rculist_nulls.h
10634 ++++ b/include/linux/rculist_nulls.h
10635 +@@ -33,7 +33,7 @@ static inline void hlist_nulls_del_init_rcu(struct hlist_nulls_node *n)
10636 + {
10637 + if (!hlist_nulls_unhashed(n)) {
10638 + __hlist_nulls_del(n);
10639 +- n->pprev = NULL;
10640 ++ WRITE_ONCE(n->pprev, NULL);
10641 + }
10642 + }
10643 +
10644 +@@ -65,7 +65,7 @@ static inline void hlist_nulls_del_init_rcu(struct hlist_nulls_node *n)
10645 + static inline void hlist_nulls_del_rcu(struct hlist_nulls_node *n)
10646 + {
10647 + __hlist_nulls_del(n);
10648 +- n->pprev = LIST_POISON2;
10649 ++ WRITE_ONCE(n->pprev, LIST_POISON2);
10650 + }
10651 +
10652 + /**
10653 +@@ -93,10 +93,10 @@ static inline void hlist_nulls_add_head_rcu(struct hlist_nulls_node *n,
10654 + struct hlist_nulls_node *first = h->first;
10655 +
10656 + n->next = first;
10657 +- n->pprev = &h->first;
10658 ++ WRITE_ONCE(n->pprev, &h->first);
10659 + rcu_assign_pointer(hlist_nulls_first_rcu(h), n);
10660 + if (!is_a_nulls(first))
10661 +- first->pprev = &n->next;
10662 ++ WRITE_ONCE(first->pprev, &n->next);
10663 + }
10664 + /**
10665 + * hlist_nulls_for_each_entry_rcu - iterate over rcu list of given type
10666 +diff --git a/include/scsi/iscsi_proto.h b/include/scsi/iscsi_proto.h
10667 +index 1a2ae0862e23..c1260d80ef30 100644
10668 +--- a/include/scsi/iscsi_proto.h
10669 ++++ b/include/scsi/iscsi_proto.h
10670 +@@ -638,7 +638,6 @@ struct iscsi_reject {
10671 + #define ISCSI_REASON_BOOKMARK_INVALID 9
10672 + #define ISCSI_REASON_BOOKMARK_NO_RESOURCES 10
10673 + #define ISCSI_REASON_NEGOTIATION_RESET 11
10674 +-#define ISCSI_REASON_WAITING_FOR_LOGOUT 12
10675 +
10676 + /* Max. number of Key=Value pairs in a text message */
10677 + #define MAX_KEY_VALUE_PAIRS 8192
10678 +diff --git a/include/sound/rawmidi.h b/include/sound/rawmidi.h
10679 +index 3b91ad5d5115..27b2c653d2f0 100644
10680 +--- a/include/sound/rawmidi.h
10681 ++++ b/include/sound/rawmidi.h
10682 +@@ -92,9 +92,9 @@ struct snd_rawmidi_substream {
10683 + struct list_head list; /* list of all substream for given stream */
10684 + int stream; /* direction */
10685 + int number; /* substream number */
10686 +- unsigned int opened: 1, /* open flag */
10687 +- append: 1, /* append flag (merge more streams) */
10688 +- active_sensing: 1; /* send active sensing when close */
10689 ++ bool opened; /* open flag */
10690 ++ bool append; /* append flag (merge more streams) */
10691 ++ bool active_sensing; /* send active sensing when close */
10692 + int use_count; /* use counter (for output) */
10693 + size_t bytes;
10694 + struct snd_rawmidi *rmidi;
10695 +diff --git a/ipc/sem.c b/ipc/sem.c
10696 +index 9862c3d1c26d..9963ed351b43 100644
10697 +--- a/ipc/sem.c
10698 ++++ b/ipc/sem.c
10699 +@@ -2151,11 +2151,9 @@ void exit_sem(struct task_struct *tsk)
10700 + ipc_assert_locked_object(&sma->sem_perm);
10701 + list_del(&un->list_id);
10702 +
10703 +- /* we are the last process using this ulp, acquiring ulp->lock
10704 +- * isn't required. Besides that, we are also protected against
10705 +- * IPC_RMID as we hold sma->sem_perm lock now
10706 +- */
10707 ++ spin_lock(&ulp->lock);
10708 + list_del_rcu(&un->list_proc);
10709 ++ spin_unlock(&ulp->lock);
10710 +
10711 + /* perform adjustments registered in un */
10712 + for (i = 0; i < sma->sem_nsems; i++) {
10713 +diff --git a/kernel/padata.c b/kernel/padata.c
10714 +index 282b489a286d..0d7ec5fd520b 100644
10715 +--- a/kernel/padata.c
10716 ++++ b/kernel/padata.c
10717 +@@ -33,6 +33,8 @@
10718 +
10719 + #define MAX_OBJ_NUM 1000
10720 +
10721 ++static void padata_free_pd(struct parallel_data *pd);
10722 ++
10723 + static int padata_index_to_cpu(struct parallel_data *pd, int cpu_index)
10724 + {
10725 + int cpu, target_cpu;
10726 +@@ -300,6 +302,7 @@ static void padata_serial_worker(struct work_struct *serial_work)
10727 + struct padata_serial_queue *squeue;
10728 + struct parallel_data *pd;
10729 + LIST_HEAD(local_list);
10730 ++ int cnt;
10731 +
10732 + local_bh_disable();
10733 + squeue = container_of(serial_work, struct padata_serial_queue, work);
10734 +@@ -309,6 +312,8 @@ static void padata_serial_worker(struct work_struct *serial_work)
10735 + list_replace_init(&squeue->serial.list, &local_list);
10736 + spin_unlock(&squeue->serial.lock);
10737 +
10738 ++ cnt = 0;
10739 ++
10740 + while (!list_empty(&local_list)) {
10741 + struct padata_priv *padata;
10742 +
10743 +@@ -318,9 +323,12 @@ static void padata_serial_worker(struct work_struct *serial_work)
10744 + list_del_init(&padata->list);
10745 +
10746 + padata->serial(padata);
10747 +- atomic_dec(&pd->refcnt);
10748 ++ cnt++;
10749 + }
10750 + local_bh_enable();
10751 ++
10752 ++ if (atomic_sub_and_test(cnt, &pd->refcnt))
10753 ++ padata_free_pd(pd);
10754 + }
10755 +
10756 + /**
10757 +@@ -443,7 +451,7 @@ static struct parallel_data *padata_alloc_pd(struct padata_instance *pinst,
10758 + setup_timer(&pd->timer, padata_reorder_timer, (unsigned long)pd);
10759 + atomic_set(&pd->seq_nr, -1);
10760 + atomic_set(&pd->reorder_objects, 0);
10761 +- atomic_set(&pd->refcnt, 0);
10762 ++ atomic_set(&pd->refcnt, 1);
10763 + pd->pinst = pinst;
10764 + spin_lock_init(&pd->lock);
10765 +
10766 +@@ -468,31 +476,6 @@ static void padata_free_pd(struct parallel_data *pd)
10767 + kfree(pd);
10768 + }
10769 +
10770 +-/* Flush all objects out of the padata queues. */
10771 +-static void padata_flush_queues(struct parallel_data *pd)
10772 +-{
10773 +- int cpu;
10774 +- struct padata_parallel_queue *pqueue;
10775 +- struct padata_serial_queue *squeue;
10776 +-
10777 +- for_each_cpu(cpu, pd->cpumask.pcpu) {
10778 +- pqueue = per_cpu_ptr(pd->pqueue, cpu);
10779 +- flush_work(&pqueue->work);
10780 +- }
10781 +-
10782 +- del_timer_sync(&pd->timer);
10783 +-
10784 +- if (atomic_read(&pd->reorder_objects))
10785 +- padata_reorder(pd);
10786 +-
10787 +- for_each_cpu(cpu, pd->cpumask.cbcpu) {
10788 +- squeue = per_cpu_ptr(pd->squeue, cpu);
10789 +- flush_work(&squeue->work);
10790 +- }
10791 +-
10792 +- BUG_ON(atomic_read(&pd->refcnt) != 0);
10793 +-}
10794 +-
10795 + static void __padata_start(struct padata_instance *pinst)
10796 + {
10797 + pinst->flags |= PADATA_INIT;
10798 +@@ -506,10 +489,6 @@ static void __padata_stop(struct padata_instance *pinst)
10799 + pinst->flags &= ~PADATA_INIT;
10800 +
10801 + synchronize_rcu();
10802 +-
10803 +- get_online_cpus();
10804 +- padata_flush_queues(pinst->pd);
10805 +- put_online_cpus();
10806 + }
10807 +
10808 + /* Replace the internal control structure with a new one. */
10809 +@@ -530,8 +509,8 @@ static void padata_replace(struct padata_instance *pinst,
10810 + if (!cpumask_equal(pd_old->cpumask.cbcpu, pd_new->cpumask.cbcpu))
10811 + notification_mask |= PADATA_CPU_SERIAL;
10812 +
10813 +- padata_flush_queues(pd_old);
10814 +- padata_free_pd(pd_old);
10815 ++ if (atomic_dec_and_test(&pd_old->refcnt))
10816 ++ padata_free_pd(pd_old);
10817 +
10818 + if (notification_mask)
10819 + blocking_notifier_call_chain(&pinst->cpumask_change_notifier,
10820 +diff --git a/kernel/trace/trace_events_trigger.c b/kernel/trace/trace_events_trigger.c
10821 +index 8be66a2b0cac..6524920c6ebc 100644
10822 +--- a/kernel/trace/trace_events_trigger.c
10823 ++++ b/kernel/trace/trace_events_trigger.c
10824 +@@ -121,9 +121,10 @@ static void *trigger_next(struct seq_file *m, void *t, loff_t *pos)
10825 + {
10826 + struct trace_event_file *event_file = event_file_data(m->private);
10827 +
10828 +- if (t == SHOW_AVAILABLE_TRIGGERS)
10829 ++ if (t == SHOW_AVAILABLE_TRIGGERS) {
10830 ++ (*pos)++;
10831 + return NULL;
10832 +-
10833 ++ }
10834 + return seq_list_next(t, &event_file->triggers, pos);
10835 + }
10836 +
10837 +diff --git a/kernel/trace/trace_stat.c b/kernel/trace/trace_stat.c
10838 +index 6cf935316769..a2081a7f0c2c 100644
10839 +--- a/kernel/trace/trace_stat.c
10840 ++++ b/kernel/trace/trace_stat.c
10841 +@@ -302,7 +302,7 @@ static int init_stat_file(struct stat_session *session)
10842 + int register_stat_tracer(struct tracer_stat *trace)
10843 + {
10844 + struct stat_session *session, *node;
10845 +- int ret;
10846 ++ int ret = -EINVAL;
10847 +
10848 + if (!trace)
10849 + return -EINVAL;
10850 +@@ -313,17 +313,15 @@ int register_stat_tracer(struct tracer_stat *trace)
10851 + /* Already registered? */
10852 + mutex_lock(&all_stat_sessions_mutex);
10853 + list_for_each_entry(node, &all_stat_sessions, session_list) {
10854 +- if (node->ts == trace) {
10855 +- mutex_unlock(&all_stat_sessions_mutex);
10856 +- return -EINVAL;
10857 +- }
10858 ++ if (node->ts == trace)
10859 ++ goto out;
10860 + }
10861 +- mutex_unlock(&all_stat_sessions_mutex);
10862 +
10863 ++ ret = -ENOMEM;
10864 + /* Init the session */
10865 + session = kzalloc(sizeof(*session), GFP_KERNEL);
10866 + if (!session)
10867 +- return -ENOMEM;
10868 ++ goto out;
10869 +
10870 + session->ts = trace;
10871 + INIT_LIST_HEAD(&session->session_list);
10872 +@@ -332,15 +330,16 @@ int register_stat_tracer(struct tracer_stat *trace)
10873 + ret = init_stat_file(session);
10874 + if (ret) {
10875 + destroy_session(session);
10876 +- return ret;
10877 ++ goto out;
10878 + }
10879 +
10880 ++ ret = 0;
10881 + /* Register */
10882 +- mutex_lock(&all_stat_sessions_mutex);
10883 + list_add_tail(&session->session_list, &all_stat_sessions);
10884 ++ out:
10885 + mutex_unlock(&all_stat_sessions_mutex);
10886 +
10887 +- return 0;
10888 ++ return ret;
10889 + }
10890 +
10891 + void unregister_stat_tracer(struct tracer_stat *trace)
10892 +diff --git a/lib/scatterlist.c b/lib/scatterlist.c
10893 +index 0b86b7992f93..1875c09eede9 100644
10894 +--- a/lib/scatterlist.c
10895 ++++ b/lib/scatterlist.c
10896 +@@ -317,7 +317,7 @@ int __sg_alloc_table(struct sg_table *table, unsigned int nents,
10897 + if (prv)
10898 + table->nents = ++table->orig_nents;
10899 +
10900 +- return -ENOMEM;
10901 ++ return -ENOMEM;
10902 + }
10903 +
10904 + sg_init_table(sg, alloc_size);
10905 +diff --git a/net/netfilter/xt_bpf.c b/net/netfilter/xt_bpf.c
10906 +index dffee9d47ec4..7b993f25aab9 100644
10907 +--- a/net/netfilter/xt_bpf.c
10908 ++++ b/net/netfilter/xt_bpf.c
10909 +@@ -25,6 +25,9 @@ static int bpf_mt_check(const struct xt_mtchk_param *par)
10910 + struct xt_bpf_info *info = par->matchinfo;
10911 + struct sock_fprog_kern program;
10912 +
10913 ++ if (info->bpf_program_num_elem > XT_BPF_MAX_NUM_INSTR)
10914 ++ return -EINVAL;
10915 ++
10916 + program.len = info->bpf_program_num_elem;
10917 + program.filter = info->bpf_program;
10918 +
10919 +diff --git a/scripts/kconfig/confdata.c b/scripts/kconfig/confdata.c
10920 +index 138d7f100f7e..4216940e875d 100644
10921 +--- a/scripts/kconfig/confdata.c
10922 ++++ b/scripts/kconfig/confdata.c
10923 +@@ -1236,7 +1236,7 @@ bool conf_set_all_new_symbols(enum conf_def_mode mode)
10924 +
10925 + sym_calc_value(csym);
10926 + if (mode == def_random)
10927 +- has_changed = randomize_choice_values(csym);
10928 ++ has_changed |= randomize_choice_values(csym);
10929 + else {
10930 + set_all_choice_values(csym);
10931 + has_changed = true;
10932 +diff --git a/security/selinux/avc.c b/security/selinux/avc.c
10933 +index 52f3c550abcc..f3c473791b69 100644
10934 +--- a/security/selinux/avc.c
10935 ++++ b/security/selinux/avc.c
10936 +@@ -865,7 +865,7 @@ static int avc_update_node(u32 event, u32 perms, u8 driver, u8 xperm, u32 ssid,
10937 + if (orig->ae.xp_node) {
10938 + rc = avc_xperms_populate(node, orig->ae.xp_node);
10939 + if (rc) {
10940 +- kmem_cache_free(avc_node_cachep, node);
10941 ++ avc_node_kill(node);
10942 + goto out_unlock;
10943 + }
10944 + }
10945 +diff --git a/sound/core/seq/seq_clientmgr.c b/sound/core/seq/seq_clientmgr.c
10946 +index 331a2b00e53f..4c31db1246c3 100644
10947 +--- a/sound/core/seq/seq_clientmgr.c
10948 ++++ b/sound/core/seq/seq_clientmgr.c
10949 +@@ -577,7 +577,7 @@ static int update_timestamp_of_queue(struct snd_seq_event *event,
10950 + event->queue = queue;
10951 + event->flags &= ~SNDRV_SEQ_TIME_STAMP_MASK;
10952 + if (real_time) {
10953 +- event->time.time = snd_seq_timer_get_cur_time(q->timer);
10954 ++ event->time.time = snd_seq_timer_get_cur_time(q->timer, true);
10955 + event->flags |= SNDRV_SEQ_TIME_STAMP_REAL;
10956 + } else {
10957 + event->time.tick = snd_seq_timer_get_cur_tick(q->timer);
10958 +@@ -1694,7 +1694,7 @@ static int snd_seq_ioctl_get_queue_status(struct snd_seq_client *client,
10959 + tmr = queue->timer;
10960 + status.events = queue->tickq->cells + queue->timeq->cells;
10961 +
10962 +- status.time = snd_seq_timer_get_cur_time(tmr);
10963 ++ status.time = snd_seq_timer_get_cur_time(tmr, true);
10964 + status.tick = snd_seq_timer_get_cur_tick(tmr);
10965 +
10966 + status.running = tmr->running;
10967 +diff --git a/sound/core/seq/seq_queue.c b/sound/core/seq/seq_queue.c
10968 +index 1a6dc4ff44a6..ea1aa0796276 100644
10969 +--- a/sound/core/seq/seq_queue.c
10970 ++++ b/sound/core/seq/seq_queue.c
10971 +@@ -261,6 +261,8 @@ void snd_seq_check_queue(struct snd_seq_queue *q, int atomic, int hop)
10972 + {
10973 + unsigned long flags;
10974 + struct snd_seq_event_cell *cell;
10975 ++ snd_seq_tick_time_t cur_tick;
10976 ++ snd_seq_real_time_t cur_time;
10977 +
10978 + if (q == NULL)
10979 + return;
10980 +@@ -277,17 +279,18 @@ void snd_seq_check_queue(struct snd_seq_queue *q, int atomic, int hop)
10981 +
10982 + __again:
10983 + /* Process tick queue... */
10984 ++ cur_tick = snd_seq_timer_get_cur_tick(q->timer);
10985 + for (;;) {
10986 +- cell = snd_seq_prioq_cell_out(q->tickq,
10987 +- &q->timer->tick.cur_tick);
10988 ++ cell = snd_seq_prioq_cell_out(q->tickq, &cur_tick);
10989 + if (!cell)
10990 + break;
10991 + snd_seq_dispatch_event(cell, atomic, hop);
10992 + }
10993 +
10994 + /* Process time queue... */
10995 ++ cur_time = snd_seq_timer_get_cur_time(q->timer, false);
10996 + for (;;) {
10997 +- cell = snd_seq_prioq_cell_out(q->timeq, &q->timer->cur_time);
10998 ++ cell = snd_seq_prioq_cell_out(q->timeq, &cur_time);
10999 + if (!cell)
11000 + break;
11001 + snd_seq_dispatch_event(cell, atomic, hop);
11002 +@@ -415,6 +418,7 @@ int snd_seq_queue_check_access(int queueid, int client)
11003 + int snd_seq_queue_set_owner(int queueid, int client, int locked)
11004 + {
11005 + struct snd_seq_queue *q = queueptr(queueid);
11006 ++ unsigned long flags;
11007 +
11008 + if (q == NULL)
11009 + return -EINVAL;
11010 +@@ -424,8 +428,10 @@ int snd_seq_queue_set_owner(int queueid, int client, int locked)
11011 + return -EPERM;
11012 + }
11013 +
11014 ++ spin_lock_irqsave(&q->owner_lock, flags);
11015 + q->locked = locked ? 1 : 0;
11016 + q->owner = client;
11017 ++ spin_unlock_irqrestore(&q->owner_lock, flags);
11018 + queue_access_unlock(q);
11019 + queuefree(q);
11020 +
11021 +@@ -564,15 +570,17 @@ void snd_seq_queue_client_termination(int client)
11022 + unsigned long flags;
11023 + int i;
11024 + struct snd_seq_queue *q;
11025 ++ bool matched;
11026 +
11027 + for (i = 0; i < SNDRV_SEQ_MAX_QUEUES; i++) {
11028 + if ((q = queueptr(i)) == NULL)
11029 + continue;
11030 + spin_lock_irqsave(&q->owner_lock, flags);
11031 +- if (q->owner == client)
11032 ++ matched = (q->owner == client);
11033 ++ if (matched)
11034 + q->klocked = 1;
11035 + spin_unlock_irqrestore(&q->owner_lock, flags);
11036 +- if (q->owner == client) {
11037 ++ if (matched) {
11038 + if (q->timer->running)
11039 + snd_seq_timer_stop(q->timer);
11040 + snd_seq_timer_reset(q->timer);
11041 +@@ -764,6 +772,8 @@ void snd_seq_info_queues_read(struct snd_info_entry *entry,
11042 + int i, bpm;
11043 + struct snd_seq_queue *q;
11044 + struct snd_seq_timer *tmr;
11045 ++ bool locked;
11046 ++ int owner;
11047 +
11048 + for (i = 0; i < SNDRV_SEQ_MAX_QUEUES; i++) {
11049 + if ((q = queueptr(i)) == NULL)
11050 +@@ -775,9 +785,14 @@ void snd_seq_info_queues_read(struct snd_info_entry *entry,
11051 + else
11052 + bpm = 0;
11053 +
11054 ++ spin_lock_irq(&q->owner_lock);
11055 ++ locked = q->locked;
11056 ++ owner = q->owner;
11057 ++ spin_unlock_irq(&q->owner_lock);
11058 ++
11059 + snd_iprintf(buffer, "queue %d: [%s]\n", q->queue, q->name);
11060 +- snd_iprintf(buffer, "owned by client : %d\n", q->owner);
11061 +- snd_iprintf(buffer, "lock status : %s\n", q->locked ? "Locked" : "Free");
11062 ++ snd_iprintf(buffer, "owned by client : %d\n", owner);
11063 ++ snd_iprintf(buffer, "lock status : %s\n", locked ? "Locked" : "Free");
11064 + snd_iprintf(buffer, "queued time events : %d\n", snd_seq_prioq_avail(q->timeq));
11065 + snd_iprintf(buffer, "queued tick events : %d\n", snd_seq_prioq_avail(q->tickq));
11066 + snd_iprintf(buffer, "timer state : %s\n", tmr->running ? "Running" : "Stopped");
11067 +diff --git a/sound/core/seq/seq_timer.c b/sound/core/seq/seq_timer.c
11068 +index c526201fd0df..adc820f874ee 100644
11069 +--- a/sound/core/seq/seq_timer.c
11070 ++++ b/sound/core/seq/seq_timer.c
11071 +@@ -436,14 +436,15 @@ int snd_seq_timer_continue(struct snd_seq_timer *tmr)
11072 + }
11073 +
11074 + /* return current 'real' time. use timeofday() to get better granularity. */
11075 +-snd_seq_real_time_t snd_seq_timer_get_cur_time(struct snd_seq_timer *tmr)
11076 ++snd_seq_real_time_t snd_seq_timer_get_cur_time(struct snd_seq_timer *tmr,
11077 ++ bool adjust_ktime)
11078 + {
11079 + snd_seq_real_time_t cur_time;
11080 + unsigned long flags;
11081 +
11082 + spin_lock_irqsave(&tmr->lock, flags);
11083 + cur_time = tmr->cur_time;
11084 +- if (tmr->running) {
11085 ++ if (adjust_ktime && tmr->running) {
11086 + struct timeval tm;
11087 + int usec;
11088 + do_gettimeofday(&tm);
11089 +@@ -465,7 +466,13 @@ snd_seq_real_time_t snd_seq_timer_get_cur_time(struct snd_seq_timer *tmr)
11090 + high PPQ values) */
11091 + snd_seq_tick_time_t snd_seq_timer_get_cur_tick(struct snd_seq_timer *tmr)
11092 + {
11093 +- return tmr->tick.cur_tick;
11094 ++ snd_seq_tick_time_t cur_tick;
11095 ++ unsigned long flags;
11096 ++
11097 ++ spin_lock_irqsave(&tmr->lock, flags);
11098 ++ cur_tick = tmr->tick.cur_tick;
11099 ++ spin_unlock_irqrestore(&tmr->lock, flags);
11100 ++ return cur_tick;
11101 + }
11102 +
11103 +
11104 +diff --git a/sound/core/seq/seq_timer.h b/sound/core/seq/seq_timer.h
11105 +index 88dfb71805ae..6221a43c307a 100644
11106 +--- a/sound/core/seq/seq_timer.h
11107 ++++ b/sound/core/seq/seq_timer.h
11108 +@@ -135,7 +135,8 @@ int snd_seq_timer_set_ppq(struct snd_seq_timer *tmr, int ppq);
11109 + int snd_seq_timer_set_position_tick(struct snd_seq_timer *tmr, snd_seq_tick_time_t position);
11110 + int snd_seq_timer_set_position_time(struct snd_seq_timer *tmr, snd_seq_real_time_t position);
11111 + int snd_seq_timer_set_skew(struct snd_seq_timer *tmr, unsigned int skew, unsigned int base);
11112 +-snd_seq_real_time_t snd_seq_timer_get_cur_time(struct snd_seq_timer *tmr);
11113 ++snd_seq_real_time_t snd_seq_timer_get_cur_time(struct snd_seq_timer *tmr,
11114 ++ bool adjust_ktime);
11115 + snd_seq_tick_time_t snd_seq_timer_get_cur_tick(struct snd_seq_timer *tmr);
11116 +
11117 + extern int seq_default_timer_class;
11118 +diff --git a/sound/pci/hda/hda_codec.c b/sound/pci/hda/hda_codec.c
11119 +index ad0b23a21bc8..16664b07b553 100644
11120 +--- a/sound/pci/hda/hda_codec.c
11121 ++++ b/sound/pci/hda/hda_codec.c
11122 +@@ -4098,7 +4098,7 @@ void snd_print_pcm_bits(int pcm, char *buf, int buflen)
11123 +
11124 + for (i = 0, j = 0; i < ARRAY_SIZE(bits); i++)
11125 + if (pcm & (AC_SUPPCM_BITS_8 << i))
11126 +- j += snprintf(buf + j, buflen - j, " %d", bits[i]);
11127 ++ j += scnprintf(buf + j, buflen - j, " %d", bits[i]);
11128 +
11129 + buf[j] = '\0'; /* necessary when j == 0 */
11130 + }
11131 +diff --git a/sound/pci/hda/hda_eld.c b/sound/pci/hda/hda_eld.c
11132 +index 563984dd2562..d469c76b5e92 100644
11133 +--- a/sound/pci/hda/hda_eld.c
11134 ++++ b/sound/pci/hda/hda_eld.c
11135 +@@ -385,7 +385,7 @@ static void hdmi_print_pcm_rates(int pcm, char *buf, int buflen)
11136 +
11137 + for (i = 0, j = 0; i < ARRAY_SIZE(alsa_rates); i++)
11138 + if (pcm & (1 << i))
11139 +- j += snprintf(buf + j, buflen - j, " %d",
11140 ++ j += scnprintf(buf + j, buflen - j, " %d",
11141 + alsa_rates[i]);
11142 +
11143 + buf[j] = '\0'; /* necessary when j == 0 */
11144 +diff --git a/sound/pci/hda/hda_sysfs.c b/sound/pci/hda/hda_sysfs.c
11145 +index 9739fce9e032..f3ac19d33bd4 100644
11146 +--- a/sound/pci/hda/hda_sysfs.c
11147 ++++ b/sound/pci/hda/hda_sysfs.c
11148 +@@ -221,7 +221,7 @@ static ssize_t init_verbs_show(struct device *dev,
11149 + mutex_lock(&codec->user_mutex);
11150 + for (i = 0; i < codec->init_verbs.used; i++) {
11151 + struct hda_verb *v = snd_array_elem(&codec->init_verbs, i);
11152 +- len += snprintf(buf + len, PAGE_SIZE - len,
11153 ++ len += scnprintf(buf + len, PAGE_SIZE - len,
11154 + "0x%02x 0x%03x 0x%04x\n",
11155 + v->nid, v->verb, v->param);
11156 + }
11157 +@@ -271,7 +271,7 @@ static ssize_t hints_show(struct device *dev,
11158 + mutex_lock(&codec->user_mutex);
11159 + for (i = 0; i < codec->hints.used; i++) {
11160 + struct hda_hint *hint = snd_array_elem(&codec->hints, i);
11161 +- len += snprintf(buf + len, PAGE_SIZE - len,
11162 ++ len += scnprintf(buf + len, PAGE_SIZE - len,
11163 + "%s = %s\n", hint->key, hint->val);
11164 + }
11165 + mutex_unlock(&codec->user_mutex);
11166 +diff --git a/sound/pci/hda/patch_conexant.c b/sound/pci/hda/patch_conexant.c
11167 +index 05e745e2f427..3150ddfbdb25 100644
11168 +--- a/sound/pci/hda/patch_conexant.c
11169 ++++ b/sound/pci/hda/patch_conexant.c
11170 +@@ -866,6 +866,7 @@ static const struct snd_pci_quirk cxt5066_fixups[] = {
11171 + SND_PCI_QUIRK(0x17aa, 0x215f, "Lenovo T510", CXT_PINCFG_LENOVO_TP410),
11172 + SND_PCI_QUIRK(0x17aa, 0x21ce, "Lenovo T420", CXT_PINCFG_LENOVO_TP410),
11173 + SND_PCI_QUIRK(0x17aa, 0x21cf, "Lenovo T520", CXT_PINCFG_LENOVO_TP410),
11174 ++ SND_PCI_QUIRK(0x17aa, 0x21d2, "Lenovo T420s", CXT_PINCFG_LENOVO_TP410),
11175 + SND_PCI_QUIRK(0x17aa, 0x21da, "Lenovo X220", CXT_PINCFG_LENOVO_TP410),
11176 + SND_PCI_QUIRK(0x17aa, 0x21db, "Lenovo X220-tablet", CXT_PINCFG_LENOVO_TP410),
11177 + SND_PCI_QUIRK(0x17aa, 0x38af, "Lenovo IdeaPad Z560", CXT_FIXUP_MUTE_LED_EAPD),
11178 +diff --git a/sound/sh/aica.c b/sound/sh/aica.c
11179 +index ad3d9ae38034..dd601b39f69e 100644
11180 +--- a/sound/sh/aica.c
11181 ++++ b/sound/sh/aica.c
11182 +@@ -120,10 +120,10 @@ static void spu_memset(u32 toi, u32 what, int length)
11183 + }
11184 +
11185 + /* spu_memload - write to SPU address space */
11186 +-static void spu_memload(u32 toi, void *from, int length)
11187 ++static void spu_memload(u32 toi, const void *from, int length)
11188 + {
11189 + unsigned long flags;
11190 +- u32 *froml = from;
11191 ++ const u32 *froml = from;
11192 + u32 __iomem *to = (u32 __iomem *) (SPU_MEMORY_BASE + toi);
11193 + int i;
11194 + u32 val;
11195 +diff --git a/sound/soc/atmel/Kconfig b/sound/soc/atmel/Kconfig
11196 +index 2d30464b81ce..d7b471c69f4f 100644
11197 +--- a/sound/soc/atmel/Kconfig
11198 ++++ b/sound/soc/atmel/Kconfig
11199 +@@ -24,6 +24,8 @@ config SND_ATMEL_SOC_DMA
11200 +
11201 + config SND_ATMEL_SOC_SSC_DMA
11202 + tristate
11203 ++ select SND_ATMEL_SOC_DMA
11204 ++ select SND_ATMEL_SOC_PDC
11205 +
11206 + config SND_ATMEL_SOC_SSC
11207 + tristate
11208 +diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c
11209 +index 5e50386c8ebb..b7a7bf0e566c 100644
11210 +--- a/sound/usb/quirks.c
11211 ++++ b/sound/usb/quirks.c
11212 +@@ -1150,6 +1150,7 @@ bool snd_usb_get_sample_rate_quirk(struct snd_usb_audio *chip)
11213 + case USB_ID(0x1de7, 0x0014): /* Phoenix Audio TMX320 */
11214 + case USB_ID(0x1de7, 0x0114): /* Phoenix Audio MT202pcs */
11215 + case USB_ID(0x21B4, 0x0081): /* AudioQuest DragonFly */
11216 ++ case USB_ID(0x2912, 0x30c8): /* Audioengine D1 */
11217 + return true;
11218 + }
11219 + return false;
11220 +diff --git a/sound/usb/usx2y/usX2Yhwdep.c b/sound/usb/usx2y/usX2Yhwdep.c
11221 +index 0b34dbc8f302..7dcb33d3886b 100644
11222 +--- a/sound/usb/usx2y/usX2Yhwdep.c
11223 ++++ b/sound/usb/usx2y/usX2Yhwdep.c
11224 +@@ -132,7 +132,7 @@ static int snd_usX2Y_hwdep_dsp_status(struct snd_hwdep *hw,
11225 + info->num_dsps = 2; // 0: Prepad Data, 1: FPGA Code
11226 + if (us428->chip_status & USX2Y_STAT_CHIP_INIT)
11227 + info->chip_ready = 1;
11228 +- info->version = USX2Y_DRIVER_VERSION;
11229 ++ info->version = USX2Y_DRIVER_VERSION;
11230 + return 0;
11231 + }
11232 +
11233 +diff --git a/tools/lib/api/fs/fs.c b/tools/lib/api/fs/fs.c
11234 +index 459599d1b6c4..58f05748dd39 100644
11235 +--- a/tools/lib/api/fs/fs.c
11236 ++++ b/tools/lib/api/fs/fs.c
11237 +@@ -179,6 +179,7 @@ static bool fs__env_override(struct fs *fs)
11238 + size_t name_len = strlen(fs->name);
11239 + /* name + "_PATH" + '\0' */
11240 + char upper_name[name_len + 5 + 1];
11241 ++
11242 + memcpy(upper_name, fs->name, name_len);
11243 + mem_toupper(upper_name, name_len);
11244 + strcpy(&upper_name[name_len], "_PATH");
11245 +@@ -188,7 +189,8 @@ static bool fs__env_override(struct fs *fs)
11246 + return false;
11247 +
11248 + fs->found = true;
11249 +- strncpy(fs->path, override_path, sizeof(fs->path));
11250 ++ strncpy(fs->path, override_path, sizeof(fs->path) - 1);
11251 ++ fs->path[sizeof(fs->path) - 1] = '\0';
11252 + return true;
11253 + }
11254 +
11255 +diff --git a/tools/usb/usbip/src/usbip_network.c b/tools/usb/usbip/src/usbip_network.c
11256 +index b4c37e76a6e0..187dfaa67d0a 100644
11257 +--- a/tools/usb/usbip/src/usbip_network.c
11258 ++++ b/tools/usb/usbip/src/usbip_network.c
11259 +@@ -62,39 +62,39 @@ void usbip_setup_port_number(char *arg)
11260 + info("using port %d (\"%s\")", usbip_port, usbip_port_string);
11261 + }
11262 +
11263 +-void usbip_net_pack_uint32_t(int pack, uint32_t *num)
11264 ++uint32_t usbip_net_pack_uint32_t(int pack, uint32_t num)
11265 + {
11266 + uint32_t i;
11267 +
11268 + if (pack)
11269 +- i = htonl(*num);
11270 ++ i = htonl(num);
11271 + else
11272 +- i = ntohl(*num);
11273 ++ i = ntohl(num);
11274 +
11275 +- *num = i;
11276 ++ return i;
11277 + }
11278 +
11279 +-void usbip_net_pack_uint16_t(int pack, uint16_t *num)
11280 ++uint16_t usbip_net_pack_uint16_t(int pack, uint16_t num)
11281 + {
11282 + uint16_t i;
11283 +
11284 + if (pack)
11285 +- i = htons(*num);
11286 ++ i = htons(num);
11287 + else
11288 +- i = ntohs(*num);
11289 ++ i = ntohs(num);
11290 +
11291 +- *num = i;
11292 ++ return i;
11293 + }
11294 +
11295 + void usbip_net_pack_usb_device(int pack, struct usbip_usb_device *udev)
11296 + {
11297 +- usbip_net_pack_uint32_t(pack, &udev->busnum);
11298 +- usbip_net_pack_uint32_t(pack, &udev->devnum);
11299 +- usbip_net_pack_uint32_t(pack, &udev->speed);
11300 ++ udev->busnum = usbip_net_pack_uint32_t(pack, udev->busnum);
11301 ++ udev->devnum = usbip_net_pack_uint32_t(pack, udev->devnum);
11302 ++ udev->speed = usbip_net_pack_uint32_t(pack, udev->speed);
11303 +
11304 +- usbip_net_pack_uint16_t(pack, &udev->idVendor);
11305 +- usbip_net_pack_uint16_t(pack, &udev->idProduct);
11306 +- usbip_net_pack_uint16_t(pack, &udev->bcdDevice);
11307 ++ udev->idVendor = usbip_net_pack_uint16_t(pack, udev->idVendor);
11308 ++ udev->idProduct = usbip_net_pack_uint16_t(pack, udev->idProduct);
11309 ++ udev->bcdDevice = usbip_net_pack_uint16_t(pack, udev->bcdDevice);
11310 + }
11311 +
11312 + void usbip_net_pack_usb_interface(int pack __attribute__((unused)),
11313 +@@ -141,6 +141,14 @@ ssize_t usbip_net_send(int sockfd, void *buff, size_t bufflen)
11314 + return usbip_net_xmit(sockfd, buff, bufflen, 1);
11315 + }
11316 +
11317 ++static inline void usbip_net_pack_op_common(int pack,
11318 ++ struct op_common *op_common)
11319 ++{
11320 ++ op_common->version = usbip_net_pack_uint16_t(pack, op_common->version);
11321 ++ op_common->code = usbip_net_pack_uint16_t(pack, op_common->code);
11322 ++ op_common->status = usbip_net_pack_uint32_t(pack, op_common->status);
11323 ++}
11324 ++
11325 + int usbip_net_send_op_common(int sockfd, uint32_t code, uint32_t status)
11326 + {
11327 + struct op_common op_common;
11328 +@@ -152,7 +160,7 @@ int usbip_net_send_op_common(int sockfd, uint32_t code, uint32_t status)
11329 + op_common.code = code;
11330 + op_common.status = status;
11331 +
11332 +- PACK_OP_COMMON(1, &op_common);
11333 ++ usbip_net_pack_op_common(1, &op_common);
11334 +
11335 + rc = usbip_net_send(sockfd, &op_common, sizeof(op_common));
11336 + if (rc < 0) {
11337 +@@ -176,7 +184,7 @@ int usbip_net_recv_op_common(int sockfd, uint16_t *code)
11338 + goto err;
11339 + }
11340 +
11341 +- PACK_OP_COMMON(0, &op_common);
11342 ++ usbip_net_pack_op_common(0, &op_common);
11343 +
11344 + if (op_common.version != USBIP_VERSION) {
11345 + dbg("version mismatch: %d %d", op_common.version,
11346 +diff --git a/tools/usb/usbip/src/usbip_network.h b/tools/usb/usbip/src/usbip_network.h
11347 +index c1e875cf1078..573fa839b66b 100644
11348 +--- a/tools/usb/usbip/src/usbip_network.h
11349 ++++ b/tools/usb/usbip/src/usbip_network.h
11350 +@@ -33,12 +33,6 @@ struct op_common {
11351 +
11352 + } __attribute__((packed));
11353 +
11354 +-#define PACK_OP_COMMON(pack, op_common) do {\
11355 +- usbip_net_pack_uint16_t(pack, &(op_common)->version);\
11356 +- usbip_net_pack_uint16_t(pack, &(op_common)->code);\
11357 +- usbip_net_pack_uint32_t(pack, &(op_common)->status);\
11358 +-} while (0)
11359 +-
11360 + /* ---------------------------------------------------------------------- */
11361 + /* Dummy Code */
11362 + #define OP_UNSPEC 0x00
11363 +@@ -164,11 +158,11 @@ struct op_devlist_reply_extra {
11364 + } while (0)
11365 +
11366 + #define PACK_OP_DEVLIST_REPLY(pack, reply) do {\
11367 +- usbip_net_pack_uint32_t(pack, &(reply)->ndev);\
11368 ++ (reply)->ndev = usbip_net_pack_uint32_t(pack, (reply)->ndev);\
11369 + } while (0)
11370 +
11371 +-void usbip_net_pack_uint32_t(int pack, uint32_t *num);
11372 +-void usbip_net_pack_uint16_t(int pack, uint16_t *num);
11373 ++uint32_t usbip_net_pack_uint32_t(int pack, uint32_t num);
11374 ++uint16_t usbip_net_pack_uint16_t(int pack, uint16_t num);
11375 + void usbip_net_pack_usb_device(int pack, struct usbip_usb_device *udev);
11376 + void usbip_net_pack_usb_interface(int pack, struct usbip_usb_interface *uinf);
11377 +