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commit: 4bbf7865096bfbbeb861ac51585e6fb3ba9f6ded |
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Author: Huang Rui <vowstar <AT> gmail <DOT> com> |
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AuthorDate: Mon Dec 23 02:45:38 2019 +0000 |
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Commit: Joonas Niilola <juippis <AT> gentoo <DOT> org> |
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CommitDate: Sun Jan 5 10:09:45 2020 +0000 |
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URL: https://gitweb.gentoo.org/repo/gentoo.git/commit/?id=4bbf7865 |
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|
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sci-electronics/iverilog: bump to 10.3 |
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|
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Bump iverilog version to 10.3 |
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|
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Follow these URL: |
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* http://iverilog.icarus.com |
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* https://github.com/steveicarus/iverilog |
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Update LICENSE to LGPL-2.1 |
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Rewrite ebuild to download file from iverilog official github repo |
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Update maintainer list, add proxy-maint |
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Add github upstream https://github.com/steveicarus/iverilog |
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Bump the version with bugfixes |
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Replace autoconf.sh to make it utilize the autotools eclass |
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Fix upstream parallel compilation bug |
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Add https://github.com/steveicarus/iverilog in HOMEPAGE array |
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Happy new year 2020 |
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|
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Tested from my overlay: |
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https://github.com/vowstar/vowstar-overlay/ |
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|
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Closes: https://bugs.gentoo.org/687080 |
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Closes: https://bugs.gentoo.org/701122 |
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Closes: https://bugs.gentoo.org/704344 |
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Package-Manager: Portage-2.3.82, Repoman-2.3.20 |
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Signed-off-by: Huang Rui <vowstar <AT> gmail.com> |
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Closes: https://github.com/gentoo/gentoo/pull/14096 |
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Signed-off-by: Joonas Niilola <juippis <AT> gentoo.org> |
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|
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sci-electronics/iverilog/Manifest | 1 + |
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sci-electronics/iverilog/iverilog-10.3.ebuild | 68 +++++++++++++++++++++++++++ |
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sci-electronics/iverilog/metadata.xml | 31 ++++++++---- |
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3 files changed, 90 insertions(+), 10 deletions(-) |
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|
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diff --git a/sci-electronics/iverilog/Manifest b/sci-electronics/iverilog/Manifest |
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index 2459fd7d45c..19e0b1a4411 100644 |
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--- a/sci-electronics/iverilog/Manifest |
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+++ b/sci-electronics/iverilog/Manifest |
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@@ -1,3 +1,4 @@ |
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+DIST iverilog-10.3.tar.gz 1600835 BLAKE2B 107c57c61fb27c18f4020f7853bf6ca83d1a86fdc73c57ea207828baf6b7a26d42e43ce7b33580f050a4c0b8f63bca6accecf678323a3bbbee1eb9c1d8fa2caa SHA512 67076e19a208576c21a0462ff7d15d00a9d47740c47518a5523bd928b3118360d85eb84c317963717d15e5246ece3727259f6ff3baf59e195340530cc9086a1d |
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DIST verilog-0.9.6.tar.gz 1219982 BLAKE2B 12f7dfb1ab8b7e4524cf0a3061ce801bfa741015fc1446aef7ffe51c42d76b5d0578e78ce13cd8c3fb6bac580e9da1ed11ca03e1fd02f8cb75dd74425546f851 SHA512 63c18f211eb9711547db65b859551063129cf18acb1196eaa88562f194231079fe929a6f7b8fbe2160863c521f02dde079e792f1b0bbe1c2514deafd55d5288c |
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DIST verilog-0.9.7.tar.gz 1238088 BLAKE2B c0b173b4857abc0d35ad05d9f11d5265763c92e625aadb1b487978c40e0679725b8e6de0fc05cc8e4bc7a6db6e1d9abacf886942b05e27d8513b9586cca156f9 SHA512 1a81f132c667f5cd33a11156364a366806ef9b6ef59b86f69df852af79cc92db17df8db0bace4e3c14929b0110df0aa7d83f35f664057e715842acf7bd21c1f5 |
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DIST verilog-10.2.tar.gz 1695227 BLAKE2B ea2488de55ef60a248e7f5ffd5e06c6d86d57f3cff4536cb64a727ab70d8868847e53beec093e21243a1e81ede021b0ccde771d66ce1d986f737b5d925aaff11 SHA512 21e0861ee994daf0a98d0da3e0ad665e37cba4669faa873ae57d05eb41794b6cc2948c88cc07ebe1e9266850ad2bad189096ae6911b9c4064f772279d0901aef |
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|
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diff --git a/sci-electronics/iverilog/iverilog-10.3.ebuild b/sci-electronics/iverilog/iverilog-10.3.ebuild |
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new file mode 100644 |
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index 00000000000..145ceb786d7 |
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--- /dev/null |
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+++ b/sci-electronics/iverilog/iverilog-10.3.ebuild |
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@@ -0,0 +1,68 @@ |
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+# Copyright 1999-2020 Gentoo Authors |
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+# Distributed under the terms of the GNU General Public License v2 |
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+ |
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+EAPI=7 |
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+ |
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+inherit autotools |
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+ |
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+GITHUB_PV=$(ver_rs 1- '_') |
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+ |
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+DESCRIPTION="A Verilog simulation and synthesis tool" |
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+HOMEPAGE=" |
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+ http://iverilog.icarus.com |
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+ https://github.com/steveicarus/iverilog |
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+" |
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+ |
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+if [[ ${PV} == "9999" ]] ; then |
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+ inherit git-r3 |
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+ EGIT_REPO_URI="https://github.com/steveicarus/${PN}.git" |
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+else |
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+ SRC_URI="https://github.com/steveicarus/${PN}/archive/v${GITHUB_PV}.tar.gz -> ${P}.tar.gz" |
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+ KEYWORDS="~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sh ~sparc ~x86" |
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+ S="${WORKDIR}/${PN}-${GITHUB_PV}" |
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+fi |
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+ |
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+LICENSE="LGPL-2.1" |
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+SLOT="0" |
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+IUSE="examples" |
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+ |
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+# If you are building from git, you will also need gperf to generate |
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+# the configure scripts. |
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+RDEPEND=" |
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+ sys-libs/readline:0 |
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+ sys-libs/zlib |
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+" |
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+ |
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+DEPEND=" |
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+ dev-util/gperf |
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+ ${RDEPEND} |
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+" |
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+ |
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+src_prepare() { |
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+ default |
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+ |
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+ # From upstreams autoconf.sh, to make it utilize the autotools eclass |
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+ # Here translate the autoconf.sh, equivalent to the following code |
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+ # > sh autoconf.sh |
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+ |
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+ # Fix build fail problem when using large job number, make it parallel safe |
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+ echo ".NOTPARALLEL: install" >> ./Makefile.in || die |
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+ |
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+ # Autoconf in root ... |
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+ eautoconf --force |
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+ # Precompiling lexor_keyword.gperf |
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+ gperf -o -i 7 -C -k 1-4,6,9,\$ -H keyword_hash -N check_identifier -t ./lexor_keyword.gperf > lexor_keyword.cc || die |
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+ # Precompiling vhdlpp/lexor_keyword.gperf |
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+ cd vhdlpp || die |
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+ gperf -o -i 7 --ignore-case -C -k 1-4,6,9,\$ -H keyword_hash -N check_identifier -t ./lexor_keyword.gperf > lexor_keyword.cc || die |
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+} |
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+ |
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+src_install() { |
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+ local DOCS=( *.txt ) |
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+ default |
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+ |
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+ if use examples; then |
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+ dodoc -r examples |
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+ docompress -x /usr/share/doc/${PF}/examples |
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+ fi |
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+} |
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|
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diff --git a/sci-electronics/iverilog/metadata.xml b/sci-electronics/iverilog/metadata.xml |
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index 21d969b3bbd..edc7fde50a3 100644 |
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--- a/sci-electronics/iverilog/metadata.xml |
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+++ b/sci-electronics/iverilog/metadata.xml |
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@@ -1,14 +1,25 @@ |
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<?xml version="1.0" encoding="UTF-8"?> |
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<!DOCTYPE pkgmetadata SYSTEM "http://www.gentoo.org/dtd/metadata.dtd"> |
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<pkgmetadata> |
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- <maintainer type="project"> |
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- <email>sci-electronics@g.o</email> |
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- <name>Gentoo Electronics Project</name> |
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- </maintainer> |
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- <longdescription> |
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- Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a |
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- compiler, compiling source code writen in Verilog (IEEE-1364) into some target |
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- format. The compiler proper is intended to parse and elaborate design |
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- descriptions written to the IEEE standard IEEE Std 1364-2001. |
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- </longdescription> |
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+ <maintainer type="person"> |
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+ <email>vowstar@×××××.com</email> |
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+ <name>Huang Rui</name> |
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+ </maintainer> |
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+ <maintainer type="project"> |
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+ <email>sci-electronics@g.o</email> |
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+ <name>Gentoo Electronics Project</name> |
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+ </maintainer> |
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+ <maintainer type="project"> |
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+ <email>proxy-maint@g.o</email> |
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+ <name>Proxy Maintainers</name> |
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+ </maintainer> |
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+ <upstream> |
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+ <remote-id type="github">steveicarus/iverilog</remote-id> |
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+ </upstream> |
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+ <longdescription> |
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+ Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a |
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+ compiler, compiling source code writen in Verilog (IEEE-1364) into some target |
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+ format. The compiler proper is intended to parse and elaborate design |
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+ descriptions written to the IEEE standard IEEE Std 1364-2001. |
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+ </longdescription> |
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</pkgmetadata> |