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commit: 6abc54887ecc2c99d920f03dfaec2d1ca3bfe334 |
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Author: Andreas K. Hüttel <dilfridge <AT> gentoo <DOT> org> |
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AuthorDate: Fri Jun 25 19:07:00 2021 +0000 |
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Commit: Andreas K. Hüttel <dilfridge <AT> gentoo <DOT> org> |
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CommitDate: Fri Jun 25 19:07:25 2021 +0000 |
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URL: https://gitweb.gentoo.org/proj/releng.git/commit/?id=6abc5488 |
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|
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riscv: also upload 20.0 multilib |
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|
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Signed-off-by: Andreas K. Hüttel <dilfridge <AT> gentoo.org> |
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|
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tools/catalyst-auto-qemu-riscv.conf | 7 +------ |
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1 file changed, 1 insertion(+), 6 deletions(-) |
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|
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diff --git a/tools/catalyst-auto-qemu-riscv.conf b/tools/catalyst-auto-qemu-riscv.conf |
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index 6212a8fe..78b7197d 100644 |
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--- a/tools/catalyst-auto-qemu-riscv.conf |
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+++ b/tools/catalyst-auto-qemu-riscv.conf |
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@@ -46,16 +46,11 @@ post_build() { |
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local set=$1 spec=$2 |
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|
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case ${spec} in |
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- stage3*lp64*20.0*.spec) |
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+ stage3*.spec) |
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pushd "${BUILD_SRCDIR_BASE}/builds/20.0" >/dev/null |
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upload stage3-rv64_$(echo ${spec}|sed -e 's:^stage3-::g' -e 's:\.spec$::g')-${TIMESTAMP}*.xz* |
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popd >/dev/null |
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;; |
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- stage3*lp64*.spec) |
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- pushd "${BUILD_SRCDIR_BASE}/builds/default" >/dev/null |
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- upload stage3-rv64_$(echo ${spec}|sed -e 's:^stage3-::g' -e 's:\.spec$::g')-${TIMESTAMP}*.xz* |
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- popd >/dev/null |
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- ;; |
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*) |
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echo "Finished ${spec}" |
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;; |
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