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commit: ff88ce93296fc216eded48e4b26a1354380e3d60 |
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Author: Andreas K. Hüttel <dilfridge <AT> gentoo <DOT> org> |
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AuthorDate: Fri Sep 11 19:04:38 2020 +0000 |
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Commit: Andreas K. Hüttel <dilfridge <AT> gentoo <DOT> org> |
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CommitDate: Fri Sep 11 19:04:38 2020 +0000 |
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URL: https://gitweb.gentoo.org/proj/catalyst.git/commit/?id=ff88ce93 |
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|
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Add rv32 subarch names (all cflags magic is done in the profiles) |
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|
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Signed-off-by: Andreas K. Hüttel <dilfridge <AT> gentoo.org> |
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|
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catalyst/arch/riscv.py | 14 +++++++++++++- |
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1 file changed, 13 insertions(+), 1 deletion(-) |
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|
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diff --git a/catalyst/arch/riscv.py b/catalyst/arch/riscv.py |
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index 9f7a421f..18695b51 100644 |
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--- a/catalyst/arch/riscv.py |
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+++ b/catalyst/arch/riscv.py |
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@@ -28,6 +28,16 @@ class arch_rv64_lp64(generic_riscv): |
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def __init__(self,myspec): |
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generic_riscv.__init__(self,myspec) |
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|
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+class arch_rv32_ilp32d(generic_riscv): |
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+ "builder class for rv64_lp64" |
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+ def __init__(self,myspec): |
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+ generic_riscv.__init__(self,myspec) |
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+ |
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+class arch_rv32_ilp32(generic_riscv): |
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+ "builder class for rv64_lp64" |
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+ def __init__(self,myspec): |
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+ generic_riscv.__init__(self,myspec) |
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+ |
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|
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def register(): |
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"Inform main catalyst program of the contents of this plugin." |
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@@ -35,5 +45,7 @@ def register(): |
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"riscv" : arch_riscv, |
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"rv64_multilib" : arch_rv64_multilib, |
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"rv64_lp64d" : arch_rv64_lp64d, |
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- "rv64_lp64" : arch_rv64_lp64 |
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+ "rv64_lp64" : arch_rv64_lp64, |
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+ "rv32_ilp32d" : arch_rv32_ilp32d, |
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+ "rv32_ilp32" : arch_rv32_ilp32 |
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}, ("rv64_multilib")) |
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