Gentoo Archives: gentoo-commits

From: Mike Pagano <mpagano@g.o>
To: gentoo-commits@l.g.o
Subject: [gentoo-commits] proj/linux-patches:5.16 commit in: /
Date: Sun, 16 Jan 2022 10:19:21
Message-Id: 1642169472.856d11ee1caf5f42639c1727cd391e3fe53822ee.mpagano@gentoo
1 commit: 856d11ee1caf5f42639c1727cd391e3fe53822ee
2 Author: Mike Pagano <mpagano <AT> gentoo <DOT> org>
3 AuthorDate: Fri Jan 14 14:11:12 2022 +0000
4 Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org>
5 CommitDate: Fri Jan 14 14:11:12 2022 +0000
6 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=856d11ee
7
8 mt76: mt7921e: fix possible probe failure after reboot
9
10 See bug #830977
11
12 Signed-off-by: Mike Pagano <mpagano <AT> gentoo.org>
13
14 0000_README | 4 +
15 ...e-fix-possible-probe-failure-after-reboot.patch | 436 +++++++++++++++++++++
16 2 files changed, 440 insertions(+)
17
18 diff --git a/0000_README b/0000_README
19 index efde5c7d..c012760e 100644
20 --- a/0000_README
21 +++ b/0000_README
22 @@ -55,6 +55,10 @@ Patch: 2000_BT-Check-key-sizes-only-if-Secure-Simple-Pairing-enabled.patch
23 From: https://lore.kernel.org/linux-bluetooth/20190522070540.48895-1-marcel@××××××××.org/raw
24 Desc: Bluetooth: Check key sizes only when Secure Simple Pairing is enabled. See bug #686758
25
26 +Patch: 2400_mt76-mt7921e-fix-possible-probe-failure-after-reboot.patch
27 +From: https://patchwork.kernel.org/project/linux-wireless/patch/70e27cbc652cbdb78277b9c691a3a5ba02653afb.1641540175.git.objelf@×××××.com/
28 +Desc: mt76: mt7921e: fix possible probe failure after reboot
29 +
30 Patch: 2900_tmp513-Fix-build-issue-by-selecting-CONFIG_REG.patch
31 From: https://bugs.gentoo.org/710790
32 Desc: tmp513 requies REGMAP_I2C to build. Select it by default in Kconfig. See bug #710790. Thanks to Phil Stracchino
33
34 diff --git a/2400_mt76-mt7921e-fix-possible-probe-failure-after-reboot.patch b/2400_mt76-mt7921e-fix-possible-probe-failure-after-reboot.patch
35 new file mode 100644
36 index 00000000..4440e910
37 --- /dev/null
38 +++ b/2400_mt76-mt7921e-fix-possible-probe-failure-after-reboot.patch
39 @@ -0,0 +1,436 @@
40 +From patchwork Fri Jan 7 07:30:03 2022
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44 +X-Patchwork-Submitter: Sean Wang <sean.wang@××××××××.com>
45 +X-Patchwork-Id: 12706336
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90 + <linux-wireless@×××××××××××.org>,
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92 + "Deren Wu" <deren.wu@××××××××.com>
93 +Subject: [PATCH] mt76: mt7921e: fix possible probe failure after reboot
94 +Date: Fri, 7 Jan 2022 15:30:03 +0800
95 +Message-ID:
96 + <70e27cbc652cbdb78277b9c691a3a5ba02653afb.1641540175.git.objelf@×××××.com>
97 +X-Mailer: git-send-email 1.7.9.5
98 +MIME-Version: 1.0
99 +X-MTK: N
100 +Precedence: bulk
101 +List-ID: <linux-wireless.vger.kernel.org>
102 +X-Mailing-List: linux-wireless@×××××××××××.org
103 +
104 +From: Sean Wang <sean.wang@××××××××.com>
105 +
106 +It doesn't guarantee the mt7921e gets started with ASPM L0 after each
107 +machine reboot on every platform.
108 +
109 +If mt7921e gets started with not ASPM L0, it would be possible that the
110 +driver encounters time to time failure in mt7921_pci_probe, like a
111 +weird chip identifier is read
112 +
113 +[ 215.514503] mt7921e 0000:05:00.0: ASIC revision: feed0000
114 +[ 216.604741] mt7921e: probe of 0000:05:00.0 failed with error -110
115 +
116 +or failing to init hardware because the driver is not allowed to access the
117 +register until the device is in ASPM L0 state. So, we call
118 +__mt7921e_mcu_drv_pmctrl in early mt7921_pci_probe to force the device
119 +to bring back to the L0 state for we can safely access registers in any
120 +case.
121 +
122 +In the patch, we move all functions from dma.c to pci.c and register mt76
123 +bus operation earilier, that is the __mt7921e_mcu_drv_pmctrl depends on.
124 +
125 +Fixes: bf3747ae2e25 ("mt76: mt7921: enable aspm by default")
126 +Reported-by: Kai-Chuan Hsieh <kaichuan.hsieh@×××××××××.com>
127 +Co-developed-by: Deren Wu <deren.wu@××××××××.com>
128 +Signed-off-by: Deren Wu <deren.wu@××××××××.com>
129 +Signed-off-by: Sean Wang <sean.wang@××××××××.com>
130 +---
131 + .../net/wireless/mediatek/mt76/mt7921/dma.c | 119 -----------------
132 + .../wireless/mediatek/mt76/mt7921/mt7921.h | 1 +
133 + .../net/wireless/mediatek/mt76/mt7921/pci.c | 124 ++++++++++++++++++
134 + .../wireless/mediatek/mt76/mt7921/pci_mcu.c | 18 ++-
135 + 4 files changed, 139 insertions(+), 123 deletions(-)
136 +
137 +diff --git a/drivers/net/wireless/mediatek/mt76/mt7921/dma.c b/drivers/net/wireless/mediatek/mt76/mt7921/dma.c
138 +index cdff1fd52d93..39d6ce4ecddd 100644
139 +--- a/drivers/net/wireless/mediatek/mt76/mt7921/dma.c
140 ++++ b/drivers/net/wireless/mediatek/mt76/mt7921/dma.c
141 +@@ -78,110 +78,6 @@ static void mt7921_dma_prefetch(struct mt7921_dev *dev)
142 + mt76_wr(dev, MT_WFDMA0_TX_RING17_EXT_CTRL, PREFETCH(0x380, 0x4));
143 + }
144 +
145 +-static u32 __mt7921_reg_addr(struct mt7921_dev *dev, u32 addr)
146 +-{
147 +- static const struct {
148 +- u32 phys;
149 +- u32 mapped;
150 +- u32 size;
151 +- } fixed_map[] = {
152 +- { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
153 +- { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
154 +- { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
155 +- { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
156 +- { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
157 +- { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
158 +- { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
159 +- { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
160 +- { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
161 +- { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
162 +- { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
163 +- { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */
164 +- { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */
165 +- { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
166 +- { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
167 +- { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
168 +- { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
169 +- { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
170 +- { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
171 +- { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
172 +- { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
173 +- { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
174 +- { 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */
175 +- { 0x820cd000, 0x0f000, 0x1000 }, /* WF_MDP_TOP */
176 +- { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
177 +- { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
178 +- { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
179 +- { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
180 +- { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
181 +- { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
182 +- { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
183 +- { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
184 +- { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
185 +- { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
186 +- { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
187 +- { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
188 +- { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
189 +- { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
190 +- { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
191 +- { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
192 +- { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
193 +- { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
194 +- { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
195 +- };
196 +- int i;
197 +-
198 +- if (addr < 0x100000)
199 +- return addr;
200 +-
201 +- for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
202 +- u32 ofs;
203 +-
204 +- if (addr < fixed_map[i].phys)
205 +- continue;
206 +-
207 +- ofs = addr - fixed_map[i].phys;
208 +- if (ofs > fixed_map[i].size)
209 +- continue;
210 +-
211 +- return fixed_map[i].mapped + ofs;
212 +- }
213 +-
214 +- if ((addr >= 0x18000000 && addr < 0x18c00000) ||
215 +- (addr >= 0x70000000 && addr < 0x78000000) ||
216 +- (addr >= 0x7c000000 && addr < 0x7c400000))
217 +- return mt7921_reg_map_l1(dev, addr);
218 +-
219 +- dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n",
220 +- addr);
221 +-
222 +- return 0;
223 +-}
224 +-
225 +-static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset)
226 +-{
227 +- struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
228 +- u32 addr = __mt7921_reg_addr(dev, offset);
229 +-
230 +- return dev->bus_ops->rr(mdev, addr);
231 +-}
232 +-
233 +-static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val)
234 +-{
235 +- struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
236 +- u32 addr = __mt7921_reg_addr(dev, offset);
237 +-
238 +- dev->bus_ops->wr(mdev, addr, val);
239 +-}
240 +-
241 +-static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
242 +-{
243 +- struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
244 +- u32 addr = __mt7921_reg_addr(dev, offset);
245 +-
246 +- return dev->bus_ops->rmw(mdev, addr, mask, val);
247 +-}
248 +-
249 + static int mt7921_dma_disable(struct mt7921_dev *dev, bool force)
250 + {
251 + if (force) {
252 +@@ -341,23 +237,8 @@ int mt7921_wpdma_reinit_cond(struct mt7921_dev *dev)
253 +
254 + int mt7921_dma_init(struct mt7921_dev *dev)
255 + {
256 +- struct mt76_bus_ops *bus_ops;
257 + int ret;
258 +
259 +- dev->phy.dev = dev;
260 +- dev->phy.mt76 = &dev->mt76.phy;
261 +- dev->mt76.phy.priv = &dev->phy;
262 +- dev->bus_ops = dev->mt76.bus;
263 +- bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
264 +- GFP_KERNEL);
265 +- if (!bus_ops)
266 +- return -ENOMEM;
267 +-
268 +- bus_ops->rr = mt7921_rr;
269 +- bus_ops->wr = mt7921_wr;
270 +- bus_ops->rmw = mt7921_rmw;
271 +- dev->mt76.bus = bus_ops;
272 +-
273 + mt76_dma_attach(&dev->mt76);
274 +
275 + ret = mt7921_dma_disable(dev, true);
276 +diff --git a/drivers/net/wireless/mediatek/mt76/mt7921/mt7921.h b/drivers/net/wireless/mediatek/mt76/mt7921/mt7921.h
277 +index 8b674e042568..63e3c7ef5e89 100644
278 +--- a/drivers/net/wireless/mediatek/mt76/mt7921/mt7921.h
279 ++++ b/drivers/net/wireless/mediatek/mt76/mt7921/mt7921.h
280 +@@ -443,6 +443,7 @@ int mt7921e_mcu_init(struct mt7921_dev *dev);
281 + int mt7921s_wfsys_reset(struct mt7921_dev *dev);
282 + int mt7921s_mac_reset(struct mt7921_dev *dev);
283 + int mt7921s_init_reset(struct mt7921_dev *dev);
284 ++int __mt7921e_mcu_drv_pmctrl(struct mt7921_dev *dev);
285 + int mt7921e_mcu_drv_pmctrl(struct mt7921_dev *dev);
286 + int mt7921e_mcu_fw_pmctrl(struct mt7921_dev *dev);
287 +
288 +diff --git a/drivers/net/wireless/mediatek/mt76/mt7921/pci.c b/drivers/net/wireless/mediatek/mt76/mt7921/pci.c
289 +index 1ae0d5826ca7..a0c82d19c4d9 100644
290 +--- a/drivers/net/wireless/mediatek/mt76/mt7921/pci.c
291 ++++ b/drivers/net/wireless/mediatek/mt76/mt7921/pci.c
292 +@@ -121,6 +121,110 @@ static void mt7921e_unregister_device(struct mt7921_dev *dev)
293 + mt76_free_device(&dev->mt76);
294 + }
295 +
296 ++static u32 __mt7921_reg_addr(struct mt7921_dev *dev, u32 addr)
297 ++{
298 ++ static const struct {
299 ++ u32 phys;
300 ++ u32 mapped;
301 ++ u32 size;
302 ++ } fixed_map[] = {
303 ++ { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
304 ++ { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
305 ++ { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
306 ++ { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
307 ++ { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
308 ++ { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
309 ++ { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
310 ++ { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
311 ++ { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
312 ++ { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
313 ++ { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
314 ++ { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */
315 ++ { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */
316 ++ { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
317 ++ { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
318 ++ { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
319 ++ { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
320 ++ { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
321 ++ { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
322 ++ { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
323 ++ { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
324 ++ { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
325 ++ { 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */
326 ++ { 0x820cd000, 0x0f000, 0x1000 }, /* WF_MDP_TOP */
327 ++ { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
328 ++ { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
329 ++ { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
330 ++ { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
331 ++ { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
332 ++ { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
333 ++ { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
334 ++ { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
335 ++ { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
336 ++ { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
337 ++ { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
338 ++ { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
339 ++ { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
340 ++ { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
341 ++ { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
342 ++ { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
343 ++ { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
344 ++ { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
345 ++ { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
346 ++ };
347 ++ int i;
348 ++
349 ++ if (addr < 0x100000)
350 ++ return addr;
351 ++
352 ++ for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
353 ++ u32 ofs;
354 ++
355 ++ if (addr < fixed_map[i].phys)
356 ++ continue;
357 ++
358 ++ ofs = addr - fixed_map[i].phys;
359 ++ if (ofs > fixed_map[i].size)
360 ++ continue;
361 ++
362 ++ return fixed_map[i].mapped + ofs;
363 ++ }
364 ++
365 ++ if ((addr >= 0x18000000 && addr < 0x18c00000) ||
366 ++ (addr >= 0x70000000 && addr < 0x78000000) ||
367 ++ (addr >= 0x7c000000 && addr < 0x7c400000))
368 ++ return mt7921_reg_map_l1(dev, addr);
369 ++
370 ++ dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n",
371 ++ addr);
372 ++
373 ++ return 0;
374 ++}
375 ++
376 ++static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset)
377 ++{
378 ++ struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
379 ++ u32 addr = __mt7921_reg_addr(dev, offset);
380 ++
381 ++ return dev->bus_ops->rr(mdev, addr);
382 ++}
383 ++
384 ++static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val)
385 ++{
386 ++ struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
387 ++ u32 addr = __mt7921_reg_addr(dev, offset);
388 ++
389 ++ dev->bus_ops->wr(mdev, addr, val);
390 ++}
391 ++
392 ++static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
393 ++{
394 ++ struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
395 ++ u32 addr = __mt7921_reg_addr(dev, offset);
396 ++
397 ++ return dev->bus_ops->rmw(mdev, addr, mask, val);
398 ++}
399 ++
400 + static int mt7921_pci_probe(struct pci_dev *pdev,
401 + const struct pci_device_id *id)
402 + {
403 +@@ -152,6 +256,7 @@ static int mt7921_pci_probe(struct pci_dev *pdev,
404 + .fw_own = mt7921e_mcu_fw_pmctrl,
405 + };
406 +
407 ++ struct mt76_bus_ops *bus_ops;
408 + struct mt7921_dev *dev;
409 + struct mt76_dev *mdev;
410 + int ret;
411 +@@ -189,6 +294,25 @@ static int mt7921_pci_probe(struct pci_dev *pdev,
412 +
413 + mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]);
414 + tasklet_init(&dev->irq_tasklet, mt7921_irq_tasklet, (unsigned long)dev);
415 ++
416 ++ dev->phy.dev = dev;
417 ++ dev->phy.mt76 = &dev->mt76.phy;
418 ++ dev->mt76.phy.priv = &dev->phy;
419 ++ dev->bus_ops = dev->mt76.bus;
420 ++ bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
421 ++ GFP_KERNEL);
422 ++ if (!bus_ops)
423 ++ return -ENOMEM;
424 ++
425 ++ bus_ops->rr = mt7921_rr;
426 ++ bus_ops->wr = mt7921_wr;
427 ++ bus_ops->rmw = mt7921_rmw;
428 ++ dev->mt76.bus = bus_ops;
429 ++
430 ++ ret = __mt7921e_mcu_drv_pmctrl(dev);
431 ++ if (ret)
432 ++ return ret;
433 ++
434 + mdev->rev = (mt7921_l1_rr(dev, MT_HW_CHIPID) << 16) |
435 + (mt7921_l1_rr(dev, MT_HW_REV) & 0xff);
436 + dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
437 +diff --git a/drivers/net/wireless/mediatek/mt76/mt7921/pci_mcu.c b/drivers/net/wireless/mediatek/mt76/mt7921/pci_mcu.c
438 +index f9e350b67fdc..36669e5aeef3 100644
439 +--- a/drivers/net/wireless/mediatek/mt76/mt7921/pci_mcu.c
440 ++++ b/drivers/net/wireless/mediatek/mt76/mt7921/pci_mcu.c
441 +@@ -59,10 +59,8 @@ int mt7921e_mcu_init(struct mt7921_dev *dev)
442 + return err;
443 + }
444 +
445 +-int mt7921e_mcu_drv_pmctrl(struct mt7921_dev *dev)
446 ++int __mt7921e_mcu_drv_pmctrl(struct mt7921_dev *dev)
447 + {
448 +- struct mt76_phy *mphy = &dev->mt76.phy;
449 +- struct mt76_connac_pm *pm = &dev->pm;
450 + int i, err = 0;
451 +
452 + for (i = 0; i < MT7921_DRV_OWN_RETRY_COUNT; i++) {
453 +@@ -75,9 +73,21 @@ int mt7921e_mcu_drv_pmctrl(struct mt7921_dev *dev)
454 + if (i == MT7921_DRV_OWN_RETRY_COUNT) {
455 + dev_err(dev->mt76.dev, "driver own failed\n");
456 + err = -EIO;
457 +- goto out;
458 + }
459 +
460 ++ return err;
461 ++}
462 ++
463 ++int mt7921e_mcu_drv_pmctrl(struct mt7921_dev *dev)
464 ++{
465 ++ struct mt76_phy *mphy = &dev->mt76.phy;
466 ++ struct mt76_connac_pm *pm = &dev->pm;
467 ++ int err;
468 ++
469 ++ err = __mt7921e_mcu_drv_pmctrl(dev);
470 ++ if (err < 0)
471 ++ goto out;
472 ++
473 + mt7921_wpdma_reinit_cond(dev);
474 + clear_bit(MT76_STATE_PM, &mphy->state);
475 +