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commit: 5d3374055d11d0c07beb738301f42c896e6c146d |
2 |
Author: Mike Pagano <mpagano <AT> gentoo <DOT> org> |
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AuthorDate: Tue Apr 18 10:21:26 2017 +0000 |
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Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org> |
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CommitDate: Tue Apr 18 10:21:26 2017 +0000 |
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URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=5d337405 |
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|
8 |
Linux patch 4.4.62 |
9 |
|
10 |
0000_README | 4 + |
11 |
1061_linux-4.4.62.patch | 839 ++++++++++++++++++++++++++++++++++++++++++++++++ |
12 |
2 files changed, 843 insertions(+) |
13 |
|
14 |
diff --git a/0000_README b/0000_README |
15 |
index 84c1648..d954e4b 100644 |
16 |
--- a/0000_README |
17 |
+++ b/0000_README |
18 |
@@ -287,6 +287,10 @@ Patch: 1060_linux-4.4.61.patch |
19 |
From: http://www.kernel.org |
20 |
Desc: Linux 4.4.61 |
21 |
|
22 |
+Patch: 1061_linux-4.4.62.patch |
23 |
+From: http://www.kernel.org |
24 |
+Desc: Linux 4.4.62 |
25 |
+ |
26 |
Patch: 1500_XATTR_USER_PREFIX.patch |
27 |
From: https://bugs.gentoo.org/show_bug.cgi?id=470644 |
28 |
Desc: Support for namespace user.pax.* on tmpfs. |
29 |
|
30 |
diff --git a/1061_linux-4.4.62.patch b/1061_linux-4.4.62.patch |
31 |
new file mode 100644 |
32 |
index 0000000..8c493e1 |
33 |
--- /dev/null |
34 |
+++ b/1061_linux-4.4.62.patch |
35 |
@@ -0,0 +1,839 @@ |
36 |
+diff --git a/Makefile b/Makefile |
37 |
+index ef5045b8201d..0309acc34472 100644 |
38 |
+--- a/Makefile |
39 |
++++ b/Makefile |
40 |
+@@ -1,6 +1,6 @@ |
41 |
+ VERSION = 4 |
42 |
+ PATCHLEVEL = 4 |
43 |
+-SUBLEVEL = 61 |
44 |
++SUBLEVEL = 62 |
45 |
+ EXTRAVERSION = |
46 |
+ NAME = Blurry Fish Butt |
47 |
+ |
48 |
+diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig |
49 |
+index 75bfca69e418..d5cfa937d622 100644 |
50 |
+--- a/arch/mips/Kconfig |
51 |
++++ b/arch/mips/Kconfig |
52 |
+@@ -9,6 +9,7 @@ config MIPS |
53 |
+ select HAVE_CONTEXT_TRACKING |
54 |
+ select HAVE_GENERIC_DMA_COHERENT |
55 |
+ select HAVE_IDE |
56 |
++ select HAVE_IRQ_EXIT_ON_IRQ_STACK |
57 |
+ select HAVE_OPROFILE |
58 |
+ select HAVE_PERF_EVENTS |
59 |
+ select PERF_USE_VMALLOC |
60 |
+diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h |
61 |
+index 15e0fecbc300..ebb9efb02502 100644 |
62 |
+--- a/arch/mips/include/asm/irq.h |
63 |
++++ b/arch/mips/include/asm/irq.h |
64 |
+@@ -17,6 +17,18 @@ |
65 |
+ |
66 |
+ #include <irq.h> |
67 |
+ |
68 |
++#define IRQ_STACK_SIZE THREAD_SIZE |
69 |
++ |
70 |
++extern void *irq_stack[NR_CPUS]; |
71 |
++ |
72 |
++static inline bool on_irq_stack(int cpu, unsigned long sp) |
73 |
++{ |
74 |
++ unsigned long low = (unsigned long)irq_stack[cpu]; |
75 |
++ unsigned long high = low + IRQ_STACK_SIZE; |
76 |
++ |
77 |
++ return (low <= sp && sp <= high); |
78 |
++} |
79 |
++ |
80 |
+ #ifdef CONFIG_I8259 |
81 |
+ static inline int irq_canonicalize(int irq) |
82 |
+ { |
83 |
+diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h |
84 |
+index a71da576883c..5347f130f536 100644 |
85 |
+--- a/arch/mips/include/asm/stackframe.h |
86 |
++++ b/arch/mips/include/asm/stackframe.h |
87 |
+@@ -216,12 +216,19 @@ |
88 |
+ LONG_S $25, PT_R25(sp) |
89 |
+ LONG_S $28, PT_R28(sp) |
90 |
+ LONG_S $31, PT_R31(sp) |
91 |
++ |
92 |
++ /* Set thread_info if we're coming from user mode */ |
93 |
++ mfc0 k0, CP0_STATUS |
94 |
++ sll k0, 3 /* extract cu0 bit */ |
95 |
++ bltz k0, 9f |
96 |
++ |
97 |
+ ori $28, sp, _THREAD_MASK |
98 |
+ xori $28, _THREAD_MASK |
99 |
+ #ifdef CONFIG_CPU_CAVIUM_OCTEON |
100 |
+ .set mips64 |
101 |
+ pref 0, 0($28) /* Prefetch the current pointer */ |
102 |
+ #endif |
103 |
++9: |
104 |
+ .set pop |
105 |
+ .endm |
106 |
+ |
107 |
+diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c |
108 |
+index 154e2039ea5e..ec053ce7bb38 100644 |
109 |
+--- a/arch/mips/kernel/asm-offsets.c |
110 |
++++ b/arch/mips/kernel/asm-offsets.c |
111 |
+@@ -101,6 +101,7 @@ void output_thread_info_defines(void) |
112 |
+ OFFSET(TI_REGS, thread_info, regs); |
113 |
+ DEFINE(_THREAD_SIZE, THREAD_SIZE); |
114 |
+ DEFINE(_THREAD_MASK, THREAD_MASK); |
115 |
++ DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE); |
116 |
+ BLANK(); |
117 |
+ } |
118 |
+ |
119 |
+diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S |
120 |
+index baa7b6fc0a60..619e30e2c4f0 100644 |
121 |
+--- a/arch/mips/kernel/genex.S |
122 |
++++ b/arch/mips/kernel/genex.S |
123 |
+@@ -188,9 +188,44 @@ NESTED(handle_int, PT_SIZE, sp) |
124 |
+ |
125 |
+ LONG_L s0, TI_REGS($28) |
126 |
+ LONG_S sp, TI_REGS($28) |
127 |
+- PTR_LA ra, ret_from_irq |
128 |
+- PTR_LA v0, plat_irq_dispatch |
129 |
+- jr v0 |
130 |
++ |
131 |
++ /* |
132 |
++ * SAVE_ALL ensures we are using a valid kernel stack for the thread. |
133 |
++ * Check if we are already using the IRQ stack. |
134 |
++ */ |
135 |
++ move s1, sp # Preserve the sp |
136 |
++ |
137 |
++ /* Get IRQ stack for this CPU */ |
138 |
++ ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG |
139 |
++#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) |
140 |
++ lui k1, %hi(irq_stack) |
141 |
++#else |
142 |
++ lui k1, %highest(irq_stack) |
143 |
++ daddiu k1, %higher(irq_stack) |
144 |
++ dsll k1, 16 |
145 |
++ daddiu k1, %hi(irq_stack) |
146 |
++ dsll k1, 16 |
147 |
++#endif |
148 |
++ LONG_SRL k0, SMP_CPUID_PTRSHIFT |
149 |
++ LONG_ADDU k1, k0 |
150 |
++ LONG_L t0, %lo(irq_stack)(k1) |
151 |
++ |
152 |
++ # Check if already on IRQ stack |
153 |
++ PTR_LI t1, ~(_THREAD_SIZE-1) |
154 |
++ and t1, t1, sp |
155 |
++ beq t0, t1, 2f |
156 |
++ |
157 |
++ /* Switch to IRQ stack */ |
158 |
++ li t1, _IRQ_STACK_SIZE |
159 |
++ PTR_ADD sp, t0, t1 |
160 |
++ |
161 |
++2: |
162 |
++ jal plat_irq_dispatch |
163 |
++ |
164 |
++ /* Restore sp */ |
165 |
++ move sp, s1 |
166 |
++ |
167 |
++ j ret_from_irq |
168 |
+ #ifdef CONFIG_CPU_MICROMIPS |
169 |
+ nop |
170 |
+ #endif |
171 |
+@@ -263,8 +298,44 @@ NESTED(except_vec_vi_handler, 0, sp) |
172 |
+ |
173 |
+ LONG_L s0, TI_REGS($28) |
174 |
+ LONG_S sp, TI_REGS($28) |
175 |
+- PTR_LA ra, ret_from_irq |
176 |
+- jr v0 |
177 |
++ |
178 |
++ /* |
179 |
++ * SAVE_ALL ensures we are using a valid kernel stack for the thread. |
180 |
++ * Check if we are already using the IRQ stack. |
181 |
++ */ |
182 |
++ move s1, sp # Preserve the sp |
183 |
++ |
184 |
++ /* Get IRQ stack for this CPU */ |
185 |
++ ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG |
186 |
++#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) |
187 |
++ lui k1, %hi(irq_stack) |
188 |
++#else |
189 |
++ lui k1, %highest(irq_stack) |
190 |
++ daddiu k1, %higher(irq_stack) |
191 |
++ dsll k1, 16 |
192 |
++ daddiu k1, %hi(irq_stack) |
193 |
++ dsll k1, 16 |
194 |
++#endif |
195 |
++ LONG_SRL k0, SMP_CPUID_PTRSHIFT |
196 |
++ LONG_ADDU k1, k0 |
197 |
++ LONG_L t0, %lo(irq_stack)(k1) |
198 |
++ |
199 |
++ # Check if already on IRQ stack |
200 |
++ PTR_LI t1, ~(_THREAD_SIZE-1) |
201 |
++ and t1, t1, sp |
202 |
++ beq t0, t1, 2f |
203 |
++ |
204 |
++ /* Switch to IRQ stack */ |
205 |
++ li t1, _IRQ_STACK_SIZE |
206 |
++ PTR_ADD sp, t0, t1 |
207 |
++ |
208 |
++2: |
209 |
++ jalr v0 |
210 |
++ |
211 |
++ /* Restore sp */ |
212 |
++ move sp, s1 |
213 |
++ |
214 |
++ j ret_from_irq |
215 |
+ END(except_vec_vi_handler) |
216 |
+ |
217 |
+ /* |
218 |
+diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c |
219 |
+index 8eb5af805964..dc1180a8bfa1 100644 |
220 |
+--- a/arch/mips/kernel/irq.c |
221 |
++++ b/arch/mips/kernel/irq.c |
222 |
+@@ -25,6 +25,8 @@ |
223 |
+ #include <linux/atomic.h> |
224 |
+ #include <asm/uaccess.h> |
225 |
+ |
226 |
++void *irq_stack[NR_CPUS]; |
227 |
++ |
228 |
+ /* |
229 |
+ * 'what should we do if we get a hw irq event on an illegal vector'. |
230 |
+ * each architecture has to answer this themselves. |
231 |
+@@ -55,6 +57,15 @@ void __init init_IRQ(void) |
232 |
+ irq_set_noprobe(i); |
233 |
+ |
234 |
+ arch_init_irq(); |
235 |
++ |
236 |
++ for_each_possible_cpu(i) { |
237 |
++ int irq_pages = IRQ_STACK_SIZE / PAGE_SIZE; |
238 |
++ void *s = (void *)__get_free_pages(GFP_KERNEL, irq_pages); |
239 |
++ |
240 |
++ irq_stack[i] = s; |
241 |
++ pr_debug("CPU%d IRQ stack at 0x%p - 0x%p\n", i, |
242 |
++ irq_stack[i], irq_stack[i] + IRQ_STACK_SIZE); |
243 |
++ } |
244 |
+ } |
245 |
+ |
246 |
+ #ifdef CONFIG_DEBUG_STACKOVERFLOW |
247 |
+diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c |
248 |
+index fc537d1b649d..8c26ecac930d 100644 |
249 |
+--- a/arch/mips/kernel/process.c |
250 |
++++ b/arch/mips/kernel/process.c |
251 |
+@@ -32,6 +32,7 @@ |
252 |
+ #include <asm/cpu.h> |
253 |
+ #include <asm/dsp.h> |
254 |
+ #include <asm/fpu.h> |
255 |
++#include <asm/irq.h> |
256 |
+ #include <asm/msa.h> |
257 |
+ #include <asm/pgtable.h> |
258 |
+ #include <asm/mipsregs.h> |
259 |
+@@ -552,7 +553,19 @@ EXPORT_SYMBOL(unwind_stack_by_address); |
260 |
+ unsigned long unwind_stack(struct task_struct *task, unsigned long *sp, |
261 |
+ unsigned long pc, unsigned long *ra) |
262 |
+ { |
263 |
+- unsigned long stack_page = (unsigned long)task_stack_page(task); |
264 |
++ unsigned long stack_page = 0; |
265 |
++ int cpu; |
266 |
++ |
267 |
++ for_each_possible_cpu(cpu) { |
268 |
++ if (on_irq_stack(cpu, *sp)) { |
269 |
++ stack_page = (unsigned long)irq_stack[cpu]; |
270 |
++ break; |
271 |
++ } |
272 |
++ } |
273 |
++ |
274 |
++ if (!stack_page) |
275 |
++ stack_page = (unsigned long)task_stack_page(task); |
276 |
++ |
277 |
+ return unwind_stack_by_address(stack_page, sp, pc, ra); |
278 |
+ } |
279 |
+ #endif |
280 |
+diff --git a/block/blk-mq.c b/block/blk-mq.c |
281 |
+index d8d63c38bf29..0d1af3e44efb 100644 |
282 |
+--- a/block/blk-mq.c |
283 |
++++ b/block/blk-mq.c |
284 |
+@@ -1470,7 +1470,7 @@ static struct blk_mq_tags *blk_mq_init_rq_map(struct blk_mq_tag_set *set, |
285 |
+ INIT_LIST_HEAD(&tags->page_list); |
286 |
+ |
287 |
+ tags->rqs = kzalloc_node(set->queue_depth * sizeof(struct request *), |
288 |
+- GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY, |
289 |
++ GFP_NOIO | __GFP_NOWARN | __GFP_NORETRY, |
290 |
+ set->numa_node); |
291 |
+ if (!tags->rqs) { |
292 |
+ blk_mq_free_tags(tags); |
293 |
+@@ -1496,7 +1496,7 @@ static struct blk_mq_tags *blk_mq_init_rq_map(struct blk_mq_tag_set *set, |
294 |
+ |
295 |
+ do { |
296 |
+ page = alloc_pages_node(set->numa_node, |
297 |
+- GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY | __GFP_ZERO, |
298 |
++ GFP_NOIO | __GFP_NOWARN | __GFP_NORETRY | __GFP_ZERO, |
299 |
+ this_order); |
300 |
+ if (page) |
301 |
+ break; |
302 |
+@@ -1517,7 +1517,7 @@ static struct blk_mq_tags *blk_mq_init_rq_map(struct blk_mq_tag_set *set, |
303 |
+ * Allow kmemleak to scan these pages as they contain pointers |
304 |
+ * to additional allocations like via ops->init_request(). |
305 |
+ */ |
306 |
+- kmemleak_alloc(p, order_to_size(this_order), 1, GFP_KERNEL); |
307 |
++ kmemleak_alloc(p, order_to_size(this_order), 1, GFP_NOIO); |
308 |
+ entries_per_page = order_to_size(this_order) / rq_size; |
309 |
+ to_do = min(entries_per_page, set->queue_depth - i); |
310 |
+ left -= to_do * rq_size; |
311 |
+diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c |
312 |
+index 69d4a1326fee..53e61459c69f 100644 |
313 |
+--- a/drivers/crypto/caam/ctrl.c |
314 |
++++ b/drivers/crypto/caam/ctrl.c |
315 |
+@@ -278,7 +278,8 @@ static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask) |
316 |
+ /* Try to run it through DECO0 */ |
317 |
+ ret = run_descriptor_deco0(ctrldev, desc, &status); |
318 |
+ |
319 |
+- if (ret || status) { |
320 |
++ if (ret || |
321 |
++ (status && status != JRSTA_SSRC_JUMP_HALT_CC)) { |
322 |
+ dev_err(ctrldev, |
323 |
+ "Failed to deinstantiate RNG4 SH%d\n", |
324 |
+ sh_idx); |
325 |
+diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h |
326 |
+index fb9f647bb5cd..5044f2257e89 100644 |
327 |
+--- a/drivers/gpu/drm/i915/i915_drv.h |
328 |
++++ b/drivers/gpu/drm/i915/i915_drv.h |
329 |
+@@ -1159,7 +1159,7 @@ struct intel_gen6_power_mgmt { |
330 |
+ struct intel_rps_client semaphores, mmioflips; |
331 |
+ |
332 |
+ /* manual wa residency calculations */ |
333 |
+- struct intel_rps_ei up_ei, down_ei; |
334 |
++ struct intel_rps_ei ei; |
335 |
+ |
336 |
+ /* |
337 |
+ * Protects RPS/RC6 register access and PCU communication. |
338 |
+diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c |
339 |
+index 0f42a2782afc..b7b0a38acd67 100644 |
340 |
+--- a/drivers/gpu/drm/i915/i915_irq.c |
341 |
++++ b/drivers/gpu/drm/i915/i915_irq.c |
342 |
+@@ -994,68 +994,51 @@ static void vlv_c0_read(struct drm_i915_private *dev_priv, |
343 |
+ ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT); |
344 |
+ } |
345 |
+ |
346 |
+-static bool vlv_c0_above(struct drm_i915_private *dev_priv, |
347 |
+- const struct intel_rps_ei *old, |
348 |
+- const struct intel_rps_ei *now, |
349 |
+- int threshold) |
350 |
+-{ |
351 |
+- u64 time, c0; |
352 |
+- unsigned int mul = 100; |
353 |
+- |
354 |
+- if (old->cz_clock == 0) |
355 |
+- return false; |
356 |
+- |
357 |
+- if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) |
358 |
+- mul <<= 8; |
359 |
+- |
360 |
+- time = now->cz_clock - old->cz_clock; |
361 |
+- time *= threshold * dev_priv->czclk_freq; |
362 |
+- |
363 |
+- /* Workload can be split between render + media, e.g. SwapBuffers |
364 |
+- * being blitted in X after being rendered in mesa. To account for |
365 |
+- * this we need to combine both engines into our activity counter. |
366 |
+- */ |
367 |
+- c0 = now->render_c0 - old->render_c0; |
368 |
+- c0 += now->media_c0 - old->media_c0; |
369 |
+- c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC; |
370 |
+- |
371 |
+- return c0 >= time; |
372 |
+-} |
373 |
+- |
374 |
+ void gen6_rps_reset_ei(struct drm_i915_private *dev_priv) |
375 |
+ { |
376 |
+- vlv_c0_read(dev_priv, &dev_priv->rps.down_ei); |
377 |
+- dev_priv->rps.up_ei = dev_priv->rps.down_ei; |
378 |
++ memset(&dev_priv->rps.ei, 0, sizeof(dev_priv->rps.ei)); |
379 |
+ } |
380 |
+ |
381 |
+ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) |
382 |
+ { |
383 |
++ const struct intel_rps_ei *prev = &dev_priv->rps.ei; |
384 |
+ struct intel_rps_ei now; |
385 |
+ u32 events = 0; |
386 |
+ |
387 |
+- if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0) |
388 |
++ if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0) |
389 |
+ return 0; |
390 |
+ |
391 |
+ vlv_c0_read(dev_priv, &now); |
392 |
+ if (now.cz_clock == 0) |
393 |
+ return 0; |
394 |
+ |
395 |
+- if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) { |
396 |
+- if (!vlv_c0_above(dev_priv, |
397 |
+- &dev_priv->rps.down_ei, &now, |
398 |
+- dev_priv->rps.down_threshold)) |
399 |
+- events |= GEN6_PM_RP_DOWN_THRESHOLD; |
400 |
+- dev_priv->rps.down_ei = now; |
401 |
+- } |
402 |
++ if (prev->cz_clock) { |
403 |
++ u64 time, c0; |
404 |
++ unsigned int mul; |
405 |
+ |
406 |
+- if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { |
407 |
+- if (vlv_c0_above(dev_priv, |
408 |
+- &dev_priv->rps.up_ei, &now, |
409 |
+- dev_priv->rps.up_threshold)) |
410 |
+- events |= GEN6_PM_RP_UP_THRESHOLD; |
411 |
+- dev_priv->rps.up_ei = now; |
412 |
++ mul = VLV_CZ_CLOCK_TO_MILLI_SEC * 100; /* scale to threshold% */ |
413 |
++ if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) |
414 |
++ mul <<= 8; |
415 |
++ |
416 |
++ time = now.cz_clock - prev->cz_clock; |
417 |
++ time *= dev_priv->czclk_freq; |
418 |
++ |
419 |
++ /* Workload can be split between render + media, |
420 |
++ * e.g. SwapBuffers being blitted in X after being rendered in |
421 |
++ * mesa. To account for this we need to combine both engines |
422 |
++ * into our activity counter. |
423 |
++ */ |
424 |
++ c0 = now.render_c0 - prev->render_c0; |
425 |
++ c0 += now.media_c0 - prev->media_c0; |
426 |
++ c0 *= mul; |
427 |
++ |
428 |
++ if (c0 > time * dev_priv->rps.up_threshold) |
429 |
++ events = GEN6_PM_RP_UP_THRESHOLD; |
430 |
++ else if (c0 < time * dev_priv->rps.down_threshold) |
431 |
++ events = GEN6_PM_RP_DOWN_THRESHOLD; |
432 |
+ } |
433 |
+ |
434 |
++ dev_priv->rps.ei = now; |
435 |
+ return events; |
436 |
+ } |
437 |
+ |
438 |
+@@ -4390,7 +4373,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) |
439 |
+ /* Let's track the enabled rps events */ |
440 |
+ if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
441 |
+ /* WaGsvRC0ResidencyMethod:vlv */ |
442 |
+- dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED; |
443 |
++ dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; |
444 |
+ else |
445 |
+ dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; |
446 |
+ |
447 |
+diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c |
448 |
+index e7c18519274a..fd4690ed93c0 100644 |
449 |
+--- a/drivers/gpu/drm/i915/intel_pm.c |
450 |
++++ b/drivers/gpu/drm/i915/intel_pm.c |
451 |
+@@ -4376,6 +4376,12 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
452 |
+ break; |
453 |
+ } |
454 |
+ |
455 |
++ /* When byt can survive without system hang with dynamic |
456 |
++ * sw freq adjustments, this restriction can be lifted. |
457 |
++ */ |
458 |
++ if (IS_VALLEYVIEW(dev_priv)) |
459 |
++ goto skip_hw_write; |
460 |
++ |
461 |
+ I915_WRITE(GEN6_RP_UP_EI, |
462 |
+ GT_INTERVAL_FROM_US(dev_priv, ei_up)); |
463 |
+ I915_WRITE(GEN6_RP_UP_THRESHOLD, |
464 |
+@@ -4394,6 +4400,7 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
465 |
+ GEN6_RP_UP_BUSY_AVG | |
466 |
+ GEN6_RP_DOWN_IDLE_AVG); |
467 |
+ |
468 |
++skip_hw_write: |
469 |
+ dev_priv->rps.power = new_power; |
470 |
+ dev_priv->rps.up_threshold = threshold_up; |
471 |
+ dev_priv->rps.down_threshold = threshold_down; |
472 |
+@@ -4404,8 +4411,9 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
473 |
+ { |
474 |
+ u32 mask = 0; |
475 |
+ |
476 |
++ /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */ |
477 |
+ if (val > dev_priv->rps.min_freq_softlimit) |
478 |
+- mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; |
479 |
++ mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; |
480 |
+ if (val < dev_priv->rps.max_freq_softlimit) |
481 |
+ mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; |
482 |
+ |
483 |
+@@ -4509,7 +4517,7 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv) |
484 |
+ { |
485 |
+ mutex_lock(&dev_priv->rps.hw_lock); |
486 |
+ if (dev_priv->rps.enabled) { |
487 |
+- if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) |
488 |
++ if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED) |
489 |
+ gen6_rps_reset_ei(dev_priv); |
490 |
+ I915_WRITE(GEN6_PMINTRMSK, |
491 |
+ gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); |
492 |
+diff --git a/drivers/mtd/bcm47xxpart.c b/drivers/mtd/bcm47xxpart.c |
493 |
+index c0720c1ee4c9..5abab8800891 100644 |
494 |
+--- a/drivers/mtd/bcm47xxpart.c |
495 |
++++ b/drivers/mtd/bcm47xxpart.c |
496 |
+@@ -225,12 +225,10 @@ static int bcm47xxpart_parse(struct mtd_info *master, |
497 |
+ |
498 |
+ last_trx_part = curr_part - 1; |
499 |
+ |
500 |
+- /* |
501 |
+- * We have whole TRX scanned, skip to the next part. Use |
502 |
+- * roundown (not roundup), as the loop will increase |
503 |
+- * offset in next step. |
504 |
+- */ |
505 |
+- offset = rounddown(offset + trx->length, blocksize); |
506 |
++ /* Jump to the end of TRX */ |
507 |
++ offset = roundup(offset + trx->length, blocksize); |
508 |
++ /* Next loop iteration will increase the offset */ |
509 |
++ offset -= blocksize; |
510 |
+ continue; |
511 |
+ } |
512 |
+ |
513 |
+diff --git a/drivers/net/ethernet/ibm/ibmveth.c b/drivers/net/ethernet/ibm/ibmveth.c |
514 |
+index 7af870a3c549..855c43d8f7e0 100644 |
515 |
+--- a/drivers/net/ethernet/ibm/ibmveth.c |
516 |
++++ b/drivers/net/ethernet/ibm/ibmveth.c |
517 |
+@@ -58,7 +58,7 @@ static struct kobj_type ktype_veth_pool; |
518 |
+ |
519 |
+ static const char ibmveth_driver_name[] = "ibmveth"; |
520 |
+ static const char ibmveth_driver_string[] = "IBM Power Virtual Ethernet Driver"; |
521 |
+-#define ibmveth_driver_version "1.05" |
522 |
++#define ibmveth_driver_version "1.06" |
523 |
+ |
524 |
+ MODULE_AUTHOR("Santiago Leon <santil@××××××××××××××.com>"); |
525 |
+ MODULE_DESCRIPTION("IBM Power Virtual Ethernet Driver"); |
526 |
+@@ -137,6 +137,11 @@ static inline int ibmveth_rxq_frame_offset(struct ibmveth_adapter *adapter) |
527 |
+ return ibmveth_rxq_flags(adapter) & IBMVETH_RXQ_OFF_MASK; |
528 |
+ } |
529 |
+ |
530 |
++static inline int ibmveth_rxq_large_packet(struct ibmveth_adapter *adapter) |
531 |
++{ |
532 |
++ return ibmveth_rxq_flags(adapter) & IBMVETH_RXQ_LRG_PKT; |
533 |
++} |
534 |
++ |
535 |
+ static inline int ibmveth_rxq_frame_length(struct ibmveth_adapter *adapter) |
536 |
+ { |
537 |
+ return be32_to_cpu(adapter->rx_queue.queue_addr[adapter->rx_queue.index].length); |
538 |
+@@ -1172,6 +1177,45 @@ map_failed: |
539 |
+ goto retry_bounce; |
540 |
+ } |
541 |
+ |
542 |
++static void ibmveth_rx_mss_helper(struct sk_buff *skb, u16 mss, int lrg_pkt) |
543 |
++{ |
544 |
++ int offset = 0; |
545 |
++ |
546 |
++ /* only TCP packets will be aggregated */ |
547 |
++ if (skb->protocol == htons(ETH_P_IP)) { |
548 |
++ struct iphdr *iph = (struct iphdr *)skb->data; |
549 |
++ |
550 |
++ if (iph->protocol == IPPROTO_TCP) { |
551 |
++ offset = iph->ihl * 4; |
552 |
++ skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; |
553 |
++ } else { |
554 |
++ return; |
555 |
++ } |
556 |
++ } else if (skb->protocol == htons(ETH_P_IPV6)) { |
557 |
++ struct ipv6hdr *iph6 = (struct ipv6hdr *)skb->data; |
558 |
++ |
559 |
++ if (iph6->nexthdr == IPPROTO_TCP) { |
560 |
++ offset = sizeof(struct ipv6hdr); |
561 |
++ skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; |
562 |
++ } else { |
563 |
++ return; |
564 |
++ } |
565 |
++ } else { |
566 |
++ return; |
567 |
++ } |
568 |
++ /* if mss is not set through Large Packet bit/mss in rx buffer, |
569 |
++ * expect that the mss will be written to the tcp header checksum. |
570 |
++ */ |
571 |
++ if (lrg_pkt) { |
572 |
++ skb_shinfo(skb)->gso_size = mss; |
573 |
++ } else if (offset) { |
574 |
++ struct tcphdr *tcph = (struct tcphdr *)(skb->data + offset); |
575 |
++ |
576 |
++ skb_shinfo(skb)->gso_size = ntohs(tcph->check); |
577 |
++ tcph->check = 0; |
578 |
++ } |
579 |
++} |
580 |
++ |
581 |
+ static int ibmveth_poll(struct napi_struct *napi, int budget) |
582 |
+ { |
583 |
+ struct ibmveth_adapter *adapter = |
584 |
+@@ -1180,6 +1224,7 @@ static int ibmveth_poll(struct napi_struct *napi, int budget) |
585 |
+ int frames_processed = 0; |
586 |
+ unsigned long lpar_rc; |
587 |
+ struct iphdr *iph; |
588 |
++ u16 mss = 0; |
589 |
+ |
590 |
+ restart_poll: |
591 |
+ while (frames_processed < budget) { |
592 |
+@@ -1197,9 +1242,21 @@ restart_poll: |
593 |
+ int length = ibmveth_rxq_frame_length(adapter); |
594 |
+ int offset = ibmveth_rxq_frame_offset(adapter); |
595 |
+ int csum_good = ibmveth_rxq_csum_good(adapter); |
596 |
++ int lrg_pkt = ibmveth_rxq_large_packet(adapter); |
597 |
+ |
598 |
+ skb = ibmveth_rxq_get_buffer(adapter); |
599 |
+ |
600 |
++ /* if the large packet bit is set in the rx queue |
601 |
++ * descriptor, the mss will be written by PHYP eight |
602 |
++ * bytes from the start of the rx buffer, which is |
603 |
++ * skb->data at this stage |
604 |
++ */ |
605 |
++ if (lrg_pkt) { |
606 |
++ __be64 *rxmss = (__be64 *)(skb->data + 8); |
607 |
++ |
608 |
++ mss = (u16)be64_to_cpu(*rxmss); |
609 |
++ } |
610 |
++ |
611 |
+ new_skb = NULL; |
612 |
+ if (length < rx_copybreak) |
613 |
+ new_skb = netdev_alloc_skb(netdev, length); |
614 |
+@@ -1233,11 +1290,15 @@ restart_poll: |
615 |
+ if (iph->check == 0xffff) { |
616 |
+ iph->check = 0; |
617 |
+ iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl); |
618 |
+- adapter->rx_large_packets++; |
619 |
+ } |
620 |
+ } |
621 |
+ } |
622 |
+ |
623 |
++ if (length > netdev->mtu + ETH_HLEN) { |
624 |
++ ibmveth_rx_mss_helper(skb, mss, lrg_pkt); |
625 |
++ adapter->rx_large_packets++; |
626 |
++ } |
627 |
++ |
628 |
+ napi_gro_receive(napi, skb); /* send it up */ |
629 |
+ |
630 |
+ netdev->stats.rx_packets++; |
631 |
+diff --git a/drivers/net/ethernet/ibm/ibmveth.h b/drivers/net/ethernet/ibm/ibmveth.h |
632 |
+index 4eade67fe30c..7acda04d034e 100644 |
633 |
+--- a/drivers/net/ethernet/ibm/ibmveth.h |
634 |
++++ b/drivers/net/ethernet/ibm/ibmveth.h |
635 |
+@@ -209,6 +209,7 @@ struct ibmveth_rx_q_entry { |
636 |
+ #define IBMVETH_RXQ_TOGGLE 0x80000000 |
637 |
+ #define IBMVETH_RXQ_TOGGLE_SHIFT 31 |
638 |
+ #define IBMVETH_RXQ_VALID 0x40000000 |
639 |
++#define IBMVETH_RXQ_LRG_PKT 0x04000000 |
640 |
+ #define IBMVETH_RXQ_NO_CSUM 0x02000000 |
641 |
+ #define IBMVETH_RXQ_CSUM_GOOD 0x01000000 |
642 |
+ #define IBMVETH_RXQ_OFF_MASK 0x0000FFFF |
643 |
+diff --git a/drivers/net/ethernet/mellanox/mlx4/cq.c b/drivers/net/ethernet/mellanox/mlx4/cq.c |
644 |
+index 3348e646db70..6eba58044456 100644 |
645 |
+--- a/drivers/net/ethernet/mellanox/mlx4/cq.c |
646 |
++++ b/drivers/net/ethernet/mellanox/mlx4/cq.c |
647 |
+@@ -101,13 +101,19 @@ void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn) |
648 |
+ { |
649 |
+ struct mlx4_cq *cq; |
650 |
+ |
651 |
++ rcu_read_lock(); |
652 |
+ cq = radix_tree_lookup(&mlx4_priv(dev)->cq_table.tree, |
653 |
+ cqn & (dev->caps.num_cqs - 1)); |
654 |
++ rcu_read_unlock(); |
655 |
++ |
656 |
+ if (!cq) { |
657 |
+ mlx4_dbg(dev, "Completion event for bogus CQ %08x\n", cqn); |
658 |
+ return; |
659 |
+ } |
660 |
+ |
661 |
++ /* Acessing the CQ outside of rcu_read_lock is safe, because |
662 |
++ * the CQ is freed only after interrupt handling is completed. |
663 |
++ */ |
664 |
+ ++cq->arm_sn; |
665 |
+ |
666 |
+ cq->comp(cq); |
667 |
+@@ -118,23 +124,19 @@ void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type) |
668 |
+ struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table; |
669 |
+ struct mlx4_cq *cq; |
670 |
+ |
671 |
+- spin_lock(&cq_table->lock); |
672 |
+- |
673 |
++ rcu_read_lock(); |
674 |
+ cq = radix_tree_lookup(&cq_table->tree, cqn & (dev->caps.num_cqs - 1)); |
675 |
+- if (cq) |
676 |
+- atomic_inc(&cq->refcount); |
677 |
+- |
678 |
+- spin_unlock(&cq_table->lock); |
679 |
++ rcu_read_unlock(); |
680 |
+ |
681 |
+ if (!cq) { |
682 |
+- mlx4_warn(dev, "Async event for bogus CQ %08x\n", cqn); |
683 |
++ mlx4_dbg(dev, "Async event for bogus CQ %08x\n", cqn); |
684 |
+ return; |
685 |
+ } |
686 |
+ |
687 |
++ /* Acessing the CQ outside of rcu_read_lock is safe, because |
688 |
++ * the CQ is freed only after interrupt handling is completed. |
689 |
++ */ |
690 |
+ cq->event(cq, event_type); |
691 |
+- |
692 |
+- if (atomic_dec_and_test(&cq->refcount)) |
693 |
+- complete(&cq->free); |
694 |
+ } |
695 |
+ |
696 |
+ static int mlx4_SW2HW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, |
697 |
+@@ -301,9 +303,9 @@ int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, |
698 |
+ if (err) |
699 |
+ return err; |
700 |
+ |
701 |
+- spin_lock_irq(&cq_table->lock); |
702 |
++ spin_lock(&cq_table->lock); |
703 |
+ err = radix_tree_insert(&cq_table->tree, cq->cqn, cq); |
704 |
+- spin_unlock_irq(&cq_table->lock); |
705 |
++ spin_unlock(&cq_table->lock); |
706 |
+ if (err) |
707 |
+ goto err_icm; |
708 |
+ |
709 |
+@@ -347,9 +349,9 @@ int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, |
710 |
+ return 0; |
711 |
+ |
712 |
+ err_radix: |
713 |
+- spin_lock_irq(&cq_table->lock); |
714 |
++ spin_lock(&cq_table->lock); |
715 |
+ radix_tree_delete(&cq_table->tree, cq->cqn); |
716 |
+- spin_unlock_irq(&cq_table->lock); |
717 |
++ spin_unlock(&cq_table->lock); |
718 |
+ |
719 |
+ err_icm: |
720 |
+ mlx4_cq_free_icm(dev, cq->cqn); |
721 |
+@@ -368,15 +370,15 @@ void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq) |
722 |
+ if (err) |
723 |
+ mlx4_warn(dev, "HW2SW_CQ failed (%d) for CQN %06x\n", err, cq->cqn); |
724 |
+ |
725 |
++ spin_lock(&cq_table->lock); |
726 |
++ radix_tree_delete(&cq_table->tree, cq->cqn); |
727 |
++ spin_unlock(&cq_table->lock); |
728 |
++ |
729 |
+ synchronize_irq(priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq->vector)].irq); |
730 |
+ if (priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq->vector)].irq != |
731 |
+ priv->eq_table.eq[MLX4_EQ_ASYNC].irq) |
732 |
+ synchronize_irq(priv->eq_table.eq[MLX4_EQ_ASYNC].irq); |
733 |
+ |
734 |
+- spin_lock_irq(&cq_table->lock); |
735 |
+- radix_tree_delete(&cq_table->tree, cq->cqn); |
736 |
+- spin_unlock_irq(&cq_table->lock); |
737 |
+- |
738 |
+ if (atomic_dec_and_test(&cq->refcount)) |
739 |
+ complete(&cq->free); |
740 |
+ wait_for_completion(&cq->free); |
741 |
+diff --git a/drivers/net/ethernet/mellanox/mlx4/en_rx.c b/drivers/net/ethernet/mellanox/mlx4/en_rx.c |
742 |
+index 28a4b34310b2..82bf1b539d87 100644 |
743 |
+--- a/drivers/net/ethernet/mellanox/mlx4/en_rx.c |
744 |
++++ b/drivers/net/ethernet/mellanox/mlx4/en_rx.c |
745 |
+@@ -439,8 +439,14 @@ int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) |
746 |
+ ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn; |
747 |
+ |
748 |
+ ring->stride = stride; |
749 |
+- if (ring->stride <= TXBB_SIZE) |
750 |
++ if (ring->stride <= TXBB_SIZE) { |
751 |
++ /* Stamp first unused send wqe */ |
752 |
++ __be32 *ptr = (__be32 *)ring->buf; |
753 |
++ __be32 stamp = cpu_to_be32(1 << STAMP_SHIFT); |
754 |
++ *ptr = stamp; |
755 |
++ /* Move pointer to start of rx section */ |
756 |
+ ring->buf += TXBB_SIZE; |
757 |
++ } |
758 |
+ |
759 |
+ ring->log_stride = ffs(ring->stride) - 1; |
760 |
+ ring->buf_size = ring->size * ring->stride; |
761 |
+diff --git a/drivers/net/ethernet/mellanox/mlx4/resource_tracker.c b/drivers/net/ethernet/mellanox/mlx4/resource_tracker.c |
762 |
+index d314d96dcb1c..d1fc7fa87b05 100644 |
763 |
+--- a/drivers/net/ethernet/mellanox/mlx4/resource_tracker.c |
764 |
++++ b/drivers/net/ethernet/mellanox/mlx4/resource_tracker.c |
765 |
+@@ -2955,6 +2955,9 @@ int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, |
766 |
+ put_res(dev, slave, srqn, RES_SRQ); |
767 |
+ qp->srq = srq; |
768 |
+ } |
769 |
++ |
770 |
++ /* Save param3 for dynamic changes from VST back to VGT */ |
771 |
++ qp->param3 = qpc->param3; |
772 |
+ put_res(dev, slave, rcqn, RES_CQ); |
773 |
+ put_res(dev, slave, mtt_base, RES_MTT); |
774 |
+ res_end_move(dev, slave, RES_QP, qpn); |
775 |
+@@ -3747,7 +3750,6 @@ int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, |
776 |
+ int qpn = vhcr->in_modifier & 0x7fffff; |
777 |
+ struct res_qp *qp; |
778 |
+ u8 orig_sched_queue; |
779 |
+- __be32 orig_param3 = qpc->param3; |
780 |
+ u8 orig_vlan_control = qpc->pri_path.vlan_control; |
781 |
+ u8 orig_fvl_rx = qpc->pri_path.fvl_rx; |
782 |
+ u8 orig_pri_path_fl = qpc->pri_path.fl; |
783 |
+@@ -3789,7 +3791,6 @@ out: |
784 |
+ */ |
785 |
+ if (!err) { |
786 |
+ qp->sched_queue = orig_sched_queue; |
787 |
+- qp->param3 = orig_param3; |
788 |
+ qp->vlan_control = orig_vlan_control; |
789 |
+ qp->fvl_rx = orig_fvl_rx; |
790 |
+ qp->pri_path_fl = orig_pri_path_fl; |
791 |
+diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c |
792 |
+index 9e62c93af96e..7c2d87befb51 100644 |
793 |
+--- a/drivers/usb/core/hub.c |
794 |
++++ b/drivers/usb/core/hub.c |
795 |
+@@ -2602,8 +2602,15 @@ static int hub_port_wait_reset(struct usb_hub *hub, int port1, |
796 |
+ if (ret < 0) |
797 |
+ return ret; |
798 |
+ |
799 |
+- /* The port state is unknown until the reset completes. */ |
800 |
+- if (!(portstatus & USB_PORT_STAT_RESET)) |
801 |
++ /* |
802 |
++ * The port state is unknown until the reset completes. |
803 |
++ * |
804 |
++ * On top of that, some chips may require additional time |
805 |
++ * to re-establish a connection after the reset is complete, |
806 |
++ * so also wait for the connection to be re-established. |
807 |
++ */ |
808 |
++ if (!(portstatus & USB_PORT_STAT_RESET) && |
809 |
++ (portstatus & USB_PORT_STAT_CONNECTION)) |
810 |
+ break; |
811 |
+ |
812 |
+ /* switch to the long delay after two short delay failures */ |
813 |
+diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c |
814 |
+index 210ff64857e1..ec7a50f98f57 100644 |
815 |
+--- a/drivers/usb/dwc3/gadget.c |
816 |
++++ b/drivers/usb/dwc3/gadget.c |
817 |
+@@ -235,6 +235,7 @@ void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, |
818 |
+ int status) |
819 |
+ { |
820 |
+ struct dwc3 *dwc = dep->dwc; |
821 |
++ unsigned int unmap_after_complete = false; |
822 |
+ int i; |
823 |
+ |
824 |
+ if (req->queued) { |
825 |
+@@ -259,11 +260,19 @@ void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, |
826 |
+ if (req->request.status == -EINPROGRESS) |
827 |
+ req->request.status = status; |
828 |
+ |
829 |
+- if (dwc->ep0_bounced && dep->number <= 1) |
830 |
++ /* |
831 |
++ * NOTICE we don't want to unmap before calling ->complete() if we're |
832 |
++ * dealing with a bounced ep0 request. If we unmap it here, we would end |
833 |
++ * up overwritting the contents of req->buf and this could confuse the |
834 |
++ * gadget driver. |
835 |
++ */ |
836 |
++ if (dwc->ep0_bounced && dep->number <= 1) { |
837 |
+ dwc->ep0_bounced = false; |
838 |
+- |
839 |
+- usb_gadget_unmap_request(&dwc->gadget, &req->request, |
840 |
+- req->direction); |
841 |
++ unmap_after_complete = true; |
842 |
++ } else { |
843 |
++ usb_gadget_unmap_request(&dwc->gadget, |
844 |
++ &req->request, req->direction); |
845 |
++ } |
846 |
+ |
847 |
+ dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", |
848 |
+ req, dep->name, req->request.actual, |
849 |
+@@ -273,6 +282,10 @@ void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, |
850 |
+ spin_unlock(&dwc->lock); |
851 |
+ usb_gadget_giveback_request(&dep->endpoint, &req->request); |
852 |
+ spin_lock(&dwc->lock); |
853 |
++ |
854 |
++ if (unmap_after_complete) |
855 |
++ usb_gadget_unmap_request(&dwc->gadget, |
856 |
++ &req->request, req->direction); |
857 |
+ } |
858 |
+ |
859 |
+ int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param) |
860 |
+diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c |
861 |
+index 3975ac809934..d76800108ddb 100644 |
862 |
+--- a/net/packet/af_packet.c |
863 |
++++ b/net/packet/af_packet.c |
864 |
+@@ -4138,8 +4138,8 @@ static int packet_set_ring(struct sock *sk, union tpacket_req_u *req_u, |
865 |
+ if (unlikely(!PAGE_ALIGNED(req->tp_block_size))) |
866 |
+ goto out; |
867 |
+ if (po->tp_version >= TPACKET_V3 && |
868 |
+- (int)(req->tp_block_size - |
869 |
+- BLK_PLUS_PRIV(req_u->req3.tp_sizeof_priv)) <= 0) |
870 |
++ req->tp_block_size <= |
871 |
++ BLK_PLUS_PRIV((u64)req_u->req3.tp_sizeof_priv)) |
872 |
+ goto out; |
873 |
+ if (unlikely(req->tp_frame_size < po->tp_hdrlen + |
874 |
+ po->tp_reserve)) |