[gentoo-commits] proj/linux-patches:4.10 commit in: /

[Mike Pagano]

commit:     4e0e4f1029afd27b8bf7999371ce7d817c11d73a
Author:     Mike Pagano <mpagano <AT> gentoo <DOT> org>
AuthorDate: Tue Apr 18 10:23:49 2017 +0000
Commit:     Mike Pagano <mpagano <AT> gentoo <DOT> org>
CommitDate: Tue Apr 18 10:23:49 2017 +0000
URL:        https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=4e0e4f10

Linux patch 4.10.11

 0000_README              |    4 +
 1010_linux-4.10.11.patch | 1128 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 1132 insertions(+)

diff --git a/0000_README b/0000_README
index abc6f43..f05d7f1 100644
--- a/0000_README
+++ b/0000_README
@@ -83,6 +83,10 @@ Patch:  1009_linux-4.10.10.patch
 From:   http://www.kernel.org
 Desc:   Linux 4.10.10
 
+Patch:  1010_linux-4.10.11.patch
+From:   http://www.kernel.org
+Desc:   Linux 4.10.11
+
 Patch:  1500_XATTR_USER_PREFIX.patch
 From:   https://bugs.gentoo.org/show_bug.cgi?id=470644
 Desc:   Support for namespace user.pax.* on tmpfs.

diff --git a/1010_linux-4.10.11.patch b/1010_linux-4.10.11.patch
new file mode 100644
index 0000000..ac7bb4e
--- /dev/null
+++ b/1010_linux-4.10.11.patch
@@ -0,0 +1,1128 @@
+diff --git a/Makefile b/Makefile
+index 52858726495b..412f2a0a3814 100644
+--- a/Makefile
++++ b/Makefile
+@@ -1,6 +1,6 @@
+ VERSION = 4
+ PATCHLEVEL = 10
+-SUBLEVEL = 10
++SUBLEVEL = 11
+ EXTRAVERSION =
+ NAME = Fearless Coyote
+ 
+diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
+index 9a6e11b6f457..5a4f2eb9d0d5 100644
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -9,6 +9,7 @@ config MIPS
+ 	select HAVE_CONTEXT_TRACKING
+ 	select HAVE_GENERIC_DMA_COHERENT
+ 	select HAVE_IDE
++	select HAVE_IRQ_EXIT_ON_IRQ_STACK
+ 	select HAVE_OPROFILE
+ 	select HAVE_PERF_EVENTS
+ 	select PERF_USE_VMALLOC
+diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
+index 6bf10e796553..956db6e201d1 100644
+--- a/arch/mips/include/asm/irq.h
++++ b/arch/mips/include/asm/irq.h
+@@ -17,6 +17,18 @@
+ 
+ #include <irq.h>
+ 
++#define IRQ_STACK_SIZE			THREAD_SIZE
++
++extern void *irq_stack[NR_CPUS];
++
++static inline bool on_irq_stack(int cpu, unsigned long sp)
++{
++	unsigned long low = (unsigned long)irq_stack[cpu];
++	unsigned long high = low + IRQ_STACK_SIZE;
++
++	return (low <= sp && sp <= high);
++}
++
+ #ifdef CONFIG_I8259
+ static inline int irq_canonicalize(int irq)
+ {
+diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
+index eebf39549606..2f182bdf024f 100644
+--- a/arch/mips/include/asm/stackframe.h
++++ b/arch/mips/include/asm/stackframe.h
+@@ -216,12 +216,19 @@
+ 		LONG_S	$25, PT_R25(sp)
+ 		LONG_S	$28, PT_R28(sp)
+ 		LONG_S	$31, PT_R31(sp)
++
++		/* Set thread_info if we're coming from user mode */
++		mfc0	k0, CP0_STATUS
++		sll	k0, 3		/* extract cu0 bit */
++		bltz	k0, 9f
++
+ 		ori	$28, sp, _THREAD_MASK
+ 		xori	$28, _THREAD_MASK
+ #ifdef CONFIG_CPU_CAVIUM_OCTEON
+ 		.set    mips64
+ 		pref    0, 0($28)       /* Prefetch the current pointer */
+ #endif
++9:
+ 		.set	pop
+ 		.endm
+ 
+diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
+index 6080582a26d1..a7277698d328 100644
+--- a/arch/mips/kernel/asm-offsets.c
++++ b/arch/mips/kernel/asm-offsets.c
+@@ -102,6 +102,7 @@ void output_thread_info_defines(void)
+ 	OFFSET(TI_REGS, thread_info, regs);
+ 	DEFINE(_THREAD_SIZE, THREAD_SIZE);
+ 	DEFINE(_THREAD_MASK, THREAD_MASK);
++	DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE);
+ 	BLANK();
+ }
+ 
+diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
+index 52a4fdfc8513..2ac6c2625c13 100644
+--- a/arch/mips/kernel/genex.S
++++ b/arch/mips/kernel/genex.S
+@@ -187,9 +187,44 @@ NESTED(handle_int, PT_SIZE, sp)
+ 
+ 	LONG_L	s0, TI_REGS($28)
+ 	LONG_S	sp, TI_REGS($28)
+-	PTR_LA	ra, ret_from_irq
+-	PTR_LA	v0, plat_irq_dispatch
+-	jr	v0
++
++	/*
++	 * SAVE_ALL ensures we are using a valid kernel stack for the thread.
++	 * Check if we are already using the IRQ stack.
++	 */
++	move	s1, sp # Preserve the sp
++
++	/* Get IRQ stack for this CPU */
++	ASM_CPUID_MFC0	k0, ASM_SMP_CPUID_REG
++#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
++	lui	k1, %hi(irq_stack)
++#else
++	lui	k1, %highest(irq_stack)
++	daddiu	k1, %higher(irq_stack)
++	dsll	k1, 16
++	daddiu	k1, %hi(irq_stack)
++	dsll	k1, 16
++#endif
++	LONG_SRL	k0, SMP_CPUID_PTRSHIFT
++	LONG_ADDU	k1, k0
++	LONG_L	t0, %lo(irq_stack)(k1)
++
++	# Check if already on IRQ stack
++	PTR_LI	t1, ~(_THREAD_SIZE-1)
++	and	t1, t1, sp
++	beq	t0, t1, 2f
++
++	/* Switch to IRQ stack */
++	li	t1, _IRQ_STACK_SIZE
++	PTR_ADD sp, t0, t1
++
++2:
++	jal	plat_irq_dispatch
++
++	/* Restore sp */
++	move	sp, s1
++
++	j	ret_from_irq
+ #ifdef CONFIG_CPU_MICROMIPS
+ 	nop
+ #endif
+@@ -262,8 +297,44 @@ NESTED(except_vec_vi_handler, 0, sp)
+ 
+ 	LONG_L	s0, TI_REGS($28)
+ 	LONG_S	sp, TI_REGS($28)
+-	PTR_LA	ra, ret_from_irq
+-	jr	v0
++
++	/*
++	 * SAVE_ALL ensures we are using a valid kernel stack for the thread.
++	 * Check if we are already using the IRQ stack.
++	 */
++	move	s1, sp # Preserve the sp
++
++	/* Get IRQ stack for this CPU */
++	ASM_CPUID_MFC0	k0, ASM_SMP_CPUID_REG
++#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
++	lui	k1, %hi(irq_stack)
++#else
++	lui	k1, %highest(irq_stack)
++	daddiu	k1, %higher(irq_stack)
++	dsll	k1, 16
++	daddiu	k1, %hi(irq_stack)
++	dsll	k1, 16
++#endif
++	LONG_SRL	k0, SMP_CPUID_PTRSHIFT
++	LONG_ADDU	k1, k0
++	LONG_L	t0, %lo(irq_stack)(k1)
++
++	# Check if already on IRQ stack
++	PTR_LI	t1, ~(_THREAD_SIZE-1)
++	and	t1, t1, sp
++	beq	t0, t1, 2f
++
++	/* Switch to IRQ stack */
++	li	t1, _IRQ_STACK_SIZE
++	PTR_ADD sp, t0, t1
++
++2:
++	jalr	v0
++
++	/* Restore sp */
++	move	sp, s1
++
++	j	ret_from_irq
+ 	END(except_vec_vi_handler)
+ 
+ /*
+diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
+index f8f5836eb3c1..ba150c755fcc 100644
+--- a/arch/mips/kernel/irq.c
++++ b/arch/mips/kernel/irq.c
+@@ -25,6 +25,8 @@
+ #include <linux/atomic.h>
+ #include <linux/uaccess.h>
+ 
++void *irq_stack[NR_CPUS];
++
+ /*
+  * 'what should we do if we get a hw irq event on an illegal vector'.
+  * each architecture has to answer this themselves.
+@@ -58,6 +60,15 @@ void __init init_IRQ(void)
+ 		clear_c0_status(ST0_IM);
+ 
+ 	arch_init_irq();
++
++	for_each_possible_cpu(i) {
++		int irq_pages = IRQ_STACK_SIZE / PAGE_SIZE;
++		void *s = (void *)__get_free_pages(GFP_KERNEL, irq_pages);
++
++		irq_stack[i] = s;
++		pr_debug("CPU%d IRQ stack at 0x%p - 0x%p\n", i,
++			irq_stack[i], irq_stack[i] + IRQ_STACK_SIZE);
++	}
+ }
+ 
+ #ifdef CONFIG_DEBUG_STACKOVERFLOW
+diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
+index 7d80447e5d03..efa1df52c616 100644
+--- a/arch/mips/kernel/process.c
++++ b/arch/mips/kernel/process.c
+@@ -33,6 +33,7 @@
+ #include <asm/dsemul.h>
+ #include <asm/dsp.h>
+ #include <asm/fpu.h>
++#include <asm/irq.h>
+ #include <asm/msa.h>
+ #include <asm/pgtable.h>
+ #include <asm/mipsregs.h>
+@@ -556,7 +557,19 @@ EXPORT_SYMBOL(unwind_stack_by_address);
+ unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
+ 			   unsigned long pc, unsigned long *ra)
+ {
+-	unsigned long stack_page = (unsigned long)task_stack_page(task);
++	unsigned long stack_page = 0;
++	int cpu;
++
++	for_each_possible_cpu(cpu) {
++		if (on_irq_stack(cpu, *sp)) {
++			stack_page = (unsigned long)irq_stack[cpu];
++			break;
++		}
++	}
++
++	if (!stack_page)
++		stack_page = (unsigned long)task_stack_page(task);
++
+ 	return unwind_stack_by_address(stack_page, sp, pc, ra);
+ }
+ #endif
+diff --git a/drivers/crypto/caam/caampkc.c b/drivers/crypto/caam/caampkc.c
+index 32100c4851dd..49cbdcba7883 100644
+--- a/drivers/crypto/caam/caampkc.c
++++ b/drivers/crypto/caam/caampkc.c
+@@ -506,7 +506,7 @@ static int caam_rsa_init_tfm(struct crypto_akcipher *tfm)
+ 	ctx->dev = caam_jr_alloc();
+ 
+ 	if (IS_ERR(ctx->dev)) {
+-		dev_err(ctx->dev, "Job Ring Device allocation for transform failed\n");
++		pr_err("Job Ring Device allocation for transform failed\n");
+ 		return PTR_ERR(ctx->dev);
+ 	}
+ 
+diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
+index 755109841cfd..6092252ce6ca 100644
+--- a/drivers/crypto/caam/ctrl.c
++++ b/drivers/crypto/caam/ctrl.c
+@@ -282,7 +282,8 @@ static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
+ 			/* Try to run it through DECO0 */
+ 			ret = run_descriptor_deco0(ctrldev, desc, &status);
+ 
+-			if (ret || status) {
++			if (ret ||
++			    (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {
+ 				dev_err(ctrldev,
+ 					"Failed to deinstantiate RNG4 SH%d\n",
+ 					sh_idx);
+diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
+index e72e64484131..686dc3e7eb0b 100644
+--- a/drivers/dma-buf/dma-buf.c
++++ b/drivers/dma-buf/dma-buf.c
+@@ -303,6 +303,9 @@ static const struct file_operations dma_buf_fops = {
+ 	.llseek		= dma_buf_llseek,
+ 	.poll		= dma_buf_poll,
+ 	.unlocked_ioctl	= dma_buf_ioctl,
++#ifdef CONFIG_COMPAT
++	.compat_ioctl	= dma_buf_ioctl,
++#endif
+ };
+ 
+ /*
+diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
+index f02da12f2860..8be958fee160 100644
+--- a/drivers/gpu/drm/i915/i915_drv.c
++++ b/drivers/gpu/drm/i915/i915_drv.c
+@@ -248,6 +248,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
+ 	case I915_PARAM_IRQ_ACTIVE:
+ 	case I915_PARAM_ALLOW_BATCHBUFFER:
+ 	case I915_PARAM_LAST_DISPATCH:
++	case I915_PARAM_HAS_EXEC_CONSTANTS:
+ 		/* Reject all old ums/dri params. */
+ 		return -ENODEV;
+ 	case I915_PARAM_CHIPSET_ID:
+@@ -274,9 +275,6 @@ static int i915_getparam(struct drm_device *dev, void *data,
+ 	case I915_PARAM_HAS_BSD2:
+ 		value = !!dev_priv->engine[VCS2];
+ 		break;
+-	case I915_PARAM_HAS_EXEC_CONSTANTS:
+-		value = INTEL_GEN(dev_priv) >= 4;
+-		break;
+ 	case I915_PARAM_HAS_LLC:
+ 		value = HAS_LLC(dev_priv);
+ 		break;
+diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
+index 8493e19b563a..4a1ed776b41d 100644
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -1263,7 +1263,7 @@ struct intel_gen6_power_mgmt {
+ 	unsigned boosts;
+ 
+ 	/* manual wa residency calculations */
+-	struct intel_rps_ei up_ei, down_ei;
++	struct intel_rps_ei ei;
+ 
+ 	/*
+ 	 * Protects RPS/RC6 register access and PCU communication.
+@@ -1805,8 +1805,6 @@ struct drm_i915_private {
+ 
+ 	const struct intel_device_info info;
+ 
+-	int relative_constants_mode;
+-
+ 	void __iomem *regs;
+ 
+ 	struct intel_uncore uncore;
+diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
+index 7f4a54b94447..b7146494d53f 100644
+--- a/drivers/gpu/drm/i915/i915_gem.c
++++ b/drivers/gpu/drm/i915/i915_gem.c
+@@ -2184,6 +2184,7 @@ i915_gem_object_truncate(struct drm_i915_gem_object *obj)
+ 	 */
+ 	shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
+ 	obj->mm.madv = __I915_MADV_PURGED;
++	obj->mm.pages = ERR_PTR(-EFAULT);
+ }
+ 
+ /* Try to discard unwanted pages */
+@@ -2283,7 +2284,9 @@ void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
+ 
+ 	__i915_gem_object_reset_page_iter(obj);
+ 
+-	obj->ops->put_pages(obj, pages);
++	if (!IS_ERR(pages))
++		obj->ops->put_pages(obj, pages);
++
+ unlock:
+ 	mutex_unlock(&obj->mm.lock);
+ }
+@@ -2501,7 +2504,7 @@ int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
+ 	if (err)
+ 		return err;
+ 
+-	if (unlikely(!obj->mm.pages)) {
++	if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
+ 		err = ____i915_gem_object_get_pages(obj);
+ 		if (err)
+ 			goto unlock;
+@@ -2579,7 +2582,7 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
+ 
+ 	pinned = true;
+ 	if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
+-		if (unlikely(!obj->mm.pages)) {
++		if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
+ 			ret = ____i915_gem_object_get_pages(obj);
+ 			if (ret)
+ 				goto err_unlock;
+@@ -3003,6 +3006,16 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+ 		args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start));
+ 		if (args->timeout_ns < 0)
+ 			args->timeout_ns = 0;
++
++		/*
++		 * Apparently ktime isn't accurate enough and occasionally has a
++		 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
++		 * things up to make the test happy. We allow up to 1 jiffy.
++		 *
++		 * This is a regression from the timespec->ktime conversion.
++		 */
++		if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns))
++			args->timeout_ns = 0;
+ 	}
+ 
+ 	i915_gem_object_put(obj);
+@@ -4554,8 +4567,6 @@ i915_gem_load_init(struct drm_device *dev)
+ 	init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
+ 	init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
+ 
+-	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
+-
+ 	init_waitqueue_head(&dev_priv->pending_flip_queue);
+ 
+ 	dev_priv->mm.interruptible = true;
+diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+index b8b877c91b0a..3d37a15531ad 100644
+--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
++++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+@@ -1410,10 +1410,7 @@ execbuf_submit(struct i915_execbuffer_params *params,
+ 	       struct drm_i915_gem_execbuffer2 *args,
+ 	       struct list_head *vmas)
+ {
+-	struct drm_i915_private *dev_priv = params->request->i915;
+ 	u64 exec_start, exec_len;
+-	int instp_mode;
+-	u32 instp_mask;
+ 	int ret;
+ 
+ 	ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas);
+@@ -1424,56 +1421,11 @@ execbuf_submit(struct i915_execbuffer_params *params,
+ 	if (ret)
+ 		return ret;
+ 
+-	instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
+-	instp_mask = I915_EXEC_CONSTANTS_MASK;
+-	switch (instp_mode) {
+-	case I915_EXEC_CONSTANTS_REL_GENERAL:
+-	case I915_EXEC_CONSTANTS_ABSOLUTE:
+-	case I915_EXEC_CONSTANTS_REL_SURFACE:
+-		if (instp_mode != 0 && params->engine->id != RCS) {
+-			DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
+-			return -EINVAL;
+-		}
+-
+-		if (instp_mode != dev_priv->relative_constants_mode) {
+-			if (INTEL_INFO(dev_priv)->gen < 4) {
+-				DRM_DEBUG("no rel constants on pre-gen4\n");
+-				return -EINVAL;
+-			}
+-
+-			if (INTEL_INFO(dev_priv)->gen > 5 &&
+-			    instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
+-				DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
+-				return -EINVAL;
+-			}
+-
+-			/* The HW changed the meaning on this bit on gen6 */
+-			if (INTEL_INFO(dev_priv)->gen >= 6)
+-				instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
+-		}
+-		break;
+-	default:
+-		DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
++	if (args->flags & I915_EXEC_CONSTANTS_MASK) {
++		DRM_DEBUG("I915_EXEC_CONSTANTS_* unsupported\n");
+ 		return -EINVAL;
+ 	}
+ 
+-	if (params->engine->id == RCS &&
+-	    instp_mode != dev_priv->relative_constants_mode) {
+-		struct intel_ring *ring = params->request->ring;
+-
+-		ret = intel_ring_begin(params->request, 4);
+-		if (ret)
+-			return ret;
+-
+-		intel_ring_emit(ring, MI_NOOP);
+-		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+-		intel_ring_emit_reg(ring, INSTPM);
+-		intel_ring_emit(ring, instp_mask << 16 | instp_mode);
+-		intel_ring_advance(ring);
+-
+-		dev_priv->relative_constants_mode = instp_mode;
+-	}
+-
+ 	if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
+ 		ret = i915_reset_gen7_sol_offsets(params->request);
+ 		if (ret)
+diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c
+index 401006b4c6a3..d5d2b4c6ed38 100644
+--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
++++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
+@@ -263,7 +263,7 @@ unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv)
+ 				I915_SHRINK_BOUND |
+ 				I915_SHRINK_UNBOUND |
+ 				I915_SHRINK_ACTIVE);
+-	rcu_barrier(); /* wait until our RCU delayed slab frees are completed */
++	synchronize_rcu(); /* wait for our earlier RCU delayed slab frees */
+ 
+ 	return freed;
+ }
+diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
+index f914581b1729..de6710f02d95 100644
+--- a/drivers/gpu/drm/i915/i915_irq.c
++++ b/drivers/gpu/drm/i915/i915_irq.c
+@@ -1046,68 +1046,51 @@ static void vlv_c0_read(struct drm_i915_private *dev_priv,
+ 	ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
+ }
+ 
+-static bool vlv_c0_above(struct drm_i915_private *dev_priv,
+-			 const struct intel_rps_ei *old,
+-			 const struct intel_rps_ei *now,
+-			 int threshold)
+-{
+-	u64 time, c0;
+-	unsigned int mul = 100;
+-
+-	if (old->cz_clock == 0)
+-		return false;
+-
+-	if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
+-		mul <<= 8;
+-
+-	time = now->cz_clock - old->cz_clock;
+-	time *= threshold * dev_priv->czclk_freq;
+-
+-	/* Workload can be split between render + media, e.g. SwapBuffers
+-	 * being blitted in X after being rendered in mesa. To account for
+-	 * this we need to combine both engines into our activity counter.
+-	 */
+-	c0 = now->render_c0 - old->render_c0;
+-	c0 += now->media_c0 - old->media_c0;
+-	c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
+-
+-	return c0 >= time;
+-}
+-
+ void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
+ {
+-	vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
+-	dev_priv->rps.up_ei = dev_priv->rps.down_ei;
++	memset(&dev_priv->rps.ei, 0, sizeof(dev_priv->rps.ei));
+ }
+ 
+ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
+ {
++	const struct intel_rps_ei *prev = &dev_priv->rps.ei;
+ 	struct intel_rps_ei now;
+ 	u32 events = 0;
+ 
+-	if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
++	if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
+ 		return 0;
+ 
+ 	vlv_c0_read(dev_priv, &now);
+ 	if (now.cz_clock == 0)
+ 		return 0;
+ 
+-	if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
+-		if (!vlv_c0_above(dev_priv,
+-				  &dev_priv->rps.down_ei, &now,
+-				  dev_priv->rps.down_threshold))
+-			events |= GEN6_PM_RP_DOWN_THRESHOLD;
+-		dev_priv->rps.down_ei = now;
+-	}
++	if (prev->cz_clock) {
++		u64 time, c0;
++		unsigned int mul;
++
++		mul = VLV_CZ_CLOCK_TO_MILLI_SEC * 100; /* scale to threshold% */
++		if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
++			mul <<= 8;
+ 
+-	if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
+-		if (vlv_c0_above(dev_priv,
+-				 &dev_priv->rps.up_ei, &now,
+-				 dev_priv->rps.up_threshold))
+-			events |= GEN6_PM_RP_UP_THRESHOLD;
+-		dev_priv->rps.up_ei = now;
++		time = now.cz_clock - prev->cz_clock;
++		time *= dev_priv->czclk_freq;
++
++		/* Workload can be split between render + media,
++		 * e.g. SwapBuffers being blitted in X after being rendered in
++		 * mesa. To account for this we need to combine both engines
++		 * into our activity counter.
++		 */
++		c0 = now.render_c0 - prev->render_c0;
++		c0 += now.media_c0 - prev->media_c0;
++		c0 *= mul;
++
++		if (c0 > time * dev_priv->rps.up_threshold)
++			events = GEN6_PM_RP_UP_THRESHOLD;
++		else if (c0 < time * dev_priv->rps.down_threshold)
++			events = GEN6_PM_RP_DOWN_THRESHOLD;
+ 	}
+ 
++	dev_priv->rps.ei = now;
+ 	return events;
+ }
+ 
+@@ -4178,7 +4161,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
+ 	/* Let's track the enabled rps events */
+ 	if (IS_VALLEYVIEW(dev_priv))
+ 		/* WaGsvRC0ResidencyMethod:vlv */
+-		dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
++		dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
+ 	else
+ 		dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
+ 
+@@ -4216,6 +4199,16 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
+ 	if (!IS_GEN2(dev_priv))
+ 		dev->vblank_disable_immediate = true;
+ 
++	/* Most platforms treat the display irq block as an always-on
++	 * power domain. vlv/chv can disable it at runtime and need
++	 * special care to avoid writing any of the display block registers
++	 * outside of the power domain. We defer setting up the display irqs
++	 * in this case to the runtime pm.
++	 */
++	dev_priv->display_irqs_enabled = true;
++	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
++		dev_priv->display_irqs_enabled = false;
++
+ 	dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
+ 	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
+ 
+diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
+index 891c86aef99d..59231312c4e0 100644
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -3677,10 +3677,6 @@ static void intel_update_pipe_config(struct intel_crtc *crtc,
+ 	/* drm_atomic_helper_update_legacy_modeset_state might not be called. */
+ 	crtc->base.mode = crtc->base.state->mode;
+ 
+-	DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
+-		      old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
+-		      pipe_config->pipe_src_w, pipe_config->pipe_src_h);
+-
+ 	/*
+ 	 * Update pipe size and adjust fitter if needed: the reason for this is
+ 	 * that in compute_mode_changes we check the native mode (not the pfit
+@@ -4805,23 +4801,17 @@ static void skylake_pfit_enable(struct intel_crtc *crtc)
+ 	struct intel_crtc_scaler_state *scaler_state =
+ 		&crtc->config->scaler_state;
+ 
+-	DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
+-
+ 	if (crtc->config->pch_pfit.enabled) {
+ 		int id;
+ 
+-		if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
+-			DRM_ERROR("Requesting pfit without getting a scaler first\n");
++		if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
+ 			return;
+-		}
+ 
+ 		id = scaler_state->scaler_id;
+ 		I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
+ 			PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
+ 		I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
+ 		I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
+-
+-		DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
+ 	}
+ }
+ 
+@@ -14895,17 +14885,19 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
+ 		to_intel_atomic_state(old_crtc_state->state);
+ 	bool modeset = needs_modeset(crtc->state);
+ 
++	if (!modeset &&
++	    (intel_cstate->base.color_mgmt_changed ||
++	     intel_cstate->update_pipe)) {
++		intel_color_set_csc(crtc->state);
++		intel_color_load_luts(crtc->state);
++	}
++
+ 	/* Perform vblank evasion around commit operation */
+ 	intel_pipe_update_start(intel_crtc);
+ 
+ 	if (modeset)
+ 		goto out;
+ 
+-	if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
+-		intel_color_set_csc(crtc->state);
+-		intel_color_load_luts(crtc->state);
+-	}
+-
+ 	if (intel_cstate->update_pipe)
+ 		intel_update_pipe_config(intel_crtc, old_intel_cstate);
+ 	else if (INTEL_GEN(dev_priv) >= 9)
+@@ -16497,12 +16489,11 @@ int intel_modeset_init(struct drm_device *dev)
+ 		}
+ 	}
+ 
+-	intel_update_czclk(dev_priv);
+-	intel_update_cdclk(dev_priv);
+-	dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
+-
+ 	intel_shared_dpll_init(dev);
+ 
++	intel_update_czclk(dev_priv);
++	intel_modeset_init_hw(dev);
++
+ 	if (dev_priv->max_cdclk_freq == 0)
+ 		intel_update_max_cdclk(dev_priv);
+ 
+@@ -17057,8 +17048,6 @@ void intel_modeset_gem_init(struct drm_device *dev)
+ 
+ 	intel_init_gt_powersave(dev_priv);
+ 
+-	intel_modeset_init_hw(dev);
+-
+ 	intel_setup_overlay(dev_priv);
+ }
+ 
+diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
+index f4a8c4fc57c4..c20ca8e08390 100644
+--- a/drivers/gpu/drm/i915/intel_fbdev.c
++++ b/drivers/gpu/drm/i915/intel_fbdev.c
+@@ -357,14 +357,13 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
+ 				    bool *enabled, int width, int height)
+ {
+ 	struct drm_i915_private *dev_priv = to_i915(fb_helper->dev);
+-	unsigned long conn_configured, mask;
++	unsigned long conn_configured, conn_seq, mask;
+ 	unsigned int count = min(fb_helper->connector_count, BITS_PER_LONG);
+ 	int i, j;
+ 	bool *save_enabled;
+ 	bool fallback = true;
+ 	int num_connectors_enabled = 0;
+ 	int num_connectors_detected = 0;
+-	int pass = 0;
+ 
+ 	save_enabled = kcalloc(count, sizeof(bool), GFP_KERNEL);
+ 	if (!save_enabled)
+@@ -374,6 +373,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
+ 	mask = BIT(count) - 1;
+ 	conn_configured = 0;
+ retry:
++	conn_seq = conn_configured;
+ 	for (i = 0; i < count; i++) {
+ 		struct drm_fb_helper_connector *fb_conn;
+ 		struct drm_connector *connector;
+@@ -387,7 +387,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
+ 		if (conn_configured & BIT(i))
+ 			continue;
+ 
+-		if (pass == 0 && !connector->has_tile)
++		if (conn_seq == 0 && !connector->has_tile)
+ 			continue;
+ 
+ 		if (connector->status == connector_status_connected)
+@@ -498,10 +498,8 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
+ 		conn_configured |= BIT(i);
+ 	}
+ 
+-	if ((conn_configured & mask) != mask) {
+-		pass++;
++	if ((conn_configured & mask) != mask && conn_configured != conn_seq)
+ 		goto retry;
+-	}
+ 
+ 	/*
+ 	 * If the BIOS didn't enable everything it could, fall back to have the
+diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
+index fb88e32e25a3..fe8f8a4c384e 100644
+--- a/drivers/gpu/drm/i915/intel_hdmi.c
++++ b/drivers/gpu/drm/i915/intel_hdmi.c
+@@ -1293,16 +1293,34 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
+ 
+ static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
+ {
+-	struct drm_device *dev = crtc_state->base.crtc->dev;
++	struct drm_i915_private *dev_priv =
++		to_i915(crtc_state->base.crtc->dev);
++	struct drm_atomic_state *state = crtc_state->base.state;
++	struct drm_connector_state *connector_state;
++	struct drm_connector *connector;
++	int i;
+ 
+-	if (HAS_GMCH_DISPLAY(to_i915(dev)))
++	if (HAS_GMCH_DISPLAY(dev_priv))
+ 		return false;
+ 
+ 	/*
+ 	 * HDMI 12bpc affects the clocks, so it's only possible
+ 	 * when not cloning with other encoder types.
+ 	 */
+-	return crtc_state->output_types == 1 << INTEL_OUTPUT_HDMI;
++	if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
++		return false;
++
++	for_each_connector_in_state(state, connector, connector_state, i) {
++		const struct drm_display_info *info = &connector->display_info;
++
++		if (connector_state->crtc != crtc_state->base.crtc)
++			continue;
++
++		if ((info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36) == 0)
++			return false;
++	}
++
++	return true;
+ }
+ 
+ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
+diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
+index 3d546c019de0..b782f22856f8 100644
+--- a/drivers/gpu/drm/i915/intel_hotplug.c
++++ b/drivers/gpu/drm/i915/intel_hotplug.c
+@@ -219,7 +219,7 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
+ 			}
+ 		}
+ 	}
+-	if (dev_priv->display.hpd_irq_setup)
++	if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup)
+ 		dev_priv->display.hpd_irq_setup(dev_priv);
+ 	spin_unlock_irq(&dev_priv->irq_lock);
+ 
+@@ -425,7 +425,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
+ 		}
+ 	}
+ 
+-	if (storm_detected)
++	if (storm_detected && dev_priv->display_irqs_enabled)
+ 		dev_priv->display.hpd_irq_setup(dev_priv);
+ 	spin_unlock(&dev_priv->irq_lock);
+ 
+@@ -471,10 +471,12 @@ void intel_hpd_init(struct drm_i915_private *dev_priv)
+ 	 * Interrupt setup is already guaranteed to be single-threaded, this is
+ 	 * just to make the assert_spin_locked checks happy.
+ 	 */
+-	spin_lock_irq(&dev_priv->irq_lock);
+-	if (dev_priv->display.hpd_irq_setup)
+-		dev_priv->display.hpd_irq_setup(dev_priv);
+-	spin_unlock_irq(&dev_priv->irq_lock);
++	if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup) {
++		spin_lock_irq(&dev_priv->irq_lock);
++		if (dev_priv->display_irqs_enabled)
++			dev_priv->display.hpd_irq_setup(dev_priv);
++		spin_unlock_irq(&dev_priv->irq_lock);
++	}
+ }
+ 
+ static void i915_hpd_poll_init_work(struct work_struct *work)
+diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
+index ae2c0bb4b2e8..3af22cf865f4 100644
+--- a/drivers/gpu/drm/i915/intel_pm.c
++++ b/drivers/gpu/drm/i915/intel_pm.c
+@@ -4876,6 +4876,12 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
+ 		break;
+ 	}
+ 
++	/* When byt can survive without system hang with dynamic
++	 * sw freq adjustments, this restriction can be lifted.
++	 */
++	if (IS_VALLEYVIEW(dev_priv))
++		goto skip_hw_write;
++
+ 	I915_WRITE(GEN6_RP_UP_EI,
+ 		   GT_INTERVAL_FROM_US(dev_priv, ei_up));
+ 	I915_WRITE(GEN6_RP_UP_THRESHOLD,
+@@ -4896,6 +4902,7 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
+ 		   GEN6_RP_UP_BUSY_AVG |
+ 		   GEN6_RP_DOWN_IDLE_AVG);
+ 
++skip_hw_write:
+ 	dev_priv->rps.power = new_power;
+ 	dev_priv->rps.up_threshold = threshold_up;
+ 	dev_priv->rps.down_threshold = threshold_down;
+@@ -4906,8 +4913,9 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
+ {
+ 	u32 mask = 0;
+ 
++	/* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
+ 	if (val > dev_priv->rps.min_freq_softlimit)
+-		mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
++		mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
+ 	if (val < dev_priv->rps.max_freq_softlimit)
+ 		mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
+ 
+@@ -5007,7 +5015,7 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
+ {
+ 	mutex_lock(&dev_priv->rps.hw_lock);
+ 	if (dev_priv->rps.enabled) {
+-		if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
++		if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
+ 			gen6_rps_reset_ei(dev_priv);
+ 		I915_WRITE(GEN6_PMINTRMSK,
+ 			   gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
+@@ -7895,10 +7903,10 @@ static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
+  * @timeout_base_ms: timeout for polling with preemption enabled
+  *
+  * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
+- * reports an error or an overall timeout of @timeout_base_ms+10 ms expires.
++ * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
+  * The request is acknowledged once the PCODE reply dword equals @reply after
+  * applying @reply_mask. Polling is first attempted with preemption enabled
+- * for @timeout_base_ms and if this times out for another 10 ms with
++ * for @timeout_base_ms and if this times out for another 50 ms with
+  * preemption disabled.
+  *
+  * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
+@@ -7934,14 +7942,15 @@ int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
+ 	 * worst case) _and_ PCODE was busy for some reason even after a
+ 	 * (queued) request and @timeout_base_ms delay. As a workaround retry
+ 	 * the poll with preemption disabled to maximize the number of
+-	 * requests. Increase the timeout from @timeout_base_ms to 10ms to
++	 * requests. Increase the timeout from @timeout_base_ms to 50ms to
+ 	 * account for interrupts that could reduce the number of these
+-	 * requests.
++	 * requests, and for any quirks of the PCODE firmware that delays
++	 * the request completion.
+ 	 */
+ 	DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
+ 	WARN_ON_ONCE(timeout_base_ms > 3);
+ 	preempt_disable();
+-	ret = wait_for_atomic(COND, 10);
++	ret = wait_for_atomic(COND, 50);
+ 	preempt_enable();
+ 
+ out:
+diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
+index 0bffd3f0c15d..2e4fbed3a826 100644
+--- a/drivers/gpu/drm/i915/intel_uncore.c
++++ b/drivers/gpu/drm/i915/intel_uncore.c
+@@ -119,6 +119,8 @@ fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_doma
+ 
+ 	for_each_fw_domain_masked(d, fw_domains, dev_priv)
+ 		fw_domain_wait_ack(d);
++
++	dev_priv->uncore.fw_domains_active |= fw_domains;
+ }
+ 
+ static void
+@@ -130,6 +132,8 @@ fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_doma
+ 		fw_domain_put(d);
+ 		fw_domain_posting_read(d);
+ 	}
++
++	dev_priv->uncore.fw_domains_active &= ~fw_domains;
+ }
+ 
+ static void
+@@ -240,10 +244,8 @@ intel_uncore_fw_release_timer(struct hrtimer *timer)
+ 	if (WARN_ON(domain->wake_count == 0))
+ 		domain->wake_count++;
+ 
+-	if (--domain->wake_count == 0) {
++	if (--domain->wake_count == 0)
+ 		dev_priv->uncore.funcs.force_wake_put(dev_priv, domain->mask);
+-		dev_priv->uncore.fw_domains_active &= ~domain->mask;
+-	}
+ 
+ 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+ 
+@@ -455,10 +457,8 @@ static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
+ 			fw_domains &= ~domain->mask;
+ 	}
+ 
+-	if (fw_domains) {
++	if (fw_domains)
+ 		dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
+-		dev_priv->uncore.fw_domains_active |= fw_domains;
+-	}
+ }
+ 
+ /**
+@@ -962,7 +962,6 @@ static noinline void ___force_wake_auto(struct drm_i915_private *dev_priv,
+ 		fw_domain_arm_timer(domain);
+ 
+ 	dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
+-	dev_priv->uncore.fw_domains_active |= fw_domains;
+ }
+ 
+ static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
+diff --git a/drivers/net/wireless/ralink/rt2x00/rt2x00usb.c b/drivers/net/wireless/ralink/rt2x00/rt2x00usb.c
+index 6005e14213ca..662705e31136 100644
+--- a/drivers/net/wireless/ralink/rt2x00/rt2x00usb.c
++++ b/drivers/net/wireless/ralink/rt2x00/rt2x00usb.c
+@@ -319,10 +319,8 @@ static bool rt2x00usb_kick_tx_entry(struct queue_entry *entry, void *data)
+ 			  entry->skb->data, length,
+ 			  rt2x00usb_interrupt_txdone, entry);
+ 
+-	usb_anchor_urb(entry_priv->urb, rt2x00dev->anchor);
+ 	status = usb_submit_urb(entry_priv->urb, GFP_ATOMIC);
+ 	if (status) {
+-		usb_unanchor_urb(entry_priv->urb);
+ 		if (status == -ENODEV)
+ 			clear_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags);
+ 		set_bit(ENTRY_DATA_IO_FAILED, &entry->flags);
+@@ -410,10 +408,8 @@ static bool rt2x00usb_kick_rx_entry(struct queue_entry *entry, void *data)
+ 			  entry->skb->data, entry->skb->len,
+ 			  rt2x00usb_interrupt_rxdone, entry);
+ 
+-	usb_anchor_urb(entry_priv->urb, rt2x00dev->anchor);
+ 	status = usb_submit_urb(entry_priv->urb, GFP_ATOMIC);
+ 	if (status) {
+-		usb_unanchor_urb(entry_priv->urb);
+ 		if (status == -ENODEV)
+ 			clear_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags);
+ 		set_bit(ENTRY_DATA_IO_FAILED, &entry->flags);
+@@ -824,10 +820,6 @@ int rt2x00usb_probe(struct usb_interface *usb_intf,
+ 	if (retval)
+ 		goto exit_free_device;
+ 
+-	retval = rt2x00lib_probe_dev(rt2x00dev);
+-	if (retval)
+-		goto exit_free_reg;
+-
+ 	rt2x00dev->anchor = devm_kmalloc(&usb_dev->dev,
+ 					sizeof(struct usb_anchor),
+ 					GFP_KERNEL);
+@@ -835,10 +827,17 @@ int rt2x00usb_probe(struct usb_interface *usb_intf,
+ 		retval = -ENOMEM;
+ 		goto exit_free_reg;
+ 	}
+-
+ 	init_usb_anchor(rt2x00dev->anchor);
++
++	retval = rt2x00lib_probe_dev(rt2x00dev);
++	if (retval)
++		goto exit_free_anchor;
++
+ 	return 0;
+ 
++exit_free_anchor:
++	usb_kill_anchored_urbs(rt2x00dev->anchor);
++
+ exit_free_reg:
+ 	rt2x00usb_free_reg(rt2x00dev);
+ 
+diff --git a/fs/nfs/flexfilelayout/flexfilelayoutdev.c b/fs/nfs/flexfilelayout/flexfilelayoutdev.c
+index e5a6f248697b..15421e625a12 100644
+--- a/fs/nfs/flexfilelayout/flexfilelayoutdev.c
++++ b/fs/nfs/flexfilelayout/flexfilelayoutdev.c
+@@ -208,6 +208,10 @@ static bool ff_layout_mirror_valid(struct pnfs_layout_segment *lseg,
+ 		} else
+ 			goto outerr;
+ 	}
++
++	if (IS_ERR(mirror->mirror_ds))
++		goto outerr;
++
+ 	if (mirror->mirror_ds->ds == NULL) {
+ 		struct nfs4_deviceid_node *devid;
+ 		devid = &mirror->mirror_ds->id_node;
+diff --git a/fs/orangefs/devorangefs-req.c b/fs/orangefs/devorangefs-req.c
+index b0ced669427e..c4ab6fdf17a0 100644
+--- a/fs/orangefs/devorangefs-req.c
++++ b/fs/orangefs/devorangefs-req.c
+@@ -400,8 +400,9 @@ static ssize_t orangefs_devreq_write_iter(struct kiocb *iocb,
+ 	/* remove the op from the in progress hash table */
+ 	op = orangefs_devreq_remove_op(head.tag);
+ 	if (!op) {
+-		gossip_err("WARNING: No one's waiting for tag %llu\n",
+-			   llu(head.tag));
++		gossip_debug(GOSSIP_DEV_DEBUG,
++			     "%s: No one's waiting for tag %llu\n",
++			     __func__, llu(head.tag));
+ 		return ret;
+ 	}
+ 
+diff --git a/fs/orangefs/orangefs-debugfs.c b/fs/orangefs/orangefs-debugfs.c
+index 27e75cf28b3a..791912da97d7 100644
+--- a/fs/orangefs/orangefs-debugfs.c
++++ b/fs/orangefs/orangefs-debugfs.c
+@@ -967,13 +967,13 @@ int orangefs_debugfs_new_client_string(void __user *arg)
+ 	int ret;
+ 
+ 	ret = copy_from_user(&client_debug_array_string,
+-                                     (void __user *)arg,
+-                                     ORANGEFS_MAX_DEBUG_STRING_LEN);
++			     (void __user *)arg,
++			     ORANGEFS_MAX_DEBUG_STRING_LEN);
+ 
+ 	if (ret != 0) {
+ 		pr_info("%s: CLIENT_STRING: copy_from_user failed\n",
+ 			__func__);
+-		return -EIO;
++		return -EFAULT;
+ 	}
+ 
+ 	/*
+@@ -988,17 +988,18 @@ int orangefs_debugfs_new_client_string(void __user *arg)
+ 	 */
+ 	client_debug_array_string[ORANGEFS_MAX_DEBUG_STRING_LEN - 1] =
+ 		'\0';
+-	
++
+ 	pr_info("%s: client debug array string has been received.\n",
+ 		__func__);
+ 
+ 	if (!help_string_initialized) {
+ 
+ 		/* Build a proper debug help string. */
+-		if (orangefs_prepare_debugfs_help_string(0)) {
++		ret = orangefs_prepare_debugfs_help_string(0);
++		if (ret) {
+ 			gossip_err("%s: no debug help string \n",
+ 				   __func__);
+-			return -EIO;
++			return ret;
+ 		}
+ 
+ 	}
+@@ -1011,7 +1012,7 @@ int orangefs_debugfs_new_client_string(void __user *arg)
+ 
+ 	help_string_initialized++;
+ 
+-	return ret;
++	return 0;
+ }
+ 
+ int orangefs_debugfs_new_debug(void __user *arg) 
+diff --git a/fs/orangefs/orangefs-dev-proto.h b/fs/orangefs/orangefs-dev-proto.h
+index a3d84ffee905..f380f9ed1b28 100644
+--- a/fs/orangefs/orangefs-dev-proto.h
++++ b/fs/orangefs/orangefs-dev-proto.h
+@@ -50,8 +50,7 @@
+  * Misc constants. Please retain them as multiples of 8!
+  * Otherwise 32-64 bit interactions will be messed up :)
+  */
+-#define ORANGEFS_MAX_DEBUG_STRING_LEN	0x00000400
+-#define ORANGEFS_MAX_DEBUG_ARRAY_LEN	0x00000800
++#define ORANGEFS_MAX_DEBUG_STRING_LEN	0x00000800
+ 
+ /*
+  * The maximum number of directory entries in a single request is 96.
+diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c
+index c59fcc79ba32..5c919933a39b 100644
+--- a/net/packet/af_packet.c
++++ b/net/packet/af_packet.c
+@@ -4177,8 +4177,8 @@ static int packet_set_ring(struct sock *sk, union tpacket_req_u *req_u,
+ 		if (unlikely(!PAGE_ALIGNED(req->tp_block_size)))
+ 			goto out;
+ 		if (po->tp_version >= TPACKET_V3 &&
+-		    (int)(req->tp_block_size -
+-			  BLK_PLUS_PRIV(req_u->req3.tp_sizeof_priv)) <= 0)
++		    req->tp_block_size <=
++			  BLK_PLUS_PRIV((u64)req_u->req3.tp_sizeof_priv))
+ 			goto out;
+ 		if (unlikely(req->tp_frame_size < po->tp_hdrlen +
+ 					po->tp_reserve))