1 |
commit: 54fde3444f274bf683002783835a1a98be8904d0 |
2 |
Author: Michał Górny <mgorny <AT> gentoo <DOT> org> |
3 |
AuthorDate: Mon Aug 12 12:32:08 2019 +0000 |
4 |
Commit: Michał Górny <mgorny <AT> gentoo <DOT> org> |
5 |
CommitDate: Mon Aug 12 13:20:47 2019 +0000 |
6 |
URL: https://gitweb.gentoo.org/repo/gentoo.git/commit/?id=54fde344 |
7 |
|
8 |
sys-devel/clang: RISCV is no longer exp. in 9.0+ |
9 |
|
10 |
Closes: https://bugs.gentoo.org/691816 |
11 |
Signed-off-by: Michał Górny <mgorny <AT> gentoo.org> |
12 |
|
13 |
sys-devel/clang/clang-10.0.0.9999.ebuild | 4 ++-- |
14 |
sys-devel/clang/clang-9.0.0.9999.ebuild | 2 +- |
15 |
2 files changed, 3 insertions(+), 3 deletions(-) |
16 |
|
17 |
diff --git a/sys-devel/clang/clang-10.0.0.9999.ebuild b/sys-devel/clang/clang-10.0.0.9999.ebuild |
18 |
index cd46cc44021..8c2f969f179 100644 |
19 |
--- a/sys-devel/clang/clang-10.0.0.9999.ebuild |
20 |
+++ b/sys-devel/clang/clang-10.0.0.9999.ebuild |
21 |
@@ -18,9 +18,9 @@ EGIT_REPO_URI="https://git.llvm.org/git/clang.git |
22 |
https://github.com/llvm-mirror/clang.git" |
23 |
|
24 |
# Keep in sync with sys-devel/llvm |
25 |
-ALL_LLVM_EXPERIMENTAL_TARGETS=( AVR Nios2 RISCV ) |
26 |
+ALL_LLVM_EXPERIMENTAL_TARGETS=( AVR Nios2 ) |
27 |
ALL_LLVM_TARGETS=( AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430 |
28 |
- NVPTX PowerPC Sparc SystemZ WebAssembly X86 XCore |
29 |
+ NVPTX PowerPC RISCV Sparc SystemZ WebAssembly X86 XCore |
30 |
"${ALL_LLVM_EXPERIMENTAL_TARGETS[@]}" ) |
31 |
ALL_LLVM_TARGETS=( "${ALL_LLVM_TARGETS[@]/#/llvm_targets_}" ) |
32 |
LLVM_TARGET_USEDEPS=${ALL_LLVM_TARGETS[@]/%/?} |
33 |
|
34 |
diff --git a/sys-devel/clang/clang-9.0.0.9999.ebuild b/sys-devel/clang/clang-9.0.0.9999.ebuild |
35 |
index 080cdf67037..2a3b7d07905 100644 |
36 |
--- a/sys-devel/clang/clang-9.0.0.9999.ebuild |
37 |
+++ b/sys-devel/clang/clang-9.0.0.9999.ebuild |
38 |
@@ -20,7 +20,7 @@ EGIT_BRANCH="release_90" |
39 |
|
40 |
# Keep in sync with sys-devel/llvm |
41 |
ALL_LLVM_TARGETS=( AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430 |
42 |
- NVPTX PowerPC Sparc SystemZ WebAssembly X86 XCore ) |
43 |
+ NVPTX PowerPC RISCV Sparc SystemZ WebAssembly X86 XCore ) |
44 |
ALL_LLVM_TARGETS=( "${ALL_LLVM_TARGETS[@]/#/llvm_targets_}" ) |
45 |
LLVM_TARGET_USEDEPS=${ALL_LLVM_TARGETS[@]/%/?} |