1 |
chainsaw 08/05/07 16:33:41 |
2 |
|
3 |
Added: NVIDIA_kernel-173.08-2404825.diff |
4 |
Log: |
5 |
Masked beta driver 173.08 with upstream patch from Zander ( http://www.nvnews.net/vbulletin/showpost.php?p=1648357&postcount=35 ) for >=2.6.26-rc1 compatibility. Dropped keywords as this has only been tested on 2.6.26-rc1-00166-gc0a1811 SMP x86_64 so far. Now installs module control file in modprobe.d where it belongs. Upstream advises to use PAT over MTRR. Some reports of low performance and 2D corruption, tread carefully. Quoted variables for greater repoman happiness. |
6 |
(Portage version: 2.1.5_rc7) |
7 |
|
8 |
Revision Changes Path |
9 |
1.1 x11-drivers/nvidia-drivers/files/NVIDIA_kernel-173.08-2404825.diff |
10 |
|
11 |
file : http://sources.gentoo.org/viewcvs.py/gentoo-x86/x11-drivers/nvidia-drivers/files/NVIDIA_kernel-173.08-2404825.diff?rev=1.1&view=markup |
12 |
plain: http://sources.gentoo.org/viewcvs.py/gentoo-x86/x11-drivers/nvidia-drivers/files/NVIDIA_kernel-173.08-2404825.diff?rev=1.1&content-type=text/plain |
13 |
|
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Index: NVIDIA_kernel-173.08-2404825.diff |
15 |
=================================================================== |
16 |
diff -ru usr/src/nv/nv-linux.h usr/src/nv.2404825/nv-linux.h |
17 |
--- usr/src/nv/nv-linux.h 2008-04-02 01:17:56.000000000 -0700 |
18 |
+++ usr/src/nv.2404825/nv-linux.h 2008-05-06 16:22:16.603101044 -0700 |
19 |
@@ -145,16 +145,19 @@ |
20 |
#endif |
21 |
|
22 |
#if (defined(NVCPU_X86) || defined(NVCPU_X86_64)) && !defined(CONFIG_XEN) |
23 |
-#define NV_BUILD_NV_PAT_SUPPORT 1 |
24 |
+#define NV_ENABLE_PAT_SUPPORT |
25 |
#endif |
26 |
|
27 |
-#if defined(NV_BUILD_NV_PAT_SUPPORT) |
28 |
-#include "pat.h" |
29 |
+#define NV_PAT_MODE_DISABLED 0 |
30 |
+#define NV_PAT_MODE_KERNEL 1 |
31 |
+#define NV_PAT_MODE_BUILTIN 2 |
32 |
+ |
33 |
+extern int nv_pat_mode; |
34 |
+ |
35 |
#if defined(CONFIG_HOTPLUG_CPU) |
36 |
#include <linux/cpu.h> /* CPU hotplug support */ |
37 |
#include <linux/notifier.h> /* struct notifier_block, etc */ |
38 |
#endif |
39 |
-#endif |
40 |
|
41 |
#if (defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)) |
42 |
#include <linux/i2c.h> |
43 |
@@ -681,6 +684,13 @@ |
44 |
#define nv_down(lock) down(&lock) |
45 |
#define nv_up(lock) up(&lock) |
46 |
|
47 |
+#define NV_INIT_MUTEX(mutex) \ |
48 |
+ { \ |
49 |
+ struct semaphore __mutex = \ |
50 |
+ __SEMAPHORE_INITIALIZER(*(mutex), 1); \ |
51 |
+ *(mutex) = __mutex; \ |
52 |
+ } |
53 |
+ |
54 |
#if defined (KERNEL_2_4) |
55 |
# define NV_IS_SUSER() suser() |
56 |
# define NV_PCI_DEVICE_NAME(dev) ((dev)->name) |
57 |
@@ -1029,20 +1039,6 @@ |
58 |
return new_prot; |
59 |
} |
60 |
#endif |
61 |
- |
62 |
-#if defined(NV_BUILD_NV_PAT_SUPPORT) && !defined (pgprot_writecombined) |
63 |
-static inline pgprot_t pgprot_writecombined(pgprot_t old_prot) |
64 |
- { |
65 |
- pgprot_t new_prot = old_prot; |
66 |
- if (boot_cpu_data.x86 > 3) |
67 |
- { |
68 |
- pgprot_val(old_prot) &= ~(_PAGE_PCD | _PAGE_PWT); |
69 |
- new_prot = __pgprot(pgprot_val(old_prot) | _PAGE_WRTCOMB); |
70 |
- } |
71 |
- return new_prot; |
72 |
- } |
73 |
-#endif |
74 |
- |
75 |
#endif /* defined(NVCPU_X86) || defined(NVCPU_X86_64) */ |
76 |
|
77 |
#if defined(KERNEL_2_4) && defined(NVCPU_X86) && !defined(pfn_to_page) |
78 |
@@ -1142,8 +1138,6 @@ |
79 |
struct semaphore at_lock; |
80 |
} nv_linux_state_t; |
81 |
|
82 |
-extern int nv_pat_enabled; |
83 |
- |
84 |
#if defined(NV_LINUX_ACPI_EVENTS_SUPPORTED) |
85 |
/* |
86 |
* acpi data storage structure |
87 |
diff -ru usr/src/nv/nv-reg.h usr/src/nv.2404825/nv-reg.h |
88 |
--- usr/src/nv/nv-reg.h 2008-04-02 01:17:56.000000000 -0700 |
89 |
+++ usr/src/nv.2404825/nv-reg.h 2008-05-06 16:22:16.603101044 -0700 |
90 |
@@ -471,6 +471,37 @@ |
91 |
#define __NV_RM_EDGE_INTR_CHECK RMEdgeIntrCheck |
92 |
#define NV_REG_RM_EDGE_INTR_CHECK NV_REG_STRING(__NV_RM_EDGE_INTR_CHECK) |
93 |
|
94 |
+/* |
95 |
+ * Option: UsePageAttributeTable |
96 |
+ * |
97 |
+ * Description: |
98 |
+ * |
99 |
+ * Enable/disable use of the page attribute table (PAT) available in |
100 |
+ * modern x86/x86-64 processors to set the effective memory type of memory |
101 |
+ * mappings to write-combining (WC). If disabled, the driver will fall |
102 |
+ * back to using MTRRs, if possible. |
103 |
+ * |
104 |
+ * If enabled, an x86 processor with PAT support is present and the host |
105 |
+ * system's Linux kernel did not configure one of the PAT entries to |
106 |
+ * indicate the WC memory type, the driver will change the second entry in |
107 |
+ * the PAT from its default (write-through (WT)) to WC at module load |
108 |
+ * time. If the kernel did update one of the PAT entries, the driver will |
109 |
+ * not modify the PAT. |
110 |
+ * |
111 |
+ * In both cases, the driver will honor attempts to map memory with the WC |
112 |
+ * memory type by selecting the appropriate PAT entry using the correct |
113 |
+ * set of PTE flags. |
114 |
+ * |
115 |
+ * Possible values: |
116 |
+ * |
117 |
+ * ~0 = use the NVIDIA driver's default logic (default) |
118 |
+ * 1 = enable use of the PAT for WC mappings. |
119 |
+ * 0 = disable use of the PAT for WC mappings. |
120 |
+ */ |
121 |
+ |
122 |
+#define __NV_USE_PAGE_ATTRIBUTE_TABLE UsePageAttributeTable |
123 |
+#define NV_USE_PAGE_ATTRIBUTE_TABLE NV_REG_STRING(__NV_USE_PAGE_ATTRIBUTE_TABLE) |
124 |
+ |
125 |
|
126 |
|
127 |
#if defined(NV_DEFINE_REGISTRY_KEY_TABLE) |
128 |
@@ -495,6 +526,7 @@ |
129 |
NV_DEFINE_REG_ENTRY(__NV_UPDATE_MEMORY_TYPES, ~0); |
130 |
NV_DEFINE_REG_ENTRY(__NV_USE_VBIOS, 1); |
131 |
NV_DEFINE_REG_ENTRY(__NV_RM_EDGE_INTR_CHECK, 1); |
132 |
+NV_DEFINE_REG_ENTRY(__NV_USE_PAGE_ATTRIBUTE_TABLE, ~0); |
133 |
|
134 |
#if defined(NV_LINUX) |
135 |
NV_DEFINE_REG_STRING_ENTRY(__NV_REGISTRY_DWORDS, NULL); |
136 |
@@ -540,6 +572,7 @@ |
137 |
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_UPDATE_MEMORY_TYPES), |
138 |
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_USE_VBIOS), |
139 |
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_RM_EDGE_INTR_CHECK), |
140 |
+ NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_USE_PAGE_ATTRIBUTE_TABLE), |
141 |
{NULL, NULL, NULL} |
142 |
}; |
143 |
|
144 |
diff -ru usr/src/nv/nv.c usr/src/nv.2404825/nv.c |
145 |
--- usr/src/nv/nv.c 2008-04-02 01:17:56.000000000 -0700 |
146 |
+++ usr/src/nv.2404825/nv.c 2008-05-06 16:22:16.603101044 -0700 |
147 |
@@ -22,10 +22,9 @@ |
148 |
#endif |
149 |
|
150 |
#if defined(KERNEL_2_4) && (defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)) |
151 |
-// weak linking? |
152 |
extern int i2c_add_adapter (struct i2c_adapter *) __attribute__ ((weak)); |
153 |
extern int i2c_del_adapter (struct i2c_adapter *) __attribute__ ((weak)); |
154 |
-#endif // defined(KERNEL_2_4) && (defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)) |
155 |
+#endif |
156 |
|
157 |
/* |
158 |
* our global state; one per device |
159 |
@@ -41,14 +40,7 @@ |
160 |
static struct pm_dev *apm_nv_dev[NV_MAX_DEVICES] = { 0 }; |
161 |
#endif |
162 |
|
163 |
-int nv_pat_enabled = 0; |
164 |
- |
165 |
-#if !defined(NV_BUILD_NV_PAT_SUPPORT) |
166 |
-static int nv_disable_pat = 1; |
167 |
-#else |
168 |
-static int nv_disable_pat = 0; |
169 |
-NV_MODULE_PARAMETER(nv_disable_pat); |
170 |
-#endif |
171 |
+int nv_pat_mode = NV_PAT_MODE_DISABLED; |
172 |
|
173 |
#if defined(NVCPU_X86) || defined(NVCPU_X86_64) |
174 |
NvU64 __nv_supported_pte_mask = ~_PAGE_NX; |
175 |
@@ -611,7 +603,7 @@ |
176 |
nv_state_t *nv; |
177 |
nv_linux_state_t *nvl; |
178 |
|
179 |
- proc_nvidia = create_proc_entry("nvidia", d_flags, proc_root_driver); |
180 |
+ proc_nvidia = create_proc_entry("driver/nvidia", d_flags, NULL); |
181 |
if (!proc_nvidia) |
182 |
goto failed; |
183 |
|
184 |
@@ -863,18 +855,20 @@ |
185 |
static int __nv_enable_pat_support (void); |
186 |
static void __nv_disable_pat_support (void); |
187 |
|
188 |
-#if defined(NV_BUILD_NV_PAT_SUPPORT) |
189 |
+#if defined(NV_ENABLE_PAT_SUPPORT) |
190 |
/* |
191 |
- * Private PAT support for use by the NVIDIA driver. This is an |
192 |
- * interim solution until the kernel offers PAT support. |
193 |
+ * Private PAT support for use by the NVIDIA driver. This is used on |
194 |
+ * kernels that do not modify the PAT to include a write-combining |
195 |
+ * entry. |
196 |
*/ |
197 |
static int __check_pat_support (void); |
198 |
static void __nv_setup_pat_entries (void *); |
199 |
static void __nv_restore_pat_entries (void *); |
200 |
|
201 |
-#define NV_READ_PAT_ENTRIES(pat1, pat2) rdmsr(IA32_CR_PAT, (pat1), (pat2)) |
202 |
-#define NV_WRITE_PAT_ENTRIES(pat1, pat2) wrmsr(IA32_CR_PAT, (pat1), (pat2)) |
203 |
-#define NV_PAT_ENTRY(pat, index) (((pat) & (0xff<<((index)*8)))>>((index)*8)) |
204 |
+#define NV_READ_PAT_ENTRIES(pat1, pat2) rdmsr(0x277, (pat1), (pat2)) |
205 |
+#define NV_WRITE_PAT_ENTRIES(pat1, pat2) wrmsr(0x277, (pat1), (pat2)) |
206 |
+#define NV_PAT_ENTRY(pat, index) \ |
207 |
+ (((pat) & (0xff << ((index)*8))) >> ((index)*8)) |
208 |
|
209 |
static inline void __nv_disable_caches(unsigned long *cr4) |
210 |
{ |
211 |
@@ -898,8 +892,10 @@ |
212 |
static int __check_pat_support() |
213 |
{ |
214 |
unsigned int pat1, pat2, i; |
215 |
+ U008 PAT_WC_index; |
216 |
|
217 |
- if (!test_bit(X86_FEATURE_PAT, (volatile unsigned long *)&boot_cpu_data.x86_capability)) |
218 |
+ if (!test_bit(X86_FEATURE_PAT, |
219 |
+ (volatile unsigned long *)&boot_cpu_data.x86_capability)) |
220 |
{ |
221 |
nv_printf(NV_DBG_ERRORS, |
222 |
"NVRM: CPU does not support the PAT, falling back to MTRRs.\n"); |
223 |
@@ -907,24 +903,30 @@ |
224 |
} |
225 |
|
226 |
NV_READ_PAT_ENTRIES(pat1, pat2); |
227 |
+ PAT_WC_index = 0xf; |
228 |
|
229 |
for (i = 0; i < 4; i++) |
230 |
{ |
231 |
- // we plan to mark PAT entry 1 as WC. if it's already marked such, |
232 |
- // that's fine, since it would be no different than us setting it. |
233 |
- if ((i != 1) && NV_PAT_ENTRY(pat1, i) == 1) |
234 |
- { |
235 |
- nv_printf(NV_DBG_ERRORS, "NVRM: PAT index %d already configured for Write-Combining!\n", i); |
236 |
- nv_printf(NV_DBG_ERRORS, "NVRM: Aborting, due to PAT already being configured\n"); |
237 |
- return 0; |
238 |
- } |
239 |
- |
240 |
- if (NV_PAT_ENTRY(pat2, i) == 1) |
241 |
- { |
242 |
- nv_printf(NV_DBG_ERRORS, "NVRM: PAT index %d already configured for Write-Combining!\n", i + 4); |
243 |
- nv_printf(NV_DBG_ERRORS, "NVRM: Aborting, due to PAT already being configured\n"); |
244 |
- return 0; |
245 |
- } |
246 |
+ if (NV_PAT_ENTRY(pat1, i) == 0x01) |
247 |
+ { |
248 |
+ PAT_WC_index = i; |
249 |
+ break; |
250 |
+ } |
251 |
+ |
252 |
+ if (NV_PAT_ENTRY(pat2, i) == 0x01) |
253 |
+ { |
254 |
+ PAT_WC_index = (i + 4); |
255 |
+ break; |
256 |
+ } |
257 |
+ } |
258 |
+ |
259 |
+ if (PAT_WC_index == 1) |
260 |
+ nv_pat_mode = NV_PAT_MODE_KERNEL; |
261 |
+ else if (PAT_WC_index != 0xf) |
262 |
+ { |
263 |
+ nv_printf(NV_DBG_ERRORS, |
264 |
+ "NVRM: PAT configuration unsupported, falling back to MTRRs.\n"); |
265 |
+ return 0; |
266 |
} |
267 |
|
268 |
return 1; |
269 |
@@ -978,20 +980,22 @@ |
270 |
__nv_enable_caches(cr4); |
271 |
NV_RESTORE_FLAGS(eflags); |
272 |
} |
273 |
- |
274 |
-#endif /* defined(NV_BUILD_NV_PAT_SUPPORT) */ |
275 |
+#endif |
276 |
|
277 |
static int __nv_enable_pat_support() |
278 |
{ |
279 |
-#if defined(NV_BUILD_NV_PAT_SUPPORT) |
280 |
+#if defined(NV_ENABLE_PAT_SUPPORT) |
281 |
unsigned long pat1, pat2; |
282 |
|
283 |
- if (nv_pat_enabled) |
284 |
+ if (nv_pat_mode != NV_PAT_MODE_DISABLED) |
285 |
return 1; |
286 |
|
287 |
if (!__check_pat_support()) |
288 |
return 0; |
289 |
|
290 |
+ if (nv_pat_mode != NV_PAT_MODE_DISABLED) |
291 |
+ return 1; |
292 |
+ |
293 |
NV_READ_PAT_ENTRIES(orig_pat1, orig_pat2); |
294 |
nv_printf(NV_DBG_SETUP, "saved orig pats as 0x%lx 0x%lx\n", orig_pat1, orig_pat2); |
295 |
|
296 |
@@ -1001,31 +1005,30 @@ |
297 |
return 0; |
298 |
} |
299 |
|
300 |
- nv_pat_enabled = 1; |
301 |
+ nv_pat_mode = NV_PAT_MODE_BUILTIN; |
302 |
|
303 |
NV_READ_PAT_ENTRIES(pat1, pat2); |
304 |
nv_printf(NV_DBG_SETUP, "changed pats to 0x%lx 0x%lx\n", pat1, pat2); |
305 |
-#endif /* defined(NV_BUILD_NV_PAT_SUPPORT) */ |
306 |
- |
307 |
+#endif |
308 |
return 1; |
309 |
} |
310 |
|
311 |
static void __nv_disable_pat_support() |
312 |
{ |
313 |
-#if defined(NV_BUILD_NV_PAT_SUPPORT) |
314 |
+#if defined(NV_ENABLE_PAT_SUPPORT) |
315 |
unsigned long pat1, pat2; |
316 |
|
317 |
- if (!nv_pat_enabled) |
318 |
+ if (nv_pat_mode != NV_PAT_MODE_BUILTIN) |
319 |
return; |
320 |
|
321 |
if (nv_execute_on_all_cpus(__nv_restore_pat_entries, NULL) != 0) |
322 |
return; |
323 |
|
324 |
- nv_pat_enabled = 0; |
325 |
+ nv_pat_mode = NV_PAT_MODE_DISABLED; |
326 |
|
327 |
NV_READ_PAT_ENTRIES(pat1, pat2); |
328 |
nv_printf(NV_DBG_SETUP, "restored orig pats as 0x%lx 0x%lx\n", pat1, pat2); |
329 |
-#endif /* defined(NV_BUILD_NV_PAT_SUPPORT) */ |
330 |
+#endif |
331 |
} |
332 |
|
333 |
#if defined(NV_CHANGE_PAGE_ATTR_BUG_PRESENT) |
334 |
@@ -1242,7 +1245,7 @@ |
335 |
break; |
336 |
default: |
337 |
expected = pgprot_val(PAGE_KERNEL_NOCACHE); |
338 |
- if ((flags & ~_PAGE_NX) == (expected & ~_PAGE_NX)) |
339 |
+ if ((flags & ~(_PAGE_NX | _PAGE_PWT)) == (expected & ~(_PAGE_NX | _PAGE_PWT))) |
340 |
retval = 0; |
341 |
break; |
342 |
} |
343 |
@@ -1273,7 +1276,7 @@ |
344 |
#endif |
345 |
} |
346 |
|
347 |
-#if defined(NV_BUILD_NV_PAT_SUPPORT) && defined(CONFIG_HOTPLUG_CPU) |
348 |
+#if defined(NV_ENABLE_PAT_SUPPORT) && defined(CONFIG_HOTPLUG_CPU) |
349 |
static int |
350 |
nv_kern_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) |
351 |
{ |
352 |
@@ -1305,8 +1308,7 @@ |
353 |
.notifier_call = nv_kern_cpu_callback, |
354 |
.priority = 0 |
355 |
}; |
356 |
- |
357 |
-#endif /* defined(NV_BUILD_NV_PAT_SUPPORT) && defined(CONFIG_HOTPLUG_CPU) */ |
358 |
+#endif |
359 |
|
360 |
|
361 |
/*** |
362 |
@@ -1315,7 +1317,7 @@ |
363 |
|
364 |
static int __init nvidia_init_module(void) |
365 |
{ |
366 |
- int rc; |
367 |
+ int rc, disable_pat = 0; |
368 |
U032 i, count, data; |
369 |
nv_state_t *nv = NV_STATE_PTR(&nv_ctl_device); |
370 |
nv_stack_t *sp = NULL; |
371 |
@@ -1443,18 +1445,6 @@ |
372 |
nv_printf(NV_DBG_ERRORS, "NVRM: pte cache allocation failed\n"); |
373 |
goto failed; |
374 |
} |
375 |
- |
376 |
-#if defined(NV_BUILD_NV_PAT_SUPPORT) && defined(CONFIG_HOTPLUG_CPU) |
377 |
- if (!nv_disable_pat) |
378 |
- { |
379 |
- if (register_hotcpu_notifier(&nv_hotcpu_nfb) != 0) |
380 |
- { |
381 |
- rc = -EIO; |
382 |
- nv_printf(NV_DBG_ERRORS, "NVRM: CPU hotplug notifier registration failed!\n"); |
383 |
- goto failed; |
384 |
- } |
385 |
- } |
386 |
-#endif |
387 |
|
388 |
#if defined(NV_SG_MAP_BUFFERS) |
389 |
rm_read_registry_dword(sp, nv, "NVreg", "RemapLimit", &nv_remap_limit); |
390 |
@@ -1532,8 +1522,30 @@ |
391 |
|
392 |
nvos_proc_add_warning_file("README", __README_warning); |
393 |
|
394 |
- if (!nv_disable_pat) |
395 |
+ rc = rm_read_registry_dword(sp, nv, |
396 |
+ "NVreg", NV_USE_PAGE_ATTRIBUTE_TABLE, &data); |
397 |
+ if ((rc == 0) && ((int)data != ~0)) |
398 |
+ { |
399 |
+ disable_pat = (data == 0); |
400 |
+ } |
401 |
+ |
402 |
+ if (!disable_pat) |
403 |
+ { |
404 |
__nv_enable_pat_support(); |
405 |
+#if defined(NV_ENABLE_PAT_SUPPORT) && defined(CONFIG_HOTPLUG_CPU) |
406 |
+ if (nv_pat_mode == NV_PAT_MODE_BUILTIN) |
407 |
+ { |
408 |
+ if (register_hotcpu_notifier(&nv_hotcpu_nfb) != 0)) |
409 |
+ { |
410 |
+ __nv_disable_pat_support(); |
411 |
+ rc = -EIO; |
412 |
+ nv_printf(NV_DBG_ERRORS, |
413 |
+ "NVRM: CPU hotplug notifier registration failed!\n"); |
414 |
+ goto failed; |
415 |
+ } |
416 |
+ } |
417 |
+#endif |
418 |
+ } |
419 |
else |
420 |
{ |
421 |
nv_printf(NV_DBG_ERRORS, |
422 |
@@ -1686,10 +1698,10 @@ |
423 |
rm_unregister_compatible_ioctls(sp); |
424 |
#endif |
425 |
|
426 |
- if (nv_pat_enabled) |
427 |
+ if (nv_pat_mode == NV_PAT_MODE_BUILTIN) |
428 |
{ |
429 |
__nv_disable_pat_support(); |
430 |
-#if defined(NV_BUILD_NV_PAT_SUPPORT) && defined(CONFIG_HOTPLUG_CPU) |
431 |
+#if defined(NV_ENABLE_PAT_SUPPORT) && defined(CONFIG_HOTPLUG_CPU) |
432 |
unregister_hotcpu_notifier(&nv_hotcpu_nfb); |
433 |
#endif |
434 |
} |
435 |
@@ -1825,6 +1837,8 @@ |
436 |
} |
437 |
} |
438 |
|
439 |
+#if !defined(NV_VM_INSERT_PAGE_PRESENT) |
440 |
+static |
441 |
struct page *nv_kern_vma_nopage( |
442 |
struct vm_area_struct *vma, |
443 |
unsigned long address, |
444 |
@@ -1835,22 +1849,21 @@ |
445 |
#endif |
446 |
) |
447 |
{ |
448 |
-#if !defined(NV_VM_INSERT_PAGE_PRESENT) |
449 |
struct page *page; |
450 |
|
451 |
page = pfn_to_page(vma->vm_pgoff); |
452 |
get_page(page); |
453 |
|
454 |
return page; |
455 |
-#else |
456 |
- return NOPAGE_SIGBUS; |
457 |
-#endif |
458 |
} |
459 |
+#endif |
460 |
|
461 |
struct vm_operations_struct nv_vm_ops = { |
462 |
.open = nv_kern_vma_open, |
463 |
.close = nv_kern_vma_release, /* "close" */ |
464 |
+#if !defined(NV_VM_INSERT_PAGE_PRESENT) |
465 |
.nopage = nv_kern_vma_nopage, |
466 |
+#endif |
467 |
}; |
468 |
|
469 |
static nv_file_private_t * |
470 |
@@ -1864,7 +1877,7 @@ |
471 |
|
472 |
memset(nvfp, 0, sizeof(nv_file_private_t)); |
473 |
|
474 |
- sema_init(&nvfp->sp_lock, 1); |
475 |
+ NV_INIT_MUTEX(&nvfp->sp_lock); |
476 |
|
477 |
// initialize this file's event queue |
478 |
init_waitqueue_head(&nvfp->waitqueue); |
479 |
@@ -2214,11 +2227,12 @@ |
480 |
break; |
481 |
#if defined(NVCPU_X86) || defined(NVCPU_X86_64) |
482 |
case NV_MEMORY_WRITECOMBINED: |
483 |
-#if defined(NV_BUILD_NV_PAT_SUPPORT) |
484 |
- if (nv_pat_enabled && |
485 |
- (memory_type != NV_MEMORY_TYPE_REGISTERS)) |
486 |
+#if defined(NV_ENABLE_PAT_SUPPORT) |
487 |
+ if ((nv_pat_mode != NV_PAT_MODE_DISABLED) && |
488 |
+ (memory_type != NV_MEMORY_TYPE_REGISTERS)) |
489 |
{ |
490 |
- *prot = pgprot_writecombined(*prot); |
491 |
+ pgprot_val(*prot) &= ~(_PAGE_PSE | _PAGE_PCD | _PAGE_PWT); |
492 |
+ *prot = __pgprot(pgprot_val(*prot) | _PAGE_PWT); |
493 |
break; |
494 |
} |
495 |
#endif |
496 |
@@ -2242,7 +2256,6 @@ |
497 |
return 1; |
498 |
#endif |
499 |
case NV_MEMORY_CACHED: |
500 |
- //case NV_MEMORY_WRITEBACK: |
501 |
#if !defined(NVCPU_X86) && !defined(NVCPU_X86_64) |
502 |
if (memory_type != NV_MEMORY_TYPE_REGISTERS) |
503 |
break; |
504 |
@@ -2264,8 +2277,6 @@ |
505 |
if (memory_type == NV_MEMORY_TYPE_SYSTEM) |
506 |
break; |
507 |
#endif |
508 |
- //case NV_MEMORY_WRITETHRU: |
509 |
- //case NV_MEMORY_WRITEPROTECT: |
510 |
default: |
511 |
if(nv_ext_encode_caching(prot, cache_type, memory_type) == 0) |
512 |
return 0; |
513 |
@@ -3501,6 +3512,10 @@ |
514 |
BOOL kern |
515 |
) |
516 |
{ |
517 |
+#if defined(NV_SET_PAGES_UC_PRESENT) && defined(NVCPU_X86) |
518 |
+ nv_printf(NV_DBG_ERRORS, |
519 |
+ "NVRM: can't translate address in nv_get_phys_address()!\n"); |
520 |
+#else |
521 |
struct mm_struct *mm; |
522 |
pgd_t *pgd = NULL; |
523 |
pmd_t *pmd = NULL; |
524 |
@@ -3513,15 +3528,7 @@ |
525 |
down_read(&mm->mmap_sem); |
526 |
} |
527 |
else |
528 |
- { |
529 |
-#if defined(NV_SET_PAGES_UC_PRESENT) && defined(NVCPU_X86) |
530 |
- nv_printf(NV_DBG_ERRORS, |
531 |
- "NVRM: can't translate KVA in nv_get_phys_address()!\n"); |
532 |
- return 0; |
533 |
-#else |
534 |
mm = NULL; |
535 |
-#endif |
536 |
- } |
537 |
|
538 |
pgd = NV_PGD_OFFSET(address, kern, mm); |
539 |
if (!NV_PGD_PRESENT(pgd)) |
540 |
@@ -3549,6 +3556,7 @@ |
541 |
failed: |
542 |
if (!kern) |
543 |
up_read(&mm->mmap_sem); |
544 |
+#endif |
545 |
return 0; |
546 |
} |
547 |
|
548 |
@@ -3789,8 +3797,9 @@ |
549 |
|
550 |
nv_init_lock(nvl->rm_lock); |
551 |
|
552 |
- sema_init(&nvl->ldata_lock, 1); |
553 |
- sema_init(&nvl->at_lock, 1); |
554 |
+ NV_INIT_MUTEX(&nvl->ldata_lock); |
555 |
+ NV_INIT_MUTEX(&nvl->at_lock); |
556 |
+ |
557 |
NV_ATOMIC_SET(nvl->usage_count, 0); |
558 |
|
559 |
nvl->rm_lock_cpu = -1; |
560 |
diff -ru usr/src/nv/os-agp.c usr/src/nv.2404825/os-agp.c |
561 |
--- usr/src/nv/os-agp.c 2008-04-02 01:17:56.000000000 -0700 |
562 |
+++ usr/src/nv.2404825/os-agp.c 2008-05-06 16:22:16.603101044 -0700 |
563 |
@@ -115,7 +115,7 @@ |
564 |
goto release; |
565 |
} |
566 |
|
567 |
- if (!nv_pat_enabled) |
568 |
+ if (nv_pat_mode == NV_PAT_MODE_DISABLED) |
569 |
{ |
570 |
#ifdef CONFIG_MTRR |
571 |
/* |
572 |
@@ -175,7 +175,7 @@ |
573 |
|
574 |
failed: |
575 |
#ifdef CONFIG_MTRR |
576 |
- if (!nv_pat_enabled) |
577 |
+ if (nv_pat_mode == NV_PAT_MODE_DISABLED) |
578 |
mtrr_del(-1, agp_info.aper_base, agp_info.aper_size << 20); |
579 |
#endif |
580 |
release: |
581 |
@@ -205,7 +205,7 @@ |
582 |
nvl = NV_GET_NVL_FROM_NV_STATE(nv); |
583 |
|
584 |
#ifdef CONFIG_MTRR |
585 |
- if (!nv_pat_enabled) |
586 |
+ if (nv_pat_mode == NV_PAT_MODE_DISABLED) |
587 |
mtrr_del(-1, nv->agp.address, nv->agp.size); |
588 |
#endif |
589 |
|
590 |
diff -ru usr/src/nv/os-interface.c usr/src/nv.2404825/os-interface.c |
591 |
--- usr/src/nv/os-interface.c 2008-04-02 01:17:56.000000000 -0700 |
592 |
+++ usr/src/nv.2404825/os-interface.c 2008-05-06 16:22:16.607101272 -0700 |
593 |
@@ -1355,7 +1355,7 @@ |
594 |
|
595 |
BOOL NV_API_CALL os_pat_supported(void) |
596 |
{ |
597 |
- return nv_pat_enabled; |
598 |
+ return (nv_pat_mode != NV_PAT_MODE_DISABLED); |
599 |
} |
600 |
|
601 |
void NV_API_CALL os_dump_stack() |
602 |
|
603 |
|
604 |
|
605 |
-- |
606 |
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