Gentoo Archives: gentoo-commits

From: Mike Pagano <mpagano@g.o>
To: gentoo-commits@l.g.o
Subject: [gentoo-commits] proj/linux-patches:4.16 commit in: /
Date: Wed, 02 May 2018 16:15:44
Message-Id: 1525277730.7cde86eb95c44a9bfb0eab9ae50e3ac566563f2c.mpagano@gentoo
1 commit: 7cde86eb95c44a9bfb0eab9ae50e3ac566563f2c
2 Author: Mike Pagano <mpagano <AT> gentoo <DOT> org>
3 AuthorDate: Wed May 2 16:15:30 2018 +0000
4 Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org>
5 CommitDate: Wed May 2 16:15:30 2018 +0000
6 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=7cde86eb
7
8 Linux patch 4.16.7
9
10 0000_README | 4 +
11 1006_linux-4.16.7.patch | 4737 +++++++++++++++++++++++++++++++++++++++++++++++
12 2 files changed, 4741 insertions(+)
13
14 diff --git a/0000_README b/0000_README
15 index d4182dc..1139362 100644
16 --- a/0000_README
17 +++ b/0000_README
18 @@ -67,6 +67,10 @@ Patch: 1005_linux-4.16.6.patch
19 From: http://www.kernel.org
20 Desc: Linux 4.16.6
21
22 +Patch: 1006_linux-4.16.7.patch
23 +From: http://www.kernel.org
24 +Desc: Linux 4.16.7
25 +
26 Patch: 1500_XATTR_USER_PREFIX.patch
27 From: https://bugs.gentoo.org/show_bug.cgi?id=470644
28 Desc: Support for namespace user.pax.* on tmpfs.
29
30 diff --git a/1006_linux-4.16.7.patch b/1006_linux-4.16.7.patch
31 new file mode 100644
32 index 0000000..4dec6c8
33 --- /dev/null
34 +++ b/1006_linux-4.16.7.patch
35 @@ -0,0 +1,4737 @@
36 +diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt
37 +index d6b3ff51a14f..36187fc32ab2 100644
38 +--- a/Documentation/virtual/kvm/api.txt
39 ++++ b/Documentation/virtual/kvm/api.txt
40 +@@ -1960,6 +1960,9 @@ ARM 32-bit VFP control registers have the following id bit patterns:
41 + ARM 64-bit FP registers have the following id bit patterns:
42 + 0x4030 0000 0012 0 <regno:12>
43 +
44 ++ARM firmware pseudo-registers have the following bit pattern:
45 ++ 0x4030 0000 0014 <regno:16>
46 ++
47 +
48 + arm64 registers are mapped using the lower 32 bits. The upper 16 of
49 + that is the register group type, or coprocessor number:
50 +@@ -1976,6 +1979,9 @@ arm64 CCSIDR registers are demultiplexed by CSSELR value:
51 + arm64 system registers have the following id bit patterns:
52 + 0x6030 0000 0013 <op0:2> <op1:3> <crn:4> <crm:4> <op2:3>
53 +
54 ++arm64 firmware pseudo-registers have the following bit pattern:
55 ++ 0x6030 0000 0014 <regno:16>
56 ++
57 +
58 + MIPS registers are mapped using the lower 32 bits. The upper 16 of that is
59 + the register group type:
60 +@@ -2510,7 +2516,8 @@ Possible features:
61 + and execute guest code when KVM_RUN is called.
62 + - KVM_ARM_VCPU_EL1_32BIT: Starts the CPU in a 32bit mode.
63 + Depends on KVM_CAP_ARM_EL1_32BIT (arm64 only).
64 +- - KVM_ARM_VCPU_PSCI_0_2: Emulate PSCI v0.2 for the CPU.
65 ++ - KVM_ARM_VCPU_PSCI_0_2: Emulate PSCI v0.2 (or a future revision
66 ++ backward compatible with v0.2) for the CPU.
67 + Depends on KVM_CAP_ARM_PSCI_0_2.
68 + - KVM_ARM_VCPU_PMU_V3: Emulate PMUv3 for the CPU.
69 + Depends on KVM_CAP_ARM_PMU_V3.
70 +diff --git a/Documentation/virtual/kvm/arm/psci.txt b/Documentation/virtual/kvm/arm/psci.txt
71 +new file mode 100644
72 +index 000000000000..aafdab887b04
73 +--- /dev/null
74 ++++ b/Documentation/virtual/kvm/arm/psci.txt
75 +@@ -0,0 +1,30 @@
76 ++KVM implements the PSCI (Power State Coordination Interface)
77 ++specification in order to provide services such as CPU on/off, reset
78 ++and power-off to the guest.
79 ++
80 ++The PSCI specification is regularly updated to provide new features,
81 ++and KVM implements these updates if they make sense from a virtualization
82 ++point of view.
83 ++
84 ++This means that a guest booted on two different versions of KVM can
85 ++observe two different "firmware" revisions. This could cause issues if
86 ++a given guest is tied to a particular PSCI revision (unlikely), or if
87 ++a migration causes a different PSCI version to be exposed out of the
88 ++blue to an unsuspecting guest.
89 ++
90 ++In order to remedy this situation, KVM exposes a set of "firmware
91 ++pseudo-registers" that can be manipulated using the GET/SET_ONE_REG
92 ++interface. These registers can be saved/restored by userspace, and set
93 ++to a convenient value if required.
94 ++
95 ++The following register is defined:
96 ++
97 ++* KVM_REG_ARM_PSCI_VERSION:
98 ++
99 ++ - Only valid if the vcpu has the KVM_ARM_VCPU_PSCI_0_2 feature set
100 ++ (and thus has already been initialized)
101 ++ - Returns the current PSCI version on GET_ONE_REG (defaulting to the
102 ++ highest PSCI version implemented by KVM and compatible with v0.2)
103 ++ - Allows any PSCI version implemented by KVM and compatible with
104 ++ v0.2 to be set with SET_ONE_REG
105 ++ - Affects the whole VM (even if the register view is per-vcpu)
106 +diff --git a/Makefile b/Makefile
107 +index 41f07b2b7905..1c5d5d8c45e2 100644
108 +--- a/Makefile
109 ++++ b/Makefile
110 +@@ -1,7 +1,7 @@
111 + # SPDX-License-Identifier: GPL-2.0
112 + VERSION = 4
113 + PATCHLEVEL = 16
114 +-SUBLEVEL = 6
115 ++SUBLEVEL = 7
116 + EXTRAVERSION =
117 + NAME = Fearless Coyote
118 +
119 +diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts
120 +index 8bbb6f85d161..4785fbcc41ed 100644
121 +--- a/arch/arm/boot/dts/gemini-nas4220b.dts
122 ++++ b/arch/arm/boot/dts/gemini-nas4220b.dts
123 +@@ -134,37 +134,37 @@
124 + function = "gmii";
125 + groups = "gmii_gmac0_grp";
126 + };
127 +- /* Settings come from OpenWRT */
128 ++ /* Settings come from OpenWRT, pins on SL3516 */
129 + conf0 {
130 +- pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV";
131 ++ pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV";
132 + skew-delay = <0>;
133 + };
134 + conf1 {
135 +- pins = "T8 GMAC0 RXC", "T11 GMAC1 RXC";
136 ++ pins = "Y7 GMAC0 RXC", "Y11 GMAC1 RXC";
137 + skew-delay = <15>;
138 + };
139 + conf2 {
140 +- pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN";
141 ++ pins = "T8 GMAC0 TXEN", "W11 GMAC1 TXEN";
142 + skew-delay = <7>;
143 + };
144 + conf3 {
145 +- pins = "V7 GMAC0 TXC";
146 ++ pins = "U8 GMAC0 TXC";
147 + skew-delay = <11>;
148 + };
149 + conf4 {
150 +- pins = "P10 GMAC1 TXC";
151 ++ pins = "V11 GMAC1 TXC";
152 + skew-delay = <10>;
153 + };
154 + conf5 {
155 + /* The data lines all have default skew */
156 +- pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1",
157 +- "P9 GMAC0 RXD2", "R9 GMAC0 RXD3",
158 +- "U7 GMAC0 TXD0", "T7 GMAC0 TXD1",
159 +- "R7 GMAC0 TXD2", "P7 GMAC0 TXD3",
160 +- "R11 GMAC1 RXD0", "P11 GMAC1 RXD1",
161 +- "V12 GMAC1 RXD2", "U12 GMAC1 RXD3",
162 +- "R10 GMAC1 TXD0", "T10 GMAC1 TXD1",
163 +- "U10 GMAC1 TXD2", "V10 GMAC1 TXD3";
164 ++ pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1",
165 ++ "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3",
166 ++ "T7 GMAC0 TXD0", "U6 GMAC0 TXD1",
167 ++ "V7 GMAC0 TXD2", "U7 GMAC0 TXD3",
168 ++ "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1",
169 ++ "T11 GMAC1 RXD2", "W12 GMAC1 RXD3",
170 ++ "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1",
171 ++ "W10 GMAC1 TXD2", "T9 GMAC1 TXD3";
172 + skew-delay = <7>;
173 + };
174 + /* Set up drive strength on GMAC0 to 16 mA */
175 +diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
176 +index 2620ce790db0..371fca4e1ab7 100644
177 +--- a/arch/arm/configs/socfpga_defconfig
178 ++++ b/arch/arm/configs/socfpga_defconfig
179 +@@ -57,6 +57,7 @@ CONFIG_MTD_M25P80=y
180 + CONFIG_MTD_NAND=y
181 + CONFIG_MTD_NAND_DENALI_DT=y
182 + CONFIG_MTD_SPI_NOR=y
183 ++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
184 + CONFIG_SPI_CADENCE_QUADSPI=y
185 + CONFIG_OF_OVERLAY=y
186 + CONFIG_OF_CONFIGFS=y
187 +diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
188 +index 248b930563e5..8b908d23c58a 100644
189 +--- a/arch/arm/include/asm/kvm_host.h
190 ++++ b/arch/arm/include/asm/kvm_host.h
191 +@@ -77,6 +77,9 @@ struct kvm_arch {
192 + /* Interrupt controller */
193 + struct vgic_dist vgic;
194 + int max_vcpus;
195 ++
196 ++ /* Mandated version of PSCI */
197 ++ u32 psci_version;
198 + };
199 +
200 + #define KVM_NR_MEM_OBJS 40
201 +diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
202 +index 6edd177bb1c7..47dfc99f5cd0 100644
203 +--- a/arch/arm/include/uapi/asm/kvm.h
204 ++++ b/arch/arm/include/uapi/asm/kvm.h
205 +@@ -186,6 +186,12 @@ struct kvm_arch_memory_slot {
206 + #define KVM_REG_ARM_VFP_FPINST 0x1009
207 + #define KVM_REG_ARM_VFP_FPINST2 0x100A
208 +
209 ++/* KVM-as-firmware specific pseudo-registers */
210 ++#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
211 ++#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM | KVM_REG_SIZE_U64 | \
212 ++ KVM_REG_ARM_FW | ((r) & 0xffff))
213 ++#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)
214 ++
215 + /* Device Control API: ARM VGIC */
216 + #define KVM_DEV_ARM_VGIC_GRP_ADDR 0
217 + #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
218 +diff --git a/arch/arm/kvm/guest.c b/arch/arm/kvm/guest.c
219 +index 1e0784ebbfd6..a18f33edc471 100644
220 +--- a/arch/arm/kvm/guest.c
221 ++++ b/arch/arm/kvm/guest.c
222 +@@ -22,6 +22,7 @@
223 + #include <linux/module.h>
224 + #include <linux/vmalloc.h>
225 + #include <linux/fs.h>
226 ++#include <kvm/arm_psci.h>
227 + #include <asm/cputype.h>
228 + #include <linux/uaccess.h>
229 + #include <asm/kvm.h>
230 +@@ -176,6 +177,7 @@ static unsigned long num_core_regs(void)
231 + unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu)
232 + {
233 + return num_core_regs() + kvm_arm_num_coproc_regs(vcpu)
234 ++ + kvm_arm_get_fw_num_regs(vcpu)
235 + + NUM_TIMER_REGS;
236 + }
237 +
238 +@@ -196,6 +198,11 @@ int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
239 + uindices++;
240 + }
241 +
242 ++ ret = kvm_arm_copy_fw_reg_indices(vcpu, uindices);
243 ++ if (ret)
244 ++ return ret;
245 ++ uindices += kvm_arm_get_fw_num_regs(vcpu);
246 ++
247 + ret = copy_timer_indices(vcpu, uindices);
248 + if (ret)
249 + return ret;
250 +@@ -214,6 +221,9 @@ int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
251 + if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
252 + return get_core_reg(vcpu, reg);
253 +
254 ++ if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_FW)
255 ++ return kvm_arm_get_fw_reg(vcpu, reg);
256 ++
257 + if (is_timer_reg(reg->id))
258 + return get_timer_reg(vcpu, reg);
259 +
260 +@@ -230,6 +240,9 @@ int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
261 + if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
262 + return set_core_reg(vcpu, reg);
263 +
264 ++ if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_FW)
265 ++ return kvm_arm_set_fw_reg(vcpu, reg);
266 ++
267 + if (is_timer_reg(reg->id))
268 + return set_timer_reg(vcpu, reg);
269 +
270 +diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
271 +index 596f8e414a4c..b9e355bd3b78 100644
272 +--- a/arch/arm64/include/asm/kvm_host.h
273 ++++ b/arch/arm64/include/asm/kvm_host.h
274 +@@ -75,6 +75,9 @@ struct kvm_arch {
275 +
276 + /* Interrupt controller */
277 + struct vgic_dist vgic;
278 ++
279 ++ /* Mandated version of PSCI */
280 ++ u32 psci_version;
281 + };
282 +
283 + #define KVM_NR_MEM_OBJS 40
284 +diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
285 +index 9abbf3044654..04b3256f8e6d 100644
286 +--- a/arch/arm64/include/uapi/asm/kvm.h
287 ++++ b/arch/arm64/include/uapi/asm/kvm.h
288 +@@ -206,6 +206,12 @@ struct kvm_arch_memory_slot {
289 + #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
290 + #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
291 +
292 ++/* KVM-as-firmware specific pseudo-registers */
293 ++#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
294 ++#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
295 ++ KVM_REG_ARM_FW | ((r) & 0xffff))
296 ++#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)
297 ++
298 + /* Device Control API: ARM VGIC */
299 + #define KVM_DEV_ARM_VGIC_GRP_ADDR 0
300 + #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
301 +diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c
302 +index 959e50d2588c..56a0260ceb11 100644
303 +--- a/arch/arm64/kvm/guest.c
304 ++++ b/arch/arm64/kvm/guest.c
305 +@@ -25,6 +25,7 @@
306 + #include <linux/module.h>
307 + #include <linux/vmalloc.h>
308 + #include <linux/fs.h>
309 ++#include <kvm/arm_psci.h>
310 + #include <asm/cputype.h>
311 + #include <linux/uaccess.h>
312 + #include <asm/kvm.h>
313 +@@ -205,7 +206,7 @@ static int get_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
314 + unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu)
315 + {
316 + return num_core_regs() + kvm_arm_num_sys_reg_descs(vcpu)
317 +- + NUM_TIMER_REGS;
318 ++ + kvm_arm_get_fw_num_regs(vcpu) + NUM_TIMER_REGS;
319 + }
320 +
321 + /**
322 +@@ -225,6 +226,11 @@ int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
323 + uindices++;
324 + }
325 +
326 ++ ret = kvm_arm_copy_fw_reg_indices(vcpu, uindices);
327 ++ if (ret)
328 ++ return ret;
329 ++ uindices += kvm_arm_get_fw_num_regs(vcpu);
330 ++
331 + ret = copy_timer_indices(vcpu, uindices);
332 + if (ret)
333 + return ret;
334 +@@ -243,6 +249,9 @@ int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
335 + if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
336 + return get_core_reg(vcpu, reg);
337 +
338 ++ if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_FW)
339 ++ return kvm_arm_get_fw_reg(vcpu, reg);
340 ++
341 + if (is_timer_reg(reg->id))
342 + return get_timer_reg(vcpu, reg);
343 +
344 +@@ -259,6 +268,9 @@ int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
345 + if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
346 + return set_core_reg(vcpu, reg);
347 +
348 ++ if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_FW)
349 ++ return kvm_arm_set_fw_reg(vcpu, reg);
350 ++
351 + if (is_timer_reg(reg->id))
352 + return set_timer_reg(vcpu, reg);
353 +
354 +diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c
355 +index fe6fc63251fe..38c5b4764bfe 100644
356 +--- a/arch/powerpc/kernel/mce_power.c
357 ++++ b/arch/powerpc/kernel/mce_power.c
358 +@@ -441,7 +441,6 @@ static int mce_handle_ierror(struct pt_regs *regs,
359 + if (pfn != ULONG_MAX) {
360 + *phys_addr =
361 + (pfn << PAGE_SHIFT);
362 +- handled = 1;
363 + }
364 + }
365 + }
366 +@@ -532,9 +531,7 @@ static int mce_handle_derror(struct pt_regs *regs,
367 + * kernel/exception-64s.h
368 + */
369 + if (get_paca()->in_mce < MAX_MCE_DEPTH)
370 +- if (!mce_find_instr_ea_and_pfn(regs, addr,
371 +- phys_addr))
372 +- handled = 1;
373 ++ mce_find_instr_ea_and_pfn(regs, addr, phys_addr);
374 + }
375 + found = 1;
376 + }
377 +@@ -572,7 +569,7 @@ static long mce_handle_error(struct pt_regs *regs,
378 + const struct mce_ierror_table itable[])
379 + {
380 + struct mce_error_info mce_err = { 0 };
381 +- uint64_t addr, phys_addr;
382 ++ uint64_t addr, phys_addr = ULONG_MAX;
383 + uint64_t srr1 = regs->msr;
384 + long handled;
385 +
386 +diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
387 +index fe8c61149fb8..0cd9031b6b54 100644
388 +--- a/arch/powerpc/mm/mem.c
389 ++++ b/arch/powerpc/mm/mem.c
390 +@@ -143,6 +143,7 @@ int arch_add_memory(int nid, u64 start, u64 size, struct vmem_altmap *altmap,
391 + start, start + size, rc);
392 + return -EFAULT;
393 + }
394 ++ flush_inval_dcache_range(start, start + size);
395 +
396 + return __add_pages(nid, start_pfn, nr_pages, altmap, want_memblock);
397 + }
398 +@@ -169,6 +170,7 @@ int arch_remove_memory(u64 start, u64 size, struct vmem_altmap *altmap)
399 +
400 + /* Remove htab bolted mappings for this section of memory */
401 + start = (unsigned long)__va(start);
402 ++ flush_inval_dcache_range(start, start + size);
403 + ret = remove_section_mapping(start, start + size);
404 +
405 + /* Ensure all vmalloc mappings are flushed in case they also
406 +diff --git a/arch/powerpc/platforms/powernv/npu-dma.c b/arch/powerpc/platforms/powernv/npu-dma.c
407 +index 0a253b64ac5f..e7b621f619b2 100644
408 +--- a/arch/powerpc/platforms/powernv/npu-dma.c
409 ++++ b/arch/powerpc/platforms/powernv/npu-dma.c
410 +@@ -33,6 +33,13 @@
411 +
412 + #define npu_to_phb(x) container_of(x, struct pnv_phb, npu)
413 +
414 ++/*
415 ++ * When an address shootdown range exceeds this threshold we invalidate the
416 ++ * entire TLB on the GPU for the given PID rather than each specific address in
417 ++ * the range.
418 ++ */
419 ++#define ATSD_THRESHOLD (2*1024*1024)
420 ++
421 + /*
422 + * Other types of TCE cache invalidation are not functional in the
423 + * hardware.
424 +@@ -627,11 +634,19 @@ static void pnv_npu2_mn_invalidate_range(struct mmu_notifier *mn,
425 + struct npu_context *npu_context = mn_to_npu_context(mn);
426 + unsigned long address;
427 +
428 +- for (address = start; address < end; address += PAGE_SIZE)
429 +- mmio_invalidate(npu_context, 1, address, false);
430 ++ if (end - start > ATSD_THRESHOLD) {
431 ++ /*
432 ++ * Just invalidate the entire PID if the address range is too
433 ++ * large.
434 ++ */
435 ++ mmio_invalidate(npu_context, 0, 0, true);
436 ++ } else {
437 ++ for (address = start; address < end; address += PAGE_SIZE)
438 ++ mmio_invalidate(npu_context, 1, address, false);
439 +
440 +- /* Do the flush only on the final addess == end */
441 +- mmio_invalidate(npu_context, 1, address, true);
442 ++ /* Do the flush only on the final addess == end */
443 ++ mmio_invalidate(npu_context, 1, address, true);
444 ++ }
445 + }
446 +
447 + static const struct mmu_notifier_ops nv_nmmu_notifier_ops = {
448 +diff --git a/arch/powerpc/platforms/powernv/opal-rtc.c b/arch/powerpc/platforms/powernv/opal-rtc.c
449 +index f8868864f373..aa2a5139462e 100644
450 +--- a/arch/powerpc/platforms/powernv/opal-rtc.c
451 ++++ b/arch/powerpc/platforms/powernv/opal-rtc.c
452 +@@ -48,10 +48,12 @@ unsigned long __init opal_get_boot_time(void)
453 +
454 + while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
455 + rc = opal_rtc_read(&__y_m_d, &__h_m_s_ms);
456 +- if (rc == OPAL_BUSY_EVENT)
457 ++ if (rc == OPAL_BUSY_EVENT) {
458 ++ mdelay(OPAL_BUSY_DELAY_MS);
459 + opal_poll_events(NULL);
460 +- else if (rc == OPAL_BUSY)
461 +- mdelay(10);
462 ++ } else if (rc == OPAL_BUSY) {
463 ++ mdelay(OPAL_BUSY_DELAY_MS);
464 ++ }
465 + }
466 + if (rc != OPAL_SUCCESS)
467 + return 0;
468 +diff --git a/arch/sparc/include/uapi/asm/oradax.h b/arch/sparc/include/uapi/asm/oradax.h
469 +index 722951908b0a..4f6676fe4bcc 100644
470 +--- a/arch/sparc/include/uapi/asm/oradax.h
471 ++++ b/arch/sparc/include/uapi/asm/oradax.h
472 +@@ -3,7 +3,7 @@
473 + *
474 + * This program is free software: you can redistribute it and/or modify
475 + * it under the terms of the GNU General Public License as published by
476 +- * the Free Software Foundation, either version 3 of the License, or
477 ++ * the Free Software Foundation, either version 2 of the License, or
478 + * (at your option) any later version.
479 + *
480 + * This program is distributed in the hope that it will be useful,
481 +diff --git a/arch/x86/include/uapi/asm/msgbuf.h b/arch/x86/include/uapi/asm/msgbuf.h
482 +index 809134c644a6..90ab9a795b49 100644
483 +--- a/arch/x86/include/uapi/asm/msgbuf.h
484 ++++ b/arch/x86/include/uapi/asm/msgbuf.h
485 +@@ -1 +1,32 @@
486 ++/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
487 ++#ifndef __ASM_X64_MSGBUF_H
488 ++#define __ASM_X64_MSGBUF_H
489 ++
490 ++#if !defined(__x86_64__) || !defined(__ILP32__)
491 + #include <asm-generic/msgbuf.h>
492 ++#else
493 ++/*
494 ++ * The msqid64_ds structure for x86 architecture with x32 ABI.
495 ++ *
496 ++ * On x86-32 and x86-64 we can just use the generic definition, but
497 ++ * x32 uses the same binary layout as x86_64, which is differnet
498 ++ * from other 32-bit architectures.
499 ++ */
500 ++
501 ++struct msqid64_ds {
502 ++ struct ipc64_perm msg_perm;
503 ++ __kernel_time_t msg_stime; /* last msgsnd time */
504 ++ __kernel_time_t msg_rtime; /* last msgrcv time */
505 ++ __kernel_time_t msg_ctime; /* last change time */
506 ++ __kernel_ulong_t msg_cbytes; /* current number of bytes on queue */
507 ++ __kernel_ulong_t msg_qnum; /* number of messages in queue */
508 ++ __kernel_ulong_t msg_qbytes; /* max number of bytes on queue */
509 ++ __kernel_pid_t msg_lspid; /* pid of last msgsnd */
510 ++ __kernel_pid_t msg_lrpid; /* last receive pid */
511 ++ __kernel_ulong_t __unused4;
512 ++ __kernel_ulong_t __unused5;
513 ++};
514 ++
515 ++#endif
516 ++
517 ++#endif /* __ASM_GENERIC_MSGBUF_H */
518 +diff --git a/arch/x86/include/uapi/asm/shmbuf.h b/arch/x86/include/uapi/asm/shmbuf.h
519 +index 83c05fc2de38..644421f3823b 100644
520 +--- a/arch/x86/include/uapi/asm/shmbuf.h
521 ++++ b/arch/x86/include/uapi/asm/shmbuf.h
522 +@@ -1 +1,43 @@
523 ++/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
524 ++#ifndef __ASM_X86_SHMBUF_H
525 ++#define __ASM_X86_SHMBUF_H
526 ++
527 ++#if !defined(__x86_64__) || !defined(__ILP32__)
528 + #include <asm-generic/shmbuf.h>
529 ++#else
530 ++/*
531 ++ * The shmid64_ds structure for x86 architecture with x32 ABI.
532 ++ *
533 ++ * On x86-32 and x86-64 we can just use the generic definition, but
534 ++ * x32 uses the same binary layout as x86_64, which is differnet
535 ++ * from other 32-bit architectures.
536 ++ */
537 ++
538 ++struct shmid64_ds {
539 ++ struct ipc64_perm shm_perm; /* operation perms */
540 ++ size_t shm_segsz; /* size of segment (bytes) */
541 ++ __kernel_time_t shm_atime; /* last attach time */
542 ++ __kernel_time_t shm_dtime; /* last detach time */
543 ++ __kernel_time_t shm_ctime; /* last change time */
544 ++ __kernel_pid_t shm_cpid; /* pid of creator */
545 ++ __kernel_pid_t shm_lpid; /* pid of last operator */
546 ++ __kernel_ulong_t shm_nattch; /* no. of current attaches */
547 ++ __kernel_ulong_t __unused4;
548 ++ __kernel_ulong_t __unused5;
549 ++};
550 ++
551 ++struct shminfo64 {
552 ++ __kernel_ulong_t shmmax;
553 ++ __kernel_ulong_t shmmin;
554 ++ __kernel_ulong_t shmmni;
555 ++ __kernel_ulong_t shmseg;
556 ++ __kernel_ulong_t shmall;
557 ++ __kernel_ulong_t __unused1;
558 ++ __kernel_ulong_t __unused2;
559 ++ __kernel_ulong_t __unused3;
560 ++ __kernel_ulong_t __unused4;
561 ++};
562 ++
563 ++#endif
564 ++
565 ++#endif /* __ASM_X86_SHMBUF_H */
566 +diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c
567 +index 10c4fc2c91f8..77e201301528 100644
568 +--- a/arch/x86/kernel/cpu/microcode/core.c
569 ++++ b/arch/x86/kernel/cpu/microcode/core.c
570 +@@ -564,14 +564,12 @@ static int __reload_late(void *info)
571 + apply_microcode_local(&err);
572 + spin_unlock(&update_lock);
573 +
574 ++ /* siblings return UCODE_OK because their engine got updated already */
575 + if (err > UCODE_NFOUND) {
576 + pr_warn("Error reloading microcode on CPU %d\n", cpu);
577 +- return -1;
578 +- /* siblings return UCODE_OK because their engine got updated already */
579 ++ ret = -1;
580 + } else if (err == UCODE_UPDATED || err == UCODE_OK) {
581 + ret = 1;
582 +- } else {
583 +- return ret;
584 + }
585 +
586 + /*
587 +diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
588 +index 32b8e5724f96..1c2cfa0644aa 100644
589 +--- a/arch/x86/kernel/cpu/microcode/intel.c
590 ++++ b/arch/x86/kernel/cpu/microcode/intel.c
591 +@@ -485,7 +485,6 @@ static void show_saved_mc(void)
592 + */
593 + static void save_mc_for_early(u8 *mc, unsigned int size)
594 + {
595 +-#ifdef CONFIG_HOTPLUG_CPU
596 + /* Synchronization during CPU hotplug. */
597 + static DEFINE_MUTEX(x86_cpu_microcode_mutex);
598 +
599 +@@ -495,7 +494,6 @@ static void save_mc_for_early(u8 *mc, unsigned int size)
600 + show_saved_mc();
601 +
602 + mutex_unlock(&x86_cpu_microcode_mutex);
603 +-#endif
604 + }
605 +
606 + static bool load_builtin_intel_microcode(struct cpio_data *cp)
607 +diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
608 +index ff99e2b6fc54..12599e55e040 100644
609 +--- a/arch/x86/kernel/smpboot.c
610 ++++ b/arch/x86/kernel/smpboot.c
611 +@@ -1536,6 +1536,8 @@ static inline void mwait_play_dead(void)
612 + void *mwait_ptr;
613 + int i;
614 +
615 ++ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
616 ++ return;
617 + if (!this_cpu_has(X86_FEATURE_MWAIT))
618 + return;
619 + if (!this_cpu_has(X86_FEATURE_CLFLUSH))
620 +diff --git a/block/bfq-iosched.c b/block/bfq-iosched.c
621 +index aeca22d91101..3193b2663bed 100644
622 +--- a/block/bfq-iosched.c
623 ++++ b/block/bfq-iosched.c
624 +@@ -4911,8 +4911,16 @@ static void bfq_prepare_request(struct request *rq, struct bio *bio)
625 + bool new_queue = false;
626 + bool bfqq_already_existing = false, split = false;
627 +
628 +- if (!rq->elv.icq)
629 ++ /*
630 ++ * Even if we don't have an icq attached, we should still clear
631 ++ * the scheduler pointers, as they might point to previously
632 ++ * allocated bic/bfqq structs.
633 ++ */
634 ++ if (!rq->elv.icq) {
635 ++ rq->elv.priv[0] = rq->elv.priv[1] = NULL;
636 + return;
637 ++ }
638 ++
639 + bic = icq_to_bic(rq->elv.icq);
640 +
641 + spin_lock_irq(&bfqd->lock);
642 +diff --git a/block/blk-core.c b/block/blk-core.c
643 +index 3b489527c8f2..b459d277d170 100644
644 +--- a/block/blk-core.c
645 ++++ b/block/blk-core.c
646 +@@ -129,6 +129,10 @@ void blk_rq_init(struct request_queue *q, struct request *rq)
647 + rq->part = NULL;
648 + seqcount_init(&rq->gstate_seq);
649 + u64_stats_init(&rq->aborted_gstate_sync);
650 ++ /*
651 ++ * See comment of blk_mq_init_request
652 ++ */
653 ++ WRITE_ONCE(rq->gstate, MQ_RQ_GEN_INC);
654 + }
655 + EXPORT_SYMBOL(blk_rq_init);
656 +
657 +@@ -825,7 +829,6 @@ int blk_queue_enter(struct request_queue *q, blk_mq_req_flags_t flags)
658 +
659 + while (true) {
660 + bool success = false;
661 +- int ret;
662 +
663 + rcu_read_lock();
664 + if (percpu_ref_tryget_live(&q->q_usage_counter)) {
665 +@@ -857,14 +860,12 @@ int blk_queue_enter(struct request_queue *q, blk_mq_req_flags_t flags)
666 + */
667 + smp_rmb();
668 +
669 +- ret = wait_event_interruptible(q->mq_freeze_wq,
670 +- (atomic_read(&q->mq_freeze_depth) == 0 &&
671 +- (preempt || !blk_queue_preempt_only(q))) ||
672 +- blk_queue_dying(q));
673 ++ wait_event(q->mq_freeze_wq,
674 ++ (atomic_read(&q->mq_freeze_depth) == 0 &&
675 ++ (preempt || !blk_queue_preempt_only(q))) ||
676 ++ blk_queue_dying(q));
677 + if (blk_queue_dying(q))
678 + return -ENODEV;
679 +- if (ret)
680 +- return ret;
681 + }
682 + }
683 +
684 +diff --git a/block/blk-mq.c b/block/blk-mq.c
685 +index 56e0c3699f9e..96de7aa4f62a 100644
686 +--- a/block/blk-mq.c
687 ++++ b/block/blk-mq.c
688 +@@ -2076,6 +2076,13 @@ static int blk_mq_init_request(struct blk_mq_tag_set *set, struct request *rq,
689 +
690 + seqcount_init(&rq->gstate_seq);
691 + u64_stats_init(&rq->aborted_gstate_sync);
692 ++ /*
693 ++ * start gstate with gen 1 instead of 0, otherwise it will be equal
694 ++ * to aborted_gstate, and be identified timed out by
695 ++ * blk_mq_terminate_expired.
696 ++ */
697 ++ WRITE_ONCE(rq->gstate, MQ_RQ_GEN_INC);
698 ++
699 + return 0;
700 + }
701 +
702 +diff --git a/crypto/drbg.c b/crypto/drbg.c
703 +index 4faa2781c964..466a112a4446 100644
704 +--- a/crypto/drbg.c
705 ++++ b/crypto/drbg.c
706 +@@ -1134,8 +1134,10 @@ static inline void drbg_dealloc_state(struct drbg_state *drbg)
707 + if (!drbg)
708 + return;
709 + kzfree(drbg->Vbuf);
710 ++ drbg->Vbuf = NULL;
711 + drbg->V = NULL;
712 + kzfree(drbg->Cbuf);
713 ++ drbg->Cbuf = NULL;
714 + drbg->C = NULL;
715 + kzfree(drbg->scratchpadbuf);
716 + drbg->scratchpadbuf = NULL;
717 +diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
718 +index 594c228d2f02..4a3ac31c07d0 100644
719 +--- a/drivers/amba/bus.c
720 ++++ b/drivers/amba/bus.c
721 +@@ -69,11 +69,12 @@ static ssize_t driver_override_show(struct device *_dev,
722 + struct device_attribute *attr, char *buf)
723 + {
724 + struct amba_device *dev = to_amba_device(_dev);
725 ++ ssize_t len;
726 +
727 +- if (!dev->driver_override)
728 +- return 0;
729 +-
730 +- return sprintf(buf, "%s\n", dev->driver_override);
731 ++ device_lock(_dev);
732 ++ len = sprintf(buf, "%s\n", dev->driver_override);
733 ++ device_unlock(_dev);
734 ++ return len;
735 + }
736 +
737 + static ssize_t driver_override_store(struct device *_dev,
738 +@@ -81,9 +82,10 @@ static ssize_t driver_override_store(struct device *_dev,
739 + const char *buf, size_t count)
740 + {
741 + struct amba_device *dev = to_amba_device(_dev);
742 +- char *driver_override, *old = dev->driver_override, *cp;
743 ++ char *driver_override, *old, *cp;
744 +
745 +- if (count > PATH_MAX)
746 ++ /* We need to keep extra room for a newline */
747 ++ if (count >= (PAGE_SIZE - 1))
748 + return -EINVAL;
749 +
750 + driver_override = kstrndup(buf, count, GFP_KERNEL);
751 +@@ -94,12 +96,15 @@ static ssize_t driver_override_store(struct device *_dev,
752 + if (cp)
753 + *cp = '\0';
754 +
755 ++ device_lock(_dev);
756 ++ old = dev->driver_override;
757 + if (strlen(driver_override)) {
758 + dev->driver_override = driver_override;
759 + } else {
760 + kfree(driver_override);
761 + dev->driver_override = NULL;
762 + }
763 ++ device_unlock(_dev);
764 +
765 + kfree(old);
766 +
767 +diff --git a/drivers/android/binder.c b/drivers/android/binder.c
768 +index 764b63a5aade..e578eee31589 100644
769 +--- a/drivers/android/binder.c
770 ++++ b/drivers/android/binder.c
771 +@@ -2839,6 +2839,14 @@ static void binder_transaction(struct binder_proc *proc,
772 + else
773 + return_error = BR_DEAD_REPLY;
774 + mutex_unlock(&context->context_mgr_node_lock);
775 ++ if (target_node && target_proc == proc) {
776 ++ binder_user_error("%d:%d got transaction to context manager from process owning it\n",
777 ++ proc->pid, thread->pid);
778 ++ return_error = BR_FAILED_REPLY;
779 ++ return_error_param = -EINVAL;
780 ++ return_error_line = __LINE__;
781 ++ goto err_invalid_target_handle;
782 ++ }
783 + }
784 + if (!target_node) {
785 + /*
786 +diff --git a/drivers/char/random.c b/drivers/char/random.c
787 +index 38729baed6ee..8f4e11842c60 100644
788 +--- a/drivers/char/random.c
789 ++++ b/drivers/char/random.c
790 +@@ -261,6 +261,7 @@
791 + #include <linux/ptrace.h>
792 + #include <linux/workqueue.h>
793 + #include <linux/irq.h>
794 ++#include <linux/ratelimit.h>
795 + #include <linux/syscalls.h>
796 + #include <linux/completion.h>
797 + #include <linux/uuid.h>
798 +@@ -438,6 +439,16 @@ static void _crng_backtrack_protect(struct crng_state *crng,
799 + static void process_random_ready_list(void);
800 + static void _get_random_bytes(void *buf, int nbytes);
801 +
802 ++static struct ratelimit_state unseeded_warning =
803 ++ RATELIMIT_STATE_INIT("warn_unseeded_randomness", HZ, 3);
804 ++static struct ratelimit_state urandom_warning =
805 ++ RATELIMIT_STATE_INIT("warn_urandom_randomness", HZ, 3);
806 ++
807 ++static int ratelimit_disable __read_mostly;
808 ++
809 ++module_param_named(ratelimit_disable, ratelimit_disable, int, 0644);
810 ++MODULE_PARM_DESC(ratelimit_disable, "Disable random ratelimit suppression");
811 ++
812 + /**********************************************************************
813 + *
814 + * OS independent entropy store. Here are the functions which handle
815 +@@ -787,6 +798,39 @@ static void crng_initialize(struct crng_state *crng)
816 + crng->init_time = jiffies - CRNG_RESEED_INTERVAL - 1;
817 + }
818 +
819 ++#ifdef CONFIG_NUMA
820 ++static void do_numa_crng_init(struct work_struct *work)
821 ++{
822 ++ int i;
823 ++ struct crng_state *crng;
824 ++ struct crng_state **pool;
825 ++
826 ++ pool = kcalloc(nr_node_ids, sizeof(*pool), GFP_KERNEL|__GFP_NOFAIL);
827 ++ for_each_online_node(i) {
828 ++ crng = kmalloc_node(sizeof(struct crng_state),
829 ++ GFP_KERNEL | __GFP_NOFAIL, i);
830 ++ spin_lock_init(&crng->lock);
831 ++ crng_initialize(crng);
832 ++ pool[i] = crng;
833 ++ }
834 ++ mb();
835 ++ if (cmpxchg(&crng_node_pool, NULL, pool)) {
836 ++ for_each_node(i)
837 ++ kfree(pool[i]);
838 ++ kfree(pool);
839 ++ }
840 ++}
841 ++
842 ++static DECLARE_WORK(numa_crng_init_work, do_numa_crng_init);
843 ++
844 ++static void numa_crng_init(void)
845 ++{
846 ++ schedule_work(&numa_crng_init_work);
847 ++}
848 ++#else
849 ++static void numa_crng_init(void) {}
850 ++#endif
851 ++
852 + /*
853 + * crng_fast_load() can be called by code in the interrupt service
854 + * path. So we can't afford to dilly-dally.
855 +@@ -893,10 +937,23 @@ static void crng_reseed(struct crng_state *crng, struct entropy_store *r)
856 + spin_unlock_irqrestore(&crng->lock, flags);
857 + if (crng == &primary_crng && crng_init < 2) {
858 + invalidate_batched_entropy();
859 ++ numa_crng_init();
860 + crng_init = 2;
861 + process_random_ready_list();
862 + wake_up_interruptible(&crng_init_wait);
863 + pr_notice("random: crng init done\n");
864 ++ if (unseeded_warning.missed) {
865 ++ pr_notice("random: %d get_random_xx warning(s) missed "
866 ++ "due to ratelimiting\n",
867 ++ unseeded_warning.missed);
868 ++ unseeded_warning.missed = 0;
869 ++ }
870 ++ if (urandom_warning.missed) {
871 ++ pr_notice("random: %d urandom warning(s) missed "
872 ++ "due to ratelimiting\n",
873 ++ urandom_warning.missed);
874 ++ urandom_warning.missed = 0;
875 ++ }
876 + }
877 + }
878 +
879 +@@ -1540,8 +1597,9 @@ static void _warn_unseeded_randomness(const char *func_name, void *caller,
880 + #ifndef CONFIG_WARN_ALL_UNSEEDED_RANDOM
881 + print_once = true;
882 + #endif
883 +- pr_notice("random: %s called from %pS with crng_init=%d\n",
884 +- func_name, caller, crng_init);
885 ++ if (__ratelimit(&unseeded_warning))
886 ++ pr_notice("random: %s called from %pS with crng_init=%d\n",
887 ++ func_name, caller, crng_init);
888 + }
889 +
890 + /*
891 +@@ -1731,29 +1789,14 @@ static void init_std_data(struct entropy_store *r)
892 + */
893 + static int rand_initialize(void)
894 + {
895 +-#ifdef CONFIG_NUMA
896 +- int i;
897 +- struct crng_state *crng;
898 +- struct crng_state **pool;
899 +-#endif
900 +-
901 + init_std_data(&input_pool);
902 + init_std_data(&blocking_pool);
903 + crng_initialize(&primary_crng);
904 + crng_global_init_time = jiffies;
905 +-
906 +-#ifdef CONFIG_NUMA
907 +- pool = kcalloc(nr_node_ids, sizeof(*pool), GFP_KERNEL|__GFP_NOFAIL);
908 +- for_each_online_node(i) {
909 +- crng = kmalloc_node(sizeof(struct crng_state),
910 +- GFP_KERNEL | __GFP_NOFAIL, i);
911 +- spin_lock_init(&crng->lock);
912 +- crng_initialize(crng);
913 +- pool[i] = crng;
914 ++ if (ratelimit_disable) {
915 ++ urandom_warning.interval = 0;
916 ++ unseeded_warning.interval = 0;
917 + }
918 +- mb();
919 +- crng_node_pool = pool;
920 +-#endif
921 + return 0;
922 + }
923 + early_initcall(rand_initialize);
924 +@@ -1821,9 +1864,10 @@ urandom_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos)
925 +
926 + if (!crng_ready() && maxwarn > 0) {
927 + maxwarn--;
928 +- printk(KERN_NOTICE "random: %s: uninitialized urandom read "
929 +- "(%zd bytes read)\n",
930 +- current->comm, nbytes);
931 ++ if (__ratelimit(&urandom_warning))
932 ++ printk(KERN_NOTICE "random: %s: uninitialized "
933 ++ "urandom read (%zd bytes read)\n",
934 ++ current->comm, nbytes);
935 + spin_lock_irqsave(&primary_crng.lock, flags);
936 + crng_init_cnt = 0;
937 + spin_unlock_irqrestore(&primary_crng.lock, flags);
938 +diff --git a/drivers/char/virtio_console.c b/drivers/char/virtio_console.c
939 +index 468f06134012..21085515814f 100644
940 +--- a/drivers/char/virtio_console.c
941 ++++ b/drivers/char/virtio_console.c
942 +@@ -422,7 +422,7 @@ static void reclaim_dma_bufs(void)
943 + }
944 + }
945 +
946 +-static struct port_buffer *alloc_buf(struct virtqueue *vq, size_t buf_size,
947 ++static struct port_buffer *alloc_buf(struct virtio_device *vdev, size_t buf_size,
948 + int pages)
949 + {
950 + struct port_buffer *buf;
951 +@@ -445,16 +445,16 @@ static struct port_buffer *alloc_buf(struct virtqueue *vq, size_t buf_size,
952 + return buf;
953 + }
954 +
955 +- if (is_rproc_serial(vq->vdev)) {
956 ++ if (is_rproc_serial(vdev)) {
957 + /*
958 + * Allocate DMA memory from ancestor. When a virtio
959 + * device is created by remoteproc, the DMA memory is
960 + * associated with the grandparent device:
961 + * vdev => rproc => platform-dev.
962 + */
963 +- if (!vq->vdev->dev.parent || !vq->vdev->dev.parent->parent)
964 ++ if (!vdev->dev.parent || !vdev->dev.parent->parent)
965 + goto free_buf;
966 +- buf->dev = vq->vdev->dev.parent->parent;
967 ++ buf->dev = vdev->dev.parent->parent;
968 +
969 + /* Increase device refcnt to avoid freeing it */
970 + get_device(buf->dev);
971 +@@ -838,7 +838,7 @@ static ssize_t port_fops_write(struct file *filp, const char __user *ubuf,
972 +
973 + count = min((size_t)(32 * 1024), count);
974 +
975 +- buf = alloc_buf(port->out_vq, count, 0);
976 ++ buf = alloc_buf(port->portdev->vdev, count, 0);
977 + if (!buf)
978 + return -ENOMEM;
979 +
980 +@@ -957,7 +957,7 @@ static ssize_t port_fops_splice_write(struct pipe_inode_info *pipe,
981 + if (ret < 0)
982 + goto error_out;
983 +
984 +- buf = alloc_buf(port->out_vq, 0, pipe->nrbufs);
985 ++ buf = alloc_buf(port->portdev->vdev, 0, pipe->nrbufs);
986 + if (!buf) {
987 + ret = -ENOMEM;
988 + goto error_out;
989 +@@ -1374,7 +1374,7 @@ static unsigned int fill_queue(struct virtqueue *vq, spinlock_t *lock)
990 +
991 + nr_added_bufs = 0;
992 + do {
993 +- buf = alloc_buf(vq, PAGE_SIZE, 0);
994 ++ buf = alloc_buf(vq->vdev, PAGE_SIZE, 0);
995 + if (!buf)
996 + break;
997 +
998 +@@ -1402,7 +1402,6 @@ static int add_port(struct ports_device *portdev, u32 id)
999 + {
1000 + char debugfs_name[16];
1001 + struct port *port;
1002 +- struct port_buffer *buf;
1003 + dev_t devt;
1004 + unsigned int nr_added_bufs;
1005 + int err;
1006 +@@ -1513,8 +1512,6 @@ static int add_port(struct ports_device *portdev, u32 id)
1007 + return 0;
1008 +
1009 + free_inbufs:
1010 +- while ((buf = virtqueue_detach_unused_buf(port->in_vq)))
1011 +- free_buf(buf, true);
1012 + free_device:
1013 + device_destroy(pdrvdata.class, port->dev->devt);
1014 + free_cdev:
1015 +@@ -1539,34 +1536,14 @@ static void remove_port(struct kref *kref)
1016 +
1017 + static void remove_port_data(struct port *port)
1018 + {
1019 +- struct port_buffer *buf;
1020 +-
1021 + spin_lock_irq(&port->inbuf_lock);
1022 + /* Remove unused data this port might have received. */
1023 + discard_port_data(port);
1024 + spin_unlock_irq(&port->inbuf_lock);
1025 +
1026 +- /* Remove buffers we queued up for the Host to send us data in. */
1027 +- do {
1028 +- spin_lock_irq(&port->inbuf_lock);
1029 +- buf = virtqueue_detach_unused_buf(port->in_vq);
1030 +- spin_unlock_irq(&port->inbuf_lock);
1031 +- if (buf)
1032 +- free_buf(buf, true);
1033 +- } while (buf);
1034 +-
1035 + spin_lock_irq(&port->outvq_lock);
1036 + reclaim_consumed_buffers(port);
1037 + spin_unlock_irq(&port->outvq_lock);
1038 +-
1039 +- /* Free pending buffers from the out-queue. */
1040 +- do {
1041 +- spin_lock_irq(&port->outvq_lock);
1042 +- buf = virtqueue_detach_unused_buf(port->out_vq);
1043 +- spin_unlock_irq(&port->outvq_lock);
1044 +- if (buf)
1045 +- free_buf(buf, true);
1046 +- } while (buf);
1047 + }
1048 +
1049 + /*
1050 +@@ -1791,13 +1768,24 @@ static void control_work_handler(struct work_struct *work)
1051 + spin_unlock(&portdev->c_ivq_lock);
1052 + }
1053 +
1054 ++static void flush_bufs(struct virtqueue *vq, bool can_sleep)
1055 ++{
1056 ++ struct port_buffer *buf;
1057 ++ unsigned int len;
1058 ++
1059 ++ while ((buf = virtqueue_get_buf(vq, &len)))
1060 ++ free_buf(buf, can_sleep);
1061 ++}
1062 ++
1063 + static void out_intr(struct virtqueue *vq)
1064 + {
1065 + struct port *port;
1066 +
1067 + port = find_port_by_vq(vq->vdev->priv, vq);
1068 +- if (!port)
1069 ++ if (!port) {
1070 ++ flush_bufs(vq, false);
1071 + return;
1072 ++ }
1073 +
1074 + wake_up_interruptible(&port->waitqueue);
1075 + }
1076 +@@ -1808,8 +1796,10 @@ static void in_intr(struct virtqueue *vq)
1077 + unsigned long flags;
1078 +
1079 + port = find_port_by_vq(vq->vdev->priv, vq);
1080 +- if (!port)
1081 ++ if (!port) {
1082 ++ flush_bufs(vq, false);
1083 + return;
1084 ++ }
1085 +
1086 + spin_lock_irqsave(&port->inbuf_lock, flags);
1087 + port->inbuf = get_inbuf(port);
1088 +@@ -1984,24 +1974,54 @@ static const struct file_operations portdev_fops = {
1089 +
1090 + static void remove_vqs(struct ports_device *portdev)
1091 + {
1092 ++ struct virtqueue *vq;
1093 ++
1094 ++ virtio_device_for_each_vq(portdev->vdev, vq) {
1095 ++ struct port_buffer *buf;
1096 ++
1097 ++ flush_bufs(vq, true);
1098 ++ while ((buf = virtqueue_detach_unused_buf(vq)))
1099 ++ free_buf(buf, true);
1100 ++ }
1101 + portdev->vdev->config->del_vqs(portdev->vdev);
1102 + kfree(portdev->in_vqs);
1103 + kfree(portdev->out_vqs);
1104 + }
1105 +
1106 +-static void remove_controlq_data(struct ports_device *portdev)
1107 ++static void virtcons_remove(struct virtio_device *vdev)
1108 + {
1109 +- struct port_buffer *buf;
1110 +- unsigned int len;
1111 ++ struct ports_device *portdev;
1112 ++ struct port *port, *port2;
1113 +
1114 +- if (!use_multiport(portdev))
1115 +- return;
1116 ++ portdev = vdev->priv;
1117 +
1118 +- while ((buf = virtqueue_get_buf(portdev->c_ivq, &len)))
1119 +- free_buf(buf, true);
1120 ++ spin_lock_irq(&pdrvdata_lock);
1121 ++ list_del(&portdev->list);
1122 ++ spin_unlock_irq(&pdrvdata_lock);
1123 +
1124 +- while ((buf = virtqueue_detach_unused_buf(portdev->c_ivq)))
1125 +- free_buf(buf, true);
1126 ++ /* Disable interrupts for vqs */
1127 ++ vdev->config->reset(vdev);
1128 ++ /* Finish up work that's lined up */
1129 ++ if (use_multiport(portdev))
1130 ++ cancel_work_sync(&portdev->control_work);
1131 ++ else
1132 ++ cancel_work_sync(&portdev->config_work);
1133 ++
1134 ++ list_for_each_entry_safe(port, port2, &portdev->ports, list)
1135 ++ unplug_port(port);
1136 ++
1137 ++ unregister_chrdev(portdev->chr_major, "virtio-portsdev");
1138 ++
1139 ++ /*
1140 ++ * When yanking out a device, we immediately lose the
1141 ++ * (device-side) queues. So there's no point in keeping the
1142 ++ * guest side around till we drop our final reference. This
1143 ++ * also means that any ports which are in an open state will
1144 ++ * have to just stop using the port, as the vqs are going
1145 ++ * away.
1146 ++ */
1147 ++ remove_vqs(portdev);
1148 ++ kfree(portdev);
1149 + }
1150 +
1151 + /*
1152 +@@ -2070,6 +2090,7 @@ static int virtcons_probe(struct virtio_device *vdev)
1153 +
1154 + spin_lock_init(&portdev->ports_lock);
1155 + INIT_LIST_HEAD(&portdev->ports);
1156 ++ INIT_LIST_HEAD(&portdev->list);
1157 +
1158 + virtio_device_ready(portdev->vdev);
1159 +
1160 +@@ -2087,8 +2108,15 @@ static int virtcons_probe(struct virtio_device *vdev)
1161 + if (!nr_added_bufs) {
1162 + dev_err(&vdev->dev,
1163 + "Error allocating buffers for control queue\n");
1164 +- err = -ENOMEM;
1165 +- goto free_vqs;
1166 ++ /*
1167 ++ * The host might want to notify mgmt sw about device
1168 ++ * add failure.
1169 ++ */
1170 ++ __send_control_msg(portdev, VIRTIO_CONSOLE_BAD_ID,
1171 ++ VIRTIO_CONSOLE_DEVICE_READY, 0);
1172 ++ /* Device was functional: we need full cleanup. */
1173 ++ virtcons_remove(vdev);
1174 ++ return -ENOMEM;
1175 + }
1176 + } else {
1177 + /*
1178 +@@ -2119,11 +2147,6 @@ static int virtcons_probe(struct virtio_device *vdev)
1179 +
1180 + return 0;
1181 +
1182 +-free_vqs:
1183 +- /* The host might want to notify mgmt sw about device add failure */
1184 +- __send_control_msg(portdev, VIRTIO_CONSOLE_BAD_ID,
1185 +- VIRTIO_CONSOLE_DEVICE_READY, 0);
1186 +- remove_vqs(portdev);
1187 + free_chrdev:
1188 + unregister_chrdev(portdev->chr_major, "virtio-portsdev");
1189 + free:
1190 +@@ -2132,43 +2155,6 @@ static int virtcons_probe(struct virtio_device *vdev)
1191 + return err;
1192 + }
1193 +
1194 +-static void virtcons_remove(struct virtio_device *vdev)
1195 +-{
1196 +- struct ports_device *portdev;
1197 +- struct port *port, *port2;
1198 +-
1199 +- portdev = vdev->priv;
1200 +-
1201 +- spin_lock_irq(&pdrvdata_lock);
1202 +- list_del(&portdev->list);
1203 +- spin_unlock_irq(&pdrvdata_lock);
1204 +-
1205 +- /* Disable interrupts for vqs */
1206 +- vdev->config->reset(vdev);
1207 +- /* Finish up work that's lined up */
1208 +- if (use_multiport(portdev))
1209 +- cancel_work_sync(&portdev->control_work);
1210 +- else
1211 +- cancel_work_sync(&portdev->config_work);
1212 +-
1213 +- list_for_each_entry_safe(port, port2, &portdev->ports, list)
1214 +- unplug_port(port);
1215 +-
1216 +- unregister_chrdev(portdev->chr_major, "virtio-portsdev");
1217 +-
1218 +- /*
1219 +- * When yanking out a device, we immediately lose the
1220 +- * (device-side) queues. So there's no point in keeping the
1221 +- * guest side around till we drop our final reference. This
1222 +- * also means that any ports which are in an open state will
1223 +- * have to just stop using the port, as the vqs are going
1224 +- * away.
1225 +- */
1226 +- remove_controlq_data(portdev);
1227 +- remove_vqs(portdev);
1228 +- kfree(portdev);
1229 +-}
1230 +-
1231 + static struct virtio_device_id id_table[] = {
1232 + { VIRTIO_ID_CONSOLE, VIRTIO_DEV_ANY_ID },
1233 + { 0 },
1234 +@@ -2209,7 +2195,6 @@ static int virtcons_freeze(struct virtio_device *vdev)
1235 + */
1236 + if (use_multiport(portdev))
1237 + virtqueue_disable_cb(portdev->c_ivq);
1238 +- remove_controlq_data(portdev);
1239 +
1240 + list_for_each_entry(port, &portdev->ports, list) {
1241 + virtqueue_disable_cb(port->in_vq);
1242 +diff --git a/drivers/cpufreq/powernv-cpufreq.c b/drivers/cpufreq/powernv-cpufreq.c
1243 +index 29cdec198657..422e1fc38b43 100644
1244 +--- a/drivers/cpufreq/powernv-cpufreq.c
1245 ++++ b/drivers/cpufreq/powernv-cpufreq.c
1246 +@@ -679,6 +679,16 @@ void gpstate_timer_handler(struct timer_list *t)
1247 +
1248 + if (!spin_trylock(&gpstates->gpstate_lock))
1249 + return;
1250 ++ /*
1251 ++ * If the timer has migrated to the different cpu then bring
1252 ++ * it back to one of the policy->cpus
1253 ++ */
1254 ++ if (!cpumask_test_cpu(raw_smp_processor_id(), policy->cpus)) {
1255 ++ gpstates->timer.expires = jiffies + msecs_to_jiffies(1);
1256 ++ add_timer_on(&gpstates->timer, cpumask_first(policy->cpus));
1257 ++ spin_unlock(&gpstates->gpstate_lock);
1258 ++ return;
1259 ++ }
1260 +
1261 + /*
1262 + * If PMCR was last updated was using fast_swtich then
1263 +@@ -718,10 +728,8 @@ void gpstate_timer_handler(struct timer_list *t)
1264 + if (gpstate_idx != gpstates->last_lpstate_idx)
1265 + queue_gpstate_timer(gpstates);
1266 +
1267 ++ set_pstate(&freq_data);
1268 + spin_unlock(&gpstates->gpstate_lock);
1269 +-
1270 +- /* Timer may get migrated to a different cpu on cpu hot unplug */
1271 +- smp_call_function_any(policy->cpus, set_pstate, &freq_data, 1);
1272 + }
1273 +
1274 + /*
1275 +diff --git a/drivers/crypto/ccp/sp-dev.c b/drivers/crypto/ccp/sp-dev.c
1276 +index eb0da6572720..e0459002eb71 100644
1277 +--- a/drivers/crypto/ccp/sp-dev.c
1278 ++++ b/drivers/crypto/ccp/sp-dev.c
1279 +@@ -252,12 +252,12 @@ struct sp_device *sp_get_psp_master_device(void)
1280 + goto unlock;
1281 +
1282 + list_for_each_entry(i, &sp_units, entry) {
1283 +- if (i->psp_data)
1284 ++ if (i->psp_data && i->get_psp_master_device) {
1285 ++ ret = i->get_psp_master_device();
1286 + break;
1287 ++ }
1288 + }
1289 +
1290 +- if (i->get_psp_master_device)
1291 +- ret = i->get_psp_master_device();
1292 + unlock:
1293 + write_unlock_irqrestore(&sp_unit_lock, flags);
1294 + return ret;
1295 +diff --git a/drivers/fpga/altera-ps-spi.c b/drivers/fpga/altera-ps-spi.c
1296 +index 14f14efdf0d5..06d212a3d49d 100644
1297 +--- a/drivers/fpga/altera-ps-spi.c
1298 ++++ b/drivers/fpga/altera-ps-spi.c
1299 +@@ -249,7 +249,7 @@ static int altera_ps_probe(struct spi_device *spi)
1300 +
1301 + conf->data = of_id->data;
1302 + conf->spi = spi;
1303 +- conf->config = devm_gpiod_get(&spi->dev, "nconfig", GPIOD_OUT_HIGH);
1304 ++ conf->config = devm_gpiod_get(&spi->dev, "nconfig", GPIOD_OUT_LOW);
1305 + if (IS_ERR(conf->config)) {
1306 + dev_err(&spi->dev, "Failed to get config gpio: %ld\n",
1307 + PTR_ERR(conf->config));
1308 +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
1309 +index 4e694ae9f308..45cc4d572897 100644
1310 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
1311 ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
1312 +@@ -1459,10 +1459,11 @@ static const u32 sgpr_init_compute_shader[] =
1313 + static const u32 vgpr_init_regs[] =
1314 + {
1315 + mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1316 +- mmCOMPUTE_RESOURCE_LIMITS, 0,
1317 ++ mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1318 + mmCOMPUTE_NUM_THREAD_X, 256*4,
1319 + mmCOMPUTE_NUM_THREAD_Y, 1,
1320 + mmCOMPUTE_NUM_THREAD_Z, 1,
1321 ++ mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
1322 + mmCOMPUTE_PGM_RSRC2, 20,
1323 + mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1324 + mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1325 +@@ -1479,10 +1480,11 @@ static const u32 vgpr_init_regs[] =
1326 + static const u32 sgpr1_init_regs[] =
1327 + {
1328 + mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1329 +- mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1330 ++ mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1331 + mmCOMPUTE_NUM_THREAD_X, 256*5,
1332 + mmCOMPUTE_NUM_THREAD_Y, 1,
1333 + mmCOMPUTE_NUM_THREAD_Z, 1,
1334 ++ mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1335 + mmCOMPUTE_PGM_RSRC2, 20,
1336 + mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1337 + mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1338 +@@ -1503,6 +1505,7 @@ static const u32 sgpr2_init_regs[] =
1339 + mmCOMPUTE_NUM_THREAD_X, 256*5,
1340 + mmCOMPUTE_NUM_THREAD_Y, 1,
1341 + mmCOMPUTE_NUM_THREAD_Z, 1,
1342 ++ mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1343 + mmCOMPUTE_PGM_RSRC2, 20,
1344 + mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1345 + mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1346 +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1347 +index 8a6e6fbc78cd..2e94881d4f7f 100644
1348 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1349 ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1350 +@@ -4506,6 +4506,7 @@ static int dm_update_crtcs_state(struct dc *dc,
1351 + struct amdgpu_dm_connector *aconnector = NULL;
1352 + struct drm_connector_state *new_con_state = NULL;
1353 + struct dm_connector_state *dm_conn_state = NULL;
1354 ++ struct drm_plane_state *new_plane_state = NULL;
1355 +
1356 + new_stream = NULL;
1357 +
1358 +@@ -4513,6 +4514,13 @@ static int dm_update_crtcs_state(struct dc *dc,
1359 + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1360 + acrtc = to_amdgpu_crtc(crtc);
1361 +
1362 ++ new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
1363 ++
1364 ++ if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
1365 ++ ret = -EINVAL;
1366 ++ goto fail;
1367 ++ }
1368 ++
1369 + aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
1370 +
1371 + /* TODO This hack should go away */
1372 +@@ -4685,7 +4693,7 @@ static int dm_update_planes_state(struct dc *dc,
1373 + if (!dm_old_crtc_state->stream)
1374 + continue;
1375 +
1376 +- DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n",
1377 ++ DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
1378 + plane->base.id, old_plane_crtc->base.id);
1379 +
1380 + if (!dc_remove_plane_from_context(
1381 +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
1382 +index 422055080df4..54a25fb048fb 100644
1383 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
1384 ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
1385 +@@ -400,14 +400,15 @@ void amdgpu_dm_irq_fini(struct amdgpu_device *adev)
1386 + {
1387 + int src;
1388 + struct irq_list_head *lh;
1389 ++ unsigned long irq_table_flags;
1390 + DRM_DEBUG_KMS("DM_IRQ: releasing resources.\n");
1391 +-
1392 + for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
1393 +-
1394 ++ DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
1395 + /* The handler was removed from the table,
1396 + * it means it is safe to flush all the 'work'
1397 + * (because no code can schedule a new one). */
1398 + lh = &adev->dm.irq_handler_list_low_tab[src];
1399 ++ DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
1400 + flush_work(&lh->work);
1401 + }
1402 +
1403 +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1404 +index 93421dad21bd..160933c16461 100644
1405 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1406 ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1407 +@@ -157,6 +157,11 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector)
1408 + struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
1409 + struct amdgpu_encoder *amdgpu_encoder = amdgpu_dm_connector->mst_encoder;
1410 +
1411 ++ if (amdgpu_dm_connector->edid) {
1412 ++ kfree(amdgpu_dm_connector->edid);
1413 ++ amdgpu_dm_connector->edid = NULL;
1414 ++ }
1415 ++
1416 + drm_encoder_cleanup(&amdgpu_encoder->base);
1417 + kfree(amdgpu_encoder);
1418 + drm_connector_cleanup(connector);
1419 +@@ -183,28 +188,22 @@ static int dm_connector_update_modes(struct drm_connector *connector,
1420 + void dm_dp_mst_dc_sink_create(struct drm_connector *connector)
1421 + {
1422 + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1423 +- struct edid *edid;
1424 + struct dc_sink *dc_sink;
1425 + struct dc_sink_init_data init_params = {
1426 + .link = aconnector->dc_link,
1427 + .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
1428 +
1429 ++ /* FIXME none of this is safe. we shouldn't touch aconnector here in
1430 ++ * atomic_check
1431 ++ */
1432 ++
1433 + /*
1434 + * TODO: Need to further figure out why ddc.algo is NULL while MST port exists
1435 + */
1436 + if (!aconnector->port || !aconnector->port->aux.ddc.algo)
1437 + return;
1438 +
1439 +- edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
1440 +-
1441 +- if (!edid) {
1442 +- drm_mode_connector_update_edid_property(
1443 +- &aconnector->base,
1444 +- NULL);
1445 +- return;
1446 +- }
1447 +-
1448 +- aconnector->edid = edid;
1449 ++ ASSERT(aconnector->edid);
1450 +
1451 + dc_sink = dc_link_add_remote_sink(
1452 + aconnector->dc_link,
1453 +@@ -217,9 +216,6 @@ void dm_dp_mst_dc_sink_create(struct drm_connector *connector)
1454 +
1455 + amdgpu_dm_add_sink_to_freesync_module(
1456 + connector, aconnector->edid);
1457 +-
1458 +- drm_mode_connector_update_edid_property(
1459 +- &aconnector->base, aconnector->edid);
1460 + }
1461 +
1462 + static int dm_dp_mst_get_modes(struct drm_connector *connector)
1463 +@@ -426,14 +422,6 @@ static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
1464 + dc_sink_release(aconnector->dc_sink);
1465 + aconnector->dc_sink = NULL;
1466 + }
1467 +- if (aconnector->edid) {
1468 +- kfree(aconnector->edid);
1469 +- aconnector->edid = NULL;
1470 +- }
1471 +-
1472 +- drm_mode_connector_update_edid_property(
1473 +- &aconnector->base,
1474 +- NULL);
1475 +
1476 + aconnector->mst_connected = false;
1477 + }
1478 +diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
1479 +index 4f751a9d71a3..2368ad0b3f4d 100644
1480 +--- a/drivers/gpu/drm/drm_edid.c
1481 ++++ b/drivers/gpu/drm/drm_edid.c
1482 +@@ -4450,6 +4450,7 @@ drm_reset_display_info(struct drm_connector *connector)
1483 + info->max_tmds_clock = 0;
1484 + info->dvi_dual = false;
1485 + info->has_hdmi_infoframe = false;
1486 ++ memset(&info->hdmi, 0, sizeof(info->hdmi));
1487 +
1488 + info->non_desktop = 0;
1489 + }
1490 +@@ -4461,17 +4462,11 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi
1491 +
1492 + u32 quirks = edid_get_quirks(edid);
1493 +
1494 ++ drm_reset_display_info(connector);
1495 ++
1496 + info->width_mm = edid->width_cm * 10;
1497 + info->height_mm = edid->height_cm * 10;
1498 +
1499 +- /* driver figures it out in this case */
1500 +- info->bpc = 0;
1501 +- info->color_formats = 0;
1502 +- info->cea_rev = 0;
1503 +- info->max_tmds_clock = 0;
1504 +- info->dvi_dual = false;
1505 +- info->has_hdmi_infoframe = false;
1506 +-
1507 + info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
1508 +
1509 + DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
1510 +diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
1511 +index 1704c8897afd..fd58647fbff3 100644
1512 +--- a/drivers/gpu/drm/i915/intel_cdclk.c
1513 ++++ b/drivers/gpu/drm/i915/intel_cdclk.c
1514 +@@ -1946,10 +1946,22 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
1515 + }
1516 + }
1517 +
1518 +- /* According to BSpec, "The CD clock frequency must be at least twice
1519 ++ /*
1520 ++ * According to BSpec, "The CD clock frequency must be at least twice
1521 + * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
1522 ++ *
1523 ++ * FIXME: Check the actual, not default, BCLK being used.
1524 ++ *
1525 ++ * FIXME: This does not depend on ->has_audio because the higher CDCLK
1526 ++ * is required for audio probe, also when there are no audio capable
1527 ++ * displays connected at probe time. This leads to unnecessarily high
1528 ++ * CDCLK when audio is not required.
1529 ++ *
1530 ++ * FIXME: This limit is only applied when there are displays connected
1531 ++ * at probe time. If we probe without displays, we'll still end up using
1532 ++ * the platform minimum CDCLK, failing audio probe.
1533 + */
1534 +- if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
1535 ++ if (INTEL_GEN(dev_priv) >= 9)
1536 + min_cdclk = max(2 * 96000, min_cdclk);
1537 +
1538 + /*
1539 +diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
1540 +index da48af11eb6b..0cf33034a8ba 100644
1541 +--- a/drivers/gpu/drm/i915/intel_fbdev.c
1542 ++++ b/drivers/gpu/drm/i915/intel_fbdev.c
1543 +@@ -801,7 +801,7 @@ void intel_fbdev_output_poll_changed(struct drm_device *dev)
1544 + return;
1545 +
1546 + intel_fbdev_sync(ifbdev);
1547 +- if (ifbdev->vma)
1548 ++ if (ifbdev->vma || ifbdev->helper.deferred_setup)
1549 + drm_fb_helper_hotplug_event(&ifbdev->helper);
1550 + }
1551 +
1552 +diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
1553 +index d758da6156a8..9faee4875ddf 100644
1554 +--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
1555 ++++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
1556 +@@ -624,19 +624,18 @@ void skl_enable_dc6(struct drm_i915_private *dev_priv)
1557 +
1558 + DRM_DEBUG_KMS("Enabling DC6\n");
1559 +
1560 +- gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
1561 ++ /* Wa Display #1183: skl,kbl,cfl */
1562 ++ if (IS_GEN9_BC(dev_priv))
1563 ++ I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
1564 ++ SKL_SELECT_ALTERNATE_DC_EXIT);
1565 +
1566 ++ gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
1567 + }
1568 +
1569 + void skl_disable_dc6(struct drm_i915_private *dev_priv)
1570 + {
1571 + DRM_DEBUG_KMS("Disabling DC6\n");
1572 +
1573 +- /* Wa Display #1183: skl,kbl,cfl */
1574 +- if (IS_GEN9_BC(dev_priv))
1575 +- I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
1576 +- SKL_SELECT_ALTERNATE_DC_EXIT);
1577 +-
1578 + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
1579 + }
1580 +
1581 +diff --git a/drivers/gpu/drm/virtio/virtgpu_vq.c b/drivers/gpu/drm/virtio/virtgpu_vq.c
1582 +index 9eb96fb2c147..26a2da1f712d 100644
1583 +--- a/drivers/gpu/drm/virtio/virtgpu_vq.c
1584 ++++ b/drivers/gpu/drm/virtio/virtgpu_vq.c
1585 +@@ -291,7 +291,7 @@ static int virtio_gpu_queue_ctrl_buffer_locked(struct virtio_gpu_device *vgdev,
1586 + ret = virtqueue_add_sgs(vq, sgs, outcnt, incnt, vbuf, GFP_ATOMIC);
1587 + if (ret == -ENOSPC) {
1588 + spin_unlock(&vgdev->ctrlq.qlock);
1589 +- wait_event(vgdev->ctrlq.ack_queue, vq->num_free);
1590 ++ wait_event(vgdev->ctrlq.ack_queue, vq->num_free >= outcnt + incnt);
1591 + spin_lock(&vgdev->ctrlq.qlock);
1592 + goto retry;
1593 + } else {
1594 +@@ -366,7 +366,7 @@ static int virtio_gpu_queue_cursor(struct virtio_gpu_device *vgdev,
1595 + ret = virtqueue_add_sgs(vq, sgs, outcnt, 0, vbuf, GFP_ATOMIC);
1596 + if (ret == -ENOSPC) {
1597 + spin_unlock(&vgdev->cursorq.qlock);
1598 +- wait_event(vgdev->cursorq.ack_queue, vq->num_free);
1599 ++ wait_event(vgdev->cursorq.ack_queue, vq->num_free >= outcnt);
1600 + spin_lock(&vgdev->cursorq.qlock);
1601 + goto retry;
1602 + } else {
1603 +diff --git a/drivers/mtd/chips/cfi_cmdset_0001.c b/drivers/mtd/chips/cfi_cmdset_0001.c
1604 +index 5e1b68cbcd0a..e1b603ca0170 100644
1605 +--- a/drivers/mtd/chips/cfi_cmdset_0001.c
1606 ++++ b/drivers/mtd/chips/cfi_cmdset_0001.c
1607 +@@ -45,6 +45,7 @@
1608 + #define I82802AB 0x00ad
1609 + #define I82802AC 0x00ac
1610 + #define PF38F4476 0x881c
1611 ++#define M28F00AP30 0x8963
1612 + /* STMicroelectronics chips */
1613 + #define M50LPW080 0x002F
1614 + #define M50FLW080A 0x0080
1615 +@@ -375,6 +376,17 @@ static void cfi_fixup_major_minor(struct cfi_private *cfi,
1616 + extp->MinorVersion = '1';
1617 + }
1618 +
1619 ++static int cfi_is_micron_28F00AP30(struct cfi_private *cfi, struct flchip *chip)
1620 ++{
1621 ++ /*
1622 ++ * Micron(was Numonyx) 1Gbit bottom boot are buggy w.r.t
1623 ++ * Erase Supend for their small Erase Blocks(0x8000)
1624 ++ */
1625 ++ if (cfi->mfr == CFI_MFR_INTEL && cfi->id == M28F00AP30)
1626 ++ return 1;
1627 ++ return 0;
1628 ++}
1629 ++
1630 + static inline struct cfi_pri_intelext *
1631 + read_pri_intelext(struct map_info *map, __u16 adr)
1632 + {
1633 +@@ -831,21 +843,30 @@ static int chip_ready (struct map_info *map, struct flchip *chip, unsigned long
1634 + (mode == FL_WRITING && (cfip->SuspendCmdSupport & 1))))
1635 + goto sleep;
1636 +
1637 ++ /* Do not allow suspend iff read/write to EB address */
1638 ++ if ((adr & chip->in_progress_block_mask) ==
1639 ++ chip->in_progress_block_addr)
1640 ++ goto sleep;
1641 ++
1642 ++ /* do not suspend small EBs, buggy Micron Chips */
1643 ++ if (cfi_is_micron_28F00AP30(cfi, chip) &&
1644 ++ (chip->in_progress_block_mask == ~(0x8000-1)))
1645 ++ goto sleep;
1646 +
1647 + /* Erase suspend */
1648 +- map_write(map, CMD(0xB0), adr);
1649 ++ map_write(map, CMD(0xB0), chip->in_progress_block_addr);
1650 +
1651 + /* If the flash has finished erasing, then 'erase suspend'
1652 + * appears to make some (28F320) flash devices switch to
1653 + * 'read' mode. Make sure that we switch to 'read status'
1654 + * mode so we get the right data. --rmk
1655 + */
1656 +- map_write(map, CMD(0x70), adr);
1657 ++ map_write(map, CMD(0x70), chip->in_progress_block_addr);
1658 + chip->oldstate = FL_ERASING;
1659 + chip->state = FL_ERASE_SUSPENDING;
1660 + chip->erase_suspended = 1;
1661 + for (;;) {
1662 +- status = map_read(map, adr);
1663 ++ status = map_read(map, chip->in_progress_block_addr);
1664 + if (map_word_andequal(map, status, status_OK, status_OK))
1665 + break;
1666 +
1667 +@@ -1041,8 +1062,8 @@ static void put_chip(struct map_info *map, struct flchip *chip, unsigned long ad
1668 + sending the 0x70 (Read Status) command to an erasing
1669 + chip and expecting it to be ignored, that's what we
1670 + do. */
1671 +- map_write(map, CMD(0xd0), adr);
1672 +- map_write(map, CMD(0x70), adr);
1673 ++ map_write(map, CMD(0xd0), chip->in_progress_block_addr);
1674 ++ map_write(map, CMD(0x70), chip->in_progress_block_addr);
1675 + chip->oldstate = FL_READY;
1676 + chip->state = FL_ERASING;
1677 + break;
1678 +@@ -1933,6 +1954,8 @@ static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip,
1679 + map_write(map, CMD(0xD0), adr);
1680 + chip->state = FL_ERASING;
1681 + chip->erase_suspended = 0;
1682 ++ chip->in_progress_block_addr = adr;
1683 ++ chip->in_progress_block_mask = ~(len - 1);
1684 +
1685 + ret = INVAL_CACHE_AND_WAIT(map, chip, adr,
1686 + adr, len,
1687 +diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c
1688 +index 56aa6b75213d..d524a64ed754 100644
1689 +--- a/drivers/mtd/chips/cfi_cmdset_0002.c
1690 ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
1691 +@@ -816,9 +816,10 @@ static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr
1692 + (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
1693 + goto sleep;
1694 +
1695 +- /* We could check to see if we're trying to access the sector
1696 +- * that is currently being erased. However, no user will try
1697 +- * anything like that so we just wait for the timeout. */
1698 ++ /* Do not allow suspend iff read/write to EB address */
1699 ++ if ((adr & chip->in_progress_block_mask) ==
1700 ++ chip->in_progress_block_addr)
1701 ++ goto sleep;
1702 +
1703 + /* Erase suspend */
1704 + /* It's harmless to issue the Erase-Suspend and Erase-Resume
1705 +@@ -2267,6 +2268,7 @@ static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
1706 + chip->state = FL_ERASING;
1707 + chip->erase_suspended = 0;
1708 + chip->in_progress_block_addr = adr;
1709 ++ chip->in_progress_block_mask = ~(map->size - 1);
1710 +
1711 + INVALIDATE_CACHE_UDELAY(map, chip,
1712 + adr, map->size,
1713 +@@ -2356,6 +2358,7 @@ static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip,
1714 + chip->state = FL_ERASING;
1715 + chip->erase_suspended = 0;
1716 + chip->in_progress_block_addr = adr;
1717 ++ chip->in_progress_block_mask = ~(len - 1);
1718 +
1719 + INVALIDATE_CACHE_UDELAY(map, chip,
1720 + adr, len,
1721 +diff --git a/drivers/mtd/nand/marvell_nand.c b/drivers/mtd/nand/marvell_nand.c
1722 +index 2196f2a233d6..795f868fe1f7 100644
1723 +--- a/drivers/mtd/nand/marvell_nand.c
1724 ++++ b/drivers/mtd/nand/marvell_nand.c
1725 +@@ -2277,29 +2277,20 @@ static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc,
1726 + /*
1727 + * The legacy "num-cs" property indicates the number of CS on the only
1728 + * chip connected to the controller (legacy bindings does not support
1729 +- * more than one chip). CS are only incremented one by one while the RB
1730 +- * pin is always the #0.
1731 ++ * more than one chip). The CS and RB pins are always the #0.
1732 + *
1733 + * When not using legacy bindings, a couple of "reg" and "nand-rb"
1734 + * properties must be filled. For each chip, expressed as a subnode,
1735 + * "reg" points to the CS lines and "nand-rb" to the RB line.
1736 + */
1737 +- if (pdata) {
1738 ++ if (pdata || nfc->caps->legacy_of_bindings) {
1739 + nsels = 1;
1740 +- } else if (nfc->caps->legacy_of_bindings &&
1741 +- !of_get_property(np, "num-cs", &nsels)) {
1742 +- dev_err(dev, "missing num-cs property\n");
1743 +- return -EINVAL;
1744 +- } else if (!of_get_property(np, "reg", &nsels)) {
1745 +- dev_err(dev, "missing reg property\n");
1746 +- return -EINVAL;
1747 +- }
1748 +-
1749 +- if (!pdata)
1750 +- nsels /= sizeof(u32);
1751 +- if (!nsels) {
1752 +- dev_err(dev, "invalid reg property size\n");
1753 +- return -EINVAL;
1754 ++ } else {
1755 ++ nsels = of_property_count_elems_of_size(np, "reg", sizeof(u32));
1756 ++ if (nsels <= 0) {
1757 ++ dev_err(dev, "missing/invalid reg property\n");
1758 ++ return -EINVAL;
1759 ++ }
1760 + }
1761 +
1762 + /* Alloc the nand chip structure */
1763 +diff --git a/drivers/mtd/nand/tango_nand.c b/drivers/mtd/nand/tango_nand.c
1764 +index c5bee00b7f5e..76761b841f1f 100644
1765 +--- a/drivers/mtd/nand/tango_nand.c
1766 ++++ b/drivers/mtd/nand/tango_nand.c
1767 +@@ -643,7 +643,7 @@ static int tango_nand_probe(struct platform_device *pdev)
1768 +
1769 + writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE);
1770 +
1771 +- clk = clk_get(&pdev->dev, NULL);
1772 ++ clk = devm_clk_get(&pdev->dev, NULL);
1773 + if (IS_ERR(clk))
1774 + return PTR_ERR(clk);
1775 +
1776 +diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
1777 +index 4b8e9183489a..5872f31eaa60 100644
1778 +--- a/drivers/mtd/spi-nor/cadence-quadspi.c
1779 ++++ b/drivers/mtd/spi-nor/cadence-quadspi.c
1780 +@@ -501,7 +501,9 @@ static int cqspi_indirect_read_execute(struct spi_nor *nor, u8 *rxbuf,
1781 + void __iomem *reg_base = cqspi->iobase;
1782 + void __iomem *ahb_base = cqspi->ahb_base;
1783 + unsigned int remaining = n_rx;
1784 ++ unsigned int mod_bytes = n_rx % 4;
1785 + unsigned int bytes_to_read = 0;
1786 ++ u8 *rxbuf_end = rxbuf + n_rx;
1787 + int ret = 0;
1788 +
1789 + writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
1790 +@@ -530,11 +532,24 @@ static int cqspi_indirect_read_execute(struct spi_nor *nor, u8 *rxbuf,
1791 + }
1792 +
1793 + while (bytes_to_read != 0) {
1794 ++ unsigned int word_remain = round_down(remaining, 4);
1795 ++
1796 + bytes_to_read *= cqspi->fifo_width;
1797 + bytes_to_read = bytes_to_read > remaining ?
1798 + remaining : bytes_to_read;
1799 +- ioread32_rep(ahb_base, rxbuf,
1800 +- DIV_ROUND_UP(bytes_to_read, 4));
1801 ++ bytes_to_read = round_down(bytes_to_read, 4);
1802 ++ /* Read 4 byte word chunks then single bytes */
1803 ++ if (bytes_to_read) {
1804 ++ ioread32_rep(ahb_base, rxbuf,
1805 ++ (bytes_to_read / 4));
1806 ++ } else if (!word_remain && mod_bytes) {
1807 ++ unsigned int temp = ioread32(ahb_base);
1808 ++
1809 ++ bytes_to_read = mod_bytes;
1810 ++ memcpy(rxbuf, &temp, min((unsigned int)
1811 ++ (rxbuf_end - rxbuf),
1812 ++ bytes_to_read));
1813 ++ }
1814 + rxbuf += bytes_to_read;
1815 + remaining -= bytes_to_read;
1816 + bytes_to_read = cqspi_get_rd_sram_level(cqspi);
1817 +diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
1818 +index 84aa9d676375..6da20b9688f7 100644
1819 +--- a/drivers/of/fdt.c
1820 ++++ b/drivers/of/fdt.c
1821 +@@ -942,7 +942,7 @@ int __init early_init_dt_scan_chosen_stdout(void)
1822 + int offset;
1823 + const char *p, *q, *options = NULL;
1824 + int l;
1825 +- const struct earlycon_id *match;
1826 ++ const struct earlycon_id **p_match;
1827 + const void *fdt = initial_boot_params;
1828 +
1829 + offset = fdt_path_offset(fdt, "/chosen");
1830 +@@ -969,7 +969,10 @@ int __init early_init_dt_scan_chosen_stdout(void)
1831 + return 0;
1832 + }
1833 +
1834 +- for (match = __earlycon_table; match < __earlycon_table_end; match++) {
1835 ++ for (p_match = __earlycon_table; p_match < __earlycon_table_end;
1836 ++ p_match++) {
1837 ++ const struct earlycon_id *match = *p_match;
1838 ++
1839 + if (!match->compatible[0])
1840 + continue;
1841 +
1842 +diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
1843 +index b04d37b3c5de..9abf549631b4 100644
1844 +--- a/drivers/pci/host/pci-aardvark.c
1845 ++++ b/drivers/pci/host/pci-aardvark.c
1846 +@@ -29,6 +29,7 @@
1847 + #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
1848 + #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
1849 + #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
1850 ++#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2
1851 + #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
1852 + #define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
1853 + #define PCIE_CORE_LINK_TRAINING BIT(5)
1854 +@@ -100,7 +101,8 @@
1855 + #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
1856 + #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
1857 + #define PCIE_ISR1_FLUSH BIT(5)
1858 +-#define PCIE_ISR1_ALL_MASK GENMASK(5, 4)
1859 ++#define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
1860 ++#define PCIE_ISR1_ALL_MASK GENMASK(11, 4)
1861 + #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
1862 + #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
1863 + #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
1864 +@@ -172,8 +174,6 @@
1865 + #define PCIE_CONFIG_WR_TYPE0 0xa
1866 + #define PCIE_CONFIG_WR_TYPE1 0xb
1867 +
1868 +-/* PCI_BDF shifts 8bit, so we need extra 4bit shift */
1869 +-#define PCIE_BDF(dev) (dev << 4)
1870 + #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
1871 + #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
1872 + #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
1873 +@@ -296,7 +296,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
1874 + reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
1875 + (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
1876 + PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
1877 +- PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
1878 ++ (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
1879 ++ PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
1880 + advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
1881 +
1882 + /* Program PCIe Control 2 to disable strict ordering */
1883 +@@ -437,7 +438,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
1884 + u32 reg;
1885 + int ret;
1886 +
1887 +- if (PCI_SLOT(devfn) != 0) {
1888 ++ if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0) {
1889 + *val = 0xffffffff;
1890 + return PCIBIOS_DEVICE_NOT_FOUND;
1891 + }
1892 +@@ -456,7 +457,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
1893 + advk_writel(pcie, reg, PIO_CTRL);
1894 +
1895 + /* Program the address registers */
1896 +- reg = PCIE_BDF(devfn) | PCIE_CONF_REG(where);
1897 ++ reg = PCIE_CONF_ADDR(bus->number, devfn, where);
1898 + advk_writel(pcie, reg, PIO_ADDR_LS);
1899 + advk_writel(pcie, 0, PIO_ADDR_MS);
1900 +
1901 +@@ -491,7 +492,7 @@ static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
1902 + int offset;
1903 + int ret;
1904 +
1905 +- if (PCI_SLOT(devfn) != 0)
1906 ++ if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0)
1907 + return PCIBIOS_DEVICE_NOT_FOUND;
1908 +
1909 + if (where % size)
1910 +@@ -609,9 +610,9 @@ static void advk_pcie_irq_mask(struct irq_data *d)
1911 + irq_hw_number_t hwirq = irqd_to_hwirq(d);
1912 + u32 mask;
1913 +
1914 +- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
1915 +- mask |= PCIE_ISR0_INTX_ASSERT(hwirq);
1916 +- advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
1917 ++ mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
1918 ++ mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
1919 ++ advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
1920 + }
1921 +
1922 + static void advk_pcie_irq_unmask(struct irq_data *d)
1923 +@@ -620,9 +621,9 @@ static void advk_pcie_irq_unmask(struct irq_data *d)
1924 + irq_hw_number_t hwirq = irqd_to_hwirq(d);
1925 + u32 mask;
1926 +
1927 +- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
1928 +- mask &= ~PCIE_ISR0_INTX_ASSERT(hwirq);
1929 +- advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
1930 ++ mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
1931 ++ mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
1932 ++ advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
1933 + }
1934 +
1935 + static int advk_pcie_irq_map(struct irq_domain *h,
1936 +@@ -765,29 +766,35 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
1937 +
1938 + static void advk_pcie_handle_int(struct advk_pcie *pcie)
1939 + {
1940 +- u32 val, mask, status;
1941 ++ u32 isr0_val, isr0_mask, isr0_status;
1942 ++ u32 isr1_val, isr1_mask, isr1_status;
1943 + int i, virq;
1944 +
1945 +- val = advk_readl(pcie, PCIE_ISR0_REG);
1946 +- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
1947 +- status = val & ((~mask) & PCIE_ISR0_ALL_MASK);
1948 ++ isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
1949 ++ isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
1950 ++ isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);
1951 ++
1952 ++ isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
1953 ++ isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
1954 ++ isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
1955 +
1956 +- if (!status) {
1957 +- advk_writel(pcie, val, PCIE_ISR0_REG);
1958 ++ if (!isr0_status && !isr1_status) {
1959 ++ advk_writel(pcie, isr0_val, PCIE_ISR0_REG);
1960 ++ advk_writel(pcie, isr1_val, PCIE_ISR1_REG);
1961 + return;
1962 + }
1963 +
1964 + /* Process MSI interrupts */
1965 +- if (status & PCIE_ISR0_MSI_INT_PENDING)
1966 ++ if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
1967 + advk_pcie_handle_msi(pcie);
1968 +
1969 + /* Process legacy interrupts */
1970 + for (i = 0; i < PCI_NUM_INTX; i++) {
1971 +- if (!(status & PCIE_ISR0_INTX_ASSERT(i)))
1972 ++ if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
1973 + continue;
1974 +
1975 +- advk_writel(pcie, PCIE_ISR0_INTX_ASSERT(i),
1976 +- PCIE_ISR0_REG);
1977 ++ advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
1978 ++ PCIE_ISR1_REG);
1979 +
1980 + virq = irq_find_mapping(pcie->irq_domain, i);
1981 + generic_handle_irq(virq);
1982 +diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
1983 +index 3bed6beda051..eede34e5ada2 100644
1984 +--- a/drivers/pci/pci-driver.c
1985 ++++ b/drivers/pci/pci-driver.c
1986 +@@ -945,10 +945,11 @@ static int pci_pm_freeze(struct device *dev)
1987 + * devices should not be touched during freeze/thaw transitions,
1988 + * however.
1989 + */
1990 +- if (!dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND))
1991 ++ if (!dev_pm_smart_suspend_and_suspended(dev)) {
1992 + pm_runtime_resume(dev);
1993 ++ pci_dev->state_saved = false;
1994 ++ }
1995 +
1996 +- pci_dev->state_saved = false;
1997 + if (pm->freeze) {
1998 + int error;
1999 +
2000 +diff --git a/drivers/rtc/rtc-opal.c b/drivers/rtc/rtc-opal.c
2001 +index 304e891e35fc..60f2250fd96b 100644
2002 +--- a/drivers/rtc/rtc-opal.c
2003 ++++ b/drivers/rtc/rtc-opal.c
2004 +@@ -57,7 +57,7 @@ static void tm_to_opal(struct rtc_time *tm, u32 *y_m_d, u64 *h_m_s_ms)
2005 +
2006 + static int opal_get_rtc_time(struct device *dev, struct rtc_time *tm)
2007 + {
2008 +- long rc = OPAL_BUSY;
2009 ++ s64 rc = OPAL_BUSY;
2010 + int retries = 10;
2011 + u32 y_m_d;
2012 + u64 h_m_s_ms;
2013 +@@ -66,13 +66,17 @@ static int opal_get_rtc_time(struct device *dev, struct rtc_time *tm)
2014 +
2015 + while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
2016 + rc = opal_rtc_read(&__y_m_d, &__h_m_s_ms);
2017 +- if (rc == OPAL_BUSY_EVENT)
2018 ++ if (rc == OPAL_BUSY_EVENT) {
2019 ++ msleep(OPAL_BUSY_DELAY_MS);
2020 + opal_poll_events(NULL);
2021 +- else if (retries-- && (rc == OPAL_HARDWARE
2022 +- || rc == OPAL_INTERNAL_ERROR))
2023 +- msleep(10);
2024 +- else if (rc != OPAL_BUSY && rc != OPAL_BUSY_EVENT)
2025 +- break;
2026 ++ } else if (rc == OPAL_BUSY) {
2027 ++ msleep(OPAL_BUSY_DELAY_MS);
2028 ++ } else if (rc == OPAL_HARDWARE || rc == OPAL_INTERNAL_ERROR) {
2029 ++ if (retries--) {
2030 ++ msleep(10); /* Wait 10ms before retry */
2031 ++ rc = OPAL_BUSY; /* go around again */
2032 ++ }
2033 ++ }
2034 + }
2035 +
2036 + if (rc != OPAL_SUCCESS)
2037 +@@ -87,21 +91,26 @@ static int opal_get_rtc_time(struct device *dev, struct rtc_time *tm)
2038 +
2039 + static int opal_set_rtc_time(struct device *dev, struct rtc_time *tm)
2040 + {
2041 +- long rc = OPAL_BUSY;
2042 ++ s64 rc = OPAL_BUSY;
2043 + int retries = 10;
2044 + u32 y_m_d = 0;
2045 + u64 h_m_s_ms = 0;
2046 +
2047 + tm_to_opal(tm, &y_m_d, &h_m_s_ms);
2048 ++
2049 + while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
2050 + rc = opal_rtc_write(y_m_d, h_m_s_ms);
2051 +- if (rc == OPAL_BUSY_EVENT)
2052 ++ if (rc == OPAL_BUSY_EVENT) {
2053 ++ msleep(OPAL_BUSY_DELAY_MS);
2054 + opal_poll_events(NULL);
2055 +- else if (retries-- && (rc == OPAL_HARDWARE
2056 +- || rc == OPAL_INTERNAL_ERROR))
2057 +- msleep(10);
2058 +- else if (rc != OPAL_BUSY && rc != OPAL_BUSY_EVENT)
2059 +- break;
2060 ++ } else if (rc == OPAL_BUSY) {
2061 ++ msleep(OPAL_BUSY_DELAY_MS);
2062 ++ } else if (rc == OPAL_HARDWARE || rc == OPAL_INTERNAL_ERROR) {
2063 ++ if (retries--) {
2064 ++ msleep(10); /* Wait 10ms before retry */
2065 ++ rc = OPAL_BUSY; /* go around again */
2066 ++ }
2067 ++ }
2068 + }
2069 +
2070 + return rc == OPAL_SUCCESS ? 0 : -EIO;
2071 +diff --git a/drivers/s390/cio/vfio_ccw_fsm.c b/drivers/s390/cio/vfio_ccw_fsm.c
2072 +index c30420c517b1..e96b85579f21 100644
2073 +--- a/drivers/s390/cio/vfio_ccw_fsm.c
2074 ++++ b/drivers/s390/cio/vfio_ccw_fsm.c
2075 +@@ -20,12 +20,12 @@ static int fsm_io_helper(struct vfio_ccw_private *private)
2076 + int ccode;
2077 + __u8 lpm;
2078 + unsigned long flags;
2079 ++ int ret;
2080 +
2081 + sch = private->sch;
2082 +
2083 + spin_lock_irqsave(sch->lock, flags);
2084 + private->state = VFIO_CCW_STATE_BUSY;
2085 +- spin_unlock_irqrestore(sch->lock, flags);
2086 +
2087 + orb = cp_get_orb(&private->cp, (u32)(addr_t)sch, sch->lpm);
2088 +
2089 +@@ -38,10 +38,12 @@ static int fsm_io_helper(struct vfio_ccw_private *private)
2090 + * Initialize device status information
2091 + */
2092 + sch->schib.scsw.cmd.actl |= SCSW_ACTL_START_PEND;
2093 +- return 0;
2094 ++ ret = 0;
2095 ++ break;
2096 + case 1: /* Status pending */
2097 + case 2: /* Busy */
2098 +- return -EBUSY;
2099 ++ ret = -EBUSY;
2100 ++ break;
2101 + case 3: /* Device/path not operational */
2102 + {
2103 + lpm = orb->cmd.lpm;
2104 +@@ -51,13 +53,16 @@ static int fsm_io_helper(struct vfio_ccw_private *private)
2105 + sch->lpm = 0;
2106 +
2107 + if (cio_update_schib(sch))
2108 +- return -ENODEV;
2109 +-
2110 +- return sch->lpm ? -EACCES : -ENODEV;
2111 ++ ret = -ENODEV;
2112 ++ else
2113 ++ ret = sch->lpm ? -EACCES : -ENODEV;
2114 ++ break;
2115 + }
2116 + default:
2117 +- return ccode;
2118 ++ ret = ccode;
2119 + }
2120 ++ spin_unlock_irqrestore(sch->lock, flags);
2121 ++ return ret;
2122 + }
2123 +
2124 + static void fsm_notoper(struct vfio_ccw_private *private,
2125 +diff --git a/drivers/sbus/char/oradax.c b/drivers/sbus/char/oradax.c
2126 +index c44d7c7ffc92..1754f55e2fac 100644
2127 +--- a/drivers/sbus/char/oradax.c
2128 ++++ b/drivers/sbus/char/oradax.c
2129 +@@ -3,7 +3,7 @@
2130 + *
2131 + * This program is free software: you can redistribute it and/or modify
2132 + * it under the terms of the GNU General Public License as published by
2133 +- * the Free Software Foundation, either version 3 of the License, or
2134 ++ * the Free Software Foundation, either version 2 of the License, or
2135 + * (at your option) any later version.
2136 + *
2137 + * This program is distributed in the hope that it will be useful,
2138 +diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c
2139 +index 1fa84d6a0f8b..d19b41bcebea 100644
2140 +--- a/drivers/scsi/sd.c
2141 ++++ b/drivers/scsi/sd.c
2142 +@@ -2121,6 +2121,8 @@ sd_spinup_disk(struct scsi_disk *sdkp)
2143 + break; /* standby */
2144 + if (sshdr.asc == 4 && sshdr.ascq == 0xc)
2145 + break; /* unavailable */
2146 ++ if (sshdr.asc == 4 && sshdr.ascq == 0x1b)
2147 ++ break; /* sanitize in progress */
2148 + /*
2149 + * Issue command to spin up drive when not ready
2150 + */
2151 +diff --git a/drivers/scsi/sd_zbc.c b/drivers/scsi/sd_zbc.c
2152 +index 89cf4498f535..973a497739f0 100644
2153 +--- a/drivers/scsi/sd_zbc.c
2154 ++++ b/drivers/scsi/sd_zbc.c
2155 +@@ -400,8 +400,10 @@ static int sd_zbc_check_capacity(struct scsi_disk *sdkp, unsigned char *buf)
2156 + *
2157 + * Check that all zones of the device are equal. The last zone can however
2158 + * be smaller. The zone size must also be a power of two number of LBAs.
2159 ++ *
2160 ++ * Returns the zone size in bytes upon success or an error code upon failure.
2161 + */
2162 +-static int sd_zbc_check_zone_size(struct scsi_disk *sdkp)
2163 ++static s64 sd_zbc_check_zone_size(struct scsi_disk *sdkp)
2164 + {
2165 + u64 zone_blocks = 0;
2166 + sector_t block = 0;
2167 +@@ -412,8 +414,6 @@ static int sd_zbc_check_zone_size(struct scsi_disk *sdkp)
2168 + int ret;
2169 + u8 same;
2170 +
2171 +- sdkp->zone_blocks = 0;
2172 +-
2173 + /* Get a buffer */
2174 + buf = kmalloc(SD_ZBC_BUF_SIZE, GFP_KERNEL);
2175 + if (!buf)
2176 +@@ -445,16 +445,17 @@ static int sd_zbc_check_zone_size(struct scsi_disk *sdkp)
2177 +
2178 + /* Parse zone descriptors */
2179 + while (rec < buf + buf_len) {
2180 +- zone_blocks = get_unaligned_be64(&rec[8]);
2181 +- if (sdkp->zone_blocks == 0) {
2182 +- sdkp->zone_blocks = zone_blocks;
2183 +- } else if (zone_blocks != sdkp->zone_blocks &&
2184 +- (block + zone_blocks < sdkp->capacity
2185 +- || zone_blocks > sdkp->zone_blocks)) {
2186 +- zone_blocks = 0;
2187 ++ u64 this_zone_blocks = get_unaligned_be64(&rec[8]);
2188 ++
2189 ++ if (zone_blocks == 0) {
2190 ++ zone_blocks = this_zone_blocks;
2191 ++ } else if (this_zone_blocks != zone_blocks &&
2192 ++ (block + this_zone_blocks < sdkp->capacity
2193 ++ || this_zone_blocks > zone_blocks)) {
2194 ++ this_zone_blocks = 0;
2195 + goto out;
2196 + }
2197 +- block += zone_blocks;
2198 ++ block += this_zone_blocks;
2199 + rec += 64;
2200 + }
2201 +
2202 +@@ -467,8 +468,6 @@ static int sd_zbc_check_zone_size(struct scsi_disk *sdkp)
2203 +
2204 + } while (block < sdkp->capacity);
2205 +
2206 +- zone_blocks = sdkp->zone_blocks;
2207 +-
2208 + out:
2209 + if (!zone_blocks) {
2210 + if (sdkp->first_scan)
2211 +@@ -488,8 +487,7 @@ static int sd_zbc_check_zone_size(struct scsi_disk *sdkp)
2212 + "Zone size too large\n");
2213 + ret = -ENODEV;
2214 + } else {
2215 +- sdkp->zone_blocks = zone_blocks;
2216 +- sdkp->zone_shift = ilog2(zone_blocks);
2217 ++ ret = zone_blocks;
2218 + }
2219 +
2220 + out_free:
2221 +@@ -500,21 +498,21 @@ static int sd_zbc_check_zone_size(struct scsi_disk *sdkp)
2222 +
2223 + /**
2224 + * sd_zbc_alloc_zone_bitmap - Allocate a zone bitmap (one bit per zone).
2225 +- * @sdkp: The disk of the bitmap
2226 ++ * @nr_zones: Number of zones to allocate space for.
2227 ++ * @numa_node: NUMA node to allocate the memory from.
2228 + */
2229 +-static inline unsigned long *sd_zbc_alloc_zone_bitmap(struct scsi_disk *sdkp)
2230 ++static inline unsigned long *
2231 ++sd_zbc_alloc_zone_bitmap(u32 nr_zones, int numa_node)
2232 + {
2233 +- struct request_queue *q = sdkp->disk->queue;
2234 +-
2235 +- return kzalloc_node(BITS_TO_LONGS(sdkp->nr_zones)
2236 +- * sizeof(unsigned long),
2237 +- GFP_KERNEL, q->node);
2238 ++ return kzalloc_node(BITS_TO_LONGS(nr_zones) * sizeof(unsigned long),
2239 ++ GFP_KERNEL, numa_node);
2240 + }
2241 +
2242 + /**
2243 + * sd_zbc_get_seq_zones - Parse report zones reply to identify sequential zones
2244 + * @sdkp: disk used
2245 + * @buf: report reply buffer
2246 ++ * @zone_shift: logarithm base 2 of the number of blocks in a zone
2247 + * @seq_zone_bitamp: bitmap of sequential zones to set
2248 + *
2249 + * Parse reported zone descriptors in @buf to identify sequential zones and
2250 +@@ -524,7 +522,7 @@ static inline unsigned long *sd_zbc_alloc_zone_bitmap(struct scsi_disk *sdkp)
2251 + * Return the LBA after the last zone reported.
2252 + */
2253 + static sector_t sd_zbc_get_seq_zones(struct scsi_disk *sdkp, unsigned char *buf,
2254 +- unsigned int buflen,
2255 ++ unsigned int buflen, u32 zone_shift,
2256 + unsigned long *seq_zones_bitmap)
2257 + {
2258 + sector_t lba, next_lba = sdkp->capacity;
2259 +@@ -543,7 +541,7 @@ static sector_t sd_zbc_get_seq_zones(struct scsi_disk *sdkp, unsigned char *buf,
2260 + if (type != ZBC_ZONE_TYPE_CONV &&
2261 + cond != ZBC_ZONE_COND_READONLY &&
2262 + cond != ZBC_ZONE_COND_OFFLINE)
2263 +- set_bit(lba >> sdkp->zone_shift, seq_zones_bitmap);
2264 ++ set_bit(lba >> zone_shift, seq_zones_bitmap);
2265 + next_lba = lba + get_unaligned_be64(&rec[8]);
2266 + rec += 64;
2267 + }
2268 +@@ -552,12 +550,16 @@ static sector_t sd_zbc_get_seq_zones(struct scsi_disk *sdkp, unsigned char *buf,
2269 + }
2270 +
2271 + /**
2272 +- * sd_zbc_setup_seq_zones_bitmap - Initialize the disk seq zone bitmap.
2273 ++ * sd_zbc_setup_seq_zones_bitmap - Initialize a seq zone bitmap.
2274 + * @sdkp: target disk
2275 ++ * @zone_shift: logarithm base 2 of the number of blocks in a zone
2276 ++ * @nr_zones: number of zones to set up a seq zone bitmap for
2277 + *
2278 + * Allocate a zone bitmap and initialize it by identifying sequential zones.
2279 + */
2280 +-static int sd_zbc_setup_seq_zones_bitmap(struct scsi_disk *sdkp)
2281 ++static unsigned long *
2282 ++sd_zbc_setup_seq_zones_bitmap(struct scsi_disk *sdkp, u32 zone_shift,
2283 ++ u32 nr_zones)
2284 + {
2285 + struct request_queue *q = sdkp->disk->queue;
2286 + unsigned long *seq_zones_bitmap;
2287 +@@ -565,9 +567,9 @@ static int sd_zbc_setup_seq_zones_bitmap(struct scsi_disk *sdkp)
2288 + unsigned char *buf;
2289 + int ret = -ENOMEM;
2290 +
2291 +- seq_zones_bitmap = sd_zbc_alloc_zone_bitmap(sdkp);
2292 ++ seq_zones_bitmap = sd_zbc_alloc_zone_bitmap(nr_zones, q->node);
2293 + if (!seq_zones_bitmap)
2294 +- return -ENOMEM;
2295 ++ return ERR_PTR(-ENOMEM);
2296 +
2297 + buf = kmalloc(SD_ZBC_BUF_SIZE, GFP_KERNEL);
2298 + if (!buf)
2299 +@@ -578,7 +580,7 @@ static int sd_zbc_setup_seq_zones_bitmap(struct scsi_disk *sdkp)
2300 + if (ret)
2301 + goto out;
2302 + lba = sd_zbc_get_seq_zones(sdkp, buf, SD_ZBC_BUF_SIZE,
2303 +- seq_zones_bitmap);
2304 ++ zone_shift, seq_zones_bitmap);
2305 + }
2306 +
2307 + if (lba != sdkp->capacity) {
2308 +@@ -590,12 +592,9 @@ static int sd_zbc_setup_seq_zones_bitmap(struct scsi_disk *sdkp)
2309 + kfree(buf);
2310 + if (ret) {
2311 + kfree(seq_zones_bitmap);
2312 +- return ret;
2313 ++ return ERR_PTR(ret);
2314 + }
2315 +-
2316 +- q->seq_zones_bitmap = seq_zones_bitmap;
2317 +-
2318 +- return 0;
2319 ++ return seq_zones_bitmap;
2320 + }
2321 +
2322 + static void sd_zbc_cleanup(struct scsi_disk *sdkp)
2323 +@@ -611,44 +610,64 @@ static void sd_zbc_cleanup(struct scsi_disk *sdkp)
2324 + q->nr_zones = 0;
2325 + }
2326 +
2327 +-static int sd_zbc_setup(struct scsi_disk *sdkp)
2328 ++static int sd_zbc_setup(struct scsi_disk *sdkp, u32 zone_blocks)
2329 + {
2330 + struct request_queue *q = sdkp->disk->queue;
2331 ++ u32 zone_shift = ilog2(zone_blocks);
2332 ++ u32 nr_zones;
2333 + int ret;
2334 +
2335 +- /* READ16/WRITE16 is mandatory for ZBC disks */
2336 +- sdkp->device->use_16_for_rw = 1;
2337 +- sdkp->device->use_10_for_rw = 0;
2338 +-
2339 + /* chunk_sectors indicates the zone size */
2340 +- blk_queue_chunk_sectors(sdkp->disk->queue,
2341 +- logical_to_sectors(sdkp->device, sdkp->zone_blocks));
2342 +- sdkp->nr_zones =
2343 +- round_up(sdkp->capacity, sdkp->zone_blocks) >> sdkp->zone_shift;
2344 ++ blk_queue_chunk_sectors(q,
2345 ++ logical_to_sectors(sdkp->device, zone_blocks));
2346 ++ nr_zones = round_up(sdkp->capacity, zone_blocks) >> zone_shift;
2347 +
2348 + /*
2349 + * Initialize the device request queue information if the number
2350 + * of zones changed.
2351 + */
2352 +- if (sdkp->nr_zones != q->nr_zones) {
2353 +-
2354 +- sd_zbc_cleanup(sdkp);
2355 +-
2356 +- q->nr_zones = sdkp->nr_zones;
2357 +- if (sdkp->nr_zones) {
2358 +- q->seq_zones_wlock = sd_zbc_alloc_zone_bitmap(sdkp);
2359 +- if (!q->seq_zones_wlock) {
2360 ++ if (nr_zones != sdkp->nr_zones || nr_zones != q->nr_zones) {
2361 ++ unsigned long *seq_zones_wlock = NULL, *seq_zones_bitmap = NULL;
2362 ++ size_t zone_bitmap_size;
2363 ++
2364 ++ if (nr_zones) {
2365 ++ seq_zones_wlock = sd_zbc_alloc_zone_bitmap(nr_zones,
2366 ++ q->node);
2367 ++ if (!seq_zones_wlock) {
2368 + ret = -ENOMEM;
2369 + goto err;
2370 + }
2371 +
2372 +- ret = sd_zbc_setup_seq_zones_bitmap(sdkp);
2373 +- if (ret) {
2374 +- sd_zbc_cleanup(sdkp);
2375 ++ seq_zones_bitmap = sd_zbc_setup_seq_zones_bitmap(sdkp,
2376 ++ zone_shift, nr_zones);
2377 ++ if (IS_ERR(seq_zones_bitmap)) {
2378 ++ ret = PTR_ERR(seq_zones_bitmap);
2379 ++ kfree(seq_zones_wlock);
2380 + goto err;
2381 + }
2382 + }
2383 +-
2384 ++ zone_bitmap_size = BITS_TO_LONGS(nr_zones) *
2385 ++ sizeof(unsigned long);
2386 ++ blk_mq_freeze_queue(q);
2387 ++ if (q->nr_zones != nr_zones) {
2388 ++ /* READ16/WRITE16 is mandatory for ZBC disks */
2389 ++ sdkp->device->use_16_for_rw = 1;
2390 ++ sdkp->device->use_10_for_rw = 0;
2391 ++
2392 ++ sdkp->zone_blocks = zone_blocks;
2393 ++ sdkp->zone_shift = zone_shift;
2394 ++ sdkp->nr_zones = nr_zones;
2395 ++ q->nr_zones = nr_zones;
2396 ++ swap(q->seq_zones_wlock, seq_zones_wlock);
2397 ++ swap(q->seq_zones_bitmap, seq_zones_bitmap);
2398 ++ } else if (memcmp(q->seq_zones_bitmap, seq_zones_bitmap,
2399 ++ zone_bitmap_size) != 0) {
2400 ++ memcpy(q->seq_zones_bitmap, seq_zones_bitmap,
2401 ++ zone_bitmap_size);
2402 ++ }
2403 ++ blk_mq_unfreeze_queue(q);
2404 ++ kfree(seq_zones_wlock);
2405 ++ kfree(seq_zones_bitmap);
2406 + }
2407 +
2408 + return 0;
2409 +@@ -660,6 +679,7 @@ static int sd_zbc_setup(struct scsi_disk *sdkp)
2410 +
2411 + int sd_zbc_read_zones(struct scsi_disk *sdkp, unsigned char *buf)
2412 + {
2413 ++ int64_t zone_blocks;
2414 + int ret;
2415 +
2416 + if (!sd_is_zoned(sdkp))
2417 +@@ -696,12 +716,16 @@ int sd_zbc_read_zones(struct scsi_disk *sdkp, unsigned char *buf)
2418 + * Check zone size: only devices with a constant zone size (except
2419 + * an eventual last runt zone) that is a power of 2 are supported.
2420 + */
2421 +- ret = sd_zbc_check_zone_size(sdkp);
2422 +- if (ret)
2423 ++ zone_blocks = sd_zbc_check_zone_size(sdkp);
2424 ++ ret = -EFBIG;
2425 ++ if (zone_blocks != (u32)zone_blocks)
2426 ++ goto err;
2427 ++ ret = zone_blocks;
2428 ++ if (ret < 0)
2429 + goto err;
2430 +
2431 + /* The drive satisfies the kernel restrictions: set it up */
2432 +- ret = sd_zbc_setup(sdkp);
2433 ++ ret = sd_zbc_setup(sdkp, zone_blocks);
2434 + if (ret)
2435 + goto err;
2436 +
2437 +diff --git a/drivers/slimbus/messaging.c b/drivers/slimbus/messaging.c
2438 +index 884419c37e84..457ea1f8db30 100644
2439 +--- a/drivers/slimbus/messaging.c
2440 ++++ b/drivers/slimbus/messaging.c
2441 +@@ -183,7 +183,7 @@ static u16 slim_slicesize(int code)
2442 + 0, 1, 2, 3, 3, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7
2443 + };
2444 +
2445 +- clamp(code, 1, (int)ARRAY_SIZE(sizetocode));
2446 ++ code = clamp(code, 1, (int)ARRAY_SIZE(sizetocode));
2447 +
2448 + return sizetocode[code - 1];
2449 + }
2450 +diff --git a/drivers/tty/n_gsm.c b/drivers/tty/n_gsm.c
2451 +index 3b3e1f6632d7..1dbe27c9946c 100644
2452 +--- a/drivers/tty/n_gsm.c
2453 ++++ b/drivers/tty/n_gsm.c
2454 +@@ -121,6 +121,9 @@ struct gsm_dlci {
2455 + struct mutex mutex;
2456 +
2457 + /* Link layer */
2458 ++ int mode;
2459 ++#define DLCI_MODE_ABM 0 /* Normal Asynchronous Balanced Mode */
2460 ++#define DLCI_MODE_ADM 1 /* Asynchronous Disconnected Mode */
2461 + spinlock_t lock; /* Protects the internal state */
2462 + struct timer_list t1; /* Retransmit timer for SABM and UA */
2463 + int retries;
2464 +@@ -1364,7 +1367,13 @@ static struct gsm_control *gsm_control_send(struct gsm_mux *gsm,
2465 + ctrl->data = data;
2466 + ctrl->len = clen;
2467 + gsm->pending_cmd = ctrl;
2468 +- gsm->cretries = gsm->n2;
2469 ++
2470 ++ /* If DLCI0 is in ADM mode skip retries, it won't respond */
2471 ++ if (gsm->dlci[0]->mode == DLCI_MODE_ADM)
2472 ++ gsm->cretries = 1;
2473 ++ else
2474 ++ gsm->cretries = gsm->n2;
2475 ++
2476 + mod_timer(&gsm->t2_timer, jiffies + gsm->t2 * HZ / 100);
2477 + gsm_control_transmit(gsm, ctrl);
2478 + spin_unlock_irqrestore(&gsm->control_lock, flags);
2479 +@@ -1472,6 +1481,7 @@ static void gsm_dlci_t1(struct timer_list *t)
2480 + if (debug & 8)
2481 + pr_info("DLCI %d opening in ADM mode.\n",
2482 + dlci->addr);
2483 ++ dlci->mode = DLCI_MODE_ADM;
2484 + gsm_dlci_open(dlci);
2485 + } else {
2486 + gsm_dlci_close(dlci);
2487 +@@ -2861,11 +2871,22 @@ static int gsmtty_modem_update(struct gsm_dlci *dlci, u8 brk)
2488 + static int gsm_carrier_raised(struct tty_port *port)
2489 + {
2490 + struct gsm_dlci *dlci = container_of(port, struct gsm_dlci, port);
2491 ++ struct gsm_mux *gsm = dlci->gsm;
2492 ++
2493 + /* Not yet open so no carrier info */
2494 + if (dlci->state != DLCI_OPEN)
2495 + return 0;
2496 + if (debug & 2)
2497 + return 1;
2498 ++
2499 ++ /*
2500 ++ * Basic mode with control channel in ADM mode may not respond
2501 ++ * to CMD_MSC at all and modem_rx is empty.
2502 ++ */
2503 ++ if (gsm->encoding == 0 && gsm->dlci[0]->mode == DLCI_MODE_ADM &&
2504 ++ !dlci->modem_rx)
2505 ++ return 1;
2506 ++
2507 + return dlci->modem_rx & TIOCM_CD;
2508 + }
2509 +
2510 +diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c
2511 +index a24278380fec..22683393a0f2 100644
2512 +--- a/drivers/tty/serial/earlycon.c
2513 ++++ b/drivers/tty/serial/earlycon.c
2514 +@@ -169,7 +169,7 @@ static int __init register_earlycon(char *buf, const struct earlycon_id *match)
2515 + */
2516 + int __init setup_earlycon(char *buf)
2517 + {
2518 +- const struct earlycon_id *match;
2519 ++ const struct earlycon_id **p_match;
2520 +
2521 + if (!buf || !buf[0])
2522 + return -EINVAL;
2523 +@@ -177,7 +177,9 @@ int __init setup_earlycon(char *buf)
2524 + if (early_con.flags & CON_ENABLED)
2525 + return -EALREADY;
2526 +
2527 +- for (match = __earlycon_table; match < __earlycon_table_end; match++) {
2528 ++ for (p_match = __earlycon_table; p_match < __earlycon_table_end;
2529 ++ p_match++) {
2530 ++ const struct earlycon_id *match = *p_match;
2531 + size_t len = strlen(match->name);
2532 +
2533 + if (strncmp(buf, match->name, len))
2534 +diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c
2535 +index a100e98259d7..03d26aabb0c4 100644
2536 +--- a/drivers/tty/serial/mvebu-uart.c
2537 ++++ b/drivers/tty/serial/mvebu-uart.c
2538 +@@ -495,7 +495,6 @@ static void mvebu_uart_set_termios(struct uart_port *port,
2539 + termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR);
2540 + termios->c_cflag &= CREAD | CBAUD;
2541 + termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD);
2542 +- termios->c_lflag = old->c_lflag;
2543 + }
2544 +
2545 + spin_unlock_irqrestore(&port->lock, flags);
2546 +diff --git a/drivers/tty/tty_io.c b/drivers/tty/tty_io.c
2547 +index 63114ea35ec1..7c838b90a31d 100644
2548 +--- a/drivers/tty/tty_io.c
2549 ++++ b/drivers/tty/tty_io.c
2550 +@@ -2816,7 +2816,10 @@ struct tty_struct *alloc_tty_struct(struct tty_driver *driver, int idx)
2551 +
2552 + kref_init(&tty->kref);