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From: "Mike Frysinger (vapier)" <vapier@g.o>
To: gentoo-commits@l.g.o
Subject: [gentoo-commits] gentoo commit in src/patchsets/glibc/2.13: 6610_all_glibc-r10k-workarounds.patch README.history
Date: Tue, 05 Jul 2011 06:00:14
Message-Id: 20110705060004.CE3DE20054@flycatcher.gentoo.org
1 vapier 11/07/05 06:00:04
2
3 Modified: README.history
4 Added: 6610_all_glibc-r10k-workarounds.patch
5 Log:
6 re-add the mips r10k errata workaround #373361 by Matt Turner
7
8 Revision Changes Path
9 1.22 src/patchsets/glibc/2.13/README.history
10
11 file : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/glibc/2.13/README.history?rev=1.22&view=markup
12 plain: http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/glibc/2.13/README.history?rev=1.22&content-type=text/plain
13 diff : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/glibc/2.13/README.history?r1=1.21&r2=1.22
14
15 Index: README.history
16 ===================================================================
17 RCS file: /var/cvsroot/gentoo/src/patchsets/glibc/2.13/README.history,v
18 retrieving revision 1.21
19 retrieving revision 1.22
20 diff -u -r1.21 -r1.22
21 --- README.history 28 May 2011 19:54:10 -0000 1.21
22 +++ README.history 5 Jul 2011 06:00:04 -0000 1.22
23 @@ -1,10 +1,11 @@
24 -7 [pending]
25 +7 05.07.2011
26 + 0043_all_glibc-2.12-broken-tls-init.patch
27 + 0045_all_glibc-2.13-canonical-getaddrinfo.patch
28 + 0046_all_glibc-2.13-dso-init-fini-order.patch
29 U 0050_all_glibc-2.13-ldso-prelink-segv.patch
30 + 6145_all_powerpc64-glibc-2.13-syscall.patch
31 + 6146_all_ppc-glibc-2.13-vsx-toc-O3.patch
32 + + 6610_all_glibc-r10k-workarounds.patch
33
34 6 10.04.2011
35 + 1508_all_glibc-2.13-hppa-DEFAULT_STACK_PERMS.patch
36
37
38
39 1.1 src/patchsets/glibc/2.13/6610_all_glibc-r10k-workarounds.patch
40
41 file : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/glibc/2.13/6610_all_glibc-r10k-workarounds.patch?rev=1.1&view=markup
42 plain: http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/glibc/2.13/6610_all_glibc-r10k-workarounds.patch?rev=1.1&content-type=text/plain
43
44 Index: 6610_all_glibc-r10k-workarounds.patch
45 ===================================================================
46 http://bugs.gentoo.org/373361
47
48 From c804165aae6e4055a7a8c42cf66ea0b1a29ef3ed Mon Sep 17 00:00:00 2001
49 From: Matt Turner <mattst88@×××××.com>
50 Date: Tue, 28 Jun 2011 11:30:53 -0400
51 Subject: [PATCH] mips: work-around R10k ll/sc errata
52
53 The R10000 needs an LL/SC Workaround. If not applied all R10k before
54 rev 3.0 misbehave on atomic ops and rev 2.6 and lower (e.g. SGI IP28)
55 die after very few seconds with a deadlock due to even more erratas.
56 ---
57 ChangeLog.mips | 4 ++++
58 sysdeps/mips/bits/atomic.h | 38 ++++++++++++++++++++++++++++++++------
59 2 files changed, 36 insertions(+), 6 deletions(-)
60
61 diff --git a/sysdeps/mips/bits/atomic.h b/sysdeps/mips/bits/atomic.h
62 index 11b3467..2bd723d 100644
63 --- a/ports/sysdeps/mips/bits/atomic.h
64 +++ b/ports/sysdeps/mips/bits/atomic.h
65 @@ -49,6 +49,32 @@ typedef uintmax_t uatomic_max_t;
66 # define MIPS_SYNC sync
67 #endif
68
69 +/* Certain revisions of the R10000 Processor need an LL/SC Workaround
70 + enabled. Revisions before 3.0 misbehave on atomic operations, and
71 + Revs 2.6 and lower deadlock after several seconds due to other errata.
72 +
73 + To quote the R10K Errata:
74 + Workaround: The basic idea is to inhibit the four instructions
75 + from simultaneously becoming active in R10000. Padding all
76 + ll/sc sequences with nops or changing the looping branch in the
77 + routines to a branch likely (which is always predicted taken
78 + by R10000) will work. The nops should go after the loop, and the
79 + number of them should be 28. This number could be decremented for
80 + each additional instruction in the ll/sc loop such as the lock
81 + modifier(s) between the ll and sc, the looping branch and its
82 + delay slot. For typical short routines with one ll/sc loop, any
83 + instructions after the loop could also count as a decrement. The
84 + nop workaround pollutes the cache more but would be a few cycles
85 + faster if all the code is in the cache and the looping branch
86 + is predicted not taken. */
87 +
88 +
89 +#ifdef _MIPS_ARCH_R10000
90 +#define R10K_BEQZ_INSN "beqzl"
91 +#else
92 +#define R10K_BEQZ_INSN "beqz"
93 +#endif
94 +
95 #define MIPS_SYNC_STR_2(X) #X
96 #define MIPS_SYNC_STR_1(X) MIPS_SYNC_STR_2(X)
97 #define MIPS_SYNC_STR MIPS_SYNC_STR_1(MIPS_SYNC)
98 @@ -74,7 +100,7 @@ typedef uintmax_t uatomic_max_t;
99 "bne %0,%3,2f\n\t" \
100 "move %1,%4\n\t" \
101 "sc %1,%2\n\t" \
102 - "beqz %1,1b\n" \
103 + R10K_BEQZ_INSN" %1,1b\n" \
104 acq "\n\t" \
105 ".set pop\n" \
106 "2:\n\t" \
107 @@ -98,7 +124,7 @@ typedef uintmax_t uatomic_max_t;
108 "bne %0,%3,2f\n\t" \
109 "move %1,%4\n\t" \
110 "scd %1,%2\n\t" \
111 - "beqz %1,1b\n" \
112 + R10K_BEQZ_INSN" %1,1b\n" \
113 acq "\n\t" \
114 ".set pop\n" \
115 "2:\n\t" \
116 @@ -192,7 +218,7 @@ typedef uintmax_t uatomic_max_t;
117 "ll %0,%4\n\t" \
118 "move %1,%3\n\t" \
119 "sc %1,%2\n\t" \
120 - "beqz %1,1b\n" \
121 + R10K_BEQZ_INSN" %1,1b\n" \
122 acq "\n\t" \
123 ".set pop\n" \
124 "2:\n\t" \
125 @@ -216,7 +242,7 @@ typedef uintmax_t uatomic_max_t;
126 "lld %0,%4\n\t" \
127 "move %1,%3\n\t" \
128 "scd %1,%2\n\t" \
129 - "beqz %1,1b\n" \
130 + R10K_BEQZ_INSN" %1,1b\n" \
131 acq "\n\t" \
132 ".set pop\n" \
133 "2:\n\t" \
134 @@ -251,7 +277,7 @@ typedef uintmax_t uatomic_max_t;
135 "ll %0,%4\n\t" \
136 "addu %1,%0,%3\n\t" \
137 "sc %1,%2\n\t" \
138 - "beqz %1,1b\n" \
139 + R10K_BEQZ_INSN" %1,1b\n" \
140 acq "\n\t" \
141 ".set pop\n" \
142 "2:\n\t" \
143 @@ -275,7 +301,7 @@ typedef uintmax_t uatomic_max_t;
144 "lld %0,%4\n\t" \
145 "daddu %1,%0,%3\n\t" \
146 "scd %1,%2\n\t" \
147 - "beqz %1,1b\n" \
148 + R10K_BEQZ_INSN" %1,1b\n" \
149 acq "\n\t" \
150 ".set pop\n" \
151 "2:\n\t" \
152 --
153 1.7.3.4
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