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commit: 5846980492f891a80511f1ed36d666ef8a073e1a |
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Author: Mike Pagano <mpagano <AT> gentoo <DOT> org> |
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AuthorDate: Mon Sep 14 17:35:23 2020 +0000 |
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Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org> |
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CommitDate: Mon Sep 14 17:35:23 2020 +0000 |
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URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=58469804 |
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|
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Update cpu opt patch for v9.1 >= gcc < v10.X. |
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|
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See bug #742533 |
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Reported by Balint SZENTE |
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|
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Signed-off-by: Mike Pagano <mpagano <AT> gentoo.org> |
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|
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0000_README | 4 + |
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5012_enable-cpu-optimizations-for-gcc91.patch | 641 ++++++++++++++++++++++++++ |
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2 files changed, 645 insertions(+) |
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|
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diff --git a/0000_README b/0000_README |
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index 96ae239..8c02383 100644 |
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--- a/0000_README |
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+++ b/0000_README |
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@@ -135,6 +135,10 @@ Patch: 5007_ZSTD-v10-8-8-gitignore-add-ZSTD-compressed-files.patch |
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From: https://lkml.org/lkml/2020/4/1/29 |
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Desc: .gitignore: add ZSTD-compressed files |
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|
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+Patch: 5012_enable-cpu-optimizations-for-gcc91.patch |
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+From: https://github.com/graysky2/kernel_gcc_patch/ |
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+Desc: Kernel patch enables gcc >= v9.1 >= gcc < v10 optimizations for additional CPUs. |
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+ |
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Patch: 5013_enable-cpu-optimizations-for-gcc10.patch |
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From: https://github.com/graysky2/kernel_gcc_patch/ |
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Desc: Kernel patch enables gcc = v10.1+ optimizations for additional CPUs. |
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|
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diff --git a/5012_enable-cpu-optimizations-for-gcc91.patch b/5012_enable-cpu-optimizations-for-gcc91.patch |
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new file mode 100644 |
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index 0000000..564eede |
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--- /dev/null |
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+++ b/5012_enable-cpu-optimizations-for-gcc91.patch |
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@@ -0,0 +1,641 @@ |
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+WARNING |
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+This patch works with gcc versions 9.1+ and with kernel version 5.8+ and should |
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+NOT be applied when compiling on older versions of gcc due to key name changes |
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+of the march flags introduced with the version 4.9 release of gcc.[1] |
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+ |
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+Use the older version of this patch hosted on the same github for older |
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+versions of gcc. |
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+ |
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+FEATURES |
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+This patch adds additional CPU options to the Linux kernel accessible under: |
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+ Processor type and features ---> |
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+ Processor family ---> |
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+ |
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+The expanded microarchitectures include: |
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+* AMD Improved K8-family |
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+* AMD K10-family |
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+* AMD Family 10h (Barcelona) |
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+* AMD Family 14h (Bobcat) |
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+* AMD Family 16h (Jaguar) |
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+* AMD Family 15h (Bulldozer) |
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+* AMD Family 15h (Piledriver) |
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+* AMD Family 15h (Steamroller) |
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+* AMD Family 15h (Excavator) |
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+* AMD Family 17h (Zen) |
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+* AMD Family 17h (Zen 2) |
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+* Intel Silvermont low-power processors |
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+* Intel Goldmont low-power processors (Apollo Lake and Denverton) |
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+* Intel Goldmont Plus low-power processors (Gemini Lake) |
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+* Intel 1st Gen Core i3/i5/i7 (Nehalem) |
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+* Intel 1.5 Gen Core i3/i5/i7 (Westmere) |
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+* Intel 2nd Gen Core i3/i5/i7 (Sandybridge) |
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+* Intel 3rd Gen Core i3/i5/i7 (Ivybridge) |
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+* Intel 4th Gen Core i3/i5/i7 (Haswell) |
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+* Intel 5th Gen Core i3/i5/i7 (Broadwell) |
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+* Intel 6th Gen Core i3/i5/i7 (Skylake) |
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+* Intel 6th Gen Core i7/i9 (Skylake X) |
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+* Intel 8th Gen Core i3/i5/i7 (Cannon Lake) |
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+* Intel 10th Gen Core i7/i9 (Ice Lake) |
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+* Intel Xeon (Cascade Lake) |
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+ |
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+It also offers to compile passing the 'native' option which, "selects the CPU |
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+to generate code for at compilation time by determining the processor type of |
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+the compiling machine. Using -march=native enables all instruction subsets |
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+supported by the local machine and will produce code optimized for the local |
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+machine under the constraints of the selected instruction set."[2] |
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+ |
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+Do NOT try using the 'native' option on AMD Piledriver, Steamroller, or |
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+Excavator CPUs (-march=bdver{2,3,4} flag). The build will error out due the |
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+kernel's objtool issue with these.[3a,b] |
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+ |
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+MINOR NOTES |
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+This patch also changes 'atom' to 'bonnell' in accordance with the gcc v4.9 |
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+changes. Note that upstream is using the deprecated 'match=atom' flags when I |
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+believe it should use the newer 'march=bonnell' flag for atom processors.[4] |
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+ |
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+It is not recommended to compile on Atom-CPUs with the 'native' option.[5] The |
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+recommendation is to use the 'atom' option instead. |
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+ |
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+BENEFITS |
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+Small but real speed increases are measurable using a make endpoint comparing |
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+a generic kernel to one built with one of the respective microarchs. |
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+ |
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+See the following experimental evidence supporting this statement: |
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+https://github.com/graysky2/kernel_gcc_patch |
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+ |
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+REQUIREMENTS |
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+linux version >=5.8 |
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+gcc version >=9.1 and <10 |
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+ |
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+ACKNOWLEDGMENTS |
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+This patch builds on the seminal work by Jeroen.[6] |
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+ |
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+REFERENCES |
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+1. https://gcc.gnu.org/gcc-4.9/changes.html |
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+2. https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html |
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+3a. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95671#c11 |
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+3b. https://github.com/graysky2/kernel_gcc_patch/issues/55 |
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+4. https://bugzilla.kernel.org/show_bug.cgi?id=77461 |
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+5. https://github.com/graysky2/kernel_gcc_patch/issues/15 |
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+6. http://www.linuxforge.net/docs/linux/linux-gcc.php |
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+ |
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+--- a/arch/x86/include/asm/vermagic.h 2020-06-10 14:21:45.000000000 -0400 |
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++++ b/arch/x86/include/asm/vermagic.h 2020-06-15 10:44:10.437477053 -0400 |
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+@@ -17,6 +17,36 @@ |
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+ #define MODULE_PROC_FAMILY "586MMX " |
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+ #elif defined CONFIG_MCORE2 |
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+ #define MODULE_PROC_FAMILY "CORE2 " |
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++#elif defined CONFIG_MNATIVE |
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++#define MODULE_PROC_FAMILY "NATIVE " |
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++#elif defined CONFIG_MNEHALEM |
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++#define MODULE_PROC_FAMILY "NEHALEM " |
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++#elif defined CONFIG_MWESTMERE |
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++#define MODULE_PROC_FAMILY "WESTMERE " |
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++#elif defined CONFIG_MSILVERMONT |
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++#define MODULE_PROC_FAMILY "SILVERMONT " |
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++#elif defined CONFIG_MGOLDMONT |
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++#define MODULE_PROC_FAMILY "GOLDMONT " |
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++#elif defined CONFIG_MGOLDMONTPLUS |
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++#define MODULE_PROC_FAMILY "GOLDMONTPLUS " |
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++#elif defined CONFIG_MSANDYBRIDGE |
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++#define MODULE_PROC_FAMILY "SANDYBRIDGE " |
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++#elif defined CONFIG_MIVYBRIDGE |
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++#define MODULE_PROC_FAMILY "IVYBRIDGE " |
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++#elif defined CONFIG_MHASWELL |
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++#define MODULE_PROC_FAMILY "HASWELL " |
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++#elif defined CONFIG_MBROADWELL |
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++#define MODULE_PROC_FAMILY "BROADWELL " |
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++#elif defined CONFIG_MSKYLAKE |
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++#define MODULE_PROC_FAMILY "SKYLAKE " |
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++#elif defined CONFIG_MSKYLAKEX |
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++#define MODULE_PROC_FAMILY "SKYLAKEX " |
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++#elif defined CONFIG_MCANNONLAKE |
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++#define MODULE_PROC_FAMILY "CANNONLAKE " |
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++#elif defined CONFIG_MICELAKE |
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++#define MODULE_PROC_FAMILY "ICELAKE " |
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++#elif defined CONFIG_MCASCADELAKE |
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++#define MODULE_PROC_FAMILY "CASCADELAKE " |
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+ #elif defined CONFIG_MATOM |
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+ #define MODULE_PROC_FAMILY "ATOM " |
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+ #elif defined CONFIG_M686 |
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+@@ -35,6 +65,28 @@ |
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+ #define MODULE_PROC_FAMILY "K7 " |
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+ #elif defined CONFIG_MK8 |
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+ #define MODULE_PROC_FAMILY "K8 " |
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++#elif defined CONFIG_MK8SSE3 |
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++#define MODULE_PROC_FAMILY "K8SSE3 " |
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++#elif defined CONFIG_MK10 |
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++#define MODULE_PROC_FAMILY "K10 " |
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++#elif defined CONFIG_MBARCELONA |
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++#define MODULE_PROC_FAMILY "BARCELONA " |
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++#elif defined CONFIG_MBOBCAT |
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++#define MODULE_PROC_FAMILY "BOBCAT " |
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++#elif defined CONFIG_MBULLDOZER |
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++#define MODULE_PROC_FAMILY "BULLDOZER " |
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++#elif defined CONFIG_MPILEDRIVER |
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++#define MODULE_PROC_FAMILY "PILEDRIVER " |
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++#elif defined CONFIG_MSTEAMROLLER |
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++#define MODULE_PROC_FAMILY "STEAMROLLER " |
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++#elif defined CONFIG_MJAGUAR |
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++#define MODULE_PROC_FAMILY "JAGUAR " |
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++#elif defined CONFIG_MEXCAVATOR |
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++#define MODULE_PROC_FAMILY "EXCAVATOR " |
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++#elif defined CONFIG_MZEN |
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++#define MODULE_PROC_FAMILY "ZEN " |
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++#elif defined CONFIG_MZEN2 |
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++#define MODULE_PROC_FAMILY "ZEN2 " |
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+ #elif defined CONFIG_MELAN |
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+ #define MODULE_PROC_FAMILY "ELAN " |
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+ #elif defined CONFIG_MCRUSOE |
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+--- a/arch/x86/Kconfig.cpu 2020-06-10 14:21:45.000000000 -0400 |
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++++ b/arch/x86/Kconfig.cpu 2020-06-15 10:44:10.437477053 -0400 |
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+@@ -123,6 +123,7 @@ config MPENTIUMM |
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+ config MPENTIUM4 |
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+ bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon" |
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+ depends on X86_32 |
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++ select X86_P6_NOP |
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+ help |
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+ Select this for Intel Pentium 4 chips. This includes the |
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+ Pentium 4, Pentium D, P4-based Celeron and Xeon, and |
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+@@ -155,9 +156,8 @@ config MPENTIUM4 |
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+ -Paxville |
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+ -Dempsey |
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+ |
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+- |
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+ config MK6 |
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+- bool "K6/K6-II/K6-III" |
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++ bool "AMD K6/K6-II/K6-III" |
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+ depends on X86_32 |
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+ help |
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+ Select this for an AMD K6-family processor. Enables use of |
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+@@ -165,7 +165,7 @@ config MK6 |
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+ flags to GCC. |
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+ |
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+ config MK7 |
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+- bool "Athlon/Duron/K7" |
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++ bool "AMD Athlon/Duron/K7" |
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+ depends on X86_32 |
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+ help |
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+ Select this for an AMD Athlon K7-family processor. Enables use of |
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+@@ -173,12 +173,90 @@ config MK7 |
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+ flags to GCC. |
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+ |
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+ config MK8 |
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+- bool "Opteron/Athlon64/Hammer/K8" |
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++ bool "AMD Opteron/Athlon64/Hammer/K8" |
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+ help |
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+ Select this for an AMD Opteron or Athlon64 Hammer-family processor. |
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+ Enables use of some extended instructions, and passes appropriate |
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+ optimization flags to GCC. |
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+ |
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++config MK8SSE3 |
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++ bool "AMD Opteron/Athlon64/Hammer/K8 with SSE3" |
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++ help |
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++ Select this for improved AMD Opteron or Athlon64 Hammer-family processors. |
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++ Enables use of some extended instructions, and passes appropriate |
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++ optimization flags to GCC. |
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++ |
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++config MK10 |
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++ bool "AMD 61xx/7x50/PhenomX3/X4/II/K10" |
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++ help |
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++ Select this for an AMD 61xx Eight-Core Magny-Cours, Athlon X2 7x50, |
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++ Phenom X3/X4/II, Athlon II X2/X3/X4, or Turion II-family processor. |
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++ Enables use of some extended instructions, and passes appropriate |
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++ optimization flags to GCC. |
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++ |
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++config MBARCELONA |
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++ bool "AMD Barcelona" |
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++ help |
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++ Select this for AMD Family 10h Barcelona processors. |
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++ |
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++ Enables -march=barcelona |
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++ |
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++config MBOBCAT |
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++ bool "AMD Bobcat" |
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++ help |
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++ Select this for AMD Family 14h Bobcat processors. |
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++ |
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++ Enables -march=btver1 |
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++ |
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++config MJAGUAR |
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++ bool "AMD Jaguar" |
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++ help |
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++ Select this for AMD Family 16h Jaguar processors. |
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++ |
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++ Enables -march=btver2 |
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++ |
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++config MBULLDOZER |
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++ bool "AMD Bulldozer" |
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++ help |
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++ Select this for AMD Family 15h Bulldozer processors. |
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++ |
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++ Enables -march=bdver1 |
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++ |
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++config MPILEDRIVER |
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++ bool "AMD Piledriver" |
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++ help |
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++ Select this for AMD Family 15h Piledriver processors. |
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++ |
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++ Enables -march=bdver2 |
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++ |
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++config MSTEAMROLLER |
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++ bool "AMD Steamroller" |
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++ help |
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++ Select this for AMD Family 15h Steamroller processors. |
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++ |
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++ Enables -march=bdver3 |
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++ |
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++config MEXCAVATOR |
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++ bool "AMD Excavator" |
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++ help |
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++ Select this for AMD Family 15h Excavator processors. |
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++ |
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++ Enables -march=bdver4 |
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++ |
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++config MZEN |
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++ bool "AMD Zen" |
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++ help |
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++ Select this for AMD Family 17h Zen processors. |
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++ |
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++ Enables -march=znver1 |
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++ |
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++config MZEN2 |
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++ bool "AMD Zen 2" |
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++ help |
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++ Select this for AMD Family 17h Zen 2 processors. |
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++ |
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++ Enables -march=znver2 |
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++ |
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+ config MCRUSOE |
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+ bool "Crusoe" |
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+ depends on X86_32 |
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+@@ -260,6 +338,7 @@ config MVIAC7 |
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+ |
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+ config MPSC |
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+ bool "Intel P4 / older Netburst based Xeon" |
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++ select X86_P6_NOP |
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+ depends on X86_64 |
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+ help |
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+ Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey |
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+@@ -269,8 +348,19 @@ config MPSC |
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+ using the cpu family field |
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+ in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one. |
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+ |
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++config MATOM |
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++ bool "Intel Atom" |
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++ select X86_P6_NOP |
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++ help |
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++ |
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++ Select this for the Intel Atom platform. Intel Atom CPUs have an |
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++ in-order pipelining architecture and thus can benefit from |
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++ accordingly optimized code. Use a recent GCC with specific Atom |
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++ support in order to fully benefit from selecting this option. |
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++ |
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+ config MCORE2 |
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+- bool "Core 2/newer Xeon" |
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++ bool "Intel Core 2" |
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++ select X86_P6_NOP |
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+ help |
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+ |
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+ Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and |
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+@@ -278,14 +368,133 @@ config MCORE2 |
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+ family in /proc/cpuinfo. Newer ones have 6 and older ones 15 |
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+ (not a typo) |
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+ |
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+-config MATOM |
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+- bool "Intel Atom" |
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++ Enables -march=core2 |
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++ |
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++config MNEHALEM |
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++ bool "Intel Nehalem" |
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++ select X86_P6_NOP |
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+ help |
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+ |
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+- Select this for the Intel Atom platform. Intel Atom CPUs have an |
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+- in-order pipelining architecture and thus can benefit from |
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+- accordingly optimized code. Use a recent GCC with specific Atom |
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+- support in order to fully benefit from selecting this option. |
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++ Select this for 1st Gen Core processors in the Nehalem family. |
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++ |
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++ Enables -march=nehalem |
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++ |
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++config MWESTMERE |
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++ bool "Intel Westmere" |
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++ select X86_P6_NOP |
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++ help |
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++ |
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++ Select this for the Intel Westmere formerly Nehalem-C family. |
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++ |
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++ Enables -march=westmere |
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++ |
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++config MSILVERMONT |
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++ bool "Intel Silvermont" |
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++ select X86_P6_NOP |
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++ help |
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++ |
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++ Select this for the Intel Silvermont platform. |
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++ |
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++ Enables -march=silvermont |
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++ |
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++config MGOLDMONT |
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++ bool "Intel Goldmont" |
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++ select X86_P6_NOP |
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++ help |
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++ |
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++ Select this for the Intel Goldmont platform including Apollo Lake and Denverton. |
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++ |
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++ Enables -march=goldmont |
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++ |
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++config MGOLDMONTPLUS |
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++ bool "Intel Goldmont Plus" |
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++ select X86_P6_NOP |
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++ help |
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++ |
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++ Select this for the Intel Goldmont Plus platform including Gemini Lake. |
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++ |
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++ Enables -march=goldmont-plus |
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++ |
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++config MSANDYBRIDGE |
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++ bool "Intel Sandy Bridge" |
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++ select X86_P6_NOP |
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++ help |
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++ |
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++ Select this for 2nd Gen Core processors in the Sandy Bridge family. |
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++ |
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++ Enables -march=sandybridge |
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++ |
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++config MIVYBRIDGE |
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++ bool "Intel Ivy Bridge" |
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++ select X86_P6_NOP |
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++ help |
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++ |
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++ Select this for 3rd Gen Core processors in the Ivy Bridge family. |
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++ |
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++ Enables -march=ivybridge |
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++ |
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++config MHASWELL |
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++ bool "Intel Haswell" |
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++ select X86_P6_NOP |
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++ help |
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++ |
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++ Select this for 4th Gen Core processors in the Haswell family. |
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++ |
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++ Enables -march=haswell |
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++ |
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++config MBROADWELL |
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++ bool "Intel Broadwell" |
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++ select X86_P6_NOP |
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++ help |
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++ |
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++ Select this for 5th Gen Core processors in the Broadwell family. |
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++ |
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++ Enables -march=broadwell |
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++ |
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++config MSKYLAKE |
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++ bool "Intel Skylake" |
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++ select X86_P6_NOP |
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++ help |
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++ |
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++ Select this for 6th Gen Core processors in the Skylake family. |
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++ |
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++ Enables -march=skylake |
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++ |
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++config MSKYLAKEX |
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++ bool "Intel Skylake X" |
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++ select X86_P6_NOP |
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++ help |
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++ |
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++ Select this for 6th Gen Core processors in the Skylake X family. |
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++ |
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++ Enables -march=skylake-avx512 |
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++ |
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++config MCANNONLAKE |
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++ bool "Intel Cannon Lake" |
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++ select X86_P6_NOP |
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++ help |
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++ |
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++ Select this for 8th Gen Core processors |
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++ |
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++ Enables -march=cannonlake |
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++ |
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++config MICELAKE |
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++ bool "Intel Ice Lake" |
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++ select X86_P6_NOP |
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++ help |
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++ |
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++ Select this for 10th Gen Core processors in the Ice Lake family. |
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++ |
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++ Enables -march=icelake-client |
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++ |
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++config MCASCADELAKE |
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++ bool "Intel Cascade Lake" |
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++ select X86_P6_NOP |
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++ help |
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++ |
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++ Select this for Xeon processors in the Cascade Lake family. |
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++ |
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++ Enables -march=cascadelake |
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+ |
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+ config GENERIC_CPU |
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+ bool "Generic-x86-64" |
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+@@ -294,6 +503,19 @@ config GENERIC_CPU |
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+ Generic x86-64 CPU. |
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+ Run equally well on all x86-64 CPUs. |
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+ |
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++config MNATIVE |
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++ bool "Native optimizations autodetected by GCC" |
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++ help |
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++ |
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++ GCC 4.2 and above support -march=native, which automatically detects |
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++ the optimum settings to use based on your processor. -march=native |
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++ also detects and applies additional settings beyond -march specific |
492 |
++ to your CPU, (eg. -msse4). Unless you have a specific reason not to |
493 |
++ (e.g. distcc cross-compiling), you should probably be using |
494 |
++ -march=native rather than anything listed below. |
495 |
++ |
496 |
++ Enables -march=native |
497 |
++ |
498 |
+ endchoice |
499 |
+ |
500 |
+ config X86_GENERIC |
501 |
+@@ -318,7 +540,7 @@ config X86_INTERNODE_CACHE_SHIFT |
502 |
+ config X86_L1_CACHE_SHIFT |
503 |
+ int |
504 |
+ default "7" if MPENTIUM4 || MPSC |
505 |
+- default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU |
506 |
++ default "6" if MK7 || MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MJAGUAR || MPENTIUMM || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MNATIVE || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU |
507 |
+ default "4" if MELAN || M486SX || M486 || MGEODEGX1 |
508 |
+ default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX |
509 |
+ |
510 |
+@@ -336,35 +558,36 @@ config X86_ALIGNMENT_16 |
511 |
+ |
512 |
+ config X86_INTEL_USERCOPY |
513 |
+ def_bool y |
514 |
+- depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 |
515 |
++ depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK8SSE3 || MK7 || MEFFICEON || MCORE2 || MK10 || MBARCELONA || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MNATIVE |
516 |
+ |
517 |
+ config X86_USE_PPRO_CHECKSUM |
518 |
+ def_bool y |
519 |
+- depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM |
520 |
++ depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MK10 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MATOM || MNATIVE |
521 |
+ |
522 |
+ config X86_USE_3DNOW |
523 |
+ def_bool y |
524 |
+ depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML |
525 |
+ |
526 |
+-# |
527 |
+-# P6_NOPs are a relatively minor optimization that require a family >= |
528 |
+-# 6 processor, except that it is broken on certain VIA chips. |
529 |
+-# Furthermore, AMD chips prefer a totally different sequence of NOPs |
530 |
+-# (which work on all CPUs). In addition, it looks like Virtual PC |
531 |
+-# does not understand them. |
532 |
+-# |
533 |
+-# As a result, disallow these if we're not compiling for X86_64 (these |
534 |
+-# NOPs do work on all x86-64 capable chips); the list of processors in |
535 |
+-# the right-hand clause are the cores that benefit from this optimization. |
536 |
+-# |
537 |
+ config X86_P6_NOP |
538 |
+- def_bool y |
539 |
+- depends on X86_64 |
540 |
+- depends on (MCORE2 || MPENTIUM4 || MPSC) |
541 |
++ default n |
542 |
++ bool "Support for P6_NOPs on Intel chips" |
543 |
++ depends on (MCORE2 || MPENTIUM4 || MPSC || MATOM || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MNATIVE) |
544 |
++ help |
545 |
++ P6_NOPs are a relatively minor optimization that require a family >= |
546 |
++ 6 processor, except that it is broken on certain VIA chips. |
547 |
++ Furthermore, AMD chips prefer a totally different sequence of NOPs |
548 |
++ (which work on all CPUs). In addition, it looks like Virtual PC |
549 |
++ does not understand them. |
550 |
++ |
551 |
++ As a result, disallow these if we're not compiling for X86_64 (these |
552 |
++ NOPs do work on all x86-64 capable chips); the list of processors in |
553 |
++ the right-hand clause are the cores that benefit from this optimization. |
554 |
++ |
555 |
++ Say Y if you have Intel CPU newer than Pentium Pro, N otherwise. |
556 |
+ |
557 |
+ config X86_TSC |
558 |
+ def_bool y |
559 |
+- depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64 |
560 |
++ depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MNATIVE || MATOM) || X86_64 |
561 |
+ |
562 |
+ config X86_CMPXCHG64 |
563 |
+ def_bool y |
564 |
+@@ -374,7 +597,7 @@ config X86_CMPXCHG64 |
565 |
+ # generates cmov. |
566 |
+ config X86_CMOV |
567 |
+ def_bool y |
568 |
+- depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX) |
569 |
++ depends on (MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MJAGUAR || MK7 || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MNATIVE || MATOM || MGEODE_LX) |
570 |
+ |
571 |
+ config X86_MINIMUM_CPU_FAMILY |
572 |
+ int |
573 |
+--- a/arch/x86/Makefile 2020-06-10 14:21:45.000000000 -0400 |
574 |
++++ b/arch/x86/Makefile 2020-06-15 10:44:35.608035680 -0400 |
575 |
+@@ -119,13 +119,56 @@ else |
576 |
+ KBUILD_CFLAGS += $(call cc-option,-mskip-rax-setup) |
577 |
+ |
578 |
+ # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu) |
579 |
++ cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native) |
580 |
+ cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8) |
581 |
++ cflags-$(CONFIG_MK8SSE3) += $(call cc-option,-march=k8-sse3,-mtune=k8) |
582 |
++ cflags-$(CONFIG_MK10) += $(call cc-option,-march=amdfam10) |
583 |
++ cflags-$(CONFIG_MBARCELONA) += $(call cc-option,-march=barcelona) |
584 |
++ cflags-$(CONFIG_MBOBCAT) += $(call cc-option,-march=btver1) |
585 |
++ cflags-$(CONFIG_MJAGUAR) += $(call cc-option,-march=btver2) |
586 |
++ cflags-$(CONFIG_MBULLDOZER) += $(call cc-option,-march=bdver1) |
587 |
++ cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-march=bdver2) |
588 |
++ cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-mno-tbm) |
589 |
++ cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-march=bdver3) |
590 |
++ cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-mno-tbm) |
591 |
++ cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4) |
592 |
++ cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-mno-tbm) |
593 |
++ cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1) |
594 |
++ cflags-$(CONFIG_MZEN2) += $(call cc-option,-march=znver2) |
595 |
+ cflags-$(CONFIG_MPSC) += $(call cc-option,-march=nocona) |
596 |
+ |
597 |
+ cflags-$(CONFIG_MCORE2) += \ |
598 |
+- $(call cc-option,-march=core2,$(call cc-option,-mtune=generic)) |
599 |
+- cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom) \ |
600 |
+- $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic)) |
601 |
++ $(call cc-option,-march=core2,$(call cc-option,-mtune=core2)) |
602 |
++ cflags-$(CONFIG_MNEHALEM) += \ |
603 |
++ $(call cc-option,-march=nehalem,$(call cc-option,-mtune=nehalem)) |
604 |
++ cflags-$(CONFIG_MWESTMERE) += \ |
605 |
++ $(call cc-option,-march=westmere,$(call cc-option,-mtune=westmere)) |
606 |
++ cflags-$(CONFIG_MSILVERMONT) += \ |
607 |
++ $(call cc-option,-march=silvermont,$(call cc-option,-mtune=silvermont)) |
608 |
++ cflags-$(CONFIG_MGOLDMONT) += \ |
609 |
++ $(call cc-option,-march=goldmont,$(call cc-option,-mtune=goldmont)) |
610 |
++ cflags-$(CONFIG_MGOLDMONTPLUS) += \ |
611 |
++ $(call cc-option,-march=goldmont-plus,$(call cc-option,-mtune=goldmont-plus)) |
612 |
++ cflags-$(CONFIG_MSANDYBRIDGE) += \ |
613 |
++ $(call cc-option,-march=sandybridge,$(call cc-option,-mtune=sandybridge)) |
614 |
++ cflags-$(CONFIG_MIVYBRIDGE) += \ |
615 |
++ $(call cc-option,-march=ivybridge,$(call cc-option,-mtune=ivybridge)) |
616 |
++ cflags-$(CONFIG_MHASWELL) += \ |
617 |
++ $(call cc-option,-march=haswell,$(call cc-option,-mtune=haswell)) |
618 |
++ cflags-$(CONFIG_MBROADWELL) += \ |
619 |
++ $(call cc-option,-march=broadwell,$(call cc-option,-mtune=broadwell)) |
620 |
++ cflags-$(CONFIG_MSKYLAKE) += \ |
621 |
++ $(call cc-option,-march=skylake,$(call cc-option,-mtune=skylake)) |
622 |
++ cflags-$(CONFIG_MSKYLAKEX) += \ |
623 |
++ $(call cc-option,-march=skylake-avx512,$(call cc-option,-mtune=skylake-avx512)) |
624 |
++ cflags-$(CONFIG_MCANNONLAKE) += \ |
625 |
++ $(call cc-option,-march=cannonlake,$(call cc-option,-mtune=cannonlake)) |
626 |
++ cflags-$(CONFIG_MICELAKE) += \ |
627 |
++ $(call cc-option,-march=icelake-client,$(call cc-option,-mtune=icelake-client)) |
628 |
++ cflags-$(CONFIG_MCASCADELAKE) += \ |
629 |
++ $(call cc-option,-march=cascadelake,$(call cc-option,-mtune=cascadelake)) |
630 |
++ cflags-$(CONFIG_MATOM) += $(call cc-option,-march=bonnell) \ |
631 |
++ $(call cc-option,-mtune=bonnell,$(call cc-option,-mtune=generic)) |
632 |
+ cflags-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=generic) |
633 |
+ KBUILD_CFLAGS += $(cflags-y) |
634 |
+ |
635 |
+--- a/arch/x86/Makefile_32.cpu 2020-06-10 14:21:45.000000000 -0400 |
636 |
++++ b/arch/x86/Makefile_32.cpu 2020-06-15 10:44:10.437477053 -0400 |
637 |
+@@ -24,7 +24,19 @@ cflags-$(CONFIG_MK6) += -march=k6 |
638 |
+ # Please note, that patches that add -march=athlon-xp and friends are pointless. |
639 |
+ # They make zero difference whatsosever to performance at this time. |
640 |
+ cflags-$(CONFIG_MK7) += -march=athlon |
641 |
++cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native) |
642 |
+ cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8,-march=athlon) |
643 |
++cflags-$(CONFIG_MK8SSE3) += $(call cc-option,-march=k8-sse3,-march=athlon) |
644 |
++cflags-$(CONFIG_MK10) += $(call cc-option,-march=amdfam10,-march=athlon) |
645 |
++cflags-$(CONFIG_MBARCELONA) += $(call cc-option,-march=barcelona,-march=athlon) |
646 |
++cflags-$(CONFIG_MBOBCAT) += $(call cc-option,-march=btver1,-march=athlon) |
647 |
++cflags-$(CONFIG_MJAGUAR) += $(call cc-option,-march=btver2,-march=athlon) |
648 |
++cflags-$(CONFIG_MBULLDOZER) += $(call cc-option,-march=bdver1,-march=athlon) |
649 |
++cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-march=bdver2,-march=athlon) |
650 |
++cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-march=bdver3,-march=athlon) |
651 |
++cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4,-march=athlon) |
652 |
++cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1,-march=athlon) |
653 |
++cflags-$(CONFIG_MZEN2) += $(call cc-option,-march=znver2,-march=athlon) |
654 |
+ cflags-$(CONFIG_MCRUSOE) += -march=i686 -falign-functions=0 -falign-jumps=0 -falign-loops=0 |
655 |
+ cflags-$(CONFIG_MEFFICEON) += -march=i686 $(call tune,pentium3) -falign-functions=0 -falign-jumps=0 -falign-loops=0 |
656 |
+ cflags-$(CONFIG_MWINCHIPC6) += $(call cc-option,-march=winchip-c6,-march=i586) |
657 |
+@@ -33,8 +45,22 @@ cflags-$(CONFIG_MCYRIXIII) += $(call cc- |
658 |
+ cflags-$(CONFIG_MVIAC3_2) += $(call cc-option,-march=c3-2,-march=i686) |
659 |
+ cflags-$(CONFIG_MVIAC7) += -march=i686 |
660 |
+ cflags-$(CONFIG_MCORE2) += -march=i686 $(call tune,core2) |
661 |
+-cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom,$(call cc-option,-march=core2,-march=i686)) \ |
662 |
+- $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic)) |
663 |
++cflags-$(CONFIG_MNEHALEM) += -march=i686 $(call tune,nehalem) |
664 |
++cflags-$(CONFIG_MWESTMERE) += -march=i686 $(call tune,westmere) |
665 |
++cflags-$(CONFIG_MSILVERMONT) += -march=i686 $(call tune,silvermont) |
666 |
++cflags-$(CONFIG_MGOLDMONT) += -march=i686 $(call tune,goldmont) |
667 |
++cflags-$(CONFIG_MGOLDMONTPLUS) += -march=i686 $(call tune,goldmont-plus) |
668 |
++cflags-$(CONFIG_MSANDYBRIDGE) += -march=i686 $(call tune,sandybridge) |
669 |
++cflags-$(CONFIG_MIVYBRIDGE) += -march=i686 $(call tune,ivybridge) |
670 |
++cflags-$(CONFIG_MHASWELL) += -march=i686 $(call tune,haswell) |
671 |
++cflags-$(CONFIG_MBROADWELL) += -march=i686 $(call tune,broadwell) |
672 |
++cflags-$(CONFIG_MSKYLAKE) += -march=i686 $(call tune,skylake) |
673 |
++cflags-$(CONFIG_MSKYLAKEX) += -march=i686 $(call tune,skylake-avx512) |
674 |
++cflags-$(CONFIG_MCANNONLAKE) += -march=i686 $(call tune,cannonlake) |
675 |
++cflags-$(CONFIG_MICELAKE) += -march=i686 $(call tune,icelake-client) |
676 |
++cflags-$(CONFIG_MCASCADELAKE) += -march=i686 $(call tune,cascadelake) |
677 |
++cflags-$(CONFIG_MATOM) += $(call cc-option,-march=bonnell,$(call cc-option,-march=core2,-march=i686)) \ |
678 |
++ $(call cc-option,-mtune=bonnell,$(call cc-option,-mtune=generic)) |
679 |
+ |
680 |
+ # AMD Elan support |
681 |
+ cflags-$(CONFIG_MELAN) += -march=i486 |