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commit: f2f997ab5fd674039bdfa83e02eaaaceaf1de1b1 |
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Author: Alice Ferrazzi <alicef <AT> gentoo <DOT> org> |
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AuthorDate: Thu Jan 4 07:21:56 2018 +0000 |
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Commit: Alice Ferrazzi <alicef <AT> gentoo <DOT> org> |
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CommitDate: Thu Jan 4 07:21:56 2018 +0000 |
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URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=f2f997ab |
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|
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x86/pti: Make sure the user/kernel PTEs match |
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|
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0000_README | 4 ++ |
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1701_make_sure_the_user_kernel_PTEs_match.patch | 56 +++++++++++++++++++++++++ |
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2 files changed, 60 insertions(+) |
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|
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diff --git a/0000_README b/0000_README |
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index 946c936..0cab5bc 100644 |
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--- a/0000_README |
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+++ b/0000_README |
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@@ -99,6 +99,10 @@ Patch: 1700_do_not_enable_PTI_on_AMD_processor.patch |
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From: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/patch/?id=694d99d40972f12e59a3696effee8a376b79d7c8 |
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Desc: x86/cpu, x86/pti: Do not enable PTI on AMD processors. |
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|
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+Patch: 1701_make_sure_the_user_kernel_PTEs_match.patch |
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+From: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/patch/?id=52994c256df36fda9a715697431cba9daecb6b11 |
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+Desc: x86/pti: Make sure the user/kernel PTEs match |
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+ |
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Patch: 2100_bcache-data-corruption-fix-for-bi-partno.patch |
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From: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=62530ed8b1d07a45dec94d46e521c0c6c2d476e6 |
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Desc: bio: ensure __bio_clone_fast copies bi_partno. |
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|
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diff --git a/1701_make_sure_the_user_kernel_PTEs_match.patch b/1701_make_sure_the_user_kernel_PTEs_match.patch |
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new file mode 100644 |
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index 0000000..601940b |
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--- /dev/null |
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+++ b/1701_make_sure_the_user_kernel_PTEs_match.patch |
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@@ -0,0 +1,56 @@ |
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+From 52994c256df36fda9a715697431cba9daecb6b11 Mon Sep 17 00:00:00 2001 |
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+From: Thomas Gleixner <tglx@××××××××××.de> |
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+Date: Wed, 3 Jan 2018 15:57:59 +0100 |
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+Subject: x86/pti: Make sure the user/kernel PTEs match |
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+ |
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+Meelis reported that his K8 Athlon64 emits MCE warnings when PTI is |
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+enabled: |
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+ |
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+[Hardware Error]: Error Addr: 0x0000ffff81e000e0 |
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+[Hardware Error]: MC1 Error: L1 TLB multimatch. |
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+[Hardware Error]: cache level: L1, tx: INSN |
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+ |
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+The address is in the entry area, which is mapped into kernel _AND_ user |
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+space. That's special because we switch CR3 while we are executing |
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+there. |
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+ |
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+User mapping: |
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+0xffffffff81e00000-0xffffffff82000000 2M ro PSE GLB x pmd |
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+ |
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+Kernel mapping: |
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+0xffffffff81000000-0xffffffff82000000 16M ro PSE x pmd |
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+ |
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+So the K8 is complaining that the TLB entries differ. They differ in the |
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+GLB bit. |
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+ |
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+Drop the GLB bit when installing the user shared mapping. |
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+ |
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+Fixes: 6dc72c3cbca0 ("x86/mm/pti: Share entry text PMD") |
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+Reported-by: Meelis Roos <mroos@×××××.ee> |
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+Signed-off-by: Thomas Gleixner <tglx@××××××××××.de> |
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+Tested-by: Meelis Roos <mroos@×××××.ee> |
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+Cc: Borislav Petkov <bp@××××××.de> |
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+Cc: Tom Lendacky <thomas.lendacky@×××.com> |
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+Cc: stable@×××××××××××.org |
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+Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1801031407180.1957@nanos |
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+--- |
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+ arch/x86/mm/pti.c | 3 ++- |
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+ 1 file changed, 2 insertions(+), 1 deletion(-) |
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+ |
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+diff --git a/arch/x86/mm/pti.c b/arch/x86/mm/pti.c |
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+index bce8aea..2da28ba 100644 |
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+--- a/arch/x86/mm/pti.c |
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++++ b/arch/x86/mm/pti.c |
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+@@ -367,7 +367,8 @@ static void __init pti_setup_espfix64(void) |
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+ static void __init pti_clone_entry_text(void) |
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+ { |
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+ pti_clone_pmds((unsigned long) __entry_text_start, |
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+- (unsigned long) __irqentry_text_end, _PAGE_RW); |
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++ (unsigned long) __irqentry_text_end, |
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++ _PAGE_RW | _PAGE_GLOBAL); |
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+ } |
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+ |
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+ /* |
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+-- |
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+cgit v1.1 |
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+ |