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commit: 2eb05a67750fe9fc4c720fc5176aa4177c2f4db3 |
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Author: Mike Pagano <mpagano <AT> gentoo <DOT> org> |
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AuthorDate: Mon Dec 30 23:47:43 2019 +0000 |
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Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org> |
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CommitDate: Mon Dec 30 23:47:43 2019 +0000 |
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URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=2eb05a67 |
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|
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Add patchesi for the 5.5 branch. Details below. |
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|
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Support for namespace user.pax.* on tmpfs. |
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Enable link security restrictions by default. |
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Bluetooth: Check key sizes only when Secure Simple Pairing is |
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enabled. See bug #686758.This hid-apple patch enables swapping |
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of the FN and left Control keys and some additional on some |
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apple keyboards. See bug #622902.Add Gentoo Linux support |
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config settings and defaults. Kernel patch for >= gccv8 enables |
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kernel >= v4.13 optimizations for additional CPUs. |
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Kernel patch enables gcc >= v9.1 optimizations for additional CPUs. |
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|
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Signed-off-by: Mike Pagano <mpagano <AT> gentoo.org> |
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|
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0000_README | 24 + |
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1500_XATTR_USER_PREFIX.patch | 69 +++ |
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...ble-link-security-restrictions-by-default.patch | 20 + |
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...zes-only-if-Secure-Simple-Pairing-enabled.patch | 37 ++ |
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2600_enable-key-swapping-for-apple-mac.patch | 114 ++++ |
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5011_enable-cpu-optimizations-for-gcc8.patch | 569 +++++++++++++++++++ |
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5012_enable-cpu-optimizations-for-gcc91.patch | 632 +++++++++++++++++++++ |
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7 files changed, 1465 insertions(+) |
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|
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diff --git a/0000_README b/0000_README |
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index 9018993..2f0a93e 100644 |
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--- a/0000_README |
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+++ b/0000_README |
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@@ -43,6 +43,30 @@ EXPERIMENTAL |
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Individual Patch Descriptions: |
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-------------------------------------------------------------------------- |
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|
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+Patch: 1500_XATTR_USER_PREFIX.patch |
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+From: https://bugs.gentoo.org/show_bug.cgi?id=470644 |
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+Desc: Support for namespace user.pax.* on tmpfs. |
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+ |
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+Patch: 1510_fs-enable-link-security-restrictions-by-default.patch |
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+From: http://sources.debian.net/src/linux/3.16.7-ckt4-3/debian/patches/debian/fs-enable-link-security-restrictions-by-default.patch/ |
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+Desc: Enable link security restrictions by default. |
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+ |
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+Patch: 2000_BT-Check-key-sizes-only-if-Secure-Simple-Pairing-enabled.patch |
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+From: https://lore.kernel.org/linux-bluetooth/20190522070540.48895-1-marcel@××××××××.org/raw |
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+Desc: Bluetooth: Check key sizes only when Secure Simple Pairing is enabled. See bug #686758 |
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+ |
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+Patch: 2600_enable-key-swapping-for-apple-mac.patch |
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+From: https://github.com/free5lot/hid-apple-patched |
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+Desc: This hid-apple patch enables swapping of the FN and left Control keys and some additional on some apple keyboards. See bug #622902 |
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+ |
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Patch: 4567_distro-Gentoo-Kconfig.patch |
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From: Tom Wijsman <TomWij@g.o> |
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Desc: Add Gentoo Linux support config settings and defaults. |
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+ |
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+Patch: 5011_enable-cpu-optimizations-for-gcc8.patch |
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+From: https://github.com/graysky2/kernel_gcc_patch/ |
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+Desc: Kernel patch for >= gccv8 enables kernel >= v4.13 optimizations for additional CPUs. |
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+ |
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+Patch: 5012_enable-cpu-optimizations-for-gcc91.patch |
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+From: https://github.com/graysky2/kernel_gcc_patch/ |
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+Desc: Kernel patch enables gcc >= v9.1 optimizations for additional CPUs. |
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|
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diff --git a/1500_XATTR_USER_PREFIX.patch b/1500_XATTR_USER_PREFIX.patch |
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new file mode 100644 |
69 |
index 0000000..bacd032 |
70 |
--- /dev/null |
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+++ b/1500_XATTR_USER_PREFIX.patch |
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@@ -0,0 +1,69 @@ |
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+From: Anthony G. Basile <blueness@g.o> |
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+ |
75 |
+This patch adds support for a restricted user-controlled namespace on |
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+tmpfs filesystem used to house PaX flags. The namespace must be of the |
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+form user.pax.* and its value cannot exceed a size of 8 bytes. |
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+ |
79 |
+This is needed even on all Gentoo systems so that XATTR_PAX flags |
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+are preserved for users who might build packages using portage on |
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+a tmpfs system with a non-hardened kernel and then switch to a |
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+hardened kernel with XATTR_PAX enabled. |
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+ |
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+The namespace is added to any user with Extended Attribute support |
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+enabled for tmpfs. Users who do not enable xattrs will not have |
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+the XATTR_PAX flags preserved. |
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+ |
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+diff --git a/include/uapi/linux/xattr.h b/include/uapi/linux/xattr.h |
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+index 1590c49..5eab462 100644 |
90 |
+--- a/include/uapi/linux/xattr.h |
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++++ b/include/uapi/linux/xattr.h |
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+@@ -73,5 +73,9 @@ |
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+ #define XATTR_POSIX_ACL_DEFAULT "posix_acl_default" |
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+ #define XATTR_NAME_POSIX_ACL_DEFAULT XATTR_SYSTEM_PREFIX XATTR_POSIX_ACL_DEFAULT |
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+ |
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++/* User namespace */ |
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++#define XATTR_PAX_PREFIX XATTR_USER_PREFIX "pax." |
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++#define XATTR_PAX_FLAGS_SUFFIX "flags" |
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++#define XATTR_NAME_PAX_FLAGS XATTR_PAX_PREFIX XATTR_PAX_FLAGS_SUFFIX |
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+ |
101 |
+ #endif /* _UAPI_LINUX_XATTR_H */ |
102 |
+diff --git a/mm/shmem.c b/mm/shmem.c |
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+index 440e2a7..c377172 100644 |
104 |
+--- a/mm/shmem.c |
105 |
++++ b/mm/shmem.c |
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+@@ -2667,6 +2667,14 @@ static int shmem_xattr_handler_set(const struct xattr_handler *handler, |
107 |
+ struct shmem_inode_info *info = SHMEM_I(d_inode(dentry)); |
108 |
+ |
109 |
+ name = xattr_full_name(handler, name); |
110 |
++ |
111 |
++ if (!strncmp(name, XATTR_USER_PREFIX, XATTR_USER_PREFIX_LEN)) { |
112 |
++ if (strcmp(name, XATTR_NAME_PAX_FLAGS)) |
113 |
++ return -EOPNOTSUPP; |
114 |
++ if (size > 8) |
115 |
++ return -EINVAL; |
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++ } |
117 |
++ |
118 |
+ return simple_xattr_set(&info->xattrs, name, value, size, flags); |
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+ } |
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+ |
121 |
+@@ -2682,6 +2690,12 @@ static const struct xattr_handler shmem_trusted_xattr_handler = { |
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+ .set = shmem_xattr_handler_set, |
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+ }; |
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+ |
125 |
++static const struct xattr_handler shmem_user_xattr_handler = { |
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++ .prefix = XATTR_USER_PREFIX, |
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++ .get = shmem_xattr_handler_get, |
128 |
++ .set = shmem_xattr_handler_set, |
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++}; |
130 |
++ |
131 |
+ static const struct xattr_handler *shmem_xattr_handlers[] = { |
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+ #ifdef CONFIG_TMPFS_POSIX_ACL |
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+ &posix_acl_access_xattr_handler, |
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+@@ -2689,6 +2703,7 @@ static const struct xattr_handler *shmem_xattr_handlers[] = { |
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+ #endif |
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+ &shmem_security_xattr_handler, |
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+ &shmem_trusted_xattr_handler, |
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++ &shmem_user_xattr_handler, |
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+ NULL |
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+ }; |
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+ |
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|
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diff --git a/1510_fs-enable-link-security-restrictions-by-default.patch b/1510_fs-enable-link-security-restrictions-by-default.patch |
144 |
new file mode 100644 |
145 |
index 0000000..f0ed144 |
146 |
--- /dev/null |
147 |
+++ b/1510_fs-enable-link-security-restrictions-by-default.patch |
148 |
@@ -0,0 +1,20 @@ |
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+From: Ben Hutchings <ben@××××××××××××.uk> |
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+Subject: fs: Enable link security restrictions by default |
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+Date: Fri, 02 Nov 2012 05:32:06 +0000 |
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+Bug-Debian: https://bugs.debian.org/609455 |
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+Forwarded: not-needed |
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+This reverts commit 561ec64ae67ef25cac8d72bb9c4bfc955edfd415 |
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+('VFS: don't do protected {sym,hard}links by default'). |
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+--- a/fs/namei.c 2018-09-28 07:56:07.770005006 -0400 |
157 |
++++ b/fs/namei.c 2018-09-28 07:56:43.370349204 -0400 |
158 |
+@@ -885,8 +885,8 @@ static inline void put_link(struct namei |
159 |
+ path_put(&last->link); |
160 |
+ } |
161 |
+ |
162 |
+-int sysctl_protected_symlinks __read_mostly = 0; |
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+-int sysctl_protected_hardlinks __read_mostly = 0; |
164 |
++int sysctl_protected_symlinks __read_mostly = 1; |
165 |
++int sysctl_protected_hardlinks __read_mostly = 1; |
166 |
+ int sysctl_protected_fifos __read_mostly; |
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+ int sysctl_protected_regular __read_mostly; |
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+ |
169 |
|
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diff --git a/2000_BT-Check-key-sizes-only-if-Secure-Simple-Pairing-enabled.patch b/2000_BT-Check-key-sizes-only-if-Secure-Simple-Pairing-enabled.patch |
171 |
new file mode 100644 |
172 |
index 0000000..394ad48 |
173 |
--- /dev/null |
174 |
+++ b/2000_BT-Check-key-sizes-only-if-Secure-Simple-Pairing-enabled.patch |
175 |
@@ -0,0 +1,37 @@ |
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+The encryption is only mandatory to be enforced when both sides are using |
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+Secure Simple Pairing and this means the key size check makes only sense |
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+in that case. |
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+ |
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+On legacy Bluetooth 2.0 and earlier devices like mice the encryption was |
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+optional and thus causing an issue if the key size check is not bound to |
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+using Secure Simple Pairing. |
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+ |
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+Fixes: d5bb334a8e17 ("Bluetooth: Align minimum encryption key size for LE and BR/EDR connections") |
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+Signed-off-by: Marcel Holtmann <marcel@××××××××.org> |
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+Cc: stable@×××××××××××.org |
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+--- |
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+ net/bluetooth/hci_conn.c | 9 +++++++-- |
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+ 1 file changed, 7 insertions(+), 2 deletions(-) |
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+ |
191 |
+diff --git a/net/bluetooth/hci_conn.c b/net/bluetooth/hci_conn.c |
192 |
+index 3cf0764d5793..7516cdde3373 100644 |
193 |
+--- a/net/bluetooth/hci_conn.c |
194 |
++++ b/net/bluetooth/hci_conn.c |
195 |
+@@ -1272,8 +1272,13 @@ int hci_conn_check_link_mode(struct hci_conn *conn) |
196 |
+ return 0; |
197 |
+ } |
198 |
+ |
199 |
+- if (hci_conn_ssp_enabled(conn) && |
200 |
+- !test_bit(HCI_CONN_ENCRYPT, &conn->flags)) |
201 |
++ /* If Secure Simple Pairing is not enabled, then legacy connection |
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++ * setup is used and no encryption or key sizes can be enforced. |
203 |
++ */ |
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++ if (!hci_conn_ssp_enabled(conn)) |
205 |
++ return 1; |
206 |
++ |
207 |
++ if (!test_bit(HCI_CONN_ENCRYPT, &conn->flags)) |
208 |
+ return 0; |
209 |
+ |
210 |
+ /* The minimum encryption key size needs to be enforced by the |
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+-- |
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+2.20.1 |
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|
214 |
diff --git a/2600_enable-key-swapping-for-apple-mac.patch b/2600_enable-key-swapping-for-apple-mac.patch |
215 |
new file mode 100644 |
216 |
index 0000000..ab228d3 |
217 |
--- /dev/null |
218 |
+++ b/2600_enable-key-swapping-for-apple-mac.patch |
219 |
@@ -0,0 +1,114 @@ |
220 |
+--- a/drivers/hid/hid-apple.c |
221 |
++++ b/drivers/hid/hid-apple.c |
222 |
+@@ -52,6 +52,22 @@ |
223 |
+ "(For people who want to keep Windows PC keyboard muscle memory. " |
224 |
+ "[0] = as-is, Mac layout. 1 = swapped, Windows layout.)"); |
225 |
+ |
226 |
++static unsigned int swap_fn_leftctrl; |
227 |
++module_param(swap_fn_leftctrl, uint, 0644); |
228 |
++MODULE_PARM_DESC(swap_fn_leftctrl, "Swap the Fn and left Control keys. " |
229 |
++ "(For people who want to keep PC keyboard muscle memory. " |
230 |
++ "[0] = as-is, Mac layout, 1 = swapped, PC layout)"); |
231 |
++ |
232 |
++static unsigned int rightalt_as_rightctrl; |
233 |
++module_param(rightalt_as_rightctrl, uint, 0644); |
234 |
++MODULE_PARM_DESC(rightalt_as_rightctrl, "Use the right Alt key as a right Ctrl key. " |
235 |
++ "[0] = as-is, Mac layout. 1 = Right Alt is right Ctrl"); |
236 |
++ |
237 |
++static unsigned int ejectcd_as_delete; |
238 |
++module_param(ejectcd_as_delete, uint, 0644); |
239 |
++MODULE_PARM_DESC(ejectcd_as_delete, "Use Eject-CD key as Delete key. " |
240 |
++ "([0] = disabled, 1 = enabled)"); |
241 |
++ |
242 |
+ struct apple_sc { |
243 |
+ unsigned long quirks; |
244 |
+ unsigned int fn_on; |
245 |
+@@ -164,6 +180,21 @@ |
246 |
+ { } |
247 |
+ }; |
248 |
+ |
249 |
++static const struct apple_key_translation swapped_fn_leftctrl_keys[] = { |
250 |
++ { KEY_FN, KEY_LEFTCTRL }, |
251 |
++ { } |
252 |
++}; |
253 |
++ |
254 |
++static const struct apple_key_translation rightalt_as_rightctrl_keys[] = { |
255 |
++ { KEY_RIGHTALT, KEY_RIGHTCTRL }, |
256 |
++ { } |
257 |
++}; |
258 |
++ |
259 |
++static const struct apple_key_translation ejectcd_as_delete_keys[] = { |
260 |
++ { KEY_EJECTCD, KEY_DELETE }, |
261 |
++ { } |
262 |
++}; |
263 |
++ |
264 |
+ static const struct apple_key_translation *apple_find_translation( |
265 |
+ const struct apple_key_translation *table, u16 from) |
266 |
+ { |
267 |
+@@ -183,9 +214,11 @@ |
268 |
+ struct apple_sc *asc = hid_get_drvdata(hid); |
269 |
+ const struct apple_key_translation *trans, *table; |
270 |
+ |
271 |
+- if (usage->code == KEY_FN) { |
272 |
++ u16 fn_keycode = (swap_fn_leftctrl) ? (KEY_LEFTCTRL) : (KEY_FN); |
273 |
++ |
274 |
++ if (usage->code == fn_keycode) { |
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+ asc->fn_on = !!value; |
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+- input_event(input, usage->type, usage->code, value); |
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++ input_event(input, usage->type, KEY_FN, value); |
278 |
+ return 1; |
279 |
+ } |
280 |
+ |
281 |
+@@ -264,6 +297,30 @@ |
282 |
+ } |
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+ } |
284 |
+ |
285 |
++ if (swap_fn_leftctrl) { |
286 |
++ trans = apple_find_translation(swapped_fn_leftctrl_keys, usage->code); |
287 |
++ if (trans) { |
288 |
++ input_event(input, usage->type, trans->to, value); |
289 |
++ return 1; |
290 |
++ } |
291 |
++ } |
292 |
++ |
293 |
++ if (ejectcd_as_delete) { |
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++ trans = apple_find_translation(ejectcd_as_delete_keys, usage->code); |
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++ if (trans) { |
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++ input_event(input, usage->type, trans->to, value); |
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++ return 1; |
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++ } |
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++ } |
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++ |
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++ if (rightalt_as_rightctrl) { |
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++ trans = apple_find_translation(rightalt_as_rightctrl_keys, usage->code); |
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++ if (trans) { |
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++ input_event(input, usage->type, trans->to, value); |
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++ return 1; |
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++ } |
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++ } |
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++ |
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+ return 0; |
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+ } |
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+ |
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+@@ -327,6 +384,21 @@ |
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+ |
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+ for (trans = apple_iso_keyboard; trans->from; trans++) |
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+ set_bit(trans->to, input->keybit); |
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++ |
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++ if (swap_fn_leftctrl) { |
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++ for (trans = swapped_fn_leftctrl_keys; trans->from; trans++) |
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++ set_bit(trans->to, input->keybit); |
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++ } |
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++ |
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++ if (ejectcd_as_delete) { |
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++ for (trans = ejectcd_as_delete_keys; trans->from; trans++) |
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++ set_bit(trans->to, input->keybit); |
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++ } |
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++ |
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++ if (rightalt_as_rightctrl) { |
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++ for (trans = rightalt_as_rightctrl_keys; trans->from; trans++) |
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++ set_bit(trans->to, input->keybit); |
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++ } |
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+ } |
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+ |
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+ static int apple_input_mapping(struct hid_device *hdev, struct hid_input *hi, |
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|
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diff --git a/5011_enable-cpu-optimizations-for-gcc8.patch b/5011_enable-cpu-optimizations-for-gcc8.patch |
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new file mode 100644 |
337 |
index 0000000..bfd2065 |
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--- /dev/null |
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+++ b/5011_enable-cpu-optimizations-for-gcc8.patch |
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@@ -0,0 +1,569 @@ |
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+WARNING |
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+This patch works with gcc versions 8.1+ and with kernel version 4.13+ and should |
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+NOT be applied when compiling on older versions of gcc due to key name changes |
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+of the march flags introduced with the version 4.9 release of gcc.[1] |
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+ |
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+Use the older version of this patch hosted on the same github for older |
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+versions of gcc. |
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+ |
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+FEATURES |
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+This patch adds additional CPU options to the Linux kernel accessible under: |
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+ Processor type and features ---> |
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+ Processor family ---> |
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+ |
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+The expanded microarchitectures include: |
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+* AMD Improved K8-family |
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+* AMD K10-family |
357 |
+* AMD Family 10h (Barcelona) |
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+* AMD Family 14h (Bobcat) |
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+* AMD Family 16h (Jaguar) |
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+* AMD Family 15h (Bulldozer) |
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+* AMD Family 15h (Piledriver) |
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+* AMD Family 15h (Steamroller) |
363 |
+* AMD Family 15h (Excavator) |
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+* AMD Family 17h (Zen) |
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+* Intel Silvermont low-power processors |
366 |
+* Intel 1st Gen Core i3/i5/i7 (Nehalem) |
367 |
+* Intel 1.5 Gen Core i3/i5/i7 (Westmere) |
368 |
+* Intel 2nd Gen Core i3/i5/i7 (Sandybridge) |
369 |
+* Intel 3rd Gen Core i3/i5/i7 (Ivybridge) |
370 |
+* Intel 4th Gen Core i3/i5/i7 (Haswell) |
371 |
+* Intel 5th Gen Core i3/i5/i7 (Broadwell) |
372 |
+* Intel 6th Gen Core i3/i5/i7 (Skylake) |
373 |
+* Intel 6th Gen Core i7/i9 (Skylake X) |
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+* Intel 8th Gen Core i3/i5/i7 (Cannon Lake) |
375 |
+* Intel 8th Gen Core i7/i9 (Ice Lake) |
376 |
+ |
377 |
+It also offers to compile passing the 'native' option which, "selects the CPU |
378 |
+to generate code for at compilation time by determining the processor type of |
379 |
+the compiling machine. Using -march=native enables all instruction subsets |
380 |
+supported by the local machine and will produce code optimized for the local |
381 |
+machine under the constraints of the selected instruction set."[3] |
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+ |
383 |
+MINOR NOTES |
384 |
+This patch also changes 'atom' to 'bonnell' in accordance with the gcc v4.9 |
385 |
+changes. Note that upstream is using the deprecated 'match=atom' flags when I |
386 |
+believe it should use the newer 'march=bonnell' flag for atom processors.[2] |
387 |
+ |
388 |
+It is not recommended to compile on Atom-CPUs with the 'native' option.[4] The |
389 |
+recommendation is to use the 'atom' option instead. |
390 |
+ |
391 |
+BENEFITS |
392 |
+Small but real speed increases are measurable using a make endpoint comparing |
393 |
+a generic kernel to one built with one of the respective microarchs. |
394 |
+ |
395 |
+See the following experimental evidence supporting this statement: |
396 |
+https://github.com/graysky2/kernel_gcc_patch |
397 |
+ |
398 |
+REQUIREMENTS |
399 |
+linux version >=4.20 |
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+gcc version >=8.1 |
401 |
+ |
402 |
+ACKNOWLEDGMENTS |
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+This patch builds on the seminal work by Jeroen.[5] |
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+ |
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+REFERENCES |
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+1. https://gcc.gnu.org/gcc-4.9/changes.html |
407 |
+2. https://bugzilla.kernel.org/show_bug.cgi?id=77461 |
408 |
+3. https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html |
409 |
+4. https://github.com/graysky2/kernel_gcc_patch/issues/15 |
410 |
+5. http://www.linuxforge.net/docs/linux/linux-gcc.php |
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+ |
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+--- a/arch/x86/Makefile_32.cpu 2019-02-22 09:22:03.426937735 -0500 |
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++++ b/arch/x86/Makefile_32.cpu 2019-02-22 09:37:58.680968580 -0500 |
414 |
+@@ -23,7 +23,18 @@ cflags-$(CONFIG_MK6) += -march=k6 |
415 |
+ # Please note, that patches that add -march=athlon-xp and friends are pointless. |
416 |
+ # They make zero difference whatsosever to performance at this time. |
417 |
+ cflags-$(CONFIG_MK7) += -march=athlon |
418 |
++cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native) |
419 |
+ cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8,-march=athlon) |
420 |
++cflags-$(CONFIG_MK8SSE3) += $(call cc-option,-march=k8-sse3,-march=athlon) |
421 |
++cflags-$(CONFIG_MK10) += $(call cc-option,-march=amdfam10,-march=athlon) |
422 |
++cflags-$(CONFIG_MBARCELONA) += $(call cc-option,-march=barcelona,-march=athlon) |
423 |
++cflags-$(CONFIG_MBOBCAT) += $(call cc-option,-march=btver1,-march=athlon) |
424 |
++cflags-$(CONFIG_MJAGUAR) += $(call cc-option,-march=btver2,-march=athlon) |
425 |
++cflags-$(CONFIG_MBULLDOZER) += $(call cc-option,-march=bdver1,-march=athlon) |
426 |
++cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-march=bdver2,-march=athlon) |
427 |
++cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-march=bdver3,-march=athlon) |
428 |
++cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4,-march=athlon) |
429 |
++cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1,-march=athlon) |
430 |
+ cflags-$(CONFIG_MCRUSOE) += -march=i686 -falign-functions=0 -falign-jumps=0 -falign-loops=0 |
431 |
+ cflags-$(CONFIG_MEFFICEON) += -march=i686 $(call tune,pentium3) -falign-functions=0 -falign-jumps=0 -falign-loops=0 |
432 |
+ cflags-$(CONFIG_MWINCHIPC6) += $(call cc-option,-march=winchip-c6,-march=i586) |
433 |
+@@ -32,9 +43,20 @@ cflags-$(CONFIG_MCYRIXIII) += $(call cc- |
434 |
+ cflags-$(CONFIG_MVIAC3_2) += $(call cc-option,-march=c3-2,-march=i686) |
435 |
+ cflags-$(CONFIG_MVIAC7) += -march=i686 |
436 |
+ cflags-$(CONFIG_MCORE2) += -march=i686 $(call tune,core2) |
437 |
+-cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom,$(call cc-option,-march=core2,-march=i686)) \ |
438 |
+- $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic)) |
439 |
+- |
440 |
++cflags-$(CONFIG_MNEHALEM) += -march=i686 $(call tune,nehalem) |
441 |
++cflags-$(CONFIG_MWESTMERE) += -march=i686 $(call tune,westmere) |
442 |
++cflags-$(CONFIG_MSILVERMONT) += -march=i686 $(call tune,silvermont) |
443 |
++cflags-$(CONFIG_MSANDYBRIDGE) += -march=i686 $(call tune,sandybridge) |
444 |
++cflags-$(CONFIG_MIVYBRIDGE) += -march=i686 $(call tune,ivybridge) |
445 |
++cflags-$(CONFIG_MHASWELL) += -march=i686 $(call tune,haswell) |
446 |
++cflags-$(CONFIG_MBROADWELL) += -march=i686 $(call tune,broadwell) |
447 |
++cflags-$(CONFIG_MSKYLAKE) += -march=i686 $(call tune,skylake) |
448 |
++cflags-$(CONFIG_MSKYLAKEX) += -march=i686 $(call tune,skylake-avx512) |
449 |
++cflags-$(CONFIG_MCANNONLAKE) += -march=i686 $(call tune,cannonlake) |
450 |
++cflags-$(CONFIG_MICELAKE) += -march=i686 $(call tune,icelake) |
451 |
++cflags-$(CONFIG_MATOM) += $(call cc-option,-march=bonnell,$(call cc-option,-march=core2,-march=i686)) \ |
452 |
++ $(call cc-option,-mtune=bonnell,$(call cc-option,-mtune=generic)) |
453 |
++ |
454 |
+ # AMD Elan support |
455 |
+ cflags-$(CONFIG_MELAN) += -march=i486 |
456 |
+ |
457 |
+--- a/arch/x86/Kconfig.cpu 2019-02-22 09:22:11.576958595 -0500 |
458 |
++++ b/arch/x86/Kconfig.cpu 2019-02-22 09:34:16.490003911 -0500 |
459 |
+@@ -116,6 +116,7 @@ config MPENTIUMM |
460 |
+ config MPENTIUM4 |
461 |
+ bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon" |
462 |
+ depends on X86_32 |
463 |
++ select X86_P6_NOP |
464 |
+ ---help--- |
465 |
+ Select this for Intel Pentium 4 chips. This includes the |
466 |
+ Pentium 4, Pentium D, P4-based Celeron and Xeon, and |
467 |
+@@ -150,7 +151,7 @@ config MPENTIUM4 |
468 |
+ |
469 |
+ |
470 |
+ config MK6 |
471 |
+- bool "K6/K6-II/K6-III" |
472 |
++ bool "AMD K6/K6-II/K6-III" |
473 |
+ depends on X86_32 |
474 |
+ ---help--- |
475 |
+ Select this for an AMD K6-family processor. Enables use of |
476 |
+@@ -158,7 +159,7 @@ config MK6 |
477 |
+ flags to GCC. |
478 |
+ |
479 |
+ config MK7 |
480 |
+- bool "Athlon/Duron/K7" |
481 |
++ bool "AMD Athlon/Duron/K7" |
482 |
+ depends on X86_32 |
483 |
+ ---help--- |
484 |
+ Select this for an AMD Athlon K7-family processor. Enables use of |
485 |
+@@ -166,11 +167,81 @@ config MK7 |
486 |
+ flags to GCC. |
487 |
+ |
488 |
+ config MK8 |
489 |
+- bool "Opteron/Athlon64/Hammer/K8" |
490 |
++ bool "AMD Opteron/Athlon64/Hammer/K8" |
491 |
+ ---help--- |
492 |
+ Select this for an AMD Opteron or Athlon64 Hammer-family processor. |
493 |
+ Enables use of some extended instructions, and passes appropriate |
494 |
+ optimization flags to GCC. |
495 |
++config MK8SSE3 |
496 |
++ bool "AMD Opteron/Athlon64/Hammer/K8 with SSE3" |
497 |
++ ---help--- |
498 |
++ Select this for improved AMD Opteron or Athlon64 Hammer-family processors. |
499 |
++ Enables use of some extended instructions, and passes appropriate |
500 |
++ optimization flags to GCC. |
501 |
++ |
502 |
++config MK10 |
503 |
++ bool "AMD 61xx/7x50/PhenomX3/X4/II/K10" |
504 |
++ ---help--- |
505 |
++ Select this for an AMD 61xx Eight-Core Magny-Cours, Athlon X2 7x50, |
506 |
++ Phenom X3/X4/II, Athlon II X2/X3/X4, or Turion II-family processor. |
507 |
++ Enables use of some extended instructions, and passes appropriate |
508 |
++ optimization flags to GCC. |
509 |
++ |
510 |
++config MBARCELONA |
511 |
++ bool "AMD Barcelona" |
512 |
++ ---help--- |
513 |
++ Select this for AMD Family 10h Barcelona processors. |
514 |
++ |
515 |
++ Enables -march=barcelona |
516 |
++ |
517 |
++config MBOBCAT |
518 |
++ bool "AMD Bobcat" |
519 |
++ ---help--- |
520 |
++ Select this for AMD Family 14h Bobcat processors. |
521 |
++ |
522 |
++ Enables -march=btver1 |
523 |
++ |
524 |
++config MJAGUAR |
525 |
++ bool "AMD Jaguar" |
526 |
++ ---help--- |
527 |
++ Select this for AMD Family 16h Jaguar processors. |
528 |
++ |
529 |
++ Enables -march=btver2 |
530 |
++ |
531 |
++config MBULLDOZER |
532 |
++ bool "AMD Bulldozer" |
533 |
++ ---help--- |
534 |
++ Select this for AMD Family 15h Bulldozer processors. |
535 |
++ |
536 |
++ Enables -march=bdver1 |
537 |
++ |
538 |
++config MPILEDRIVER |
539 |
++ bool "AMD Piledriver" |
540 |
++ ---help--- |
541 |
++ Select this for AMD Family 15h Piledriver processors. |
542 |
++ |
543 |
++ Enables -march=bdver2 |
544 |
++ |
545 |
++config MSTEAMROLLER |
546 |
++ bool "AMD Steamroller" |
547 |
++ ---help--- |
548 |
++ Select this for AMD Family 15h Steamroller processors. |
549 |
++ |
550 |
++ Enables -march=bdver3 |
551 |
++ |
552 |
++config MEXCAVATOR |
553 |
++ bool "AMD Excavator" |
554 |
++ ---help--- |
555 |
++ Select this for AMD Family 15h Excavator processors. |
556 |
++ |
557 |
++ Enables -march=bdver4 |
558 |
++ |
559 |
++config MZEN |
560 |
++ bool "AMD Zen" |
561 |
++ ---help--- |
562 |
++ Select this for AMD Family 17h Zen processors. |
563 |
++ |
564 |
++ Enables -march=znver1 |
565 |
+ |
566 |
+ config MCRUSOE |
567 |
+ bool "Crusoe" |
568 |
+@@ -253,6 +324,7 @@ config MVIAC7 |
569 |
+ |
570 |
+ config MPSC |
571 |
+ bool "Intel P4 / older Netburst based Xeon" |
572 |
++ select X86_P6_NOP |
573 |
+ depends on X86_64 |
574 |
+ ---help--- |
575 |
+ Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey |
576 |
+@@ -262,23 +334,126 @@ config MPSC |
577 |
+ using the cpu family field |
578 |
+ in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one. |
579 |
+ |
580 |
++config MATOM |
581 |
++ bool "Intel Atom" |
582 |
++ select X86_P6_NOP |
583 |
++ ---help--- |
584 |
++ |
585 |
++ Select this for the Intel Atom platform. Intel Atom CPUs have an |
586 |
++ in-order pipelining architecture and thus can benefit from |
587 |
++ accordingly optimized code. Use a recent GCC with specific Atom |
588 |
++ support in order to fully benefit from selecting this option. |
589 |
++ |
590 |
+ config MCORE2 |
591 |
+- bool "Core 2/newer Xeon" |
592 |
++ bool "Intel Core 2" |
593 |
++ select X86_P6_NOP |
594 |
++ |
595 |
+ ---help--- |
596 |
+ |
597 |
+ Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and |
598 |
+ 53xx) CPUs. You can distinguish newer from older Xeons by the CPU |
599 |
+ family in /proc/cpuinfo. Newer ones have 6 and older ones 15 |
600 |
+ (not a typo) |
601 |
++ Enables -march=core2 |
602 |
+ |
603 |
+-config MATOM |
604 |
+- bool "Intel Atom" |
605 |
++config MNEHALEM |
606 |
++ bool "Intel Nehalem" |
607 |
++ select X86_P6_NOP |
608 |
+ ---help--- |
609 |
+ |
610 |
+- Select this for the Intel Atom platform. Intel Atom CPUs have an |
611 |
+- in-order pipelining architecture and thus can benefit from |
612 |
+- accordingly optimized code. Use a recent GCC with specific Atom |
613 |
+- support in order to fully benefit from selecting this option. |
614 |
++ Select this for 1st Gen Core processors in the Nehalem family. |
615 |
++ |
616 |
++ Enables -march=nehalem |
617 |
++ |
618 |
++config MWESTMERE |
619 |
++ bool "Intel Westmere" |
620 |
++ select X86_P6_NOP |
621 |
++ ---help--- |
622 |
++ |
623 |
++ Select this for the Intel Westmere formerly Nehalem-C family. |
624 |
++ |
625 |
++ Enables -march=westmere |
626 |
++ |
627 |
++config MSILVERMONT |
628 |
++ bool "Intel Silvermont" |
629 |
++ select X86_P6_NOP |
630 |
++ ---help--- |
631 |
++ |
632 |
++ Select this for the Intel Silvermont platform. |
633 |
++ |
634 |
++ Enables -march=silvermont |
635 |
++ |
636 |
++config MSANDYBRIDGE |
637 |
++ bool "Intel Sandy Bridge" |
638 |
++ select X86_P6_NOP |
639 |
++ ---help--- |
640 |
++ |
641 |
++ Select this for 2nd Gen Core processors in the Sandy Bridge family. |
642 |
++ |
643 |
++ Enables -march=sandybridge |
644 |
++ |
645 |
++config MIVYBRIDGE |
646 |
++ bool "Intel Ivy Bridge" |
647 |
++ select X86_P6_NOP |
648 |
++ ---help--- |
649 |
++ |
650 |
++ Select this for 3rd Gen Core processors in the Ivy Bridge family. |
651 |
++ |
652 |
++ Enables -march=ivybridge |
653 |
++ |
654 |
++config MHASWELL |
655 |
++ bool "Intel Haswell" |
656 |
++ select X86_P6_NOP |
657 |
++ ---help--- |
658 |
++ |
659 |
++ Select this for 4th Gen Core processors in the Haswell family. |
660 |
++ |
661 |
++ Enables -march=haswell |
662 |
++ |
663 |
++config MBROADWELL |
664 |
++ bool "Intel Broadwell" |
665 |
++ select X86_P6_NOP |
666 |
++ ---help--- |
667 |
++ |
668 |
++ Select this for 5th Gen Core processors in the Broadwell family. |
669 |
++ |
670 |
++ Enables -march=broadwell |
671 |
++ |
672 |
++config MSKYLAKE |
673 |
++ bool "Intel Skylake" |
674 |
++ select X86_P6_NOP |
675 |
++ ---help--- |
676 |
++ |
677 |
++ Select this for 6th Gen Core processors in the Skylake family. |
678 |
++ |
679 |
++ Enables -march=skylake |
680 |
++ |
681 |
++config MSKYLAKEX |
682 |
++ bool "Intel Skylake X" |
683 |
++ select X86_P6_NOP |
684 |
++ ---help--- |
685 |
++ |
686 |
++ Select this for 6th Gen Core processors in the Skylake X family. |
687 |
++ |
688 |
++ Enables -march=skylake-avx512 |
689 |
++ |
690 |
++config MCANNONLAKE |
691 |
++ bool "Intel Cannon Lake" |
692 |
++ select X86_P6_NOP |
693 |
++ ---help--- |
694 |
++ |
695 |
++ Select this for 8th Gen Core processors |
696 |
++ |
697 |
++ Enables -march=cannonlake |
698 |
++ |
699 |
++config MICELAKE |
700 |
++ bool "Intel Ice Lake" |
701 |
++ select X86_P6_NOP |
702 |
++ ---help--- |
703 |
++ |
704 |
++ Select this for 8th Gen Core processors in the Ice Lake family. |
705 |
++ |
706 |
++ Enables -march=icelake |
707 |
+ |
708 |
+ config GENERIC_CPU |
709 |
+ bool "Generic-x86-64" |
710 |
+@@ -287,6 +462,19 @@ config GENERIC_CPU |
711 |
+ Generic x86-64 CPU. |
712 |
+ Run equally well on all x86-64 CPUs. |
713 |
+ |
714 |
++config MNATIVE |
715 |
++ bool "Native optimizations autodetected by GCC" |
716 |
++ ---help--- |
717 |
++ |
718 |
++ GCC 4.2 and above support -march=native, which automatically detects |
719 |
++ the optimum settings to use based on your processor. -march=native |
720 |
++ also detects and applies additional settings beyond -march specific |
721 |
++ to your CPU, (eg. -msse4). Unless you have a specific reason not to |
722 |
++ (e.g. distcc cross-compiling), you should probably be using |
723 |
++ -march=native rather than anything listed below. |
724 |
++ |
725 |
++ Enables -march=native |
726 |
++ |
727 |
+ endchoice |
728 |
+ |
729 |
+ config X86_GENERIC |
730 |
+@@ -311,7 +499,7 @@ config X86_INTERNODE_CACHE_SHIFT |
731 |
+ config X86_L1_CACHE_SHIFT |
732 |
+ int |
733 |
+ default "7" if MPENTIUM4 || MPSC |
734 |
+- default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU |
735 |
++ default "6" if MK7 || MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MJAGUAR || MPENTIUMM || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MNATIVE || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU |
736 |
+ default "4" if MELAN || M486 || MGEODEGX1 |
737 |
+ default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX |
738 |
+ |
739 |
+@@ -329,39 +517,40 @@ config X86_ALIGNMENT_16 |
740 |
+ |
741 |
+ config X86_INTEL_USERCOPY |
742 |
+ def_bool y |
743 |
+- depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 |
744 |
++ depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK8SSE3 || MK7 || MEFFICEON || MCORE2 || MK10 || MBARCELONA || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MNATIVE |
745 |
+ |
746 |
+ config X86_USE_PPRO_CHECKSUM |
747 |
+ def_bool y |
748 |
+- depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM |
749 |
++ depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MK10 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MATOM || MNATIVE |
750 |
+ |
751 |
+ config X86_USE_3DNOW |
752 |
+ def_bool y |
753 |
+ depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML |
754 |
+ |
755 |
+-# |
756 |
+-# P6_NOPs are a relatively minor optimization that require a family >= |
757 |
+-# 6 processor, except that it is broken on certain VIA chips. |
758 |
+-# Furthermore, AMD chips prefer a totally different sequence of NOPs |
759 |
+-# (which work on all CPUs). In addition, it looks like Virtual PC |
760 |
+-# does not understand them. |
761 |
+-# |
762 |
+-# As a result, disallow these if we're not compiling for X86_64 (these |
763 |
+-# NOPs do work on all x86-64 capable chips); the list of processors in |
764 |
+-# the right-hand clause are the cores that benefit from this optimization. |
765 |
+-# |
766 |
+ config X86_P6_NOP |
767 |
+- def_bool y |
768 |
+- depends on X86_64 |
769 |
+- depends on (MCORE2 || MPENTIUM4 || MPSC) |
770 |
++ default n |
771 |
++ bool "Support for P6_NOPs on Intel chips" |
772 |
++ depends on (MCORE2 || MPENTIUM4 || MPSC || MATOM || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MNATIVE) |
773 |
++ ---help--- |
774 |
++ P6_NOPs are a relatively minor optimization that require a family >= |
775 |
++ 6 processor, except that it is broken on certain VIA chips. |
776 |
++ Furthermore, AMD chips prefer a totally different sequence of NOPs |
777 |
++ (which work on all CPUs). In addition, it looks like Virtual PC |
778 |
++ does not understand them. |
779 |
++ |
780 |
++ As a result, disallow these if we're not compiling for X86_64 (these |
781 |
++ NOPs do work on all x86-64 capable chips); the list of processors in |
782 |
++ the right-hand clause are the cores that benefit from this optimization. |
783 |
+ |
784 |
++ Say Y if you have Intel CPU newer than Pentium Pro, N otherwise. |
785 |
++ |
786 |
+ config X86_TSC |
787 |
+ def_bool y |
788 |
+- depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64 |
789 |
++ depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MNATIVE || MATOM) || X86_64 |
790 |
+ |
791 |
+ config X86_CMPXCHG64 |
792 |
+ def_bool y |
793 |
+- depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586TSC || M586MMX || MATOM || MGEODE_LX || MGEODEGX1 || MK6 || MK7 || MK8 |
794 |
++ depends on (MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MJAGUAR || MK7 || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MNATIVE || MATOM || MGEODE_LX) |
795 |
+ |
796 |
+ # this should be set for all -march=.. options where the compiler |
797 |
+ # generates cmov. |
798 |
+--- a/arch/x86/Makefile 2019-02-22 09:21:58.196924367 -0500 |
799 |
++++ b/arch/x86/Makefile 2019-02-22 09:36:27.310577832 -0500 |
800 |
+@@ -118,13 +118,46 @@ else |
801 |
+ KBUILD_CFLAGS += $(call cc-option,-mskip-rax-setup) |
802 |
+ |
803 |
+ # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu) |
804 |
++ cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native) |
805 |
+ cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8) |
806 |
++ cflags-$(CONFIG_MK8SSE3) += $(call cc-option,-march=k8-sse3,-mtune=k8) |
807 |
++ cflags-$(CONFIG_MK10) += $(call cc-option,-march=amdfam10) |
808 |
++ cflags-$(CONFIG_MBARCELONA) += $(call cc-option,-march=barcelona) |
809 |
++ cflags-$(CONFIG_MBOBCAT) += $(call cc-option,-march=btver1) |
810 |
++ cflags-$(CONFIG_MJAGUAR) += $(call cc-option,-march=btver2) |
811 |
++ cflags-$(CONFIG_MBULLDOZER) += $(call cc-option,-march=bdver1) |
812 |
++ cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-march=bdver2) |
813 |
++ cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-march=bdver3) |
814 |
++ cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4) |
815 |
++ cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1) |
816 |
+ cflags-$(CONFIG_MPSC) += $(call cc-option,-march=nocona) |
817 |
+ |
818 |
+ cflags-$(CONFIG_MCORE2) += \ |
819 |
+- $(call cc-option,-march=core2,$(call cc-option,-mtune=generic)) |
820 |
+- cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom) \ |
821 |
+- $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic)) |
822 |
++ $(call cc-option,-march=core2,$(call cc-option,-mtune=core2)) |
823 |
++ cflags-$(CONFIG_MNEHALEM) += \ |
824 |
++ $(call cc-option,-march=nehalem,$(call cc-option,-mtune=nehalem)) |
825 |
++ cflags-$(CONFIG_MWESTMERE) += \ |
826 |
++ $(call cc-option,-march=westmere,$(call cc-option,-mtune=westmere)) |
827 |
++ cflags-$(CONFIG_MSILVERMONT) += \ |
828 |
++ $(call cc-option,-march=silvermont,$(call cc-option,-mtune=silvermont)) |
829 |
++ cflags-$(CONFIG_MSANDYBRIDGE) += \ |
830 |
++ $(call cc-option,-march=sandybridge,$(call cc-option,-mtune=sandybridge)) |
831 |
++ cflags-$(CONFIG_MIVYBRIDGE) += \ |
832 |
++ $(call cc-option,-march=ivybridge,$(call cc-option,-mtune=ivybridge)) |
833 |
++ cflags-$(CONFIG_MHASWELL) += \ |
834 |
++ $(call cc-option,-march=haswell,$(call cc-option,-mtune=haswell)) |
835 |
++ cflags-$(CONFIG_MBROADWELL) += \ |
836 |
++ $(call cc-option,-march=broadwell,$(call cc-option,-mtune=broadwell)) |
837 |
++ cflags-$(CONFIG_MSKYLAKE) += \ |
838 |
++ $(call cc-option,-march=skylake,$(call cc-option,-mtune=skylake)) |
839 |
++ cflags-$(CONFIG_MSKYLAKEX) += \ |
840 |
++ $(call cc-option,-march=skylake-avx512,$(call cc-option,-mtune=skylake-avx512)) |
841 |
++ cflags-$(CONFIG_MCANNONLAKE) += \ |
842 |
++ $(call cc-option,-march=cannonlake,$(call cc-option,-mtune=cannonlake)) |
843 |
++ cflags-$(CONFIG_MICELAKE) += \ |
844 |
++ $(call cc-option,-march=icelake,$(call cc-option,-mtune=icelake)) |
845 |
++ cflags-$(CONFIG_MATOM) += $(call cc-option,-march=bonnell) \ |
846 |
++ $(call cc-option,-mtune=bonnell,$(call cc-option,-mtune=generic)) |
847 |
+ cflags-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=generic) |
848 |
+ KBUILD_CFLAGS += $(cflags-y) |
849 |
+ |
850 |
+--- a/arch/x86/include/asm/module.h 2019-02-22 09:22:26.726997480 -0500 |
851 |
++++ b/arch/x86/include/asm/module.h 2019-02-22 09:40:04.231493392 -0500 |
852 |
+@@ -25,6 +25,30 @@ struct mod_arch_specific { |
853 |
+ #define MODULE_PROC_FAMILY "586MMX " |
854 |
+ #elif defined CONFIG_MCORE2 |
855 |
+ #define MODULE_PROC_FAMILY "CORE2 " |
856 |
++#elif defined CONFIG_MNATIVE |
857 |
++#define MODULE_PROC_FAMILY "NATIVE " |
858 |
++#elif defined CONFIG_MNEHALEM |
859 |
++#define MODULE_PROC_FAMILY "NEHALEM " |
860 |
++#elif defined CONFIG_MWESTMERE |
861 |
++#define MODULE_PROC_FAMILY "WESTMERE " |
862 |
++#elif defined CONFIG_MSILVERMONT |
863 |
++#define MODULE_PROC_FAMILY "SILVERMONT " |
864 |
++#elif defined CONFIG_MSANDYBRIDGE |
865 |
++#define MODULE_PROC_FAMILY "SANDYBRIDGE " |
866 |
++#elif defined CONFIG_MIVYBRIDGE |
867 |
++#define MODULE_PROC_FAMILY "IVYBRIDGE " |
868 |
++#elif defined CONFIG_MHASWELL |
869 |
++#define MODULE_PROC_FAMILY "HASWELL " |
870 |
++#elif defined CONFIG_MBROADWELL |
871 |
++#define MODULE_PROC_FAMILY "BROADWELL " |
872 |
++#elif defined CONFIG_MSKYLAKE |
873 |
++#define MODULE_PROC_FAMILY "SKYLAKE " |
874 |
++#elif defined CONFIG_MSKYLAKEX |
875 |
++#define MODULE_PROC_FAMILY "SKYLAKEX " |
876 |
++#elif defined CONFIG_MCANNONLAKE |
877 |
++#define MODULE_PROC_FAMILY "CANNONLAKE " |
878 |
++#elif defined CONFIG_MICELAKE |
879 |
++#define MODULE_PROC_FAMILY "ICELAKE " |
880 |
+ #elif defined CONFIG_MATOM |
881 |
+ #define MODULE_PROC_FAMILY "ATOM " |
882 |
+ #elif defined CONFIG_M686 |
883 |
+@@ -43,6 +67,26 @@ struct mod_arch_specific { |
884 |
+ #define MODULE_PROC_FAMILY "K7 " |
885 |
+ #elif defined CONFIG_MK8 |
886 |
+ #define MODULE_PROC_FAMILY "K8 " |
887 |
++#elif defined CONFIG_MK8SSE3 |
888 |
++#define MODULE_PROC_FAMILY "K8SSE3 " |
889 |
++#elif defined CONFIG_MK10 |
890 |
++#define MODULE_PROC_FAMILY "K10 " |
891 |
++#elif defined CONFIG_MBARCELONA |
892 |
++#define MODULE_PROC_FAMILY "BARCELONA " |
893 |
++#elif defined CONFIG_MBOBCAT |
894 |
++#define MODULE_PROC_FAMILY "BOBCAT " |
895 |
++#elif defined CONFIG_MBULLDOZER |
896 |
++#define MODULE_PROC_FAMILY "BULLDOZER " |
897 |
++#elif defined CONFIG_MPILEDRIVER |
898 |
++#define MODULE_PROC_FAMILY "PILEDRIVER " |
899 |
++#elif defined CONFIG_MSTEAMROLLER |
900 |
++#define MODULE_PROC_FAMILY "STEAMROLLER " |
901 |
++#elif defined CONFIG_MJAGUAR |
902 |
++#define MODULE_PROC_FAMILY "JAGUAR " |
903 |
++#elif defined CONFIG_MEXCAVATOR |
904 |
++#define MODULE_PROC_FAMILY "EXCAVATOR " |
905 |
++#elif defined CONFIG_MZEN |
906 |
++#define MODULE_PROC_FAMILY "ZEN " |
907 |
+ #elif defined CONFIG_MELAN |
908 |
+ #define MODULE_PROC_FAMILY "ELAN " |
909 |
+ #elif defined CONFIG_MCRUSOE |
910 |
|
911 |
diff --git a/5012_enable-cpu-optimizations-for-gcc91.patch b/5012_enable-cpu-optimizations-for-gcc91.patch |
912 |
new file mode 100644 |
913 |
index 0000000..455c8b2 |
914 |
--- /dev/null |
915 |
+++ b/5012_enable-cpu-optimizations-for-gcc91.patch |
916 |
@@ -0,0 +1,632 @@ |
917 |
+WARNING |
918 |
+This patch works with gcc versions 9.1+ and with kernel version 5.5+ and should |
919 |
+NOT be applied when compiling on older versions of gcc due to key name changes |
920 |
+of the march flags introduced with the version 4.9 release of gcc.[1] |
921 |
+ |
922 |
+Use the older version of this patch hosted on the same github for older |
923 |
+versions of gcc. |
924 |
+ |
925 |
+FEATURES |
926 |
+This patch adds additional CPU options to the Linux kernel accessible under: |
927 |
+ Processor type and features ---> |
928 |
+ Processor family ---> |
929 |
+ |
930 |
+The expanded microarchitectures include: |
931 |
+* AMD Improved K8-family |
932 |
+* AMD K10-family |
933 |
+* AMD Family 10h (Barcelona) |
934 |
+* AMD Family 14h (Bobcat) |
935 |
+* AMD Family 16h (Jaguar) |
936 |
+* AMD Family 15h (Bulldozer) |
937 |
+* AMD Family 15h (Piledriver) |
938 |
+* AMD Family 15h (Steamroller) |
939 |
+* AMD Family 15h (Excavator) |
940 |
+* AMD Family 17h (Zen) |
941 |
+* AMD Family 17h (Zen 2) |
942 |
+* Intel Silvermont low-power processors |
943 |
+* Intel Goldmont low-power processors (Apollo Lake and Denverton) |
944 |
+* Intel Goldmont Plus low-power processors (Gemini Lake) |
945 |
+* Intel 1st Gen Core i3/i5/i7 (Nehalem) |
946 |
+* Intel 1.5 Gen Core i3/i5/i7 (Westmere) |
947 |
+* Intel 2nd Gen Core i3/i5/i7 (Sandybridge) |
948 |
+* Intel 3rd Gen Core i3/i5/i7 (Ivybridge) |
949 |
+* Intel 4th Gen Core i3/i5/i7 (Haswell) |
950 |
+* Intel 5th Gen Core i3/i5/i7 (Broadwell) |
951 |
+* Intel 6th Gen Core i3/i5/i7 (Skylake) |
952 |
+* Intel 6th Gen Core i7/i9 (Skylake X) |
953 |
+* Intel 8th Gen Core i3/i5/i7 (Cannon Lake) |
954 |
+* Intel 10th Gen Core i7/i9 (Ice Lake) |
955 |
+* Intel Xeon (Cascade Lake) |
956 |
+ |
957 |
+It also offers to compile passing the 'native' option which, "selects the CPU |
958 |
+to generate code for at compilation time by determining the processor type of |
959 |
+the compiling machine. Using -march=native enables all instruction subsets |
960 |
+supported by the local machine and will produce code optimized for the local |
961 |
+machine under the constraints of the selected instruction set."[3] |
962 |
+ |
963 |
+MINOR NOTES |
964 |
+This patch also changes 'atom' to 'bonnell' in accordance with the gcc v4.9 |
965 |
+changes. Note that upstream is using the deprecated 'match=atom' flags when I |
966 |
+believe it should use the newer 'march=bonnell' flag for atom processors.[2] |
967 |
+ |
968 |
+It is not recommended to compile on Atom-CPUs with the 'native' option.[4] The |
969 |
+recommendation is to use the 'atom' option instead. |
970 |
+ |
971 |
+BENEFITS |
972 |
+Small but real speed increases are measurable using a make endpoint comparing |
973 |
+a generic kernel to one built with one of the respective microarchs. |
974 |
+ |
975 |
+See the following experimental evidence supporting this statement: |
976 |
+https://github.com/graysky2/kernel_gcc_patch |
977 |
+ |
978 |
+REQUIREMENTS |
979 |
+linux version >=5.5 |
980 |
+gcc version >=9.1 |
981 |
+ |
982 |
+ACKNOWLEDGMENTS |
983 |
+This patch builds on the seminal work by Jeroen.[5] |
984 |
+ |
985 |
+REFERENCES |
986 |
+1. https://gcc.gnu.org/gcc-4.9/changes.html |
987 |
+2. https://bugzilla.kernel.org/show_bug.cgi?id=77461 |
988 |
+3. https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html |
989 |
+4. https://github.com/graysky2/kernel_gcc_patch/issues/15 |
990 |
+5. http://www.linuxforge.net/docs/linux/linux-gcc.php |
991 |
+ |
992 |
+--- a/arch/x86/include/asm/module.h 2019-12-15 18:16:08.000000000 -0500 |
993 |
++++ b/arch/x86/include/asm/module.h 2019-12-17 14:03:55.968871551 -0500 |
994 |
+@@ -27,6 +27,36 @@ struct mod_arch_specific { |
995 |
+ #define MODULE_PROC_FAMILY "586MMX " |
996 |
+ #elif defined CONFIG_MCORE2 |
997 |
+ #define MODULE_PROC_FAMILY "CORE2 " |
998 |
++#elif defined CONFIG_MNATIVE |
999 |
++#define MODULE_PROC_FAMILY "NATIVE " |
1000 |
++#elif defined CONFIG_MNEHALEM |
1001 |
++#define MODULE_PROC_FAMILY "NEHALEM " |
1002 |
++#elif defined CONFIG_MWESTMERE |
1003 |
++#define MODULE_PROC_FAMILY "WESTMERE " |
1004 |
++#elif defined CONFIG_MSILVERMONT |
1005 |
++#define MODULE_PROC_FAMILY "SILVERMONT " |
1006 |
++#elif defined CONFIG_MGOLDMONT |
1007 |
++#define MODULE_PROC_FAMILY "GOLDMONT " |
1008 |
++#elif defined CONFIG_MGOLDMONTPLUS |
1009 |
++#define MODULE_PROC_FAMILY "GOLDMONTPLUS " |
1010 |
++#elif defined CONFIG_MSANDYBRIDGE |
1011 |
++#define MODULE_PROC_FAMILY "SANDYBRIDGE " |
1012 |
++#elif defined CONFIG_MIVYBRIDGE |
1013 |
++#define MODULE_PROC_FAMILY "IVYBRIDGE " |
1014 |
++#elif defined CONFIG_MHASWELL |
1015 |
++#define MODULE_PROC_FAMILY "HASWELL " |
1016 |
++#elif defined CONFIG_MBROADWELL |
1017 |
++#define MODULE_PROC_FAMILY "BROADWELL " |
1018 |
++#elif defined CONFIG_MSKYLAKE |
1019 |
++#define MODULE_PROC_FAMILY "SKYLAKE " |
1020 |
++#elif defined CONFIG_MSKYLAKEX |
1021 |
++#define MODULE_PROC_FAMILY "SKYLAKEX " |
1022 |
++#elif defined CONFIG_MCANNONLAKE |
1023 |
++#define MODULE_PROC_FAMILY "CANNONLAKE " |
1024 |
++#elif defined CONFIG_MICELAKE |
1025 |
++#define MODULE_PROC_FAMILY "ICELAKE " |
1026 |
++#elif defined CONFIG_MCASCADELAKE |
1027 |
++#define MODULE_PROC_FAMILY "CASCADELAKE " |
1028 |
+ #elif defined CONFIG_MATOM |
1029 |
+ #define MODULE_PROC_FAMILY "ATOM " |
1030 |
+ #elif defined CONFIG_M686 |
1031 |
+@@ -45,6 +75,28 @@ struct mod_arch_specific { |
1032 |
+ #define MODULE_PROC_FAMILY "K7 " |
1033 |
+ #elif defined CONFIG_MK8 |
1034 |
+ #define MODULE_PROC_FAMILY "K8 " |
1035 |
++#elif defined CONFIG_MK8SSE3 |
1036 |
++#define MODULE_PROC_FAMILY "K8SSE3 " |
1037 |
++#elif defined CONFIG_MK10 |
1038 |
++#define MODULE_PROC_FAMILY "K10 " |
1039 |
++#elif defined CONFIG_MBARCELONA |
1040 |
++#define MODULE_PROC_FAMILY "BARCELONA " |
1041 |
++#elif defined CONFIG_MBOBCAT |
1042 |
++#define MODULE_PROC_FAMILY "BOBCAT " |
1043 |
++#elif defined CONFIG_MBULLDOZER |
1044 |
++#define MODULE_PROC_FAMILY "BULLDOZER " |
1045 |
++#elif defined CONFIG_MPILEDRIVER |
1046 |
++#define MODULE_PROC_FAMILY "PILEDRIVER " |
1047 |
++#elif defined CONFIG_MSTEAMROLLER |
1048 |
++#define MODULE_PROC_FAMILY "STEAMROLLER " |
1049 |
++#elif defined CONFIG_MJAGUAR |
1050 |
++#define MODULE_PROC_FAMILY "JAGUAR " |
1051 |
++#elif defined CONFIG_MEXCAVATOR |
1052 |
++#define MODULE_PROC_FAMILY "EXCAVATOR " |
1053 |
++#elif defined CONFIG_MZEN |
1054 |
++#define MODULE_PROC_FAMILY "ZEN " |
1055 |
++#elif defined CONFIG_MZEN2 |
1056 |
++#define MODULE_PROC_FAMILY "ZEN2 " |
1057 |
+ #elif defined CONFIG_MELAN |
1058 |
+ #define MODULE_PROC_FAMILY "ELAN " |
1059 |
+ #elif defined CONFIG_MCRUSOE |
1060 |
+--- a/arch/x86/Kconfig.cpu 2019-12-15 18:16:08.000000000 -0500 |
1061 |
++++ b/arch/x86/Kconfig.cpu 2019-12-17 14:09:03.805642284 -0500 |
1062 |
+@@ -123,6 +123,7 @@ config MPENTIUMM |
1063 |
+ config MPENTIUM4 |
1064 |
+ bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon" |
1065 |
+ depends on X86_32 |
1066 |
++ select X86_P6_NOP |
1067 |
+ ---help--- |
1068 |
+ Select this for Intel Pentium 4 chips. This includes the |
1069 |
+ Pentium 4, Pentium D, P4-based Celeron and Xeon, and |
1070 |
+@@ -155,9 +156,8 @@ config MPENTIUM4 |
1071 |
+ -Paxville |
1072 |
+ -Dempsey |
1073 |
+ |
1074 |
+- |
1075 |
+ config MK6 |
1076 |
+- bool "K6/K6-II/K6-III" |
1077 |
++ bool "AMD K6/K6-II/K6-III" |
1078 |
+ depends on X86_32 |
1079 |
+ ---help--- |
1080 |
+ Select this for an AMD K6-family processor. Enables use of |
1081 |
+@@ -165,7 +165,7 @@ config MK6 |
1082 |
+ flags to GCC. |
1083 |
+ |
1084 |
+ config MK7 |
1085 |
+- bool "Athlon/Duron/K7" |
1086 |
++ bool "AMD Athlon/Duron/K7" |
1087 |
+ depends on X86_32 |
1088 |
+ ---help--- |
1089 |
+ Select this for an AMD Athlon K7-family processor. Enables use of |
1090 |
+@@ -173,12 +173,90 @@ config MK7 |
1091 |
+ flags to GCC. |
1092 |
+ |
1093 |
+ config MK8 |
1094 |
+- bool "Opteron/Athlon64/Hammer/K8" |
1095 |
++ bool "AMD Opteron/Athlon64/Hammer/K8" |
1096 |
+ ---help--- |
1097 |
+ Select this for an AMD Opteron or Athlon64 Hammer-family processor. |
1098 |
+ Enables use of some extended instructions, and passes appropriate |
1099 |
+ optimization flags to GCC. |
1100 |
+ |
1101 |
++config MK8SSE3 |
1102 |
++ bool "AMD Opteron/Athlon64/Hammer/K8 with SSE3" |
1103 |
++ ---help--- |
1104 |
++ Select this for improved AMD Opteron or Athlon64 Hammer-family processors. |
1105 |
++ Enables use of some extended instructions, and passes appropriate |
1106 |
++ optimization flags to GCC. |
1107 |
++ |
1108 |
++config MK10 |
1109 |
++ bool "AMD 61xx/7x50/PhenomX3/X4/II/K10" |
1110 |
++ ---help--- |
1111 |
++ Select this for an AMD 61xx Eight-Core Magny-Cours, Athlon X2 7x50, |
1112 |
++ Phenom X3/X4/II, Athlon II X2/X3/X4, or Turion II-family processor. |
1113 |
++ Enables use of some extended instructions, and passes appropriate |
1114 |
++ optimization flags to GCC. |
1115 |
++ |
1116 |
++config MBARCELONA |
1117 |
++ bool "AMD Barcelona" |
1118 |
++ ---help--- |
1119 |
++ Select this for AMD Family 10h Barcelona processors. |
1120 |
++ |
1121 |
++ Enables -march=barcelona |
1122 |
++ |
1123 |
++config MBOBCAT |
1124 |
++ bool "AMD Bobcat" |
1125 |
++ ---help--- |
1126 |
++ Select this for AMD Family 14h Bobcat processors. |
1127 |
++ |
1128 |
++ Enables -march=btver1 |
1129 |
++ |
1130 |
++config MJAGUAR |
1131 |
++ bool "AMD Jaguar" |
1132 |
++ ---help--- |
1133 |
++ Select this for AMD Family 16h Jaguar processors. |
1134 |
++ |
1135 |
++ Enables -march=btver2 |
1136 |
++ |
1137 |
++config MBULLDOZER |
1138 |
++ bool "AMD Bulldozer" |
1139 |
++ ---help--- |
1140 |
++ Select this for AMD Family 15h Bulldozer processors. |
1141 |
++ |
1142 |
++ Enables -march=bdver1 |
1143 |
++ |
1144 |
++config MPILEDRIVER |
1145 |
++ bool "AMD Piledriver" |
1146 |
++ ---help--- |
1147 |
++ Select this for AMD Family 15h Piledriver processors. |
1148 |
++ |
1149 |
++ Enables -march=bdver2 |
1150 |
++ |
1151 |
++config MSTEAMROLLER |
1152 |
++ bool "AMD Steamroller" |
1153 |
++ ---help--- |
1154 |
++ Select this for AMD Family 15h Steamroller processors. |
1155 |
++ |
1156 |
++ Enables -march=bdver3 |
1157 |
++ |
1158 |
++config MEXCAVATOR |
1159 |
++ bool "AMD Excavator" |
1160 |
++ ---help--- |
1161 |
++ Select this for AMD Family 15h Excavator processors. |
1162 |
++ |
1163 |
++ Enables -march=bdver4 |
1164 |
++ |
1165 |
++config MZEN |
1166 |
++ bool "AMD Zen" |
1167 |
++ ---help--- |
1168 |
++ Select this for AMD Family 17h Zen processors. |
1169 |
++ |
1170 |
++ Enables -march=znver1 |
1171 |
++ |
1172 |
++config MZEN2 |
1173 |
++ bool "AMD Zen 2" |
1174 |
++ ---help--- |
1175 |
++ Select this for AMD Family 17h Zen 2 processors. |
1176 |
++ |
1177 |
++ Enables -march=znver2 |
1178 |
++ |
1179 |
+ config MCRUSOE |
1180 |
+ bool "Crusoe" |
1181 |
+ depends on X86_32 |
1182 |
+@@ -260,6 +338,7 @@ config MVIAC7 |
1183 |
+ |
1184 |
+ config MPSC |
1185 |
+ bool "Intel P4 / older Netburst based Xeon" |
1186 |
++ select X86_P6_NOP |
1187 |
+ depends on X86_64 |
1188 |
+ ---help--- |
1189 |
+ Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey |
1190 |
+@@ -269,8 +348,19 @@ config MPSC |
1191 |
+ using the cpu family field |
1192 |
+ in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one. |
1193 |
+ |
1194 |
++config MATOM |
1195 |
++ bool "Intel Atom" |
1196 |
++ select X86_P6_NOP |
1197 |
++ ---help--- |
1198 |
++ |
1199 |
++ Select this for the Intel Atom platform. Intel Atom CPUs have an |
1200 |
++ in-order pipelining architecture and thus can benefit from |
1201 |
++ accordingly optimized code. Use a recent GCC with specific Atom |
1202 |
++ support in order to fully benefit from selecting this option. |
1203 |
++ |
1204 |
+ config MCORE2 |
1205 |
+- bool "Core 2/newer Xeon" |
1206 |
++ bool "Intel Core 2" |
1207 |
++ select X86_P6_NOP |
1208 |
+ ---help--- |
1209 |
+ |
1210 |
+ Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and |
1211 |
+@@ -278,14 +368,133 @@ config MCORE2 |
1212 |
+ family in /proc/cpuinfo. Newer ones have 6 and older ones 15 |
1213 |
+ (not a typo) |
1214 |
+ |
1215 |
+-config MATOM |
1216 |
+- bool "Intel Atom" |
1217 |
++ Enables -march=core2 |
1218 |
++ |
1219 |
++config MNEHALEM |
1220 |
++ bool "Intel Nehalem" |
1221 |
++ select X86_P6_NOP |
1222 |
+ ---help--- |
1223 |
+ |
1224 |
+- Select this for the Intel Atom platform. Intel Atom CPUs have an |
1225 |
+- in-order pipelining architecture and thus can benefit from |
1226 |
+- accordingly optimized code. Use a recent GCC with specific Atom |
1227 |
+- support in order to fully benefit from selecting this option. |
1228 |
++ Select this for 1st Gen Core processors in the Nehalem family. |
1229 |
++ |
1230 |
++ Enables -march=nehalem |
1231 |
++ |
1232 |
++config MWESTMERE |
1233 |
++ bool "Intel Westmere" |
1234 |
++ select X86_P6_NOP |
1235 |
++ ---help--- |
1236 |
++ |
1237 |
++ Select this for the Intel Westmere formerly Nehalem-C family. |
1238 |
++ |
1239 |
++ Enables -march=westmere |
1240 |
++ |
1241 |
++config MSILVERMONT |
1242 |
++ bool "Intel Silvermont" |
1243 |
++ select X86_P6_NOP |
1244 |
++ ---help--- |
1245 |
++ |
1246 |
++ Select this for the Intel Silvermont platform. |
1247 |
++ |
1248 |
++ Enables -march=silvermont |
1249 |
++ |
1250 |
++config MGOLDMONT |
1251 |
++ bool "Intel Goldmont" |
1252 |
++ select X86_P6_NOP |
1253 |
++ ---help--- |
1254 |
++ |
1255 |
++ Select this for the Intel Goldmont platform including Apollo Lake and Denverton. |
1256 |
++ |
1257 |
++ Enables -march=goldmont |
1258 |
++ |
1259 |
++config MGOLDMONTPLUS |
1260 |
++ bool "Intel Goldmont Plus" |
1261 |
++ select X86_P6_NOP |
1262 |
++ ---help--- |
1263 |
++ |
1264 |
++ Select this for the Intel Goldmont Plus platform including Gemini Lake. |
1265 |
++ |
1266 |
++ Enables -march=goldmont-plus |
1267 |
++ |
1268 |
++config MSANDYBRIDGE |
1269 |
++ bool "Intel Sandy Bridge" |
1270 |
++ select X86_P6_NOP |
1271 |
++ ---help--- |
1272 |
++ |
1273 |
++ Select this for 2nd Gen Core processors in the Sandy Bridge family. |
1274 |
++ |
1275 |
++ Enables -march=sandybridge |
1276 |
++ |
1277 |
++config MIVYBRIDGE |
1278 |
++ bool "Intel Ivy Bridge" |
1279 |
++ select X86_P6_NOP |
1280 |
++ ---help--- |
1281 |
++ |
1282 |
++ Select this for 3rd Gen Core processors in the Ivy Bridge family. |
1283 |
++ |
1284 |
++ Enables -march=ivybridge |
1285 |
++ |
1286 |
++config MHASWELL |
1287 |
++ bool "Intel Haswell" |
1288 |
++ select X86_P6_NOP |
1289 |
++ ---help--- |
1290 |
++ |
1291 |
++ Select this for 4th Gen Core processors in the Haswell family. |
1292 |
++ |
1293 |
++ Enables -march=haswell |
1294 |
++ |
1295 |
++config MBROADWELL |
1296 |
++ bool "Intel Broadwell" |
1297 |
++ select X86_P6_NOP |
1298 |
++ ---help--- |
1299 |
++ |
1300 |
++ Select this for 5th Gen Core processors in the Broadwell family. |
1301 |
++ |
1302 |
++ Enables -march=broadwell |
1303 |
++ |
1304 |
++config MSKYLAKE |
1305 |
++ bool "Intel Skylake" |
1306 |
++ select X86_P6_NOP |
1307 |
++ ---help--- |
1308 |
++ |
1309 |
++ Select this for 6th Gen Core processors in the Skylake family. |
1310 |
++ |
1311 |
++ Enables -march=skylake |
1312 |
++ |
1313 |
++config MSKYLAKEX |
1314 |
++ bool "Intel Skylake X" |
1315 |
++ select X86_P6_NOP |
1316 |
++ ---help--- |
1317 |
++ |
1318 |
++ Select this for 6th Gen Core processors in the Skylake X family. |
1319 |
++ |
1320 |
++ Enables -march=skylake-avx512 |
1321 |
++ |
1322 |
++config MCANNONLAKE |
1323 |
++ bool "Intel Cannon Lake" |
1324 |
++ select X86_P6_NOP |
1325 |
++ ---help--- |
1326 |
++ |
1327 |
++ Select this for 8th Gen Core processors |
1328 |
++ |
1329 |
++ Enables -march=cannonlake |
1330 |
++ |
1331 |
++config MICELAKE |
1332 |
++ bool "Intel Ice Lake" |
1333 |
++ select X86_P6_NOP |
1334 |
++ ---help--- |
1335 |
++ |
1336 |
++ Select this for 10th Gen Core processors in the Ice Lake family. |
1337 |
++ |
1338 |
++ Enables -march=icelake-client |
1339 |
++ |
1340 |
++config MCASCADELAKE |
1341 |
++ bool "Intel Cascade Lake" |
1342 |
++ select X86_P6_NOP |
1343 |
++ ---help--- |
1344 |
++ |
1345 |
++ Select this for Xeon processors in the Cascade Lake family. |
1346 |
++ |
1347 |
++ Enables -march=cascadelake |
1348 |
+ |
1349 |
+ config GENERIC_CPU |
1350 |
+ bool "Generic-x86-64" |
1351 |
+@@ -294,6 +503,19 @@ config GENERIC_CPU |
1352 |
+ Generic x86-64 CPU. |
1353 |
+ Run equally well on all x86-64 CPUs. |
1354 |
+ |
1355 |
++config MNATIVE |
1356 |
++ bool "Native optimizations autodetected by GCC" |
1357 |
++ ---help--- |
1358 |
++ |
1359 |
++ GCC 4.2 and above support -march=native, which automatically detects |
1360 |
++ the optimum settings to use based on your processor. -march=native |
1361 |
++ also detects and applies additional settings beyond -march specific |
1362 |
++ to your CPU, (eg. -msse4). Unless you have a specific reason not to |
1363 |
++ (e.g. distcc cross-compiling), you should probably be using |
1364 |
++ -march=native rather than anything listed below. |
1365 |
++ |
1366 |
++ Enables -march=native |
1367 |
++ |
1368 |
+ endchoice |
1369 |
+ |
1370 |
+ config X86_GENERIC |
1371 |
+@@ -318,7 +540,7 @@ config X86_INTERNODE_CACHE_SHIFT |
1372 |
+ config X86_L1_CACHE_SHIFT |
1373 |
+ int |
1374 |
+ default "7" if MPENTIUM4 || MPSC |
1375 |
+- default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU |
1376 |
++ default "6" if MK7 || MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MJAGUAR || MPENTIUMM || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MNATIVE || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU |
1377 |
+ default "4" if MELAN || M486SX || M486 || MGEODEGX1 |
1378 |
+ default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX |
1379 |
+ |
1380 |
+@@ -336,35 +558,36 @@ config X86_ALIGNMENT_16 |
1381 |
+ |
1382 |
+ config X86_INTEL_USERCOPY |
1383 |
+ def_bool y |
1384 |
+- depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 |
1385 |
++ depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK8SSE3 || MK7 || MEFFICEON || MCORE2 || MK10 || MBARCELONA || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MNATIVE |
1386 |
+ |
1387 |
+ config X86_USE_PPRO_CHECKSUM |
1388 |
+ def_bool y |
1389 |
+- depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM |
1390 |
++ depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MK10 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MATOM || MNATIVE |
1391 |
+ |
1392 |
+ config X86_USE_3DNOW |
1393 |
+ def_bool y |
1394 |
+ depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML |
1395 |
+ |
1396 |
+-# |
1397 |
+-# P6_NOPs are a relatively minor optimization that require a family >= |
1398 |
+-# 6 processor, except that it is broken on certain VIA chips. |
1399 |
+-# Furthermore, AMD chips prefer a totally different sequence of NOPs |
1400 |
+-# (which work on all CPUs). In addition, it looks like Virtual PC |
1401 |
+-# does not understand them. |
1402 |
+-# |
1403 |
+-# As a result, disallow these if we're not compiling for X86_64 (these |
1404 |
+-# NOPs do work on all x86-64 capable chips); the list of processors in |
1405 |
+-# the right-hand clause are the cores that benefit from this optimization. |
1406 |
+-# |
1407 |
+ config X86_P6_NOP |
1408 |
+- def_bool y |
1409 |
+- depends on X86_64 |
1410 |
+- depends on (MCORE2 || MPENTIUM4 || MPSC) |
1411 |
++ default n |
1412 |
++ bool "Support for P6_NOPs on Intel chips" |
1413 |
++ depends on (MCORE2 || MPENTIUM4 || MPSC || MATOM || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MNATIVE) |
1414 |
++ ---help--- |
1415 |
++ P6_NOPs are a relatively minor optimization that require a family >= |
1416 |
++ 6 processor, except that it is broken on certain VIA chips. |
1417 |
++ Furthermore, AMD chips prefer a totally different sequence of NOPs |
1418 |
++ (which work on all CPUs). In addition, it looks like Virtual PC |
1419 |
++ does not understand them. |
1420 |
++ |
1421 |
++ As a result, disallow these if we're not compiling for X86_64 (these |
1422 |
++ NOPs do work on all x86-64 capable chips); the list of processors in |
1423 |
++ the right-hand clause are the cores that benefit from this optimization. |
1424 |
++ |
1425 |
++ Say Y if you have Intel CPU newer than Pentium Pro, N otherwise. |
1426 |
+ |
1427 |
+ config X86_TSC |
1428 |
+ def_bool y |
1429 |
+- depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64 |
1430 |
++ depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MNATIVE || MATOM) || X86_64 |
1431 |
+ |
1432 |
+ config X86_CMPXCHG64 |
1433 |
+ def_bool y |
1434 |
+@@ -374,7 +597,7 @@ config X86_CMPXCHG64 |
1435 |
+ # generates cmov. |
1436 |
+ config X86_CMOV |
1437 |
+ def_bool y |
1438 |
+- depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX) |
1439 |
++ depends on (MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MJAGUAR || MK7 || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MNATIVE || MATOM || MGEODE_LX) |
1440 |
+ |
1441 |
+ config X86_MINIMUM_CPU_FAMILY |
1442 |
+ int |
1443 |
+--- a/arch/x86/Makefile 2019-12-15 18:16:08.000000000 -0500 |
1444 |
++++ b/arch/x86/Makefile 2019-12-17 14:03:55.972204960 -0500 |
1445 |
+@@ -119,13 +119,53 @@ else |
1446 |
+ KBUILD_CFLAGS += $(call cc-option,-mskip-rax-setup) |
1447 |
+ |
1448 |
+ # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu) |
1449 |
++ cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native) |
1450 |
+ cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8) |
1451 |
++ cflags-$(CONFIG_MK8SSE3) += $(call cc-option,-march=k8-sse3,-mtune=k8) |
1452 |
++ cflags-$(CONFIG_MK10) += $(call cc-option,-march=amdfam10) |
1453 |
++ cflags-$(CONFIG_MBARCELONA) += $(call cc-option,-march=barcelona) |
1454 |
++ cflags-$(CONFIG_MBOBCAT) += $(call cc-option,-march=btver1) |
1455 |
++ cflags-$(CONFIG_MJAGUAR) += $(call cc-option,-march=btver2) |
1456 |
++ cflags-$(CONFIG_MBULLDOZER) += $(call cc-option,-march=bdver1) |
1457 |
++ cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-march=bdver2) |
1458 |
++ cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-march=bdver3) |
1459 |
++ cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4) |
1460 |
++ cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1) |
1461 |
++ cflags-$(CONFIG_MZEN2) += $(call cc-option,-march=znver2) |
1462 |
+ cflags-$(CONFIG_MPSC) += $(call cc-option,-march=nocona) |
1463 |
+ |
1464 |
+ cflags-$(CONFIG_MCORE2) += \ |
1465 |
+- $(call cc-option,-march=core2,$(call cc-option,-mtune=generic)) |
1466 |
+- cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom) \ |
1467 |
+- $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic)) |
1468 |
++ $(call cc-option,-march=core2,$(call cc-option,-mtune=core2)) |
1469 |
++ cflags-$(CONFIG_MNEHALEM) += \ |
1470 |
++ $(call cc-option,-march=nehalem,$(call cc-option,-mtune=nehalem)) |
1471 |
++ cflags-$(CONFIG_MWESTMERE) += \ |
1472 |
++ $(call cc-option,-march=westmere,$(call cc-option,-mtune=westmere)) |
1473 |
++ cflags-$(CONFIG_MSILVERMONT) += \ |
1474 |
++ $(call cc-option,-march=silvermont,$(call cc-option,-mtune=silvermont)) |
1475 |
++ cflags-$(CONFIG_MGOLDMONT) += \ |
1476 |
++ $(call cc-option,-march=goldmont,$(call cc-option,-mtune=goldmont)) |
1477 |
++ cflags-$(CONFIG_MGOLDMONTPLUS) += \ |
1478 |
++ $(call cc-option,-march=goldmont-plus,$(call cc-option,-mtune=goldmont-plus)) |
1479 |
++ cflags-$(CONFIG_MSANDYBRIDGE) += \ |
1480 |
++ $(call cc-option,-march=sandybridge,$(call cc-option,-mtune=sandybridge)) |
1481 |
++ cflags-$(CONFIG_MIVYBRIDGE) += \ |
1482 |
++ $(call cc-option,-march=ivybridge,$(call cc-option,-mtune=ivybridge)) |
1483 |
++ cflags-$(CONFIG_MHASWELL) += \ |
1484 |
++ $(call cc-option,-march=haswell,$(call cc-option,-mtune=haswell)) |
1485 |
++ cflags-$(CONFIG_MBROADWELL) += \ |
1486 |
++ $(call cc-option,-march=broadwell,$(call cc-option,-mtune=broadwell)) |
1487 |
++ cflags-$(CONFIG_MSKYLAKE) += \ |
1488 |
++ $(call cc-option,-march=skylake,$(call cc-option,-mtune=skylake)) |
1489 |
++ cflags-$(CONFIG_MSKYLAKEX) += \ |
1490 |
++ $(call cc-option,-march=skylake-avx512,$(call cc-option,-mtune=skylake-avx512)) |
1491 |
++ cflags-$(CONFIG_MCANNONLAKE) += \ |
1492 |
++ $(call cc-option,-march=cannonlake,$(call cc-option,-mtune=cannonlake)) |
1493 |
++ cflags-$(CONFIG_MICELAKE) += \ |
1494 |
++ $(call cc-option,-march=icelake-client,$(call cc-option,-mtune=icelake-client)) |
1495 |
++ cflags-$(CONFIG_MCASCADELAKE) += \ |
1496 |
++ $(call cc-option,-march=cascadelake,$(call cc-option,-mtune=cascadelake)) |
1497 |
++ cflags-$(CONFIG_MATOM) += $(call cc-option,-march=bonnell) \ |
1498 |
++ $(call cc-option,-mtune=bonnell,$(call cc-option,-mtune=generic)) |
1499 |
+ cflags-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=generic) |
1500 |
+ KBUILD_CFLAGS += $(cflags-y) |
1501 |
+ |
1502 |
+--- a/arch/x86/Makefile_32.cpu 2019-12-15 18:16:08.000000000 -0500 |
1503 |
++++ b/arch/x86/Makefile_32.cpu 2019-12-17 14:03:55.972204960 -0500 |
1504 |
+@@ -24,7 +24,19 @@ cflags-$(CONFIG_MK6) += -march=k6 |
1505 |
+ # Please note, that patches that add -march=athlon-xp and friends are pointless. |
1506 |
+ # They make zero difference whatsosever to performance at this time. |
1507 |
+ cflags-$(CONFIG_MK7) += -march=athlon |
1508 |
++cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native) |
1509 |
+ cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8,-march=athlon) |
1510 |
++cflags-$(CONFIG_MK8SSE3) += $(call cc-option,-march=k8-sse3,-march=athlon) |
1511 |
++cflags-$(CONFIG_MK10) += $(call cc-option,-march=amdfam10,-march=athlon) |
1512 |
++cflags-$(CONFIG_MBARCELONA) += $(call cc-option,-march=barcelona,-march=athlon) |
1513 |
++cflags-$(CONFIG_MBOBCAT) += $(call cc-option,-march=btver1,-march=athlon) |
1514 |
++cflags-$(CONFIG_MJAGUAR) += $(call cc-option,-march=btver2,-march=athlon) |
1515 |
++cflags-$(CONFIG_MBULLDOZER) += $(call cc-option,-march=bdver1,-march=athlon) |
1516 |
++cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-march=bdver2,-march=athlon) |
1517 |
++cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-march=bdver3,-march=athlon) |
1518 |
++cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4,-march=athlon) |
1519 |
++cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1,-march=athlon) |
1520 |
++cflags-$(CONFIG_MZEN2) += $(call cc-option,-march=znver2,-march=athlon) |
1521 |
+ cflags-$(CONFIG_MCRUSOE) += -march=i686 -falign-functions=0 -falign-jumps=0 -falign-loops=0 |
1522 |
+ cflags-$(CONFIG_MEFFICEON) += -march=i686 $(call tune,pentium3) -falign-functions=0 -falign-jumps=0 -falign-loops=0 |
1523 |
+ cflags-$(CONFIG_MWINCHIPC6) += $(call cc-option,-march=winchip-c6,-march=i586) |
1524 |
+@@ -33,8 +45,22 @@ cflags-$(CONFIG_MCYRIXIII) += $(call cc- |
1525 |
+ cflags-$(CONFIG_MVIAC3_2) += $(call cc-option,-march=c3-2,-march=i686) |
1526 |
+ cflags-$(CONFIG_MVIAC7) += -march=i686 |
1527 |
+ cflags-$(CONFIG_MCORE2) += -march=i686 $(call tune,core2) |
1528 |
+-cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom,$(call cc-option,-march=core2,-march=i686)) \ |
1529 |
+- $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic)) |
1530 |
++cflags-$(CONFIG_MNEHALEM) += -march=i686 $(call tune,nehalem) |
1531 |
++cflags-$(CONFIG_MWESTMERE) += -march=i686 $(call tune,westmere) |
1532 |
++cflags-$(CONFIG_MSILVERMONT) += -march=i686 $(call tune,silvermont) |
1533 |
++cflags-$(CONFIG_MGOLDMONT) += -march=i686 $(call tune,goldmont) |
1534 |
++cflags-$(CONFIG_MGOLDMONTPLUS) += -march=i686 $(call tune,goldmont-plus) |
1535 |
++cflags-$(CONFIG_MSANDYBRIDGE) += -march=i686 $(call tune,sandybridge) |
1536 |
++cflags-$(CONFIG_MIVYBRIDGE) += -march=i686 $(call tune,ivybridge) |
1537 |
++cflags-$(CONFIG_MHASWELL) += -march=i686 $(call tune,haswell) |
1538 |
++cflags-$(CONFIG_MBROADWELL) += -march=i686 $(call tune,broadwell) |
1539 |
++cflags-$(CONFIG_MSKYLAKE) += -march=i686 $(call tune,skylake) |
1540 |
++cflags-$(CONFIG_MSKYLAKEX) += -march=i686 $(call tune,skylake-avx512) |
1541 |
++cflags-$(CONFIG_MCANNONLAKE) += -march=i686 $(call tune,cannonlake) |
1542 |
++cflags-$(CONFIG_MICELAKE) += -march=i686 $(call tune,icelake-client) |
1543 |
++cflags-$(CONFIG_MCASCADELAKE) += -march=i686 $(call tune,cascadelake) |
1544 |
++cflags-$(CONFIG_MATOM) += $(call cc-option,-march=bonnell,$(call cc-option,-march=core2,-march=i686)) \ |
1545 |
++ $(call cc-option,-mtune=bonnell,$(call cc-option,-mtune=generic)) |
1546 |
+ |
1547 |
+ # AMD Elan support |
1548 |
+ cflags-$(CONFIG_MELAN) += -march=i486 |