Gentoo Archives: gentoo-commits

From: Mike Pagano <mpagano@g.o>
To: gentoo-commits@l.g.o
Subject: [gentoo-commits] proj/linux-patches:5.10 commit in: /
Date: Wed, 07 Jul 2021 13:13:14
Message-Id: 1625663578.b2fdf6344cc68032ac329ca3e3cc916dadc0420c.mpagano@gentoo
1 commit: b2fdf6344cc68032ac329ca3e3cc916dadc0420c
2 Author: Mike Pagano <mpagano <AT> gentoo <DOT> org>
3 AuthorDate: Wed Jul 7 13:12:58 2021 +0000
4 Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org>
5 CommitDate: Wed Jul 7 13:12:58 2021 +0000
6 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=b2fdf634
7
8 Linux patch 5.10.48
9
10 Signed-off-by: Mike Pagano <mpagano <AT> gentoo.org>
11
12 0000_README | 4 ++
13 1047_linux-5.10.48.patch | 123 +++++++++++++++++++++++++++++++++++++++++++++++
14 2 files changed, 127 insertions(+)
15
16 diff --git a/0000_README b/0000_README
17 index 58e20cf..dc7b9b6 100644
18 --- a/0000_README
19 +++ b/0000_README
20 @@ -231,6 +231,10 @@ Patch: 1046_linux-5.10.47.patch
21 From: http://www.kernel.org
22 Desc: Linux 5.10.47
23
24 +Patch: 1047_linux-5.10.48.patch
25 +From: http://www.kernel.org
26 +Desc: Linux 5.10.48
27 +
28 Patch: 1500_XATTR_USER_PREFIX.patch
29 From: https://bugs.gentoo.org/show_bug.cgi?id=470644
30 Desc: Support for namespace user.pax.* on tmpfs.
31
32 diff --git a/1047_linux-5.10.48.patch b/1047_linux-5.10.48.patch
33 new file mode 100644
34 index 0000000..fb36685
35 --- /dev/null
36 +++ b/1047_linux-5.10.48.patch
37 @@ -0,0 +1,123 @@
38 +diff --git a/Makefile b/Makefile
39 +index fb2937bca41b3..52dcfe3371c4c 100644
40 +--- a/Makefile
41 ++++ b/Makefile
42 +@@ -1,7 +1,7 @@
43 + # SPDX-License-Identifier: GPL-2.0
44 + VERSION = 5
45 + PATCHLEVEL = 10
46 +-SUBLEVEL = 47
47 ++SUBLEVEL = 48
48 + EXTRAVERSION =
49 + NAME = Dare mighty things
50 +
51 +diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
52 +index ef56780022c3e..d1ac2de41ea8a 100644
53 +--- a/arch/x86/include/asm/kvm_host.h
54 ++++ b/arch/x86/include/asm/kvm_host.h
55 +@@ -296,6 +296,7 @@ union kvm_mmu_extended_role {
56 + unsigned int cr4_pke:1;
57 + unsigned int cr4_smap:1;
58 + unsigned int cr4_smep:1;
59 ++ unsigned int cr4_la57:1;
60 + unsigned int maxphyaddr:6;
61 + };
62 + };
63 +diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
64 +index 6b794344c02db..f2eeaf197294d 100644
65 +--- a/arch/x86/kvm/mmu/mmu.c
66 ++++ b/arch/x86/kvm/mmu/mmu.c
67 +@@ -4442,6 +4442,7 @@ static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
68 + ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
69 + ext.cr4_pse = !!is_pse(vcpu);
70 + ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
71 ++ ext.cr4_la57 = !!kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
72 + ext.maxphyaddr = cpuid_maxphyaddr(vcpu);
73 +
74 + ext.valid = 1;
75 +diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
76 +index 14751c7ccd1f4..d1300fc003ed7 100644
77 +--- a/drivers/gpio/Kconfig
78 ++++ b/drivers/gpio/Kconfig
79 +@@ -1337,6 +1337,7 @@ config GPIO_TPS68470
80 + config GPIO_TQMX86
81 + tristate "TQ-Systems QTMX86 GPIO"
82 + depends on MFD_TQMX86 || COMPILE_TEST
83 ++ depends on HAS_IOPORT_MAP
84 + select GPIOLIB_IRQCHIP
85 + help
86 + This driver supports GPIO on the TQMX86 IO controller.
87 +@@ -1404,6 +1405,7 @@ menu "PCI GPIO expanders"
88 + config GPIO_AMD8111
89 + tristate "AMD 8111 GPIO driver"
90 + depends on X86 || COMPILE_TEST
91 ++ depends on HAS_IOPORT_MAP
92 + help
93 + The AMD 8111 south bridge contains 32 GPIO pins which can be used.
94 +
95 +diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
96 +index 643f4c557ac2a..ba6ed2a413f51 100644
97 +--- a/drivers/gpio/gpio-mxc.c
98 ++++ b/drivers/gpio/gpio-mxc.c
99 +@@ -361,7 +361,7 @@ static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
100 + ct->chip.irq_unmask = irq_gc_mask_set_bit;
101 + ct->chip.irq_set_type = gpio_set_irq_type;
102 + ct->chip.irq_set_wake = gpio_set_wake_irq;
103 +- ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
104 ++ ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
105 + ct->regs.ack = GPIO_ISR;
106 + ct->regs.mask = GPIO_IMR;
107 +
108 +diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
109 +index 7daa12eec01bb..b4946b595d86e 100644
110 +--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
111 ++++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
112 +@@ -590,7 +590,7 @@ nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
113 + struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
114 + int i;
115 +
116 +- if (!ttm_dma)
117 ++ if (!ttm_dma || !ttm_dma->dma_address)
118 + return;
119 +
120 + /* Don't waste time looping if the object is coherent */
121 +@@ -610,7 +610,7 @@ nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
122 + struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
123 + int i;
124 +
125 +- if (!ttm_dma)
126 ++ if (!ttm_dma || !ttm_dma->dma_address)
127 + return;
128 +
129 + /* Don't waste time looping if the object is coherent */
130 +diff --git a/drivers/infiniband/hw/mlx5/fs.c b/drivers/infiniband/hw/mlx5/fs.c
131 +index 13d50b1781660..b3391ecedda7e 100644
132 +--- a/drivers/infiniband/hw/mlx5/fs.c
133 ++++ b/drivers/infiniband/hw/mlx5/fs.c
134 +@@ -2136,6 +2136,13 @@ static int UVERBS_HANDLER(MLX5_IB_METHOD_FLOW_MATCHER_CREATE)(
135 + if (err)
136 + goto end;
137 +
138 ++ if (obj->ns_type == MLX5_FLOW_NAMESPACE_FDB &&
139 ++ mlx5_eswitch_mode(dev->mdev->priv.eswitch) !=
140 ++ MLX5_ESWITCH_OFFLOADS) {
141 ++ err = -EINVAL;
142 ++ goto end;
143 ++ }
144 ++
145 + uobj->object = obj;
146 + obj->mdev = dev->mdev;
147 + atomic_set(&obj->usecnt, 0);
148 +diff --git a/drivers/scsi/sr.c b/drivers/scsi/sr.c
149 +index fd4b582110b29..77961f0583674 100644
150 +--- a/drivers/scsi/sr.c
151 ++++ b/drivers/scsi/sr.c
152 +@@ -220,6 +220,8 @@ static unsigned int sr_get_events(struct scsi_device *sdev)
153 + return DISK_EVENT_EJECT_REQUEST;
154 + else if (med->media_event_code == 2)
155 + return DISK_EVENT_MEDIA_CHANGE;
156 ++ else if (med->media_event_code == 3)
157 ++ return DISK_EVENT_EJECT_REQUEST;
158 + return 0;
159 + }
160 +