Gentoo Archives: gentoo-commits

From: Mike Pagano <mpagano@g.o>
To: gentoo-commits@l.g.o
Subject: [gentoo-commits] proj/linux-patches:4.20 commit in: /
Date: Mon, 18 Feb 2019 23:28:42
Message-Id: 1550532436.bc008124a19efaa1c7bca498375cd34cf6d2e3fe.mpagano@gentoo
1 commit: bc008124a19efaa1c7bca498375cd34cf6d2e3fe
2 Author: Mike Pagano <mpagano <AT> gentoo <DOT> org>
3 AuthorDate: Mon Feb 18 23:27:16 2019 +0000
4 Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org>
5 CommitDate: Mon Feb 18 23:27:16 2019 +0000
6 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=bc008124
7
8 proj/linux-patches: cpu optimization patch for gcc >= 8
9
10 This patch adds addl CPU options to the Linux kernel accessible under:
11 Processor type and features --->
12 Processor family --->
13
14 Signed-off-by: Mike Pagano <mpagano <AT> gentoo.org>
15
16 0000_README | 4 +
17 5011_enable-cpu-optimizations-for-gcc8.patch | 575 +++++++++++++++++++++++++++
18 2 files changed, 579 insertions(+)
19
20 diff --git a/0000_README b/0000_README
21 index a248fc7..35bccfa 100644
22 --- a/0000_README
23 +++ b/0000_README
24 @@ -110,3 +110,7 @@ Desc: Add Gentoo Linux support config settings and defaults.
25 Patch: 5010_enable-additional-cpu-optimizations-for-gcc-4.9.patch
26 From: https://github.com/graysky2/kernel_gcc_patch/
27 Desc: Kernel patch enables gcc >= v4.13 optimizations for additional CPUs.
28 +
29 +Patch: 5011_enable-cpu-optimizations-for-gcc8.patch
30 +From: https://github.com/graysky2/kernel_gcc_patch/
31 +Desc: Kernel patch for >= gccv8 enables kernel >= v4.13 optimizations for additional CPUs.
32
33 diff --git a/5011_enable-cpu-optimizations-for-gcc8.patch b/5011_enable-cpu-optimizations-for-gcc8.patch
34 new file mode 100644
35 index 0000000..9087ee6
36 --- /dev/null
37 +++ b/5011_enable-cpu-optimizations-for-gcc8.patch
38 @@ -0,0 +1,575 @@
39 +WARNING
40 +This patch works with gcc versions 8.1+ and with kernel version 4.13+ and should
41 +NOT be applied when compiling on older versions of gcc due to key name changes
42 +of the march flags introduced with the version 4.9 release of gcc.[1]
43 +
44 +Use the older version of this patch hosted on the same github for older
45 +versions of gcc.
46 +
47 +FEATURES
48 +This patch adds additional CPU options to the Linux kernel accessible under:
49 + Processor type and features --->
50 + Processor family --->
51 +
52 +The expanded microarchitectures include:
53 +* AMD Improved K8-family
54 +* AMD K10-family
55 +* AMD Family 10h (Barcelona)
56 +* AMD Family 14h (Bobcat)
57 +* AMD Family 16h (Jaguar)
58 +* AMD Family 15h (Bulldozer)
59 +* AMD Family 15h (Piledriver)
60 +* AMD Family 15h (Steamroller)
61 +* AMD Family 15h (Excavator)
62 +* AMD Family 17h (Zen)
63 +* Intel Silvermont low-power processors
64 +* Intel 1st Gen Core i3/i5/i7 (Nehalem)
65 +* Intel 1.5 Gen Core i3/i5/i7 (Westmere)
66 +* Intel 2nd Gen Core i3/i5/i7 (Sandybridge)
67 +* Intel 3rd Gen Core i3/i5/i7 (Ivybridge)
68 +* Intel 4th Gen Core i3/i5/i7 (Haswell)
69 +* Intel 5th Gen Core i3/i5/i7 (Broadwell)
70 +* Intel 6th Gen Core i3/i5/i7 (Skylake)
71 +* Intel 6th Gen Core i7/i9 (Skylake X)
72 +* Intel 8th Gen Core i3/i5/i7 (Cannon Lake)
73 +* Intel 8th Gen Core i7/i9 (Ice Lake)
74 +
75 +It also offers to compile passing the 'native' option which, "selects the CPU
76 +to generate code for at compilation time by determining the processor type of
77 +the compiling machine. Using -march=native enables all instruction subsets
78 +supported by the local machine and will produce code optimized for the local
79 +machine under the constraints of the selected instruction set."[3]
80 +
81 +MINOR NOTES
82 +This patch also changes 'atom' to 'bonnell' in accordance with the gcc v4.9
83 +changes. Note that upstream is using the deprecated 'match=atom' flags when I
84 +believe it should use the newer 'march=bonnell' flag for atom processors.[2]
85 +
86 +It is not recommended to compile on Atom-CPUs with the 'native' option.[4] The
87 +recommendation is to use the 'atom' option instead.
88 +
89 +BENEFITS
90 +Small but real speed increases are measurable using a make endpoint comparing
91 +a generic kernel to one built with one of the respective microarchs.
92 +
93 +See the following experimental evidence supporting this statement:
94 +https://github.com/graysky2/kernel_gcc_patch
95 +
96 +REQUIREMENTS
97 +linux version >=3.15
98 +gcc version >=8.1
99 +
100 +ACKNOWLEDGMENTS
101 +This patch builds on the seminal work by Jeroen.[5]
102 +
103 +REFERENCES
104 +1. https://gcc.gnu.org/gcc-4.9/changes.html
105 +2. https://bugzilla.kernel.org/show_bug.cgi?id=77461
106 +3. https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
107 +4. https://github.com/graysky2/kernel_gcc_patch/issues/15
108 +5. http://www.linuxforge.net/docs/linux/linux-gcc.php
109 +
110 +--- a/arch/x86/include/asm/module.h 2018-04-01 17:20:27.000000000 -0400
111 ++++ b/arch/x86/include/asm/module.h 2018-05-09 17:38:40.686541611 -0400
112 +@@ -25,6 +25,30 @@ struct mod_arch_specific {
113 + #define MODULE_PROC_FAMILY "586MMX "
114 + #elif defined CONFIG_MCORE2
115 + #define MODULE_PROC_FAMILY "CORE2 "
116 ++#elif defined CONFIG_MNATIVE
117 ++#define MODULE_PROC_FAMILY "NATIVE "
118 ++#elif defined CONFIG_MNEHALEM
119 ++#define MODULE_PROC_FAMILY "NEHALEM "
120 ++#elif defined CONFIG_MWESTMERE
121 ++#define MODULE_PROC_FAMILY "WESTMERE "
122 ++#elif defined CONFIG_MSILVERMONT
123 ++#define MODULE_PROC_FAMILY "SILVERMONT "
124 ++#elif defined CONFIG_MSANDYBRIDGE
125 ++#define MODULE_PROC_FAMILY "SANDYBRIDGE "
126 ++#elif defined CONFIG_MIVYBRIDGE
127 ++#define MODULE_PROC_FAMILY "IVYBRIDGE "
128 ++#elif defined CONFIG_MHASWELL
129 ++#define MODULE_PROC_FAMILY "HASWELL "
130 ++#elif defined CONFIG_MBROADWELL
131 ++#define MODULE_PROC_FAMILY "BROADWELL "
132 ++#elif defined CONFIG_MSKYLAKE
133 ++#define MODULE_PROC_FAMILY "SKYLAKE "
134 ++#elif defined CONFIG_MSKYLAKEX
135 ++#define MODULE_PROC_FAMILY "SKYLAKEX "
136 ++#elif defined CONFIG_MCANNONLAKE
137 ++#define MODULE_PROC_FAMILY "CANNONLAKE "
138 ++#elif defined CONFIG_MICELAKE
139 ++#define MODULE_PROC_FAMILY "ICELAKE "
140 + #elif defined CONFIG_MATOM
141 + #define MODULE_PROC_FAMILY "ATOM "
142 + #elif defined CONFIG_M686
143 +@@ -43,6 +67,26 @@ struct mod_arch_specific {
144 + #define MODULE_PROC_FAMILY "K7 "
145 + #elif defined CONFIG_MK8
146 + #define MODULE_PROC_FAMILY "K8 "
147 ++#elif defined CONFIG_MK8SSE3
148 ++#define MODULE_PROC_FAMILY "K8SSE3 "
149 ++#elif defined CONFIG_MK10
150 ++#define MODULE_PROC_FAMILY "K10 "
151 ++#elif defined CONFIG_MBARCELONA
152 ++#define MODULE_PROC_FAMILY "BARCELONA "
153 ++#elif defined CONFIG_MBOBCAT
154 ++#define MODULE_PROC_FAMILY "BOBCAT "
155 ++#elif defined CONFIG_MBULLDOZER
156 ++#define MODULE_PROC_FAMILY "BULLDOZER "
157 ++#elif defined CONFIG_MPILEDRIVER
158 ++#define MODULE_PROC_FAMILY "PILEDRIVER "
159 ++#elif defined CONFIG_MSTEAMROLLER
160 ++#define MODULE_PROC_FAMILY "STEAMROLLER "
161 ++#elif defined CONFIG_MJAGUAR
162 ++#define MODULE_PROC_FAMILY "JAGUAR "
163 ++#elif defined CONFIG_MEXCAVATOR
164 ++#define MODULE_PROC_FAMILY "EXCAVATOR "
165 ++#elif defined CONFIG_MZEN
166 ++#define MODULE_PROC_FAMILY "ZEN "
167 + #elif defined CONFIG_MELAN
168 + #define MODULE_PROC_FAMILY "ELAN "
169 + #elif defined CONFIG_MCRUSOE
170 +--- a/arch/x86/Kconfig.cpu 2018-04-01 17:20:27.000000000 -0400
171 ++++ b/arch/x86/Kconfig.cpu 2018-05-07 17:44:43.306767555 -0400
172 +@@ -116,6 +116,7 @@ config MPENTIUMM
173 + config MPENTIUM4
174 + bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
175 + depends on X86_32
176 ++ select X86_P6_NOP
177 + ---help---
178 + Select this for Intel Pentium 4 chips. This includes the
179 + Pentium 4, Pentium D, P4-based Celeron and Xeon, and
180 +@@ -148,9 +149,8 @@ config MPENTIUM4
181 + -Paxville
182 + -Dempsey
183 +
184 +-
185 + config MK6
186 +- bool "K6/K6-II/K6-III"
187 ++ bool "AMD K6/K6-II/K6-III"
188 + depends on X86_32
189 + ---help---
190 + Select this for an AMD K6-family processor. Enables use of
191 +@@ -158,7 +158,7 @@ config MK6
192 + flags to GCC.
193 +
194 + config MK7
195 +- bool "Athlon/Duron/K7"
196 ++ bool "AMD Athlon/Duron/K7"
197 + depends on X86_32
198 + ---help---
199 + Select this for an AMD Athlon K7-family processor. Enables use of
200 +@@ -166,12 +166,83 @@ config MK7
201 + flags to GCC.
202 +
203 + config MK8
204 +- bool "Opteron/Athlon64/Hammer/K8"
205 ++ bool "AMD Opteron/Athlon64/Hammer/K8"
206 + ---help---
207 + Select this for an AMD Opteron or Athlon64 Hammer-family processor.
208 + Enables use of some extended instructions, and passes appropriate
209 + optimization flags to GCC.
210 +
211 ++config MK8SSE3
212 ++ bool "AMD Opteron/Athlon64/Hammer/K8 with SSE3"
213 ++ ---help---
214 ++ Select this for improved AMD Opteron or Athlon64 Hammer-family processors.
215 ++ Enables use of some extended instructions, and passes appropriate
216 ++ optimization flags to GCC.
217 ++
218 ++config MK10
219 ++ bool "AMD 61xx/7x50/PhenomX3/X4/II/K10"
220 ++ ---help---
221 ++ Select this for an AMD 61xx Eight-Core Magny-Cours, Athlon X2 7x50,
222 ++ Phenom X3/X4/II, Athlon II X2/X3/X4, or Turion II-family processor.
223 ++ Enables use of some extended instructions, and passes appropriate
224 ++ optimization flags to GCC.
225 ++
226 ++config MBARCELONA
227 ++ bool "AMD Barcelona"
228 ++ ---help---
229 ++ Select this for AMD Family 10h Barcelona processors.
230 ++
231 ++ Enables -march=barcelona
232 ++
233 ++config MBOBCAT
234 ++ bool "AMD Bobcat"
235 ++ ---help---
236 ++ Select this for AMD Family 14h Bobcat processors.
237 ++
238 ++ Enables -march=btver1
239 ++
240 ++config MJAGUAR
241 ++ bool "AMD Jaguar"
242 ++ ---help---
243 ++ Select this for AMD Family 16h Jaguar processors.
244 ++
245 ++ Enables -march=btver2
246 ++
247 ++config MBULLDOZER
248 ++ bool "AMD Bulldozer"
249 ++ ---help---
250 ++ Select this for AMD Family 15h Bulldozer processors.
251 ++
252 ++ Enables -march=bdver1
253 ++
254 ++config MPILEDRIVER
255 ++ bool "AMD Piledriver"
256 ++ ---help---
257 ++ Select this for AMD Family 15h Piledriver processors.
258 ++
259 ++ Enables -march=bdver2
260 ++
261 ++config MSTEAMROLLER
262 ++ bool "AMD Steamroller"
263 ++ ---help---
264 ++ Select this for AMD Family 15h Steamroller processors.
265 ++
266 ++ Enables -march=bdver3
267 ++
268 ++config MEXCAVATOR
269 ++ bool "AMD Excavator"
270 ++ ---help---
271 ++ Select this for AMD Family 15h Excavator processors.
272 ++
273 ++ Enables -march=bdver4
274 ++
275 ++config MZEN
276 ++ bool "AMD Zen"
277 ++ ---help---
278 ++ Select this for AMD Family 17h Zen processors.
279 ++
280 ++ Enables -march=znver1
281 ++
282 + config MCRUSOE
283 + bool "Crusoe"
284 + depends on X86_32
285 +@@ -253,6 +324,7 @@ config MVIAC7
286 +
287 + config MPSC
288 + bool "Intel P4 / older Netburst based Xeon"
289 ++ select X86_P6_NOP
290 + depends on X86_64
291 + ---help---
292 + Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
293 +@@ -262,8 +334,19 @@ config MPSC
294 + using the cpu family field
295 + in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.
296 +
297 ++config MATOM
298 ++ bool "Intel Atom"
299 ++ select X86_P6_NOP
300 ++ ---help---
301 ++
302 ++ Select this for the Intel Atom platform. Intel Atom CPUs have an
303 ++ in-order pipelining architecture and thus can benefit from
304 ++ accordingly optimized code. Use a recent GCC with specific Atom
305 ++ support in order to fully benefit from selecting this option.
306 ++
307 + config MCORE2
308 +- bool "Core 2/newer Xeon"
309 ++ bool "Intel Core 2"
310 ++ select X86_P6_NOP
311 + ---help---
312 +
313 + Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and
314 +@@ -271,14 +354,106 @@ config MCORE2
315 + family in /proc/cpuinfo. Newer ones have 6 and older ones 15
316 + (not a typo)
317 +
318 +-config MATOM
319 +- bool "Intel Atom"
320 ++ Enables -march=core2
321 ++
322 ++config MNEHALEM
323 ++ bool "Intel Nehalem"
324 ++ select X86_P6_NOP
325 + ---help---
326 +
327 +- Select this for the Intel Atom platform. Intel Atom CPUs have an
328 +- in-order pipelining architecture and thus can benefit from
329 +- accordingly optimized code. Use a recent GCC with specific Atom
330 +- support in order to fully benefit from selecting this option.
331 ++ Select this for 1st Gen Core processors in the Nehalem family.
332 ++
333 ++ Enables -march=nehalem
334 ++
335 ++config MWESTMERE
336 ++ bool "Intel Westmere"
337 ++ select X86_P6_NOP
338 ++ ---help---
339 ++
340 ++ Select this for the Intel Westmere formerly Nehalem-C family.
341 ++
342 ++ Enables -march=westmere
343 ++
344 ++config MSILVERMONT
345 ++ bool "Intel Silvermont"
346 ++ select X86_P6_NOP
347 ++ ---help---
348 ++
349 ++ Select this for the Intel Silvermont platform.
350 ++
351 ++ Enables -march=silvermont
352 ++
353 ++config MSANDYBRIDGE
354 ++ bool "Intel Sandy Bridge"
355 ++ select X86_P6_NOP
356 ++ ---help---
357 ++
358 ++ Select this for 2nd Gen Core processors in the Sandy Bridge family.
359 ++
360 ++ Enables -march=sandybridge
361 ++
362 ++config MIVYBRIDGE
363 ++ bool "Intel Ivy Bridge"
364 ++ select X86_P6_NOP
365 ++ ---help---
366 ++
367 ++ Select this for 3rd Gen Core processors in the Ivy Bridge family.
368 ++
369 ++ Enables -march=ivybridge
370 ++
371 ++config MHASWELL
372 ++ bool "Intel Haswell"
373 ++ select X86_P6_NOP
374 ++ ---help---
375 ++
376 ++ Select this for 4th Gen Core processors in the Haswell family.
377 ++
378 ++ Enables -march=haswell
379 ++
380 ++config MBROADWELL
381 ++ bool "Intel Broadwell"
382 ++ select X86_P6_NOP
383 ++ ---help---
384 ++
385 ++ Select this for 5th Gen Core processors in the Broadwell family.
386 ++
387 ++ Enables -march=broadwell
388 ++
389 ++config MSKYLAKE
390 ++ bool "Intel Skylake"
391 ++ select X86_P6_NOP
392 ++ ---help---
393 ++
394 ++ Select this for 6th Gen Core processors in the Skylake family.
395 ++
396 ++ Enables -march=skylake
397 ++
398 ++config MSKYLAKEX
399 ++ bool "Intel Skylake X"
400 ++ select X86_P6_NOP
401 ++ ---help---
402 ++
403 ++ Select this for 6th Gen Core processors in the Skylake X family.
404 ++
405 ++ Enables -march=skylake-avx512
406 ++
407 ++config MCANNONLAKE
408 ++ bool "Intel Cannon Lake"
409 ++ select X86_P6_NOP
410 ++ ---help---
411 ++
412 ++ Select this for 8th Gen Core processors
413 ++
414 ++ Enables -march=cannonlake
415 ++
416 ++config MICELAKE
417 ++ bool "Intel Ice Lake"
418 ++ select X86_P6_NOP
419 ++ ---help---
420 ++
421 ++ Select this for 8th Gen Core processors in the Ice Lake family.
422 ++
423 ++ Enables -march=icelake
424 +
425 + config GENERIC_CPU
426 + bool "Generic-x86-64"
427 +@@ -287,6 +462,19 @@ config GENERIC_CPU
428 + Generic x86-64 CPU.
429 + Run equally well on all x86-64 CPUs.
430 +
431 ++config MNATIVE
432 ++ bool "Native optimizations autodetected by GCC"
433 ++ ---help---
434 ++
435 ++ GCC 4.2 and above support -march=native, which automatically detects
436 ++ the optimum settings to use based on your processor. -march=native
437 ++ also detects and applies additional settings beyond -march specific
438 ++ to your CPU, (eg. -msse4). Unless you have a specific reason not to
439 ++ (e.g. distcc cross-compiling), you should probably be using
440 ++ -march=native rather than anything listed below.
441 ++
442 ++ Enables -march=native
443 ++
444 + endchoice
445 +
446 + config X86_GENERIC
447 +@@ -311,7 +499,7 @@ config X86_INTERNODE_CACHE_SHIFT
448 + config X86_L1_CACHE_SHIFT
449 + int
450 + default "7" if MPENTIUM4 || MPSC
451 +- default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
452 ++ default "6" if MK7 || MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MJAGUAR || MPENTIUMM || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MNATIVE || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
453 + default "4" if MELAN || M486 || MGEODEGX1
454 + default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
455 +
456 +@@ -329,35 +517,36 @@ config X86_ALIGNMENT_16
457 +
458 + config X86_INTEL_USERCOPY
459 + def_bool y
460 +- depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2
461 ++ depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK8SSE3 || MK7 || MEFFICEON || MCORE2 || MK10 || MBARCELONA || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MNATIVE
462 +
463 + config X86_USE_PPRO_CHECKSUM
464 + def_bool y
465 +- depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM
466 ++ depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MK10 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MATOM || MNATIVE
467 +
468 + config X86_USE_3DNOW
469 + def_bool y
470 + depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML
471 +
472 +-#
473 +-# P6_NOPs are a relatively minor optimization that require a family >=
474 +-# 6 processor, except that it is broken on certain VIA chips.
475 +-# Furthermore, AMD chips prefer a totally different sequence of NOPs
476 +-# (which work on all CPUs). In addition, it looks like Virtual PC
477 +-# does not understand them.
478 +-#
479 +-# As a result, disallow these if we're not compiling for X86_64 (these
480 +-# NOPs do work on all x86-64 capable chips); the list of processors in
481 +-# the right-hand clause are the cores that benefit from this optimization.
482 +-#
483 + config X86_P6_NOP
484 +- def_bool y
485 +- depends on X86_64
486 +- depends on (MCORE2 || MPENTIUM4 || MPSC)
487 ++ default n
488 ++ bool "Support for P6_NOPs on Intel chips"
489 ++ depends on (MCORE2 || MPENTIUM4 || MPSC || MATOM || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MNATIVE)
490 ++ ---help---
491 ++ P6_NOPs are a relatively minor optimization that require a family >=
492 ++ 6 processor, except that it is broken on certain VIA chips.
493 ++ Furthermore, AMD chips prefer a totally different sequence of NOPs
494 ++ (which work on all CPUs). In addition, it looks like Virtual PC
495 ++ does not understand them.
496 ++
497 ++ As a result, disallow these if we're not compiling for X86_64 (these
498 ++ NOPs do work on all x86-64 capable chips); the list of processors in
499 ++ the right-hand clause are the cores that benefit from this optimization.
500 ++
501 ++ Say Y if you have Intel CPU newer than Pentium Pro, N otherwise.
502 +
503 + config X86_TSC
504 + def_bool y
505 +- depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64
506 ++ depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MNATIVE || MATOM) || X86_64
507 +
508 + config X86_CMPXCHG64
509 + def_bool y
510 +@@ -367,7 +556,7 @@ config X86_CMPXCHG64
511 + # generates cmov.
512 + config X86_CMOV
513 + def_bool y
514 +- depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX)
515 ++ depends on (MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MJAGUAR || MK7 || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MNATIVE || MATOM || MGEODE_LX)
516 +
517 + config X86_MINIMUM_CPU_FAMILY
518 + int
519 +--- a/arch/x86/Makefile 2018-04-01 17:20:27.000000000 -0400
520 ++++ b/arch/x86/Makefile 2018-05-07 17:45:55.180101285 -0400
521 +@@ -124,13 +124,46 @@ else
522 + KBUILD_CFLAGS += $(call cc-option,-mskip-rax-setup)
523 +
524 + # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu)
525 ++ cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native)
526 + cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8)
527 ++ cflags-$(CONFIG_MK8SSE3) += $(call cc-option,-march=k8-sse3,-mtune=k8)
528 ++ cflags-$(CONFIG_MK10) += $(call cc-option,-march=amdfam10)
529 ++ cflags-$(CONFIG_MBARCELONA) += $(call cc-option,-march=barcelona)
530 ++ cflags-$(CONFIG_MBOBCAT) += $(call cc-option,-march=btver1)
531 ++ cflags-$(CONFIG_MJAGUAR) += $(call cc-option,-march=btver2)
532 ++ cflags-$(CONFIG_MBULLDOZER) += $(call cc-option,-march=bdver1)
533 ++ cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-march=bdver2)
534 ++ cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-march=bdver3)
535 ++ cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4)
536 ++ cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1)
537 + cflags-$(CONFIG_MPSC) += $(call cc-option,-march=nocona)
538 +
539 + cflags-$(CONFIG_MCORE2) += \
540 +- $(call cc-option,-march=core2,$(call cc-option,-mtune=generic))
541 +- cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom) \
542 +- $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic))
543 ++ $(call cc-option,-march=core2,$(call cc-option,-mtune=core2))
544 ++ cflags-$(CONFIG_MNEHALEM) += \
545 ++ $(call cc-option,-march=nehalem,$(call cc-option,-mtune=nehalem))
546 ++ cflags-$(CONFIG_MWESTMERE) += \
547 ++ $(call cc-option,-march=westmere,$(call cc-option,-mtune=westmere))
548 ++ cflags-$(CONFIG_MSILVERMONT) += \
549 ++ $(call cc-option,-march=silvermont,$(call cc-option,-mtune=silvermont))
550 ++ cflags-$(CONFIG_MSANDYBRIDGE) += \
551 ++ $(call cc-option,-march=sandybridge,$(call cc-option,-mtune=sandybridge))
552 ++ cflags-$(CONFIG_MIVYBRIDGE) += \
553 ++ $(call cc-option,-march=ivybridge,$(call cc-option,-mtune=ivybridge))
554 ++ cflags-$(CONFIG_MHASWELL) += \
555 ++ $(call cc-option,-march=haswell,$(call cc-option,-mtune=haswell))
556 ++ cflags-$(CONFIG_MBROADWELL) += \
557 ++ $(call cc-option,-march=broadwell,$(call cc-option,-mtune=broadwell))
558 ++ cflags-$(CONFIG_MSKYLAKE) += \
559 ++ $(call cc-option,-march=skylake,$(call cc-option,-mtune=skylake))
560 ++ cflags-$(CONFIG_MSKYLAKEX) += \
561 ++ $(call cc-option,-march=skylake-avx512,$(call cc-option,-mtune=skylake-avx512))
562 ++ cflags-$(CONFIG_MCANNONLAKE) += \
563 ++ $(call cc-option,-march=cannonlake,$(call cc-option,-mtune=cannonlake))
564 ++ cflags-$(CONFIG_MICELAKE) += \
565 ++ $(call cc-option,-march=icelake,$(call cc-option,-mtune=icelake))
566 ++ cflags-$(CONFIG_MATOM) += $(call cc-option,-march=bonnell) \
567 ++ $(call cc-option,-mtune=bonnell,$(call cc-option,-mtune=generic))
568 + cflags-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=generic)
569 + KBUILD_CFLAGS += $(cflags-y)
570 +
571 +--- a/arch/x86/Makefile_32.cpu 2018-04-01 17:20:27.000000000 -0400
572 ++++ b/arch/x86/Makefile_32.cpu 2018-05-07 17:46:27.093434792 -0400
573 +@@ -23,7 +23,18 @@ cflags-$(CONFIG_MK6) += -march=k6
574 + # Please note, that patches that add -march=athlon-xp and friends are pointless.
575 + # They make zero difference whatsosever to performance at this time.
576 + cflags-$(CONFIG_MK7) += -march=athlon
577 ++cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native)
578 + cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8,-march=athlon)
579 ++cflags-$(CONFIG_MK8SSE3) += $(call cc-option,-march=k8-sse3,-march=athlon)
580 ++cflags-$(CONFIG_MK10) += $(call cc-option,-march=amdfam10,-march=athlon)
581 ++cflags-$(CONFIG_MBARCELONA) += $(call cc-option,-march=barcelona,-march=athlon)
582 ++cflags-$(CONFIG_MBOBCAT) += $(call cc-option,-march=btver1,-march=athlon)
583 ++cflags-$(CONFIG_MJAGUAR) += $(call cc-option,-march=btver2,-march=athlon)
584 ++cflags-$(CONFIG_MBULLDOZER) += $(call cc-option,-march=bdver1,-march=athlon)
585 ++cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-march=bdver2,-march=athlon)
586 ++cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-march=bdver3,-march=athlon)
587 ++cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4,-march=athlon)
588 ++cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1,-march=athlon)
589 + cflags-$(CONFIG_MCRUSOE) += -march=i686 -falign-functions=0 -falign-jumps=0 -falign-loops=0
590 + cflags-$(CONFIG_MEFFICEON) += -march=i686 $(call tune,pentium3) -falign-functions=0 -falign-jumps=0 -falign-loops=0
591 + cflags-$(CONFIG_MWINCHIPC6) += $(call cc-option,-march=winchip-c6,-march=i586)
592 +@@ -32,8 +43,19 @@ cflags-$(CONFIG_MCYRIXIII) += $(call cc-
593 + cflags-$(CONFIG_MVIAC3_2) += $(call cc-option,-march=c3-2,-march=i686)
594 + cflags-$(CONFIG_MVIAC7) += -march=i686
595 + cflags-$(CONFIG_MCORE2) += -march=i686 $(call tune,core2)
596 +-cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom,$(call cc-option,-march=core2,-march=i686)) \
597 +- $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic))
598 ++cflags-$(CONFIG_MNEHALEM) += -march=i686 $(call tune,nehalem)
599 ++cflags-$(CONFIG_MWESTMERE) += -march=i686 $(call tune,westmere)
600 ++cflags-$(CONFIG_MSILVERMONT) += -march=i686 $(call tune,silvermont)
601 ++cflags-$(CONFIG_MSANDYBRIDGE) += -march=i686 $(call tune,sandybridge)
602 ++cflags-$(CONFIG_MIVYBRIDGE) += -march=i686 $(call tune,ivybridge)
603 ++cflags-$(CONFIG_MHASWELL) += -march=i686 $(call tune,haswell)
604 ++cflags-$(CONFIG_MBROADWELL) += -march=i686 $(call tune,broadwell)
605 ++cflags-$(CONFIG_MSKYLAKE) += -march=i686 $(call tune,skylake)
606 ++cflags-$(CONFIG_MSKYLAKEX) += -march=i686 $(call tune,skylake-avx512)
607 ++cflags-$(CONFIG_MCANNONLAKE) += -march=i686 $(call tune,cannonlake)
608 ++cflags-$(CONFIG_MICELAKE) += -march=i686 $(call tune,icelake)
609 ++cflags-$(CONFIG_MATOM) += $(call cc-option,-march=bonnell,$(call cc-option,-march=core2,-march=i686)) \
610 ++ $(call cc-option,-mtune=bonnell,$(call cc-option,-mtune=generic))
611 +
612 + # AMD Elan support
613 + cflags-$(CONFIG_MELAN) += -march=i486