Gentoo Archives: gentoo-commits

From: Mike Pagano <mpagano@g.o>
To: gentoo-commits@l.g.o
Subject: [gentoo-commits] proj/linux-patches:4.16 commit in: /
Date: Wed, 30 May 2018 11:44:53
Message-Id: 1527680678.8a5950d77db4cc1cc9e4b9b359bdd8d288d2167c.mpagano@gentoo
1 commit: 8a5950d77db4cc1cc9e4b9b359bdd8d288d2167c
2 Author: Mike Pagano <mpagano <AT> gentoo <DOT> org>
3 AuthorDate: Wed May 30 11:44:38 2018 +0000
4 Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org>
5 CommitDate: Wed May 30 11:44:38 2018 +0000
6 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=8a5950d7
7
8 Linux patch 4.16.13
9
10 0000_README | 4 +
11 1012_linux-4.16.13.patch | 10200 +++++++++++++++++++++++++++++++++++++++++++++
12 2 files changed, 10204 insertions(+)
13
14 diff --git a/0000_README b/0000_README
15 index 603fb6f..f199583 100644
16 --- a/0000_README
17 +++ b/0000_README
18 @@ -91,6 +91,10 @@ Patch: 1011_linux-4.16.12.patch
19 From: http://www.kernel.org
20 Desc: Linux 4.16.12
21
22 +Patch: 1012_linux-4.16.13.patch
23 +From: http://www.kernel.org
24 +Desc: Linux 4.16.13
25 +
26 Patch: 1500_XATTR_USER_PREFIX.patch
27 From: https://bugs.gentoo.org/show_bug.cgi?id=470644
28 Desc: Support for namespace user.pax.* on tmpfs.
29
30 diff --git a/1012_linux-4.16.13.patch b/1012_linux-4.16.13.patch
31 new file mode 100644
32 index 0000000..8fb1dc5
33 --- /dev/null
34 +++ b/1012_linux-4.16.13.patch
35 @@ -0,0 +1,10200 @@
36 +diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
37 +index 4ca21c3a6fc9..460ef27b1008 100644
38 +--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
39 ++++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
40 +@@ -20,6 +20,7 @@ Required properties :
41 + - "allwinner,sun50i-a64-ccu"
42 + - "allwinner,sun50i-a64-r-ccu"
43 + - "allwinner,sun50i-h5-ccu"
44 ++ - "allwinner,sun50i-h6-ccu"
45 + - "nextthing,gr8-ccu"
46 +
47 + - reg: Must contain the registers base address and length
48 +@@ -31,6 +32,9 @@ Required properties :
49 + - #clock-cells : must contain 1
50 + - #reset-cells : must contain 1
51 +
52 ++For the main CCU on H6, one more clock is needed:
53 ++- "iosc": the SoC's internal frequency oscillator
54 ++
55 + For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:
56 + - "pll-periph": the SoC's peripheral PLL from the main CCU
57 + - "iosc": the SoC's internal frequency oscillator
58 +diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt
59 +index a6671bd2c85a..ae38a1ee9c29 100644
60 +--- a/Documentation/devicetree/bindings/display/msm/dsi.txt
61 ++++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
62 +@@ -102,7 +102,11 @@ Required properties:
63 + - clocks: Phandles to device clocks. See [1] for details on clock bindings.
64 + - clock-names: the following clocks are required:
65 + * "iface"
66 ++ For 28nm HPM/LP, 28nm 8960 PHYs:
67 + - vddio-supply: phandle to vdd-io regulator device node
68 ++ For 20nm PHY:
69 ++- vddio-supply: phandle to vdd-io regulator device node
70 ++- vcca-supply: phandle to vcca regulator device node
71 +
72 + Optional properties:
73 + - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
74 +diff --git a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
75 +index 47284f85ec80..c3f9826692bc 100644
76 +--- a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
77 ++++ b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
78 +@@ -20,7 +20,8 @@ Required subnode-properties:
79 + gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0,
80 + i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0,
81 + spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart1grp0,
82 +- uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0
83 ++ uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0,
84 ++ uart5nocts
85 + cpuclkout: cpuclkoutgrp0
86 + udlclkout: udlclkoutgrp0
87 + i2c1: i2c1grp0
88 +@@ -37,7 +38,7 @@ Required subnode-properties:
89 + uart2: uart2grp0, uart2grp1
90 + uart3: uart3grp0
91 + uart4: uart4grp0
92 +- uart5: uart5grp0
93 ++ uart5: uart5grp0, uart5nocts
94 + nand: nandgrp0
95 + sdio0: sdio0grp0
96 + sdio1: sdio1grp0
97 +diff --git a/Makefile b/Makefile
98 +index ded9e8480d74..146e527a5e06 100644
99 +--- a/Makefile
100 ++++ b/Makefile
101 +@@ -1,7 +1,7 @@
102 + # SPDX-License-Identifier: GPL-2.0
103 + VERSION = 4
104 + PATCHLEVEL = 16
105 +-SUBLEVEL = 12
106 ++SUBLEVEL = 13
107 + EXTRAVERSION =
108 + NAME = Fearless Coyote
109 +
110 +diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
111 +index 3ea1d26e1c68..c457eff25911 100644
112 +--- a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
113 ++++ b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
114 +@@ -146,7 +146,7 @@
115 + };
116 +
117 + eeprom@50 {
118 +- compatible = "nxp,24c02";
119 ++ compatible = "nxp,se97b", "atmel,24c02";
120 + reg = <0x50>;
121 + pagesize = <16>;
122 + };
123 +diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/at91-tse850-3.dts
124 +index 9b82cc8843e1..97b227693658 100644
125 +--- a/arch/arm/boot/dts/at91-tse850-3.dts
126 ++++ b/arch/arm/boot/dts/at91-tse850-3.dts
127 +@@ -246,7 +246,7 @@
128 + };
129 +
130 + eeprom@50 {
131 +- compatible = "nxp,24c02", "atmel,24c02";
132 ++ compatible = "nxp,se97b", "atmel,24c02";
133 + reg = <0x50>;
134 + pagesize = <16>;
135 + };
136 +diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
137 +index 9d293decf8d3..8d9a0df207a4 100644
138 +--- a/arch/arm/boot/dts/bcm283x.dtsi
139 ++++ b/arch/arm/boot/dts/bcm283x.dtsi
140 +@@ -252,7 +252,7 @@
141 +
142 + jtag_gpio4: jtag_gpio4 {
143 + brcm,pins = <4 5 6 12 13>;
144 +- brcm,function = <BCM2835_FSEL_ALT4>;
145 ++ brcm,function = <BCM2835_FSEL_ALT5>;
146 + };
147 + jtag_gpio22: jtag_gpio22 {
148 + brcm,pins = <22 23 24 25 26 27>;
149 +@@ -397,8 +397,8 @@
150 +
151 + i2s: i2s@7e203000 {
152 + compatible = "brcm,bcm2835-i2s";
153 +- reg = <0x7e203000 0x20>,
154 +- <0x7e101098 0x02>;
155 ++ reg = <0x7e203000 0x24>;
156 ++ clocks = <&clocks BCM2835_CLOCK_PCM>;
157 +
158 + dmas = <&dma 2>,
159 + <&dma 3>;
160 +diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts
161 +index 41c9132eb550..64363f75c01a 100644
162 +--- a/arch/arm/boot/dts/dra71-evm.dts
163 ++++ b/arch/arm/boot/dts/dra71-evm.dts
164 +@@ -24,13 +24,13 @@
165 +
166 + regulator-name = "vddshv8";
167 + regulator-min-microvolt = <1800000>;
168 +- regulator-max-microvolt = <3000000>;
169 ++ regulator-max-microvolt = <3300000>;
170 + regulator-boot-on;
171 + vin-supply = <&evm_5v0>;
172 +
173 + gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
174 + states = <1800000 0x0
175 +- 3000000 0x1>;
176 ++ 3300000 0x1>;
177 + };
178 +
179 + evm_1v8_sw: fixedregulator-evm_1v8 {
180 +diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
181 +index ae45af1ad062..3cc1fb9ce441 100644
182 +--- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
183 ++++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
184 +@@ -213,37 +213,37 @@
185 + &iomuxc {
186 + pinctrl_enet1: enet1grp {
187 + fsl,pins = <
188 +- MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
189 +- MX7D_PAD_SD2_WP__ENET1_MDC 0x3
190 +- MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
191 +- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
192 +- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
193 +- MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
194 +- MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
195 +- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
196 +- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
197 +- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
198 +- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
199 +- MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
200 +- MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
201 +- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
202 ++ MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x30
203 ++ MX7D_PAD_SD2_WP__ENET1_MDC 0x30
204 ++ MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x11
205 ++ MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x11
206 ++ MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x11
207 ++ MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x11
208 ++ MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x11
209 ++ MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x11
210 ++ MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x11
211 ++ MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11
212 ++ MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11
213 ++ MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11
214 ++ MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x11
215 ++ MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
216 + >;
217 + };
218 +
219 + pinctrl_enet2: enet2grp {
220 + fsl,pins = <
221 +- MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
222 +- MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
223 +- MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
224 +- MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
225 +- MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
226 +- MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
227 +- MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
228 +- MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
229 +- MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
230 +- MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
231 +- MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
232 +- MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
233 ++ MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x11
234 ++ MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x11
235 ++ MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x11
236 ++ MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x11
237 ++ MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x11
238 ++ MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x11
239 ++ MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x11
240 ++ MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x11
241 ++ MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x11
242 ++ MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x11
243 ++ MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x11
244 ++ MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x11
245 + >;
246 + };
247 +
248 +diff --git a/arch/arm/boot/dts/keystone-k2e-clocks.dtsi b/arch/arm/boot/dts/keystone-k2e-clocks.dtsi
249 +index 5e0e7d232161..f7592155a740 100644
250 +--- a/arch/arm/boot/dts/keystone-k2e-clocks.dtsi
251 ++++ b/arch/arm/boot/dts/keystone-k2e-clocks.dtsi
252 +@@ -42,7 +42,7 @@ clocks {
253 + domain-id = <0>;
254 + };
255 +
256 +- clkhyperlink0: clkhyperlink02350030 {
257 ++ clkhyperlink0: clkhyperlink0@2350030 {
258 + #clock-cells = <0>;
259 + compatible = "ti,keystone,psc-clock";
260 + clocks = <&chipclk12>;
261 +diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
262 +index eb374956294f..9a02d03b23c2 100644
263 +--- a/arch/arm/boot/dts/r8a7791-porter.dts
264 ++++ b/arch/arm/boot/dts/r8a7791-porter.dts
265 +@@ -425,7 +425,7 @@
266 + "dclkin.0", "dclkin.1";
267 +
268 + ports {
269 +- port@1 {
270 ++ port@0 {
271 + endpoint {
272 + remote-endpoint = <&adv7511_in>;
273 + };
274 +diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
275 +index c42ca7022e8c..486d4e7433ed 100644
276 +--- a/arch/arm/boot/dts/socfpga.dtsi
277 ++++ b/arch/arm/boot/dts/socfpga.dtsi
278 +@@ -831,7 +831,7 @@
279 + timer@fffec600 {
280 + compatible = "arm,cortex-a9-twd-timer";
281 + reg = <0xfffec600 0x100>;
282 +- interrupts = <1 13 0xf04>;
283 ++ interrupts = <1 13 0xf01>;
284 + clocks = <&mpu_periph_clk>;
285 + };
286 +
287 +diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
288 +index 4f2f2eea0755..5df34345a354 100644
289 +--- a/arch/arm/boot/dts/sun4i-a10.dtsi
290 ++++ b/arch/arm/boot/dts/sun4i-a10.dtsi
291 +@@ -76,7 +76,7 @@
292 + allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
293 + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
294 + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
295 +- <&ccu CLK_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
296 ++ <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
297 + <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
298 + <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
299 + status = "disabled";
300 +@@ -88,7 +88,7 @@
301 + allwinner,pipeline = "de_fe0-de_be0-lcd0";
302 + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
303 + <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
304 +- <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_TCON0_CH0>,
305 ++ <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>,
306 + <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
307 + status = "disabled";
308 + };
309 +@@ -99,7 +99,7 @@
310 + allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
311 + clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
312 + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
313 +- <&ccu CLK_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
314 ++ <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
315 + <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
316 + <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
317 + status = "disabled";
318 +diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
319 +index 0a6f7952bbb1..48b85653ad66 100644
320 +--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
321 ++++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
322 +@@ -497,8 +497,8 @@
323 + blsp2_spi5: spi@75ba000{
324 + compatible = "qcom,spi-qup-v2.2.1";
325 + reg = <0x075ba000 0x600>;
326 +- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
327 +- clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
328 ++ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
329 ++ clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
330 + <&gcc GCC_BLSP2_AHB_CLK>;
331 + clock-names = "core", "iface";
332 + pinctrl-names = "default", "sleep";
333 +diff --git a/arch/arm64/include/asm/atomic_lse.h b/arch/arm64/include/asm/atomic_lse.h
334 +index 9ef0797380cb..f9b0b09153e0 100644
335 +--- a/arch/arm64/include/asm/atomic_lse.h
336 ++++ b/arch/arm64/include/asm/atomic_lse.h
337 +@@ -117,7 +117,7 @@ static inline void atomic_and(int i, atomic_t *v)
338 + /* LSE atomics */
339 + " mvn %w[i], %w[i]\n"
340 + " stclr %w[i], %[v]")
341 +- : [i] "+r" (w0), [v] "+Q" (v->counter)
342 ++ : [i] "+&r" (w0), [v] "+Q" (v->counter)
343 + : "r" (x1)
344 + : __LL_SC_CLOBBERS);
345 + }
346 +@@ -135,7 +135,7 @@ static inline int atomic_fetch_and##name(int i, atomic_t *v) \
347 + /* LSE atomics */ \
348 + " mvn %w[i], %w[i]\n" \
349 + " ldclr" #mb " %w[i], %w[i], %[v]") \
350 +- : [i] "+r" (w0), [v] "+Q" (v->counter) \
351 ++ : [i] "+&r" (w0), [v] "+Q" (v->counter) \
352 + : "r" (x1) \
353 + : __LL_SC_CLOBBERS, ##cl); \
354 + \
355 +@@ -161,7 +161,7 @@ static inline void atomic_sub(int i, atomic_t *v)
356 + /* LSE atomics */
357 + " neg %w[i], %w[i]\n"
358 + " stadd %w[i], %[v]")
359 +- : [i] "+r" (w0), [v] "+Q" (v->counter)
360 ++ : [i] "+&r" (w0), [v] "+Q" (v->counter)
361 + : "r" (x1)
362 + : __LL_SC_CLOBBERS);
363 + }
364 +@@ -180,7 +180,7 @@ static inline int atomic_sub_return##name(int i, atomic_t *v) \
365 + " neg %w[i], %w[i]\n" \
366 + " ldadd" #mb " %w[i], w30, %[v]\n" \
367 + " add %w[i], %w[i], w30") \
368 +- : [i] "+r" (w0), [v] "+Q" (v->counter) \
369 ++ : [i] "+&r" (w0), [v] "+Q" (v->counter) \
370 + : "r" (x1) \
371 + : __LL_SC_CLOBBERS , ##cl); \
372 + \
373 +@@ -207,7 +207,7 @@ static inline int atomic_fetch_sub##name(int i, atomic_t *v) \
374 + /* LSE atomics */ \
375 + " neg %w[i], %w[i]\n" \
376 + " ldadd" #mb " %w[i], %w[i], %[v]") \
377 +- : [i] "+r" (w0), [v] "+Q" (v->counter) \
378 ++ : [i] "+&r" (w0), [v] "+Q" (v->counter) \
379 + : "r" (x1) \
380 + : __LL_SC_CLOBBERS, ##cl); \
381 + \
382 +@@ -314,7 +314,7 @@ static inline void atomic64_and(long i, atomic64_t *v)
383 + /* LSE atomics */
384 + " mvn %[i], %[i]\n"
385 + " stclr %[i], %[v]")
386 +- : [i] "+r" (x0), [v] "+Q" (v->counter)
387 ++ : [i] "+&r" (x0), [v] "+Q" (v->counter)
388 + : "r" (x1)
389 + : __LL_SC_CLOBBERS);
390 + }
391 +@@ -332,7 +332,7 @@ static inline long atomic64_fetch_and##name(long i, atomic64_t *v) \
392 + /* LSE atomics */ \
393 + " mvn %[i], %[i]\n" \
394 + " ldclr" #mb " %[i], %[i], %[v]") \
395 +- : [i] "+r" (x0), [v] "+Q" (v->counter) \
396 ++ : [i] "+&r" (x0), [v] "+Q" (v->counter) \
397 + : "r" (x1) \
398 + : __LL_SC_CLOBBERS, ##cl); \
399 + \
400 +@@ -358,7 +358,7 @@ static inline void atomic64_sub(long i, atomic64_t *v)
401 + /* LSE atomics */
402 + " neg %[i], %[i]\n"
403 + " stadd %[i], %[v]")
404 +- : [i] "+r" (x0), [v] "+Q" (v->counter)
405 ++ : [i] "+&r" (x0), [v] "+Q" (v->counter)
406 + : "r" (x1)
407 + : __LL_SC_CLOBBERS);
408 + }
409 +@@ -377,7 +377,7 @@ static inline long atomic64_sub_return##name(long i, atomic64_t *v) \
410 + " neg %[i], %[i]\n" \
411 + " ldadd" #mb " %[i], x30, %[v]\n" \
412 + " add %[i], %[i], x30") \
413 +- : [i] "+r" (x0), [v] "+Q" (v->counter) \
414 ++ : [i] "+&r" (x0), [v] "+Q" (v->counter) \
415 + : "r" (x1) \
416 + : __LL_SC_CLOBBERS, ##cl); \
417 + \
418 +@@ -404,7 +404,7 @@ static inline long atomic64_fetch_sub##name(long i, atomic64_t *v) \
419 + /* LSE atomics */ \
420 + " neg %[i], %[i]\n" \
421 + " ldadd" #mb " %[i], %[i], %[v]") \
422 +- : [i] "+r" (x0), [v] "+Q" (v->counter) \
423 ++ : [i] "+&r" (x0), [v] "+Q" (v->counter) \
424 + : "r" (x1) \
425 + : __LL_SC_CLOBBERS, ##cl); \
426 + \
427 +@@ -435,7 +435,7 @@ static inline long atomic64_dec_if_positive(atomic64_t *v)
428 + " sub x30, x30, %[ret]\n"
429 + " cbnz x30, 1b\n"
430 + "2:")
431 +- : [ret] "+r" (x0), [v] "+Q" (v->counter)
432 ++ : [ret] "+&r" (x0), [v] "+Q" (v->counter)
433 + :
434 + : __LL_SC_CLOBBERS, "cc", "memory");
435 +
436 +@@ -516,7 +516,7 @@ static inline long __cmpxchg_double##name(unsigned long old1, \
437 + " eor %[old1], %[old1], %[oldval1]\n" \
438 + " eor %[old2], %[old2], %[oldval2]\n" \
439 + " orr %[old1], %[old1], %[old2]") \
440 +- : [old1] "+r" (x0), [old2] "+r" (x1), \
441 ++ : [old1] "+&r" (x0), [old2] "+&r" (x1), \
442 + [v] "+Q" (*(unsigned long *)ptr) \
443 + : [new1] "r" (x2), [new2] "r" (x3), [ptr] "r" (x4), \
444 + [oldval1] "r" (oldval1), [oldval2] "r" (oldval2) \
445 +diff --git a/arch/arm64/kernel/arm64ksyms.c b/arch/arm64/kernel/arm64ksyms.c
446 +index 66be504edb6c..d894a20b70b2 100644
447 +--- a/arch/arm64/kernel/arm64ksyms.c
448 ++++ b/arch/arm64/kernel/arm64ksyms.c
449 +@@ -75,3 +75,11 @@ NOKPROBE_SYMBOL(_mcount);
450 + /* arm-smccc */
451 + EXPORT_SYMBOL(__arm_smccc_smc);
452 + EXPORT_SYMBOL(__arm_smccc_hvc);
453 ++
454 ++ /* tishift.S */
455 ++extern long long __ashlti3(long long a, int b);
456 ++EXPORT_SYMBOL(__ashlti3);
457 ++extern long long __ashrti3(long long a, int b);
458 ++EXPORT_SYMBOL(__ashrti3);
459 ++extern long long __lshrti3(long long a, int b);
460 ++EXPORT_SYMBOL(__lshrti3);
461 +diff --git a/arch/arm64/lib/tishift.S b/arch/arm64/lib/tishift.S
462 +index d3db9b2cd479..0fdff97794de 100644
463 +--- a/arch/arm64/lib/tishift.S
464 ++++ b/arch/arm64/lib/tishift.S
465 +@@ -1,17 +1,6 @@
466 +-/*
467 +- * Copyright (C) 2017 Jason A. Donenfeld <Jason@×××××.com>. All Rights Reserved.
468 ++/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
469 + *
470 +- * This program is free software; you can redistribute it and/or modify
471 +- * it under the terms of the GNU General Public License version 2 as
472 +- * published by the Free Software Foundation.
473 +- *
474 +- * This program is distributed in the hope that it will be useful,
475 +- * but WITHOUT ANY WARRANTY; without even the implied warranty of
476 +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
477 +- * GNU General Public License for more details.
478 +- *
479 +- * You should have received a copy of the GNU General Public License
480 +- * along with this program. If not, see <http://www.gnu.org/licenses/>.
481 ++ * Copyright (C) 2017-2018 Jason A. Donenfeld <Jason@×××××.com>. All Rights Reserved.
482 + */
483 +
484 + #include <linux/linkage.h>
485 +diff --git a/arch/m68k/coldfire/device.c b/arch/m68k/coldfire/device.c
486 +index 84938fdbbada..908d58347790 100644
487 +--- a/arch/m68k/coldfire/device.c
488 ++++ b/arch/m68k/coldfire/device.c
489 +@@ -135,7 +135,11 @@ static struct platform_device mcf_fec0 = {
490 + .id = 0,
491 + .num_resources = ARRAY_SIZE(mcf_fec0_resources),
492 + .resource = mcf_fec0_resources,
493 +- .dev.platform_data = FEC_PDATA,
494 ++ .dev = {
495 ++ .dma_mask = &mcf_fec0.dev.coherent_dma_mask,
496 ++ .coherent_dma_mask = DMA_BIT_MASK(32),
497 ++ .platform_data = FEC_PDATA,
498 ++ }
499 + };
500 +
501 + #ifdef MCFFEC_BASE1
502 +@@ -167,7 +171,11 @@ static struct platform_device mcf_fec1 = {
503 + .id = 1,
504 + .num_resources = ARRAY_SIZE(mcf_fec1_resources),
505 + .resource = mcf_fec1_resources,
506 +- .dev.platform_data = FEC_PDATA,
507 ++ .dev = {
508 ++ .dma_mask = &mcf_fec1.dev.coherent_dma_mask,
509 ++ .coherent_dma_mask = DMA_BIT_MASK(32),
510 ++ .platform_data = FEC_PDATA,
511 ++ }
512 + };
513 + #endif /* MCFFEC_BASE1 */
514 + #endif /* CONFIG_FEC */
515 +diff --git a/arch/mips/boot/compressed/uart-16550.c b/arch/mips/boot/compressed/uart-16550.c
516 +index b3043c08f769..aee8d7b8f091 100644
517 +--- a/arch/mips/boot/compressed/uart-16550.c
518 ++++ b/arch/mips/boot/compressed/uart-16550.c
519 +@@ -18,9 +18,9 @@
520 + #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))
521 + #endif
522 +
523 +-#if defined(CONFIG_MACH_JZ4740) || defined(CONFIG_MACH_JZ4780)
524 +-#include <asm/mach-jz4740/base.h>
525 +-#define PORT(offset) (CKSEG1ADDR(JZ4740_UART0_BASE_ADDR) + (4 * offset))
526 ++#ifdef CONFIG_MACH_INGENIC
527 ++#define INGENIC_UART0_BASE_ADDR 0x10030000
528 ++#define PORT(offset) (CKSEG1ADDR(INGENIC_UART0_BASE_ADDR) + (4 * offset))
529 + #endif
530 +
531 + #ifdef CONFIG_CPU_XLR
532 +diff --git a/arch/mips/boot/dts/xilfpga/Makefile b/arch/mips/boot/dts/xilfpga/Makefile
533 +index 9987e0e378c5..69ca00590b8d 100644
534 +--- a/arch/mips/boot/dts/xilfpga/Makefile
535 ++++ b/arch/mips/boot/dts/xilfpga/Makefile
536 +@@ -1,4 +1,2 @@
537 + # SPDX-License-Identifier: GPL-2.0
538 + dtb-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += nexys4ddr.dtb
539 +-
540 +-obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
541 +diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
542 +index d99f5242169e..b3aec101a65d 100644
543 +--- a/arch/mips/cavium-octeon/octeon-irq.c
544 ++++ b/arch/mips/cavium-octeon/octeon-irq.c
545 +@@ -2271,7 +2271,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
546 +
547 + parent_irq = irq_of_parse_and_map(ciu_node, 0);
548 + if (!parent_irq) {
549 +- pr_err("ERROR: Couldn't acquire parent_irq for %s\n.",
550 ++ pr_err("ERROR: Couldn't acquire parent_irq for %s\n",
551 + ciu_node->name);
552 + return -EINVAL;
553 + }
554 +@@ -2283,7 +2283,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
555 +
556 + addr = of_get_address(ciu_node, 0, NULL, NULL);
557 + if (!addr) {
558 +- pr_err("ERROR: Couldn't acquire reg(0) %s\n.", ciu_node->name);
559 ++ pr_err("ERROR: Couldn't acquire reg(0) %s\n", ciu_node->name);
560 + return -EINVAL;
561 + }
562 + host_data->raw_reg = (u64)phys_to_virt(
563 +@@ -2291,7 +2291,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
564 +
565 + addr = of_get_address(ciu_node, 1, NULL, NULL);
566 + if (!addr) {
567 +- pr_err("ERROR: Couldn't acquire reg(1) %s\n.", ciu_node->name);
568 ++ pr_err("ERROR: Couldn't acquire reg(1) %s\n", ciu_node->name);
569 + return -EINVAL;
570 + }
571 + host_data->en_reg = (u64)phys_to_virt(
572 +@@ -2299,7 +2299,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
573 +
574 + r = of_property_read_u32(ciu_node, "cavium,max-bits", &val);
575 + if (r) {
576 +- pr_err("ERROR: Couldn't read cavium,max-bits from %s\n.",
577 ++ pr_err("ERROR: Couldn't read cavium,max-bits from %s\n",
578 + ciu_node->name);
579 + return r;
580 + }
581 +@@ -2309,7 +2309,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
582 + &octeon_irq_domain_cib_ops,
583 + host_data);
584 + if (!cib_domain) {
585 +- pr_err("ERROR: Couldn't irq_domain_add_linear()\n.");
586 ++ pr_err("ERROR: Couldn't irq_domain_add_linear()\n");
587 + return -ENOMEM;
588 + }
589 +
590 +diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform
591 +index b51432dd10b6..0dd0d5d460a5 100644
592 +--- a/arch/mips/generic/Platform
593 ++++ b/arch/mips/generic/Platform
594 +@@ -16,3 +16,4 @@ all-$(CONFIG_MIPS_GENERIC) := vmlinux.gz.itb
595 + its-y := vmlinux.its.S
596 + its-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += board-boston.its.S
597 + its-$(CONFIG_FIT_IMAGE_FDT_NI169445) += board-ni169445.its.S
598 ++its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S
599 +diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
600 +index aa3800c82332..d99ca862dae3 100644
601 +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
602 ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
603 +@@ -167,7 +167,7 @@
604 + #define AR71XX_AHB_DIV_MASK 0x7
605 +
606 + #define AR724X_PLL_REG_CPU_CONFIG 0x00
607 +-#define AR724X_PLL_REG_PCIE_CONFIG 0x18
608 ++#define AR724X_PLL_REG_PCIE_CONFIG 0x10
609 +
610 + #define AR724X_PLL_FB_SHIFT 0
611 + #define AR724X_PLL_FB_MASK 0x3ff
612 +diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
613 +index 0b23b1ad99e6..8d098b9f395c 100644
614 +--- a/arch/mips/kernel/ptrace.c
615 ++++ b/arch/mips/kernel/ptrace.c
616 +@@ -463,7 +463,7 @@ static int fpr_get_msa(struct task_struct *target,
617 + /*
618 + * Copy the floating-point context to the supplied NT_PRFPREG buffer.
619 + * Choose the appropriate helper for general registers, and then copy
620 +- * the FCSR register separately.
621 ++ * the FCSR and FIR registers separately.
622 + */
623 + static int fpr_get(struct task_struct *target,
624 + const struct user_regset *regset,
625 +@@ -471,6 +471,7 @@ static int fpr_get(struct task_struct *target,
626 + void *kbuf, void __user *ubuf)
627 + {
628 + const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t);
629 ++ const int fir_pos = fcr31_pos + sizeof(u32);
630 + int err;
631 +
632 + if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t))
633 +@@ -483,6 +484,12 @@ static int fpr_get(struct task_struct *target,
634 + err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
635 + &target->thread.fpu.fcr31,
636 + fcr31_pos, fcr31_pos + sizeof(u32));
637 ++ if (err)
638 ++ return err;
639 ++
640 ++ err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
641 ++ &boot_cpu_data.fpu_id,
642 ++ fir_pos, fir_pos + sizeof(u32));
643 +
644 + return err;
645 + }
646 +@@ -531,7 +538,8 @@ static int fpr_set_msa(struct task_struct *target,
647 + /*
648 + * Copy the supplied NT_PRFPREG buffer to the floating-point context.
649 + * Choose the appropriate helper for general registers, and then copy
650 +- * the FCSR register separately.
651 ++ * the FCSR register separately. Ignore the incoming FIR register
652 ++ * contents though, as the register is read-only.
653 + *
654 + * We optimize for the case where `count % sizeof(elf_fpreg_t) == 0',
655 + * which is supposed to have been guaranteed by the kernel before
656 +@@ -545,6 +553,7 @@ static int fpr_set(struct task_struct *target,
657 + const void *kbuf, const void __user *ubuf)
658 + {
659 + const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t);
660 ++ const int fir_pos = fcr31_pos + sizeof(u32);
661 + u32 fcr31;
662 + int err;
663 +
664 +@@ -572,6 +581,11 @@ static int fpr_set(struct task_struct *target,
665 + ptrace_setfcr31(target, fcr31);
666 + }
667 +
668 ++ if (count > 0)
669 ++ err = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
670 ++ fir_pos,
671 ++ fir_pos + sizeof(u32));
672 ++
673 + return err;
674 + }
675 +
676 +@@ -793,7 +807,7 @@ long arch_ptrace(struct task_struct *child, long request,
677 + fregs = get_fpu_regs(child);
678 +
679 + #ifdef CONFIG_32BIT
680 +- if (test_thread_flag(TIF_32BIT_FPREGS)) {
681 ++ if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
682 + /*
683 + * The odd registers are actually the high
684 + * order bits of the values stored in the even
685 +@@ -888,7 +902,7 @@ long arch_ptrace(struct task_struct *child, long request,
686 +
687 + init_fp_ctx(child);
688 + #ifdef CONFIG_32BIT
689 +- if (test_thread_flag(TIF_32BIT_FPREGS)) {
690 ++ if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
691 + /*
692 + * The odd registers are actually the high
693 + * order bits of the values stored in the even
694 +diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
695 +index 2b9260f92ccd..656a137c1fe2 100644
696 +--- a/arch/mips/kernel/ptrace32.c
697 ++++ b/arch/mips/kernel/ptrace32.c
698 +@@ -99,7 +99,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
699 + break;
700 + }
701 + fregs = get_fpu_regs(child);
702 +- if (test_thread_flag(TIF_32BIT_FPREGS)) {
703 ++ if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
704 + /*
705 + * The odd registers are actually the high
706 + * order bits of the values stored in the even
707 +@@ -212,7 +212,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
708 + sizeof(child->thread.fpu));
709 + child->thread.fpu.fcr31 = 0;
710 + }
711 +- if (test_thread_flag(TIF_32BIT_FPREGS)) {
712 ++ if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
713 + /*
714 + * The odd registers are actually the high
715 + * order bits of the values stored in the even
716 +diff --git a/arch/mips/kvm/mips.c b/arch/mips/kvm/mips.c
717 +index 2549fdd27ee1..0f725e9cee8f 100644
718 +--- a/arch/mips/kvm/mips.c
719 ++++ b/arch/mips/kvm/mips.c
720 +@@ -45,7 +45,7 @@ struct kvm_stats_debugfs_item debugfs_entries[] = {
721 + { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
722 + { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
723 + { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
724 +- { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
725 ++ { "cop_unusable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
726 + { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
727 + { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
728 + { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
729 +diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
730 +index 6f534b209971..e12dfa48b478 100644
731 +--- a/arch/mips/mm/c-r4k.c
732 ++++ b/arch/mips/mm/c-r4k.c
733 +@@ -851,9 +851,12 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
734 + /*
735 + * Either no secondary cache or the available caches don't have the
736 + * subset property so we have to flush the primary caches
737 +- * explicitly
738 ++ * explicitly.
739 ++ * If we would need IPI to perform an INDEX-type operation, then
740 ++ * we have to use the HIT-type alternative as IPI cannot be used
741 ++ * here due to interrupts possibly being disabled.
742 + */
743 +- if (size >= dcache_size) {
744 ++ if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
745 + r4k_blast_dcache();
746 + } else {
747 + R4600_HIT_CACHEOP_WAR_IMPL;
748 +@@ -890,7 +893,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
749 + return;
750 + }
751 +
752 +- if (size >= dcache_size) {
753 ++ if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
754 + r4k_blast_dcache();
755 + } else {
756 + R4600_HIT_CACHEOP_WAR_IMPL;
757 +diff --git a/arch/powerpc/include/asm/book3s/64/slice.h b/arch/powerpc/include/asm/book3s/64/slice.h
758 +new file mode 100644
759 +index 000000000000..db0dedab65ee
760 +--- /dev/null
761 ++++ b/arch/powerpc/include/asm/book3s/64/slice.h
762 +@@ -0,0 +1,27 @@
763 ++/* SPDX-License-Identifier: GPL-2.0 */
764 ++#ifndef _ASM_POWERPC_BOOK3S_64_SLICE_H
765 ++#define _ASM_POWERPC_BOOK3S_64_SLICE_H
766 ++
767 ++#ifdef CONFIG_PPC_MM_SLICES
768 ++
769 ++#define SLICE_LOW_SHIFT 28
770 ++#define SLICE_LOW_TOP (0x100000000ul)
771 ++#define SLICE_NUM_LOW (SLICE_LOW_TOP >> SLICE_LOW_SHIFT)
772 ++#define GET_LOW_SLICE_INDEX(addr) ((addr) >> SLICE_LOW_SHIFT)
773 ++
774 ++#define SLICE_HIGH_SHIFT 40
775 ++#define SLICE_NUM_HIGH (H_PGTABLE_RANGE >> SLICE_HIGH_SHIFT)
776 ++#define GET_HIGH_SLICE_INDEX(addr) ((addr) >> SLICE_HIGH_SHIFT)
777 ++
778 ++#else /* CONFIG_PPC_MM_SLICES */
779 ++
780 ++#define get_slice_psize(mm, addr) ((mm)->context.user_psize)
781 ++#define slice_set_user_psize(mm, psize) \
782 ++do { \
783 ++ (mm)->context.user_psize = (psize); \
784 ++ (mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \
785 ++} while (0)
786 ++
787 ++#endif /* CONFIG_PPC_MM_SLICES */
788 ++
789 ++#endif /* _ASM_POWERPC_BOOK3S_64_SLICE_H */
790 +diff --git a/arch/powerpc/include/asm/irq_work.h b/arch/powerpc/include/asm/irq_work.h
791 +index c6d3078bd8c3..b8b0be8f1a07 100644
792 +--- a/arch/powerpc/include/asm/irq_work.h
793 ++++ b/arch/powerpc/include/asm/irq_work.h
794 +@@ -6,5 +6,6 @@ static inline bool arch_irq_work_has_interrupt(void)
795 + {
796 + return true;
797 + }
798 ++extern void arch_irq_work_raise(void);
799 +
800 + #endif /* _ASM_POWERPC_IRQ_WORK_H */
801 +diff --git a/arch/powerpc/include/asm/mmu-8xx.h b/arch/powerpc/include/asm/mmu-8xx.h
802 +index 2f806e329648..b324ab46d838 100644
803 +--- a/arch/powerpc/include/asm/mmu-8xx.h
804 ++++ b/arch/powerpc/include/asm/mmu-8xx.h
805 +@@ -191,6 +191,12 @@ typedef struct {
806 + unsigned int id;
807 + unsigned int active;
808 + unsigned long vdso_base;
809 ++#ifdef CONFIG_PPC_MM_SLICES
810 ++ u16 user_psize; /* page size index */
811 ++ u64 low_slices_psize; /* page size encodings */
812 ++ unsigned char high_slices_psize[0];
813 ++ unsigned long slb_addr_limit;
814 ++#endif
815 + } mm_context_t;
816 +
817 + #define PHYS_IMMR_BASE (mfspr(SPRN_IMMR) & 0xfff80000)
818 +diff --git a/arch/powerpc/include/asm/nohash/32/slice.h b/arch/powerpc/include/asm/nohash/32/slice.h
819 +new file mode 100644
820 +index 000000000000..95d532e18092
821 +--- /dev/null
822 ++++ b/arch/powerpc/include/asm/nohash/32/slice.h
823 +@@ -0,0 +1,18 @@
824 ++/* SPDX-License-Identifier: GPL-2.0 */
825 ++#ifndef _ASM_POWERPC_NOHASH_32_SLICE_H
826 ++#define _ASM_POWERPC_NOHASH_32_SLICE_H
827 ++
828 ++#ifdef CONFIG_PPC_MM_SLICES
829 ++
830 ++#define SLICE_LOW_SHIFT 28
831 ++#define SLICE_LOW_TOP (0x100000000ull)
832 ++#define SLICE_NUM_LOW (SLICE_LOW_TOP >> SLICE_LOW_SHIFT)
833 ++#define GET_LOW_SLICE_INDEX(addr) ((addr) >> SLICE_LOW_SHIFT)
834 ++
835 ++#define SLICE_HIGH_SHIFT 0
836 ++#define SLICE_NUM_HIGH 0ul
837 ++#define GET_HIGH_SLICE_INDEX(addr) (addr & 0)
838 ++
839 ++#endif /* CONFIG_PPC_MM_SLICES */
840 ++
841 ++#endif /* _ASM_POWERPC_NOHASH_32_SLICE_H */
842 +diff --git a/arch/powerpc/include/asm/nohash/64/slice.h b/arch/powerpc/include/asm/nohash/64/slice.h
843 +new file mode 100644
844 +index 000000000000..ad0d6e3cc1c5
845 +--- /dev/null
846 ++++ b/arch/powerpc/include/asm/nohash/64/slice.h
847 +@@ -0,0 +1,12 @@
848 ++/* SPDX-License-Identifier: GPL-2.0 */
849 ++#ifndef _ASM_POWERPC_NOHASH_64_SLICE_H
850 ++#define _ASM_POWERPC_NOHASH_64_SLICE_H
851 ++
852 ++#ifdef CONFIG_PPC_64K_PAGES
853 ++#define get_slice_psize(mm, addr) MMU_PAGE_64K
854 ++#else /* CONFIG_PPC_64K_PAGES */
855 ++#define get_slice_psize(mm, addr) MMU_PAGE_4K
856 ++#endif /* !CONFIG_PPC_64K_PAGES */
857 ++#define slice_set_user_psize(mm, psize) do { BUG(); } while (0)
858 ++
859 ++#endif /* _ASM_POWERPC_NOHASH_64_SLICE_H */
860 +diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
861 +index 8da5d4c1cab2..d5f1c41b7dba 100644
862 +--- a/arch/powerpc/include/asm/page.h
863 ++++ b/arch/powerpc/include/asm/page.h
864 +@@ -344,5 +344,6 @@ typedef struct page *pgtable_t;
865 +
866 + #include <asm-generic/memory_model.h>
867 + #endif /* __ASSEMBLY__ */
868 ++#include <asm/slice.h>
869 +
870 + #endif /* _ASM_POWERPC_PAGE_H */
871 +diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
872 +index 56234c6fcd61..af04acdb873f 100644
873 +--- a/arch/powerpc/include/asm/page_64.h
874 ++++ b/arch/powerpc/include/asm/page_64.h
875 +@@ -86,65 +86,6 @@ extern u64 ppc64_pft_size;
876 +
877 + #endif /* __ASSEMBLY__ */
878 +
879 +-#ifdef CONFIG_PPC_MM_SLICES
880 +-
881 +-#define SLICE_LOW_SHIFT 28
882 +-#define SLICE_HIGH_SHIFT 40
883 +-
884 +-#define SLICE_LOW_TOP (0x100000000ul)
885 +-#define SLICE_NUM_LOW (SLICE_LOW_TOP >> SLICE_LOW_SHIFT)
886 +-#define SLICE_NUM_HIGH (H_PGTABLE_RANGE >> SLICE_HIGH_SHIFT)
887 +-
888 +-#define GET_LOW_SLICE_INDEX(addr) ((addr) >> SLICE_LOW_SHIFT)
889 +-#define GET_HIGH_SLICE_INDEX(addr) ((addr) >> SLICE_HIGH_SHIFT)
890 +-
891 +-#ifndef __ASSEMBLY__
892 +-struct mm_struct;
893 +-
894 +-extern unsigned long slice_get_unmapped_area(unsigned long addr,
895 +- unsigned long len,
896 +- unsigned long flags,
897 +- unsigned int psize,
898 +- int topdown);
899 +-
900 +-extern unsigned int get_slice_psize(struct mm_struct *mm,
901 +- unsigned long addr);
902 +-
903 +-extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize);
904 +-extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
905 +- unsigned long len, unsigned int psize);
906 +-
907 +-#endif /* __ASSEMBLY__ */
908 +-#else
909 +-#define slice_init()
910 +-#ifdef CONFIG_PPC_BOOK3S_64
911 +-#define get_slice_psize(mm, addr) ((mm)->context.user_psize)
912 +-#define slice_set_user_psize(mm, psize) \
913 +-do { \
914 +- (mm)->context.user_psize = (psize); \
915 +- (mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \
916 +-} while (0)
917 +-#else /* !CONFIG_PPC_BOOK3S_64 */
918 +-#ifdef CONFIG_PPC_64K_PAGES
919 +-#define get_slice_psize(mm, addr) MMU_PAGE_64K
920 +-#else /* CONFIG_PPC_64K_PAGES */
921 +-#define get_slice_psize(mm, addr) MMU_PAGE_4K
922 +-#endif /* !CONFIG_PPC_64K_PAGES */
923 +-#define slice_set_user_psize(mm, psize) do { BUG(); } while(0)
924 +-#endif /* CONFIG_PPC_BOOK3S_64 */
925 +-
926 +-#define slice_set_range_psize(mm, start, len, psize) \
927 +- slice_set_user_psize((mm), (psize))
928 +-#endif /* CONFIG_PPC_MM_SLICES */
929 +-
930 +-#ifdef CONFIG_HUGETLB_PAGE
931 +-
932 +-#ifdef CONFIG_PPC_MM_SLICES
933 +-#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
934 +-#endif
935 +-
936 +-#endif /* !CONFIG_HUGETLB_PAGE */
937 +-
938 + #define VM_DATA_DEFAULT_FLAGS \
939 + (is_32bit_task() ? \
940 + VM_DATA_DEFAULT_FLAGS32 : VM_DATA_DEFAULT_FLAGS64)
941 +diff --git a/arch/powerpc/include/asm/slice.h b/arch/powerpc/include/asm/slice.h
942 +new file mode 100644
943 +index 000000000000..172711fadb1c
944 +--- /dev/null
945 ++++ b/arch/powerpc/include/asm/slice.h
946 +@@ -0,0 +1,42 @@
947 ++/* SPDX-License-Identifier: GPL-2.0 */
948 ++#ifndef _ASM_POWERPC_SLICE_H
949 ++#define _ASM_POWERPC_SLICE_H
950 ++
951 ++#ifdef CONFIG_PPC_BOOK3S_64
952 ++#include <asm/book3s/64/slice.h>
953 ++#elif defined(CONFIG_PPC64)
954 ++#include <asm/nohash/64/slice.h>
955 ++#elif defined(CONFIG_PPC_MMU_NOHASH)
956 ++#include <asm/nohash/32/slice.h>
957 ++#endif
958 ++
959 ++#ifdef CONFIG_PPC_MM_SLICES
960 ++
961 ++#ifdef CONFIG_HUGETLB_PAGE
962 ++#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
963 ++#endif
964 ++#define HAVE_ARCH_UNMAPPED_AREA
965 ++#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
966 ++
967 ++#ifndef __ASSEMBLY__
968 ++
969 ++struct mm_struct;
970 ++
971 ++unsigned long slice_get_unmapped_area(unsigned long addr, unsigned long len,
972 ++ unsigned long flags, unsigned int psize,
973 ++ int topdown);
974 ++
975 ++unsigned int get_slice_psize(struct mm_struct *mm, unsigned long addr);
976 ++
977 ++void slice_set_user_psize(struct mm_struct *mm, unsigned int psize);
978 ++void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
979 ++ unsigned long len, unsigned int psize);
980 ++#endif /* __ASSEMBLY__ */
981 ++
982 ++#else /* CONFIG_PPC_MM_SLICES */
983 ++
984 ++#define slice_set_range_psize(mm, start, len, psize) \
985 ++ slice_set_user_psize((mm), (psize))
986 ++#endif /* CONFIG_PPC_MM_SLICES */
987 ++
988 ++#endif /* _ASM_POWERPC_SLICE_H */
989 +diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
990 +index 3f30c994e931..458b928dbd84 100644
991 +--- a/arch/powerpc/kernel/cpu_setup_power.S
992 ++++ b/arch/powerpc/kernel/cpu_setup_power.S
993 +@@ -28,6 +28,7 @@ _GLOBAL(__setup_cpu_power7)
994 + beqlr
995 + li r0,0
996 + mtspr SPRN_LPID,r0
997 ++ mtspr SPRN_PCR,r0
998 + mfspr r3,SPRN_LPCR
999 + li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
1000 + bl __init_LPCR_ISA206
1001 +@@ -41,6 +42,7 @@ _GLOBAL(__restore_cpu_power7)
1002 + beqlr
1003 + li r0,0
1004 + mtspr SPRN_LPID,r0
1005 ++ mtspr SPRN_PCR,r0
1006 + mfspr r3,SPRN_LPCR
1007 + li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
1008 + bl __init_LPCR_ISA206
1009 +@@ -57,6 +59,7 @@ _GLOBAL(__setup_cpu_power8)
1010 + beqlr
1011 + li r0,0
1012 + mtspr SPRN_LPID,r0
1013 ++ mtspr SPRN_PCR,r0
1014 + mfspr r3,SPRN_LPCR
1015 + ori r3, r3, LPCR_PECEDH
1016 + li r4,0 /* LPES = 0 */
1017 +@@ -78,6 +81,7 @@ _GLOBAL(__restore_cpu_power8)
1018 + beqlr
1019 + li r0,0
1020 + mtspr SPRN_LPID,r0
1021 ++ mtspr SPRN_PCR,r0
1022 + mfspr r3,SPRN_LPCR
1023 + ori r3, r3, LPCR_PECEDH
1024 + li r4,0 /* LPES = 0 */
1025 +@@ -99,6 +103,7 @@ _GLOBAL(__setup_cpu_power9)
1026 + mtspr SPRN_PSSCR,r0
1027 + mtspr SPRN_LPID,r0
1028 + mtspr SPRN_PID,r0
1029 ++ mtspr SPRN_PCR,r0
1030 + mfspr r3,SPRN_LPCR
1031 + LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
1032 + or r3, r3, r4
1033 +@@ -123,6 +128,7 @@ _GLOBAL(__restore_cpu_power9)
1034 + mtspr SPRN_PSSCR,r0
1035 + mtspr SPRN_LPID,r0
1036 + mtspr SPRN_PID,r0
1037 ++ mtspr SPRN_PCR,r0
1038 + mfspr r3,SPRN_LPCR
1039 + LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
1040 + or r3, r3, r4
1041 +diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c b/arch/powerpc/kernel/dt_cpu_ftrs.c
1042 +index 078553a177de..afe6808d7a41 100644
1043 +--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
1044 ++++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
1045 +@@ -114,6 +114,7 @@ static void __restore_cpu_cpufeatures(void)
1046 + if (hv_mode) {
1047 + mtspr(SPRN_LPID, 0);
1048 + mtspr(SPRN_HFSCR, system_registers.hfscr);
1049 ++ mtspr(SPRN_PCR, 0);
1050 + }
1051 + mtspr(SPRN_FSCR, system_registers.fscr);
1052 +
1053 +diff --git a/arch/powerpc/kernel/idle_book3s.S b/arch/powerpc/kernel/idle_book3s.S
1054 +index 01e1c1997893..2fce278446f5 100644
1055 +--- a/arch/powerpc/kernel/idle_book3s.S
1056 ++++ b/arch/powerpc/kernel/idle_book3s.S
1057 +@@ -834,6 +834,8 @@ BEGIN_FTR_SECTION
1058 + mtspr SPRN_PTCR,r4
1059 + ld r4,_RPR(r1)
1060 + mtspr SPRN_RPR,r4
1061 ++ ld r4,_AMOR(r1)
1062 ++ mtspr SPRN_AMOR,r4
1063 + END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1064 +
1065 + ld r4,_TSCR(r1)
1066 +diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
1067 +index d73ec518ef80..a6002f9449b1 100644
1068 +--- a/arch/powerpc/kernel/setup-common.c
1069 ++++ b/arch/powerpc/kernel/setup-common.c
1070 +@@ -919,6 +919,8 @@ void __init setup_arch(char **cmdline_p)
1071 + #ifdef CONFIG_PPC64
1072 + if (!radix_enabled())
1073 + init_mm.context.slb_addr_limit = DEFAULT_MAP_WINDOW_USER64;
1074 ++#elif defined(CONFIG_PPC_8xx)
1075 ++ init_mm.context.slb_addr_limit = DEFAULT_MAP_WINDOW;
1076 + #else
1077 + #error "context.addr_limit not initialized."
1078 + #endif
1079 +diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
1080 +index 1e48d157196a..578c5e80aa14 100644
1081 +--- a/arch/powerpc/kernel/traps.c
1082 ++++ b/arch/powerpc/kernel/traps.c
1083 +@@ -208,6 +208,12 @@ static void oops_end(unsigned long flags, struct pt_regs *regs,
1084 + }
1085 + raw_local_irq_restore(flags);
1086 +
1087 ++ /*
1088 ++ * system_reset_excption handles debugger, crash dump, panic, for 0x100
1089 ++ */
1090 ++ if (TRAP(regs) == 0x100)
1091 ++ return;
1092 ++
1093 + crash_fadump(regs, "die oops");
1094 +
1095 + if (kexec_should_crash(current))
1096 +@@ -272,8 +278,13 @@ void die(const char *str, struct pt_regs *regs, long err)
1097 + {
1098 + unsigned long flags;
1099 +
1100 +- if (debugger(regs))
1101 +- return;
1102 ++ /*
1103 ++ * system_reset_excption handles debugger, crash dump, panic, for 0x100
1104 ++ */
1105 ++ if (TRAP(regs) != 0x100) {
1106 ++ if (debugger(regs))
1107 ++ return;
1108 ++ }
1109 +
1110 + flags = oops_begin(regs);
1111 + if (__die(str, regs, err))
1112 +@@ -1612,6 +1623,22 @@ void facility_unavailable_exception(struct pt_regs *regs)
1113 + value = mfspr(SPRN_FSCR);
1114 +
1115 + status = value >> 56;
1116 ++ if ((hv || status >= 2) &&
1117 ++ (status < ARRAY_SIZE(facility_strings)) &&
1118 ++ facility_strings[status])
1119 ++ facility = facility_strings[status];
1120 ++
1121 ++ /* We should not have taken this interrupt in kernel */
1122 ++ if (!user_mode(regs)) {
1123 ++ pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n",
1124 ++ facility, status, regs->nip);
1125 ++ die("Unexpected facility unavailable exception", regs, SIGABRT);
1126 ++ }
1127 ++
1128 ++ /* We restore the interrupt state now */
1129 ++ if (!arch_irq_disabled_regs(regs))
1130 ++ local_irq_enable();
1131 ++
1132 + if (status == FSCR_DSCR_LG) {
1133 + /*
1134 + * User is accessing the DSCR register using the problem
1135 +@@ -1678,25 +1705,11 @@ void facility_unavailable_exception(struct pt_regs *regs)
1136 + return;
1137 + }
1138 +
1139 +- if ((hv || status >= 2) &&
1140 +- (status < ARRAY_SIZE(facility_strings)) &&
1141 +- facility_strings[status])
1142 +- facility = facility_strings[status];
1143 +-
1144 +- /* We restore the interrupt state now */
1145 +- if (!arch_irq_disabled_regs(regs))
1146 +- local_irq_enable();
1147 +-
1148 + pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
1149 + hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr);
1150 +
1151 + out:
1152 +- if (user_mode(regs)) {
1153 +- _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1154 +- return;
1155 +- }
1156 +-
1157 +- die("Unexpected facility unavailable exception", regs, SIGABRT);
1158 ++ _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1159 + }
1160 + #endif
1161 +
1162 +diff --git a/arch/powerpc/mm/8xx_mmu.c b/arch/powerpc/mm/8xx_mmu.c
1163 +index 849f50cd62f2..cf77d755246d 100644
1164 +--- a/arch/powerpc/mm/8xx_mmu.c
1165 ++++ b/arch/powerpc/mm/8xx_mmu.c
1166 +@@ -192,7 +192,7 @@ void set_context(unsigned long id, pgd_t *pgd)
1167 + mtspr(SPRN_M_TW, __pa(pgd) - offset);
1168 +
1169 + /* Update context */
1170 +- mtspr(SPRN_M_CASID, id);
1171 ++ mtspr(SPRN_M_CASID, id - 1);
1172 + /* sync */
1173 + mb();
1174 + }
1175 +diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
1176 +index 876da2bc1796..590be3fa0ce2 100644
1177 +--- a/arch/powerpc/mm/hugetlbpage.c
1178 ++++ b/arch/powerpc/mm/hugetlbpage.c
1179 +@@ -553,9 +553,11 @@ unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
1180 + struct hstate *hstate = hstate_file(file);
1181 + int mmu_psize = shift_to_mmu_psize(huge_page_shift(hstate));
1182 +
1183 ++#ifdef CONFIG_PPC_RADIX_MMU
1184 + if (radix_enabled())
1185 + return radix__hugetlb_get_unmapped_area(file, addr, len,
1186 + pgoff, flags);
1187 ++#endif
1188 + return slice_get_unmapped_area(addr, len, flags, mmu_psize, 1);
1189 + }
1190 + #endif
1191 +diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c
1192 +index 4554d6527682..d98f7e5c141b 100644
1193 +--- a/arch/powerpc/mm/mmu_context_nohash.c
1194 ++++ b/arch/powerpc/mm/mmu_context_nohash.c
1195 +@@ -331,6 +331,20 @@ int init_new_context(struct task_struct *t, struct mm_struct *mm)
1196 + {
1197 + pr_hard("initing context for mm @%p\n", mm);
1198 +
1199 ++#ifdef CONFIG_PPC_MM_SLICES
1200 ++ if (!mm->context.slb_addr_limit)
1201 ++ mm->context.slb_addr_limit = DEFAULT_MAP_WINDOW;
1202 ++
1203 ++ /*
1204 ++ * We have MMU_NO_CONTEXT set to be ~0. Hence check
1205 ++ * explicitly against context.id == 0. This ensures that we properly
1206 ++ * initialize context slice details for newly allocated mm's (which will
1207 ++ * have id == 0) and don't alter context slice inherited via fork (which
1208 ++ * will have id != 0).
1209 ++ */
1210 ++ if (mm->context.id == 0)
1211 ++ slice_set_user_psize(mm, mmu_virtual_psize);
1212 ++#endif
1213 + mm->context.id = MMU_NO_CONTEXT;
1214 + mm->context.active = 0;
1215 + return 0;
1216 +@@ -428,8 +442,8 @@ void __init mmu_context_init(void)
1217 + * -- BenH
1218 + */
1219 + if (mmu_has_feature(MMU_FTR_TYPE_8xx)) {
1220 +- first_context = 0;
1221 +- last_context = 15;
1222 ++ first_context = 1;
1223 ++ last_context = 16;
1224 + no_selective_tlbil = true;
1225 + } else if (mmu_has_feature(MMU_FTR_TYPE_47x)) {
1226 + first_context = 1;
1227 +diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
1228 +index 23ec2c5e3b78..0beca1ba2282 100644
1229 +--- a/arch/powerpc/mm/slice.c
1230 ++++ b/arch/powerpc/mm/slice.c
1231 +@@ -73,10 +73,12 @@ static void slice_range_to_mask(unsigned long start, unsigned long len,
1232 + unsigned long end = start + len - 1;
1233 +
1234 + ret->low_slices = 0;
1235 +- bitmap_zero(ret->high_slices, SLICE_NUM_HIGH);
1236 ++ if (SLICE_NUM_HIGH)
1237 ++ bitmap_zero(ret->high_slices, SLICE_NUM_HIGH);
1238 +
1239 + if (start < SLICE_LOW_TOP) {
1240 +- unsigned long mend = min(end, (SLICE_LOW_TOP - 1));
1241 ++ unsigned long mend = min(end,
1242 ++ (unsigned long)(SLICE_LOW_TOP - 1));
1243 +
1244 + ret->low_slices = (1u << (GET_LOW_SLICE_INDEX(mend) + 1))
1245 + - (1u << GET_LOW_SLICE_INDEX(start));
1246 +@@ -113,11 +115,13 @@ static int slice_high_has_vma(struct mm_struct *mm, unsigned long slice)
1247 + unsigned long start = slice << SLICE_HIGH_SHIFT;
1248 + unsigned long end = start + (1ul << SLICE_HIGH_SHIFT);
1249 +
1250 ++#ifdef CONFIG_PPC64
1251 + /* Hack, so that each addresses is controlled by exactly one
1252 + * of the high or low area bitmaps, the first high area starts
1253 + * at 4GB, not 0 */
1254 + if (start == 0)
1255 + start = SLICE_LOW_TOP;
1256 ++#endif
1257 +
1258 + return !slice_area_is_free(mm, start, end - start);
1259 + }
1260 +@@ -128,7 +132,8 @@ static void slice_mask_for_free(struct mm_struct *mm, struct slice_mask *ret,
1261 + unsigned long i;
1262 +
1263 + ret->low_slices = 0;
1264 +- bitmap_zero(ret->high_slices, SLICE_NUM_HIGH);
1265 ++ if (SLICE_NUM_HIGH)
1266 ++ bitmap_zero(ret->high_slices, SLICE_NUM_HIGH);
1267 +
1268 + for (i = 0; i < SLICE_NUM_LOW; i++)
1269 + if (!slice_low_has_vma(mm, i))
1270 +@@ -151,7 +156,8 @@ static void slice_mask_for_size(struct mm_struct *mm, int psize, struct slice_ma
1271 + u64 lpsizes;
1272 +
1273 + ret->low_slices = 0;
1274 +- bitmap_zero(ret->high_slices, SLICE_NUM_HIGH);
1275 ++ if (SLICE_NUM_HIGH)
1276 ++ bitmap_zero(ret->high_slices, SLICE_NUM_HIGH);
1277 +
1278 + lpsizes = mm->context.low_slices_psize;
1279 + for (i = 0; i < SLICE_NUM_LOW; i++)
1280 +@@ -180,6 +186,10 @@ static int slice_check_fit(struct mm_struct *mm,
1281 + */
1282 + unsigned long slice_count = GET_HIGH_SLICE_INDEX(mm->context.slb_addr_limit);
1283 +
1284 ++ if (!SLICE_NUM_HIGH)
1285 ++ return (mask.low_slices & available.low_slices) ==
1286 ++ mask.low_slices;
1287 ++
1288 + bitmap_and(result, mask.high_slices,
1289 + available.high_slices, slice_count);
1290 +
1291 +@@ -189,6 +199,7 @@ static int slice_check_fit(struct mm_struct *mm,
1292 +
1293 + static void slice_flush_segments(void *parm)
1294 + {
1295 ++#ifdef CONFIG_PPC64
1296 + struct mm_struct *mm = parm;
1297 + unsigned long flags;
1298 +
1299 +@@ -200,6 +211,7 @@ static void slice_flush_segments(void *parm)
1300 + local_irq_save(flags);
1301 + slb_flush_and_rebolt();
1302 + local_irq_restore(flags);
1303 ++#endif
1304 + }
1305 +
1306 + static void slice_convert(struct mm_struct *mm, struct slice_mask mask, int psize)
1307 +@@ -388,21 +400,21 @@ static unsigned long slice_find_area(struct mm_struct *mm, unsigned long len,
1308 +
1309 + static inline void slice_or_mask(struct slice_mask *dst, struct slice_mask *src)
1310 + {
1311 +- DECLARE_BITMAP(result, SLICE_NUM_HIGH);
1312 +-
1313 + dst->low_slices |= src->low_slices;
1314 +- bitmap_or(result, dst->high_slices, src->high_slices, SLICE_NUM_HIGH);
1315 +- bitmap_copy(dst->high_slices, result, SLICE_NUM_HIGH);
1316 ++ if (!SLICE_NUM_HIGH)
1317 ++ return;
1318 ++ bitmap_or(dst->high_slices, dst->high_slices, src->high_slices,
1319 ++ SLICE_NUM_HIGH);
1320 + }
1321 +
1322 + static inline void slice_andnot_mask(struct slice_mask *dst, struct slice_mask *src)
1323 + {
1324 +- DECLARE_BITMAP(result, SLICE_NUM_HIGH);
1325 +-
1326 + dst->low_slices &= ~src->low_slices;
1327 +
1328 +- bitmap_andnot(result, dst->high_slices, src->high_slices, SLICE_NUM_HIGH);
1329 +- bitmap_copy(dst->high_slices, result, SLICE_NUM_HIGH);
1330 ++ if (!SLICE_NUM_HIGH)
1331 ++ return;
1332 ++ bitmap_andnot(dst->high_slices, dst->high_slices, src->high_slices,
1333 ++ SLICE_NUM_HIGH);
1334 + }
1335 +
1336 + #ifdef CONFIG_PPC_64K_PAGES
1337 +@@ -450,14 +462,17 @@ unsigned long slice_get_unmapped_area(unsigned long addr, unsigned long len,
1338 + * init different masks
1339 + */
1340 + mask.low_slices = 0;
1341 +- bitmap_zero(mask.high_slices, SLICE_NUM_HIGH);
1342 +
1343 + /* silence stupid warning */;
1344 + potential_mask.low_slices = 0;
1345 +- bitmap_zero(potential_mask.high_slices, SLICE_NUM_HIGH);
1346 +
1347 + compat_mask.low_slices = 0;
1348 +- bitmap_zero(compat_mask.high_slices, SLICE_NUM_HIGH);
1349 ++
1350 ++ if (SLICE_NUM_HIGH) {
1351 ++ bitmap_zero(mask.high_slices, SLICE_NUM_HIGH);
1352 ++ bitmap_zero(potential_mask.high_slices, SLICE_NUM_HIGH);
1353 ++ bitmap_zero(compat_mask.high_slices, SLICE_NUM_HIGH);
1354 ++ }
1355 +
1356 + /* Sanity checks */
1357 + BUG_ON(mm->task_size == 0);
1358 +@@ -595,7 +610,9 @@ unsigned long slice_get_unmapped_area(unsigned long addr, unsigned long len,
1359 + convert:
1360 + slice_andnot_mask(&mask, &good_mask);
1361 + slice_andnot_mask(&mask, &compat_mask);
1362 +- if (mask.low_slices || !bitmap_empty(mask.high_slices, SLICE_NUM_HIGH)) {
1363 ++ if (mask.low_slices ||
1364 ++ (SLICE_NUM_HIGH &&
1365 ++ !bitmap_empty(mask.high_slices, SLICE_NUM_HIGH))) {
1366 + slice_convert(mm, mask, psize);
1367 + if (psize > MMU_PAGE_BASE)
1368 + on_each_cpu(slice_flush_segments, mm, 1);
1369 +diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
1370 +index f89bbd54ecec..1e55ae2f2afd 100644
1371 +--- a/arch/powerpc/perf/core-book3s.c
1372 ++++ b/arch/powerpc/perf/core-book3s.c
1373 +@@ -457,6 +457,16 @@ static void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw)
1374 + /* invalid entry */
1375 + continue;
1376 +
1377 ++ /*
1378 ++ * BHRB rolling buffer could very much contain the kernel
1379 ++ * addresses at this point. Check the privileges before
1380 ++ * exporting it to userspace (avoid exposure of regions
1381 ++ * where we could have speculative execution)
1382 ++ */
1383 ++ if (perf_paranoid_kernel() && !capable(CAP_SYS_ADMIN) &&
1384 ++ is_kernel_addr(addr))
1385 ++ continue;
1386 ++
1387 + /* Branches are read most recent first (ie. mfbhrb 0 is
1388 + * the most recent branch).
1389 + * There are two types of valid entries:
1390 +@@ -1226,6 +1236,7 @@ static void power_pmu_disable(struct pmu *pmu)
1391 + */
1392 + write_mmcr0(cpuhw, val);
1393 + mb();
1394 ++ isync();
1395 +
1396 + /*
1397 + * Disable instruction sampling if it was enabled
1398 +@@ -1234,12 +1245,26 @@ static void power_pmu_disable(struct pmu *pmu)
1399 + mtspr(SPRN_MMCRA,
1400 + cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1401 + mb();
1402 ++ isync();
1403 + }
1404 +
1405 + cpuhw->disabled = 1;
1406 + cpuhw->n_added = 0;
1407 +
1408 + ebb_switch_out(mmcr0);
1409 ++
1410 ++#ifdef CONFIG_PPC64
1411 ++ /*
1412 ++ * These are readable by userspace, may contain kernel
1413 ++ * addresses and are not switched by context switch, so clear
1414 ++ * them now to avoid leaking anything to userspace in general
1415 ++ * including to another process.
1416 ++ */
1417 ++ if (ppmu->flags & PPMU_ARCH_207S) {
1418 ++ mtspr(SPRN_SDAR, 0);
1419 ++ mtspr(SPRN_SIAR, 0);
1420 ++ }
1421 ++#endif
1422 + }
1423 +
1424 + local_irq_restore(flags);
1425 +diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
1426 +index a429d859f15d..5a8b1bf1e819 100644
1427 +--- a/arch/powerpc/platforms/Kconfig.cputype
1428 ++++ b/arch/powerpc/platforms/Kconfig.cputype
1429 +@@ -326,6 +326,7 @@ config PPC_BOOK3E_MMU
1430 + config PPC_MM_SLICES
1431 + bool
1432 + default y if PPC_BOOK3S_64
1433 ++ default y if PPC_8xx && HUGETLB_PAGE
1434 + default n
1435 +
1436 + config PPC_HAVE_PMU_SUPPORT
1437 +diff --git a/arch/powerpc/platforms/powernv/npu-dma.c b/arch/powerpc/platforms/powernv/npu-dma.c
1438 +index e7b621f619b2..a9a3d62c34d6 100644
1439 +--- a/arch/powerpc/platforms/powernv/npu-dma.c
1440 ++++ b/arch/powerpc/platforms/powernv/npu-dma.c
1441 +@@ -417,6 +417,11 @@ struct npu_context {
1442 + void *priv;
1443 + };
1444 +
1445 ++struct mmio_atsd_reg {
1446 ++ struct npu *npu;
1447 ++ int reg;
1448 ++};
1449 ++
1450 + /*
1451 + * Find a free MMIO ATSD register and mark it in use. Return -ENOSPC
1452 + * if none are available.
1453 +@@ -426,7 +431,7 @@ static int get_mmio_atsd_reg(struct npu *npu)
1454 + int i;
1455 +
1456 + for (i = 0; i < npu->mmio_atsd_count; i++) {
1457 +- if (!test_and_set_bit(i, &npu->mmio_atsd_usage))
1458 ++ if (!test_and_set_bit_lock(i, &npu->mmio_atsd_usage))
1459 + return i;
1460 + }
1461 +
1462 +@@ -435,86 +440,90 @@ static int get_mmio_atsd_reg(struct npu *npu)
1463 +
1464 + static void put_mmio_atsd_reg(struct npu *npu, int reg)
1465 + {
1466 +- clear_bit(reg, &npu->mmio_atsd_usage);
1467 ++ clear_bit_unlock(reg, &npu->mmio_atsd_usage);
1468 + }
1469 +
1470 + /* MMIO ATSD register offsets */
1471 + #define XTS_ATSD_AVA 1
1472 + #define XTS_ATSD_STAT 2
1473 +
1474 +-static int mmio_launch_invalidate(struct npu *npu, unsigned long launch,
1475 +- unsigned long va)
1476 ++static void mmio_launch_invalidate(struct mmio_atsd_reg *mmio_atsd_reg,
1477 ++ unsigned long launch, unsigned long va)
1478 + {
1479 +- int mmio_atsd_reg;
1480 +-
1481 +- do {
1482 +- mmio_atsd_reg = get_mmio_atsd_reg(npu);
1483 +- cpu_relax();
1484 +- } while (mmio_atsd_reg < 0);
1485 ++ struct npu *npu = mmio_atsd_reg->npu;
1486 ++ int reg = mmio_atsd_reg->reg;
1487 +
1488 + __raw_writeq(cpu_to_be64(va),
1489 +- npu->mmio_atsd_regs[mmio_atsd_reg] + XTS_ATSD_AVA);
1490 ++ npu->mmio_atsd_regs[reg] + XTS_ATSD_AVA);
1491 + eieio();
1492 +- __raw_writeq(cpu_to_be64(launch), npu->mmio_atsd_regs[mmio_atsd_reg]);
1493 +-
1494 +- return mmio_atsd_reg;
1495 ++ __raw_writeq(cpu_to_be64(launch), npu->mmio_atsd_regs[reg]);
1496 + }
1497 +
1498 +-static int mmio_invalidate_pid(struct npu *npu, unsigned long pid, bool flush)
1499 ++static void mmio_invalidate_pid(struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS],
1500 ++ unsigned long pid, bool flush)
1501 + {
1502 ++ int i;
1503 + unsigned long launch;
1504 +
1505 +- /* IS set to invalidate matching PID */
1506 +- launch = PPC_BIT(12);
1507 ++ for (i = 0; i <= max_npu2_index; i++) {
1508 ++ if (mmio_atsd_reg[i].reg < 0)
1509 ++ continue;
1510 ++
1511 ++ /* IS set to invalidate matching PID */
1512 ++ launch = PPC_BIT(12);
1513 +
1514 +- /* PRS set to process-scoped */
1515 +- launch |= PPC_BIT(13);
1516 ++ /* PRS set to process-scoped */
1517 ++ launch |= PPC_BIT(13);
1518 +
1519 +- /* AP */
1520 +- launch |= (u64) mmu_get_ap(mmu_virtual_psize) << PPC_BITLSHIFT(17);
1521 ++ /* AP */
1522 ++ launch |= (u64)
1523 ++ mmu_get_ap(mmu_virtual_psize) << PPC_BITLSHIFT(17);
1524 +
1525 +- /* PID */
1526 +- launch |= pid << PPC_BITLSHIFT(38);
1527 ++ /* PID */
1528 ++ launch |= pid << PPC_BITLSHIFT(38);
1529 +
1530 +- /* No flush */
1531 +- launch |= !flush << PPC_BITLSHIFT(39);
1532 ++ /* No flush */
1533 ++ launch |= !flush << PPC_BITLSHIFT(39);
1534 +
1535 +- /* Invalidating the entire process doesn't use a va */
1536 +- return mmio_launch_invalidate(npu, launch, 0);
1537 ++ /* Invalidating the entire process doesn't use a va */
1538 ++ mmio_launch_invalidate(&mmio_atsd_reg[i], launch, 0);
1539 ++ }
1540 + }
1541 +
1542 +-static int mmio_invalidate_va(struct npu *npu, unsigned long va,
1543 +- unsigned long pid, bool flush)
1544 ++static void mmio_invalidate_va(struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS],
1545 ++ unsigned long va, unsigned long pid, bool flush)
1546 + {
1547 ++ int i;
1548 + unsigned long launch;
1549 +
1550 +- /* IS set to invalidate target VA */
1551 +- launch = 0;
1552 ++ for (i = 0; i <= max_npu2_index; i++) {
1553 ++ if (mmio_atsd_reg[i].reg < 0)
1554 ++ continue;
1555 ++
1556 ++ /* IS set to invalidate target VA */
1557 ++ launch = 0;
1558 +
1559 +- /* PRS set to process scoped */
1560 +- launch |= PPC_BIT(13);
1561 ++ /* PRS set to process scoped */
1562 ++ launch |= PPC_BIT(13);
1563 +
1564 +- /* AP */
1565 +- launch |= (u64) mmu_get_ap(mmu_virtual_psize) << PPC_BITLSHIFT(17);
1566 ++ /* AP */
1567 ++ launch |= (u64)
1568 ++ mmu_get_ap(mmu_virtual_psize) << PPC_BITLSHIFT(17);
1569 +
1570 +- /* PID */
1571 +- launch |= pid << PPC_BITLSHIFT(38);
1572 ++ /* PID */
1573 ++ launch |= pid << PPC_BITLSHIFT(38);
1574 +
1575 +- /* No flush */
1576 +- launch |= !flush << PPC_BITLSHIFT(39);
1577 ++ /* No flush */
1578 ++ launch |= !flush << PPC_BITLSHIFT(39);
1579 +
1580 +- return mmio_launch_invalidate(npu, launch, va);
1581 ++ mmio_launch_invalidate(&mmio_atsd_reg[i], launch, va);
1582 ++ }
1583 + }
1584 +
1585 + #define mn_to_npu_context(x) container_of(x, struct npu_context, mn)
1586 +
1587 +-struct mmio_atsd_reg {
1588 +- struct npu *npu;
1589 +- int reg;
1590 +-};
1591 +-
1592 + static void mmio_invalidate_wait(
1593 +- struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS], bool flush)
1594 ++ struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS])
1595 + {
1596 + struct npu *npu;
1597 + int i, reg;
1598 +@@ -529,16 +538,67 @@ static void mmio_invalidate_wait(
1599 + reg = mmio_atsd_reg[i].reg;
1600 + while (__raw_readq(npu->mmio_atsd_regs[reg] + XTS_ATSD_STAT))
1601 + cpu_relax();
1602 ++ }
1603 ++}
1604 ++
1605 ++/*
1606 ++ * Acquires all the address translation shootdown (ATSD) registers required to
1607 ++ * launch an ATSD on all links this npu_context is active on.
1608 ++ */
1609 ++static void acquire_atsd_reg(struct npu_context *npu_context,
1610 ++ struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS])
1611 ++{
1612 ++ int i, j;
1613 ++ struct npu *npu;
1614 ++ struct pci_dev *npdev;
1615 ++ struct pnv_phb *nphb;
1616 +
1617 +- put_mmio_atsd_reg(npu, reg);
1618 ++ for (i = 0; i <= max_npu2_index; i++) {
1619 ++ mmio_atsd_reg[i].reg = -1;
1620 ++ for (j = 0; j < NV_MAX_LINKS; j++) {
1621 ++ /*
1622 ++ * There are no ordering requirements with respect to
1623 ++ * the setup of struct npu_context, but to ensure
1624 ++ * consistent behaviour we need to ensure npdev[][] is
1625 ++ * only read once.
1626 ++ */
1627 ++ npdev = READ_ONCE(npu_context->npdev[i][j]);
1628 ++ if (!npdev)
1629 ++ continue;
1630 +
1631 ++ nphb = pci_bus_to_host(npdev->bus)->private_data;
1632 ++ npu = &nphb->npu;
1633 ++ mmio_atsd_reg[i].npu = npu;
1634 ++ mmio_atsd_reg[i].reg = get_mmio_atsd_reg(npu);
1635 ++ while (mmio_atsd_reg[i].reg < 0) {
1636 ++ mmio_atsd_reg[i].reg = get_mmio_atsd_reg(npu);
1637 ++ cpu_relax();
1638 ++ }
1639 ++ break;
1640 ++ }
1641 ++ }
1642 ++}
1643 ++
1644 ++/*
1645 ++ * Release previously acquired ATSD registers. To avoid deadlocks the registers
1646 ++ * must be released in the same order they were acquired above in
1647 ++ * acquire_atsd_reg.
1648 ++ */
1649 ++static void release_atsd_reg(struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS])
1650 ++{
1651 ++ int i;
1652 ++
1653 ++ for (i = 0; i <= max_npu2_index; i++) {
1654 + /*
1655 +- * The GPU requires two flush ATSDs to ensure all entries have
1656 +- * been flushed. We use PID 0 as it will never be used for a
1657 +- * process on the GPU.
1658 ++ * We can't rely on npu_context->npdev[][] being the same here
1659 ++ * as when acquire_atsd_reg() was called, hence we use the
1660 ++ * values stored in mmio_atsd_reg during the acquire phase
1661 ++ * rather than re-reading npdev[][].
1662 + */
1663 +- if (flush)
1664 +- mmio_invalidate_pid(npu, 0, true);
1665 ++ if (mmio_atsd_reg[i].reg < 0)
1666 ++ continue;
1667 ++
1668 ++ put_mmio_atsd_reg(mmio_atsd_reg[i].npu, mmio_atsd_reg[i].reg);
1669 + }
1670 + }
1671 +
1672 +@@ -549,10 +609,6 @@ static void mmio_invalidate_wait(
1673 + static void mmio_invalidate(struct npu_context *npu_context, int va,
1674 + unsigned long address, bool flush)
1675 + {
1676 +- int i, j;
1677 +- struct npu *npu;
1678 +- struct pnv_phb *nphb;
1679 +- struct pci_dev *npdev;
1680 + struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS];
1681 + unsigned long pid = npu_context->mm->context.id;
1682 +
1683 +@@ -568,37 +624,25 @@ static void mmio_invalidate(struct npu_context *npu_context, int va,
1684 + * Loop over all the NPUs this process is active on and launch
1685 + * an invalidate.
1686 + */
1687 +- for (i = 0; i <= max_npu2_index; i++) {
1688 +- mmio_atsd_reg[i].reg = -1;
1689 +- for (j = 0; j < NV_MAX_LINKS; j++) {
1690 +- npdev = npu_context->npdev[i][j];
1691 +- if (!npdev)
1692 +- continue;
1693 +-
1694 +- nphb = pci_bus_to_host(npdev->bus)->private_data;
1695 +- npu = &nphb->npu;
1696 +- mmio_atsd_reg[i].npu = npu;
1697 +-
1698 +- if (va)
1699 +- mmio_atsd_reg[i].reg =
1700 +- mmio_invalidate_va(npu, address, pid,
1701 +- flush);
1702 +- else
1703 +- mmio_atsd_reg[i].reg =
1704 +- mmio_invalidate_pid(npu, pid, flush);
1705 +-
1706 +- /*
1707 +- * The NPU hardware forwards the shootdown to all GPUs
1708 +- * so we only have to launch one shootdown per NPU.
1709 +- */
1710 +- break;
1711 +- }
1712 ++ acquire_atsd_reg(npu_context, mmio_atsd_reg);
1713 ++ if (va)
1714 ++ mmio_invalidate_va(mmio_atsd_reg, address, pid, flush);
1715 ++ else
1716 ++ mmio_invalidate_pid(mmio_atsd_reg, pid, flush);
1717 ++
1718 ++ mmio_invalidate_wait(mmio_atsd_reg);
1719 ++ if (flush) {
1720 ++ /*
1721 ++ * The GPU requires two flush ATSDs to ensure all entries have
1722 ++ * been flushed. We use PID 0 as it will never be used for a
1723 ++ * process on the GPU.
1724 ++ */
1725 ++ mmio_invalidate_pid(mmio_atsd_reg, 0, true);
1726 ++ mmio_invalidate_wait(mmio_atsd_reg);
1727 ++ mmio_invalidate_pid(mmio_atsd_reg, 0, true);
1728 ++ mmio_invalidate_wait(mmio_atsd_reg);
1729 + }
1730 +-
1731 +- mmio_invalidate_wait(mmio_atsd_reg, flush);
1732 +- if (flush)
1733 +- /* Wait for the flush to complete */
1734 +- mmio_invalidate_wait(mmio_atsd_reg, false);
1735 ++ release_atsd_reg(mmio_atsd_reg);
1736 + }
1737 +
1738 + static void pnv_npu2_mn_release(struct mmu_notifier *mn,
1739 +@@ -741,7 +785,16 @@ struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
1740 + if (WARN_ON(of_property_read_u32(nvlink_dn, "ibm,npu-link-index",
1741 + &nvlink_index)))
1742 + return ERR_PTR(-ENODEV);
1743 +- npu_context->npdev[npu->index][nvlink_index] = npdev;
1744 ++
1745 ++ /*
1746 ++ * npdev is a pci_dev pointer setup by the PCI code. We assign it to
1747 ++ * npdev[][] to indicate to the mmu notifiers that an invalidation
1748 ++ * should also be sent over this nvlink. The notifiers don't use any
1749 ++ * other fields in npu_context, so we just need to ensure that when they
1750 ++ * deference npu_context->npdev[][] it is either a valid pointer or
1751 ++ * NULL.
1752 ++ */
1753 ++ WRITE_ONCE(npu_context->npdev[npu->index][nvlink_index], npdev);
1754 +
1755 + if (!nphb->npu.nmmu_flush) {
1756 + /*
1757 +@@ -793,7 +846,7 @@ void pnv_npu2_destroy_context(struct npu_context *npu_context,
1758 + if (WARN_ON(of_property_read_u32(nvlink_dn, "ibm,npu-link-index",
1759 + &nvlink_index)))
1760 + return;
1761 +- npu_context->npdev[npu->index][nvlink_index] = NULL;
1762 ++ WRITE_ONCE(npu_context->npdev[npu->index][nvlink_index], NULL);
1763 + opal_npu_destroy_context(nphb->opal_id, npu_context->mm->context.id,
1764 + PCI_DEVID(gpdev->bus->number, gpdev->devfn));
1765 + kref_put(&npu_context->kref, pnv_npu2_release_context);
1766 +diff --git a/arch/powerpc/platforms/powernv/vas-debug.c b/arch/powerpc/platforms/powernv/vas-debug.c
1767 +index ca22f1eae050..3161e39eea1d 100644
1768 +--- a/arch/powerpc/platforms/powernv/vas-debug.c
1769 ++++ b/arch/powerpc/platforms/powernv/vas-debug.c
1770 +@@ -179,6 +179,7 @@ void vas_instance_init_dbgdir(struct vas_instance *vinst)
1771 + {
1772 + struct dentry *d;
1773 +
1774 ++ vas_init_dbgdir();
1775 + if (!vas_debugfs)
1776 + return;
1777 +
1778 +@@ -201,8 +202,18 @@ void vas_instance_init_dbgdir(struct vas_instance *vinst)
1779 + vinst->dbgdir = NULL;
1780 + }
1781 +
1782 ++/*
1783 ++ * Set up the "root" VAS debugfs dir. Return if we already set it up
1784 ++ * (or failed to) in an earlier instance of VAS.
1785 ++ */
1786 + void vas_init_dbgdir(void)
1787 + {
1788 ++ static bool first_time = true;
1789 ++
1790 ++ if (!first_time)
1791 ++ return;
1792 ++
1793 ++ first_time = false;
1794 + vas_debugfs = debugfs_create_dir("vas", NULL);
1795 + if (IS_ERR(vas_debugfs))
1796 + vas_debugfs = NULL;
1797 +diff --git a/arch/powerpc/platforms/powernv/vas.c b/arch/powerpc/platforms/powernv/vas.c
1798 +index aebbe95c9230..5a2b24cbbc88 100644
1799 +--- a/arch/powerpc/platforms/powernv/vas.c
1800 ++++ b/arch/powerpc/platforms/powernv/vas.c
1801 +@@ -160,8 +160,6 @@ static int __init vas_init(void)
1802 + int found = 0;
1803 + struct device_node *dn;
1804 +
1805 +- vas_init_dbgdir();
1806 +-
1807 + platform_driver_register(&vas_driver);
1808 +
1809 + for_each_compatible_node(dn, NULL, "ibm,vas") {
1810 +@@ -169,8 +167,10 @@ static int __init vas_init(void)
1811 + found++;
1812 + }
1813 +
1814 +- if (!found)
1815 ++ if (!found) {
1816 ++ platform_driver_unregister(&vas_driver);
1817 + return -ENODEV;
1818 ++ }
1819 +
1820 + pr_devel("Found %d instances\n", found);
1821 +
1822 +diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
1823 +index 73067805300a..1d4e0ef658d3 100644
1824 +--- a/arch/powerpc/sysdev/mpic.c
1825 ++++ b/arch/powerpc/sysdev/mpic.c
1826 +@@ -626,7 +626,7 @@ static inline u32 mpic_physmask(u32 cpumask)
1827 + int i;
1828 + u32 mask = 0;
1829 +
1830 +- for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
1831 ++ for (i = 0; i < min(32, NR_CPUS) && cpu_possible(i); ++i, cpumask >>= 1)
1832 + mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
1833 + return mask;
1834 + }
1835 +diff --git a/arch/riscv/include/asm/fence.h b/arch/riscv/include/asm/fence.h
1836 +new file mode 100644
1837 +index 000000000000..2b443a3a487f
1838 +--- /dev/null
1839 ++++ b/arch/riscv/include/asm/fence.h
1840 +@@ -0,0 +1,12 @@
1841 ++#ifndef _ASM_RISCV_FENCE_H
1842 ++#define _ASM_RISCV_FENCE_H
1843 ++
1844 ++#ifdef CONFIG_SMP
1845 ++#define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n"
1846 ++#define RISCV_RELEASE_BARRIER "\tfence rw, w\n"
1847 ++#else
1848 ++#define RISCV_ACQUIRE_BARRIER
1849 ++#define RISCV_RELEASE_BARRIER
1850 ++#endif
1851 ++
1852 ++#endif /* _ASM_RISCV_FENCE_H */
1853 +diff --git a/arch/riscv/include/asm/spinlock.h b/arch/riscv/include/asm/spinlock.h
1854 +index 2fd27e8ef1fd..8eb26d1ede81 100644
1855 +--- a/arch/riscv/include/asm/spinlock.h
1856 ++++ b/arch/riscv/include/asm/spinlock.h
1857 +@@ -17,6 +17,7 @@
1858 +
1859 + #include <linux/kernel.h>
1860 + #include <asm/current.h>
1861 ++#include <asm/fence.h>
1862 +
1863 + /*
1864 + * Simple spin lock operations. These provide no fairness guarantees.
1865 +@@ -28,10 +29,7 @@
1866 +
1867 + static inline void arch_spin_unlock(arch_spinlock_t *lock)
1868 + {
1869 +- __asm__ __volatile__ (
1870 +- "amoswap.w.rl x0, x0, %0"
1871 +- : "=A" (lock->lock)
1872 +- :: "memory");
1873 ++ smp_store_release(&lock->lock, 0);
1874 + }
1875 +
1876 + static inline int arch_spin_trylock(arch_spinlock_t *lock)
1877 +@@ -39,7 +37,8 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
1878 + int tmp = 1, busy;
1879 +
1880 + __asm__ __volatile__ (
1881 +- "amoswap.w.aq %0, %2, %1"
1882 ++ " amoswap.w %0, %2, %1\n"
1883 ++ RISCV_ACQUIRE_BARRIER
1884 + : "=r" (busy), "+A" (lock->lock)
1885 + : "r" (tmp)
1886 + : "memory");
1887 +@@ -68,8 +67,9 @@ static inline void arch_read_lock(arch_rwlock_t *lock)
1888 + "1: lr.w %1, %0\n"
1889 + " bltz %1, 1b\n"
1890 + " addi %1, %1, 1\n"
1891 +- " sc.w.aq %1, %1, %0\n"
1892 ++ " sc.w %1, %1, %0\n"
1893 + " bnez %1, 1b\n"
1894 ++ RISCV_ACQUIRE_BARRIER
1895 + : "+A" (lock->lock), "=&r" (tmp)
1896 + :: "memory");
1897 + }
1898 +@@ -82,8 +82,9 @@ static inline void arch_write_lock(arch_rwlock_t *lock)
1899 + "1: lr.w %1, %0\n"
1900 + " bnez %1, 1b\n"
1901 + " li %1, -1\n"
1902 +- " sc.w.aq %1, %1, %0\n"
1903 ++ " sc.w %1, %1, %0\n"
1904 + " bnez %1, 1b\n"
1905 ++ RISCV_ACQUIRE_BARRIER
1906 + : "+A" (lock->lock), "=&r" (tmp)
1907 + :: "memory");
1908 + }
1909 +@@ -96,8 +97,9 @@ static inline int arch_read_trylock(arch_rwlock_t *lock)
1910 + "1: lr.w %1, %0\n"
1911 + " bltz %1, 1f\n"
1912 + " addi %1, %1, 1\n"
1913 +- " sc.w.aq %1, %1, %0\n"
1914 ++ " sc.w %1, %1, %0\n"
1915 + " bnez %1, 1b\n"
1916 ++ RISCV_ACQUIRE_BARRIER
1917 + "1:\n"
1918 + : "+A" (lock->lock), "=&r" (busy)
1919 + :: "memory");
1920 +@@ -113,8 +115,9 @@ static inline int arch_write_trylock(arch_rwlock_t *lock)
1921 + "1: lr.w %1, %0\n"
1922 + " bnez %1, 1f\n"
1923 + " li %1, -1\n"
1924 +- " sc.w.aq %1, %1, %0\n"
1925 ++ " sc.w %1, %1, %0\n"
1926 + " bnez %1, 1b\n"
1927 ++ RISCV_ACQUIRE_BARRIER
1928 + "1:\n"
1929 + : "+A" (lock->lock), "=&r" (busy)
1930 + :: "memory");
1931 +@@ -125,7 +128,8 @@ static inline int arch_write_trylock(arch_rwlock_t *lock)
1932 + static inline void arch_read_unlock(arch_rwlock_t *lock)
1933 + {
1934 + __asm__ __volatile__(
1935 +- "amoadd.w.rl x0, %1, %0"
1936 ++ RISCV_RELEASE_BARRIER
1937 ++ " amoadd.w x0, %1, %0\n"
1938 + : "+A" (lock->lock)
1939 + : "r" (-1)
1940 + : "memory");
1941 +@@ -133,10 +137,7 @@ static inline void arch_read_unlock(arch_rwlock_t *lock)
1942 +
1943 + static inline void arch_write_unlock(arch_rwlock_t *lock)
1944 + {
1945 +- __asm__ __volatile__ (
1946 +- "amoswap.w.rl x0, x0, %0"
1947 +- : "=A" (lock->lock)
1948 +- :: "memory");
1949 ++ smp_store_release(&lock->lock, 0);
1950 + }
1951 +
1952 + #endif /* _ASM_RISCV_SPINLOCK_H */
1953 +diff --git a/arch/s390/kvm/vsie.c b/arch/s390/kvm/vsie.c
1954 +index 8961e3970901..969882b54266 100644
1955 +--- a/arch/s390/kvm/vsie.c
1956 ++++ b/arch/s390/kvm/vsie.c
1957 +@@ -578,7 +578,7 @@ static int pin_blocks(struct kvm_vcpu *vcpu, struct vsie_page *vsie_page)
1958 +
1959 + gpa = READ_ONCE(scb_o->itdba) & ~0xffUL;
1960 + if (gpa && (scb_s->ecb & ECB_TE)) {
1961 +- if (!(gpa & ~0x1fffU)) {
1962 ++ if (!(gpa & ~0x1fffUL)) {
1963 + rc = set_validity_icpt(scb_s, 0x0080U);
1964 + goto unpin;
1965 + }
1966 +diff --git a/arch/sh/kernel/entry-common.S b/arch/sh/kernel/entry-common.S
1967 +index c001f782c5f1..28cc61216b64 100644
1968 +--- a/arch/sh/kernel/entry-common.S
1969 ++++ b/arch/sh/kernel/entry-common.S
1970 +@@ -255,7 +255,7 @@ debug_trap:
1971 + mov.l @r8, r8
1972 + jsr @r8
1973 + nop
1974 +- bra __restore_all
1975 ++ bra ret_from_exception
1976 + nop
1977 + CFI_ENDPROC
1978 +
1979 +diff --git a/arch/sparc/include/asm/atomic_64.h b/arch/sparc/include/asm/atomic_64.h
1980 +index abad97edf736..28db058d471b 100644
1981 +--- a/arch/sparc/include/asm/atomic_64.h
1982 ++++ b/arch/sparc/include/asm/atomic_64.h
1983 +@@ -83,7 +83,11 @@ ATOMIC_OPS(xor)
1984 + #define atomic64_add_negative(i, v) (atomic64_add_return(i, v) < 0)
1985 +
1986 + #define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
1987 +-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
1988 ++
1989 ++static inline int atomic_xchg(atomic_t *v, int new)
1990 ++{
1991 ++ return xchg(&v->counter, new);
1992 ++}
1993 +
1994 + static inline int __atomic_add_unless(atomic_t *v, int a, int u)
1995 + {
1996 +diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
1997 +index 06086439b7bd..70610604c360 100644
1998 +--- a/arch/x86/events/core.c
1999 ++++ b/arch/x86/events/core.c
2000 +@@ -1162,16 +1162,13 @@ int x86_perf_event_set_period(struct perf_event *event)
2001 +
2002 + per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
2003 +
2004 +- if (!(hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) ||
2005 +- local64_read(&hwc->prev_count) != (u64)-left) {
2006 +- /*
2007 +- * The hw event starts counting from this event offset,
2008 +- * mark it to be able to extra future deltas:
2009 +- */
2010 +- local64_set(&hwc->prev_count, (u64)-left);
2011 ++ /*
2012 ++ * The hw event starts counting from this event offset,
2013 ++ * mark it to be able to extra future deltas:
2014 ++ */
2015 ++ local64_set(&hwc->prev_count, (u64)-left);
2016 +
2017 +- wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
2018 +- }
2019 ++ wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
2020 +
2021 + /*
2022 + * Due to erratum on certan cpu we need
2023 +diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
2024 +index 1e41d7508d99..39cd0b36c790 100644
2025 +--- a/arch/x86/events/intel/core.c
2026 ++++ b/arch/x86/events/intel/core.c
2027 +@@ -2201,9 +2201,15 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
2028 + int bit, loops;
2029 + u64 status;
2030 + int handled;
2031 ++ int pmu_enabled;
2032 +
2033 + cpuc = this_cpu_ptr(&cpu_hw_events);
2034 +
2035 ++ /*
2036 ++ * Save the PMU state.
2037 ++ * It needs to be restored when leaving the handler.
2038 ++ */
2039 ++ pmu_enabled = cpuc->enabled;
2040 + /*
2041 + * No known reason to not always do late ACK,
2042 + * but just in case do it opt-in.
2043 +@@ -2211,6 +2217,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
2044 + if (!x86_pmu.late_ack)
2045 + apic_write(APIC_LVTPC, APIC_DM_NMI);
2046 + intel_bts_disable_local();
2047 ++ cpuc->enabled = 0;
2048 + __intel_pmu_disable_all();
2049 + handled = intel_pmu_drain_bts_buffer();
2050 + handled += intel_bts_interrupt();
2051 +@@ -2320,7 +2327,8 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
2052 +
2053 + done:
2054 + /* Only restore PMU state when it's active. See x86_pmu_disable(). */
2055 +- if (cpuc->enabled)
2056 ++ cpuc->enabled = pmu_enabled;
2057 ++ if (pmu_enabled)
2058 + __intel_pmu_enable_all(0, true);
2059 + intel_bts_enable_local();
2060 +
2061 +@@ -3188,7 +3196,7 @@ glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2062 + * Therefore the effective (average) period matches the requested period,
2063 + * despite coarser hardware granularity.
2064 + */
2065 +-static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
2066 ++static u64 bdw_limit_period(struct perf_event *event, u64 left)
2067 + {
2068 + if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
2069 + X86_CONFIG(.event=0xc0, .umask=0x01)) {
2070 +diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
2071 +index 5e526c54247e..cc0eb543cc70 100644
2072 +--- a/arch/x86/events/intel/ds.c
2073 ++++ b/arch/x86/events/intel/ds.c
2074 +@@ -1315,17 +1315,84 @@ get_next_pebs_record_by_bit(void *base, void *top, int bit)
2075 + return NULL;
2076 + }
2077 +
2078 ++/*
2079 ++ * Special variant of intel_pmu_save_and_restart() for auto-reload.
2080 ++ */
2081 ++static int
2082 ++intel_pmu_save_and_restart_reload(struct perf_event *event, int count)
2083 ++{
2084 ++ struct hw_perf_event *hwc = &event->hw;
2085 ++ int shift = 64 - x86_pmu.cntval_bits;
2086 ++ u64 period = hwc->sample_period;
2087 ++ u64 prev_raw_count, new_raw_count;
2088 ++ s64 new, old;
2089 ++
2090 ++ WARN_ON(!period);
2091 ++
2092 ++ /*
2093 ++ * drain_pebs() only happens when the PMU is disabled.
2094 ++ */
2095 ++ WARN_ON(this_cpu_read(cpu_hw_events.enabled));
2096 ++
2097 ++ prev_raw_count = local64_read(&hwc->prev_count);
2098 ++ rdpmcl(hwc->event_base_rdpmc, new_raw_count);
2099 ++ local64_set(&hwc->prev_count, new_raw_count);
2100 ++
2101 ++ /*
2102 ++ * Since the counter increments a negative counter value and
2103 ++ * overflows on the sign switch, giving the interval:
2104 ++ *
2105 ++ * [-period, 0]
2106 ++ *
2107 ++ * the difference between two consequtive reads is:
2108 ++ *
2109 ++ * A) value2 - value1;
2110 ++ * when no overflows have happened in between,
2111 ++ *
2112 ++ * B) (0 - value1) + (value2 - (-period));
2113 ++ * when one overflow happened in between,
2114 ++ *
2115 ++ * C) (0 - value1) + (n - 1) * (period) + (value2 - (-period));
2116 ++ * when @n overflows happened in between.
2117 ++ *
2118 ++ * Here A) is the obvious difference, B) is the extension to the
2119 ++ * discrete interval, where the first term is to the top of the
2120 ++ * interval and the second term is from the bottom of the next
2121 ++ * interval and C) the extension to multiple intervals, where the
2122 ++ * middle term is the whole intervals covered.
2123 ++ *
2124 ++ * An equivalent of C, by reduction, is:
2125 ++ *
2126 ++ * value2 - value1 + n * period
2127 ++ */
2128 ++ new = ((s64)(new_raw_count << shift) >> shift);
2129 ++ old = ((s64)(prev_raw_count << shift) >> shift);
2130 ++ local64_add(new - old + count * period, &event->count);
2131 ++
2132 ++ perf_event_update_userpage(event);
2133 ++
2134 ++ return 0;
2135 ++}
2136 ++
2137 + static void __intel_pmu_pebs_event(struct perf_event *event,
2138 + struct pt_regs *iregs,
2139 + void *base, void *top,
2140 + int bit, int count)
2141 + {
2142 ++ struct hw_perf_event *hwc = &event->hw;
2143 + struct perf_sample_data data;
2144 + struct pt_regs regs;
2145 + void *at = get_next_pebs_record_by_bit(base, top, bit);
2146 +
2147 +- if (!intel_pmu_save_and_restart(event) &&
2148 +- !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD))
2149 ++ if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
2150 ++ /*
2151 ++ * Now, auto-reload is only enabled in fixed period mode.
2152 ++ * The reload value is always hwc->sample_period.
2153 ++ * May need to change it, if auto-reload is enabled in
2154 ++ * freq mode later.
2155 ++ */
2156 ++ intel_pmu_save_and_restart_reload(event, count);
2157 ++ } else if (!intel_pmu_save_and_restart(event))
2158 + return;
2159 +
2160 + while (count > 1) {
2161 +@@ -1377,8 +1444,11 @@ static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
2162 + return;
2163 +
2164 + n = top - at;
2165 +- if (n <= 0)
2166 ++ if (n <= 0) {
2167 ++ if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2168 ++ intel_pmu_save_and_restart_reload(event, 0);
2169 + return;
2170 ++ }
2171 +
2172 + __intel_pmu_pebs_event(event, iregs, at, top, 0, n);
2173 + }
2174 +@@ -1401,8 +1471,22 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
2175 +
2176 + ds->pebs_index = ds->pebs_buffer_base;
2177 +
2178 +- if (unlikely(base >= top))
2179 ++ if (unlikely(base >= top)) {
2180 ++ /*
2181 ++ * The drain_pebs() could be called twice in a short period
2182 ++ * for auto-reload event in pmu::read(). There are no
2183 ++ * overflows have happened in between.
2184 ++ * It needs to call intel_pmu_save_and_restart_reload() to
2185 ++ * update the event->count for this case.
2186 ++ */
2187 ++ for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled,
2188 ++ x86_pmu.max_pebs_events) {
2189 ++ event = cpuc->events[bit];
2190 ++ if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2191 ++ intel_pmu_save_and_restart_reload(event, 0);
2192 ++ }
2193 + return;
2194 ++ }
2195 +
2196 + for (at = base; at < top; at += x86_pmu.pebs_record_size) {
2197 + struct pebs_record_nhm *p = at;
2198 +diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
2199 +index 39cd0615f04f..5e2ef399ac86 100644
2200 +--- a/arch/x86/events/perf_event.h
2201 ++++ b/arch/x86/events/perf_event.h
2202 +@@ -557,7 +557,7 @@ struct x86_pmu {
2203 + struct x86_pmu_quirk *quirks;
2204 + int perfctr_second_write;
2205 + bool late_ack;
2206 +- unsigned (*limit_period)(struct perf_event *event, unsigned l);
2207 ++ u64 (*limit_period)(struct perf_event *event, u64 l);
2208 +
2209 + /*
2210 + * sysfs attrs
2211 +diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
2212 +index 84137c22fdfa..6690cd3fc8b1 100644
2213 +--- a/arch/x86/include/asm/tlbflush.h
2214 ++++ b/arch/x86/include/asm/tlbflush.h
2215 +@@ -131,7 +131,12 @@ static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
2216 + static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
2217 + {
2218 + VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
2219 +- VM_WARN_ON_ONCE(!this_cpu_has(X86_FEATURE_PCID));
2220 ++ /*
2221 ++ * Use boot_cpu_has() instead of this_cpu_has() as this function
2222 ++ * might be called during early boot. This should work even after
2223 ++ * boot because all CPU's the have same capabilities:
2224 ++ */
2225 ++ VM_WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_PCID));
2226 + return __sme_pa(pgd) | kern_pcid(asid) | CR3_NOFLUSH;
2227 + }
2228 +
2229 +diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
2230 +index b203af0855b5..5071cc7972ea 100644
2231 +--- a/arch/x86/kernel/apic/apic.c
2232 ++++ b/arch/x86/kernel/apic/apic.c
2233 +@@ -1570,7 +1570,7 @@ void setup_local_APIC(void)
2234 + * TODO: set up through-local-APIC from through-I/O-APIC? --macro
2235 + */
2236 + value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
2237 +- if (!cpu && (pic_mode || !value)) {
2238 ++ if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
2239 + value = APIC_DM_EXTINT;
2240 + apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
2241 + } else {
2242 +diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
2243 +index 25de5f6ca997..5cd387fcc777 100644
2244 +--- a/arch/x86/kernel/devicetree.c
2245 ++++ b/arch/x86/kernel/devicetree.c
2246 +@@ -11,6 +11,7 @@
2247 + #include <linux/of_address.h>
2248 + #include <linux/of_platform.h>
2249 + #include <linux/of_irq.h>
2250 ++#include <linux/libfdt.h>
2251 + #include <linux/slab.h>
2252 + #include <linux/pci.h>
2253 + #include <linux/of_pci.h>
2254 +@@ -194,19 +195,22 @@ static struct of_ioapic_type of_ioapic_type[] =
2255 + static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2256 + unsigned int nr_irqs, void *arg)
2257 + {
2258 +- struct of_phandle_args *irq_data = (void *)arg;
2259 ++ struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
2260 + struct of_ioapic_type *it;
2261 + struct irq_alloc_info tmp;
2262 ++ int type_index;
2263 +
2264 +- if (WARN_ON(irq_data->args_count < 2))
2265 ++ if (WARN_ON(fwspec->param_count < 2))
2266 + return -EINVAL;
2267 +- if (irq_data->args[1] >= ARRAY_SIZE(of_ioapic_type))
2268 ++
2269 ++ type_index = fwspec->param[1];
2270 ++ if (type_index >= ARRAY_SIZE(of_ioapic_type))
2271 + return -EINVAL;
2272 +
2273 +- it = &of_ioapic_type[irq_data->args[1]];
2274 ++ it = &of_ioapic_type[type_index];
2275 + ioapic_set_alloc_attr(&tmp, NUMA_NO_NODE, it->trigger, it->polarity);
2276 + tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
2277 +- tmp.ioapic_pin = irq_data->args[0];
2278 ++ tmp.ioapic_pin = fwspec->param[0];
2279 +
2280 + return mp_irqdomain_alloc(domain, virq, nr_irqs, &tmp);
2281 + }
2282 +@@ -270,14 +274,15 @@ static void __init x86_flattree_get_config(void)
2283 +
2284 + map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
2285 +
2286 +- initial_boot_params = dt = early_memremap(initial_dtb, map_len);
2287 +- size = of_get_flat_dt_size();
2288 ++ dt = early_memremap(initial_dtb, map_len);
2289 ++ size = fdt_totalsize(dt);
2290 + if (map_len < size) {
2291 + early_memunmap(dt, map_len);
2292 +- initial_boot_params = dt = early_memremap(initial_dtb, size);
2293 ++ dt = early_memremap(initial_dtb, size);
2294 + map_len = size;
2295 + }
2296 +
2297 ++ early_init_dt_verify(dt);
2298 + unflatten_and_copy_device_tree();
2299 + early_memunmap(dt, map_len);
2300 + }
2301 +diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
2302 +index 3f400004f602..752f361ef453 100644
2303 +--- a/arch/x86/kvm/cpuid.c
2304 ++++ b/arch/x86/kvm/cpuid.c
2305 +@@ -402,8 +402,8 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2306 +
2307 + /* cpuid 7.0.edx*/
2308 + const u32 kvm_cpuid_7_0_edx_x86_features =
2309 +- F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | F(SSBD) |
2310 +- F(ARCH_CAPABILITIES);
2311 ++ F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
2312 ++ F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES);
2313 +
2314 + /* all calls to cpuid_count() should be made on the same cpu */
2315 + get_cpu();
2316 +@@ -490,6 +490,11 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2317 + entry->ecx &= ~F(PKU);
2318 + entry->edx &= kvm_cpuid_7_0_edx_x86_features;
2319 + cpuid_mask(&entry->edx, CPUID_7_EDX);
2320 ++ /*
2321 ++ * We emulate ARCH_CAPABILITIES in software even
2322 ++ * if the host doesn't support it.
2323 ++ */
2324 ++ entry->edx |= F(ARCH_CAPABILITIES);
2325 + } else {
2326 + entry->ebx = 0;
2327 + entry->ecx = 0;
2328 +diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
2329 +index 7cf470a3755f..3773c4625114 100644
2330 +--- a/arch/x86/kvm/lapic.c
2331 ++++ b/arch/x86/kvm/lapic.c
2332 +@@ -321,8 +321,16 @@ void kvm_apic_set_version(struct kvm_vcpu *vcpu)
2333 + if (!lapic_in_kernel(vcpu))
2334 + return;
2335 +
2336 ++ /*
2337 ++ * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
2338 ++ * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
2339 ++ * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
2340 ++ * version first and level-triggered interrupts never get EOIed in
2341 ++ * IOAPIC.
2342 ++ */
2343 + feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
2344 +- if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
2345 ++ if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))) &&
2346 ++ !ioapic_in_kernel(vcpu->kvm))
2347 + v |= APIC_LVR_DIRECTED_EOI;
2348 + kvm_lapic_set_reg(apic, APIC_LVR, v);
2349 + }
2350 +@@ -1514,11 +1522,23 @@ static bool set_target_expiration(struct kvm_lapic *apic)
2351 +
2352 + static void advance_periodic_target_expiration(struct kvm_lapic *apic)
2353 + {
2354 +- apic->lapic_timer.tscdeadline +=
2355 +- nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
2356 ++ ktime_t now = ktime_get();
2357 ++ u64 tscl = rdtsc();
2358 ++ ktime_t delta;
2359 ++
2360 ++ /*
2361 ++ * Synchronize both deadlines to the same time source or
2362 ++ * differences in the periods (caused by differences in the
2363 ++ * underlying clocks or numerical approximation errors) will
2364 ++ * cause the two to drift apart over time as the errors
2365 ++ * accumulate.
2366 ++ */
2367 + apic->lapic_timer.target_expiration =
2368 + ktime_add_ns(apic->lapic_timer.target_expiration,
2369 + apic->lapic_timer.period);
2370 ++ delta = ktime_sub(apic->lapic_timer.target_expiration, now);
2371 ++ apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
2372 ++ nsec_to_cycles(apic->vcpu, delta);
2373 + }
2374 +
2375 + static void start_sw_period(struct kvm_lapic *apic)
2376 +diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
2377 +index 3deb153bf9d9..11e2147c3824 100644
2378 +--- a/arch/x86/kvm/vmx.c
2379 ++++ b/arch/x86/kvm/vmx.c
2380 +@@ -2561,6 +2561,8 @@ static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2381 + return;
2382 + }
2383 +
2384 ++ WARN_ON_ONCE(vmx->emulation_required);
2385 ++
2386 + if (kvm_exception_is_soft(nr)) {
2387 + vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2388 + vmx->vcpu.arch.event_exit_inst_len);
2389 +@@ -6854,12 +6856,12 @@ static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
2390 + goto out;
2391 + }
2392 +
2393 +- if (err != EMULATE_DONE) {
2394 +- vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2395 +- vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2396 +- vcpu->run->internal.ndata = 0;
2397 +- return 0;
2398 +- }
2399 ++ if (err != EMULATE_DONE)
2400 ++ goto emulation_error;
2401 ++
2402 ++ if (vmx->emulation_required && !vmx->rmode.vm86_active &&
2403 ++ vcpu->arch.exception.pending)
2404 ++ goto emulation_error;
2405 +
2406 + if (vcpu->arch.halt_request) {
2407 + vcpu->arch.halt_request = 0;
2408 +@@ -6875,6 +6877,12 @@ static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
2409 +
2410 + out:
2411 + return ret;
2412 ++
2413 ++emulation_error:
2414 ++ vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2415 ++ vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2416 ++ vcpu->run->internal.ndata = 0;
2417 ++ return 0;
2418 + }
2419 +
2420 + static int __grow_ple_window(int val)
2421 +diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
2422 +index f3df3a934733..999560ff12b5 100644
2423 +--- a/arch/x86/kvm/x86.c
2424 ++++ b/arch/x86/kvm/x86.c
2425 +@@ -7777,6 +7777,7 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
2426 + {
2427 + struct msr_data apic_base_msr;
2428 + int mmu_reset_needed = 0;
2429 ++ int cpuid_update_needed = 0;
2430 + int pending_vec, max_bits, idx;
2431 + struct desc_ptr dt;
2432 + int ret = -EINVAL;
2433 +@@ -7817,8 +7818,10 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
2434 + vcpu->arch.cr0 = sregs->cr0;
2435 +
2436 + mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
2437 ++ cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
2438 ++ (X86_CR4_OSXSAVE | X86_CR4_PKE));
2439 + kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
2440 +- if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
2441 ++ if (cpuid_update_needed)
2442 + kvm_update_cpuid(vcpu);
2443 +
2444 + idx = srcu_read_lock(&vcpu->kvm->srcu);
2445 +diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
2446 +index 85cf12219dea..94c41044a578 100644
2447 +--- a/arch/x86/mm/pageattr.c
2448 ++++ b/arch/x86/mm/pageattr.c
2449 +@@ -298,9 +298,11 @@ static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
2450 +
2451 + /*
2452 + * The .rodata section needs to be read-only. Using the pfn
2453 +- * catches all aliases.
2454 ++ * catches all aliases. This also includes __ro_after_init,
2455 ++ * so do not enforce until kernel_set_to_readonly is true.
2456 + */
2457 +- if (within(pfn, __pa_symbol(__start_rodata) >> PAGE_SHIFT,
2458 ++ if (kernel_set_to_readonly &&
2459 ++ within(pfn, __pa_symbol(__start_rodata) >> PAGE_SHIFT,
2460 + __pa_symbol(__end_rodata) >> PAGE_SHIFT))
2461 + pgprot_val(forbidden) |= _PAGE_RW;
2462 +
2463 +diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
2464 +index 34cda7e0551b..c03c85e4fb6a 100644
2465 +--- a/arch/x86/mm/pgtable.c
2466 ++++ b/arch/x86/mm/pgtable.c
2467 +@@ -1,6 +1,7 @@
2468 + // SPDX-License-Identifier: GPL-2.0
2469 + #include <linux/mm.h>
2470 + #include <linux/gfp.h>
2471 ++#include <linux/hugetlb.h>
2472 + #include <asm/pgalloc.h>
2473 + #include <asm/pgtable.h>
2474 + #include <asm/tlb.h>
2475 +@@ -636,6 +637,10 @@ int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
2476 + (mtrr != MTRR_TYPE_WRBACK))
2477 + return 0;
2478 +
2479 ++ /* Bail out if we are we on a populated non-leaf entry: */
2480 ++ if (pud_present(*pud) && !pud_huge(*pud))
2481 ++ return 0;
2482 ++
2483 + prot = pgprot_4k_2_large(prot);
2484 +
2485 + set_pte((pte_t *)pud, pfn_pte(
2486 +@@ -664,6 +669,10 @@ int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
2487 + return 0;
2488 + }
2489 +
2490 ++ /* Bail out if we are we on a populated non-leaf entry: */
2491 ++ if (pmd_present(*pmd) && !pmd_huge(*pmd))
2492 ++ return 0;
2493 ++
2494 + prot = pgprot_4k_2_large(prot);
2495 +
2496 + set_pte((pte_t *)pmd, pfn_pte(
2497 +diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c
2498 +index 754431031282..552c1f725b6c 100644
2499 +--- a/drivers/acpi/acpi_pad.c
2500 ++++ b/drivers/acpi/acpi_pad.c
2501 +@@ -110,6 +110,7 @@ static void round_robin_cpu(unsigned int tsk_index)
2502 + cpumask_andnot(tmp, cpu_online_mask, pad_busy_cpus);
2503 + if (cpumask_empty(tmp)) {
2504 + mutex_unlock(&round_robin_lock);
2505 ++ free_cpumask_var(tmp);
2506 + return;
2507 + }
2508 + for_each_cpu(cpu, tmp) {
2509 +@@ -127,6 +128,8 @@ static void round_robin_cpu(unsigned int tsk_index)
2510 + mutex_unlock(&round_robin_lock);
2511 +
2512 + set_cpus_allowed_ptr(current, cpumask_of(preferred_cpu));
2513 ++
2514 ++ free_cpumask_var(tmp);
2515 + }
2516 +
2517 + static void exit_round_robin(unsigned int tsk_index)
2518 +diff --git a/drivers/acpi/acpica/evevent.c b/drivers/acpi/acpica/evevent.c
2519 +index 4b2b0b44a16b..a65c186114eb 100644
2520 +--- a/drivers/acpi/acpica/evevent.c
2521 ++++ b/drivers/acpi/acpica/evevent.c
2522 +@@ -204,6 +204,7 @@ u32 acpi_ev_fixed_event_detect(void)
2523 + u32 fixed_status;
2524 + u32 fixed_enable;
2525 + u32 i;
2526 ++ acpi_status status;
2527 +
2528 + ACPI_FUNCTION_NAME(ev_fixed_event_detect);
2529 +
2530 +@@ -211,8 +212,12 @@ u32 acpi_ev_fixed_event_detect(void)
2531 + * Read the fixed feature status and enable registers, as all the cases
2532 + * depend on their values. Ignore errors here.
2533 + */
2534 +- (void)acpi_hw_register_read(ACPI_REGISTER_PM1_STATUS, &fixed_status);
2535 +- (void)acpi_hw_register_read(ACPI_REGISTER_PM1_ENABLE, &fixed_enable);
2536 ++ status = acpi_hw_register_read(ACPI_REGISTER_PM1_STATUS, &fixed_status);
2537 ++ status |=
2538 ++ acpi_hw_register_read(ACPI_REGISTER_PM1_ENABLE, &fixed_enable);
2539 ++ if (ACPI_FAILURE(status)) {
2540 ++ return (int_status);
2541 ++ }
2542 +
2543 + ACPI_DEBUG_PRINT((ACPI_DB_INTERRUPTS,
2544 + "Fixed Event Block: Enable %08X Status %08X\n",
2545 +diff --git a/drivers/acpi/acpica/nseval.c b/drivers/acpi/acpica/nseval.c
2546 +index c2d883b8c45e..a18e61081013 100644
2547 +--- a/drivers/acpi/acpica/nseval.c
2548 ++++ b/drivers/acpi/acpica/nseval.c
2549