1 |
chainsaw 08/05/29 14:44:31 |
2 |
|
3 |
Added: NVIDIA_kernel-173.14.05-2419292.diff |
4 |
Log: |
5 |
Version bump. Supported release, upstream release highlights are at http://www.nvnews.net/vbulletin/showthread.php?t=113919. |
6 |
(Portage version: 2.1.5.2) |
7 |
|
8 |
Revision Changes Path |
9 |
1.1 x11-drivers/nvidia-drivers/files/NVIDIA_kernel-173.14.05-2419292.diff |
10 |
|
11 |
file : http://sources.gentoo.org/viewcvs.py/gentoo-x86/x11-drivers/nvidia-drivers/files/NVIDIA_kernel-173.14.05-2419292.diff?rev=1.1&view=markup |
12 |
plain: http://sources.gentoo.org/viewcvs.py/gentoo-x86/x11-drivers/nvidia-drivers/files/NVIDIA_kernel-173.14.05-2419292.diff?rev=1.1&content-type=text/plain |
13 |
|
14 |
Index: NVIDIA_kernel-173.14.05-2419292.diff |
15 |
=================================================================== |
16 |
diff -ru usr/src/nv/Makefile.kbuild usr/src/nv.2419292/Makefile.kbuild |
17 |
--- usr/src/nv/Makefile.kbuild 2008-05-19 00:37:02.000000000 -0700 |
18 |
+++ usr/src/nv.2419292/Makefile.kbuild 2008-05-21 12:07:57.551201274 -0700 |
19 |
@@ -166,10 +166,6 @@ |
20 |
CFLAGS += -DNV_MAP_REGISTERS_EARLY |
21 |
endif |
22 |
|
23 |
-ifeq ($(shell echo $(NV_BUILD_NV_PAT_SUPPORT)),1) |
24 |
-CFLAGS += -DNV_BUILD_NV_PAT_SUPPORT |
25 |
-endif |
26 |
- |
27 |
ifneq ($(PATCHLEVEL), 4) |
28 |
COMPILE_TESTS = \ |
29 |
remap_page_range \ |
30 |
diff -ru usr/src/nv/Makefile.nvidia usr/src/nv.2419292/Makefile.nvidia |
31 |
--- usr/src/nv/Makefile.nvidia 2008-05-19 00:37:02.000000000 -0700 |
32 |
+++ usr/src/nv.2419292/Makefile.nvidia 2008-05-21 12:08:08.771840702 -0700 |
33 |
@@ -56,10 +56,6 @@ |
34 |
CFLAGS += -DNV_MAP_REGISTERS_EARLY |
35 |
endif |
36 |
|
37 |
-ifeq ($(shell echo $(NV_BUILD_NV_PAT_SUPPORT)),1) |
38 |
-CFLAGS += -DNV_BUILD_NV_PAT_SUPPORT |
39 |
-endif |
40 |
- |
41 |
INCLUDES += -I$(KERNEL_HEADERS) |
42 |
|
43 |
COMPILE_TESTS = \ |
44 |
diff -ru usr/src/nv/nv-linux.h usr/src/nv.2419292/nv-linux.h |
45 |
--- usr/src/nv/nv-linux.h 2008-05-19 00:37:01.000000000 -0700 |
46 |
+++ usr/src/nv.2419292/nv-linux.h 2008-05-21 12:07:19.741046595 -0700 |
47 |
@@ -145,16 +145,19 @@ |
48 |
#endif |
49 |
|
50 |
#if (defined(NVCPU_X86) || defined(NVCPU_X86_64)) && !defined(CONFIG_XEN) |
51 |
-#define NV_BUILD_NV_PAT_SUPPORT 1 |
52 |
+#define NV_ENABLE_PAT_SUPPORT |
53 |
#endif |
54 |
|
55 |
-#if defined(NV_BUILD_NV_PAT_SUPPORT) |
56 |
-#include "pat.h" |
57 |
+#define NV_PAT_MODE_DISABLED 0 |
58 |
+#define NV_PAT_MODE_KERNEL 1 |
59 |
+#define NV_PAT_MODE_BUILTIN 2 |
60 |
+ |
61 |
+extern int nv_pat_mode; |
62 |
+ |
63 |
#if defined(CONFIG_HOTPLUG_CPU) |
64 |
#include <linux/cpu.h> /* CPU hotplug support */ |
65 |
#include <linux/notifier.h> /* struct notifier_block, etc */ |
66 |
#endif |
67 |
-#endif |
68 |
|
69 |
#if (defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)) |
70 |
#include <linux/i2c.h> |
71 |
@@ -681,6 +684,13 @@ |
72 |
#define nv_down(lock) down(&lock) |
73 |
#define nv_up(lock) up(&lock) |
74 |
|
75 |
+#define NV_INIT_MUTEX(mutex) \ |
76 |
+ { \ |
77 |
+ struct semaphore __mutex = \ |
78 |
+ __SEMAPHORE_INITIALIZER(*(mutex), 1); \ |
79 |
+ *(mutex) = __mutex; \ |
80 |
+ } |
81 |
+ |
82 |
#if defined (KERNEL_2_4) |
83 |
# define NV_IS_SUSER() suser() |
84 |
# define NV_PCI_DEVICE_NAME(dev) ((dev)->name) |
85 |
@@ -1029,20 +1039,6 @@ |
86 |
return new_prot; |
87 |
} |
88 |
#endif |
89 |
- |
90 |
-#if defined(NV_BUILD_NV_PAT_SUPPORT) && !defined (pgprot_writecombined) |
91 |
-static inline pgprot_t pgprot_writecombined(pgprot_t old_prot) |
92 |
- { |
93 |
- pgprot_t new_prot = old_prot; |
94 |
- if (boot_cpu_data.x86 > 3) |
95 |
- { |
96 |
- pgprot_val(old_prot) &= ~(_PAGE_PCD | _PAGE_PWT); |
97 |
- new_prot = __pgprot(pgprot_val(old_prot) | _PAGE_WRTCOMB); |
98 |
- } |
99 |
- return new_prot; |
100 |
- } |
101 |
-#endif |
102 |
- |
103 |
#endif /* defined(NVCPU_X86) || defined(NVCPU_X86_64) */ |
104 |
|
105 |
#if defined(KERNEL_2_4) && defined(NVCPU_X86) && !defined(pfn_to_page) |
106 |
@@ -1142,8 +1138,6 @@ |
107 |
struct semaphore at_lock; |
108 |
} nv_linux_state_t; |
109 |
|
110 |
-extern int nv_pat_enabled; |
111 |
- |
112 |
#if defined(NV_LINUX_ACPI_EVENTS_SUPPORTED) |
113 |
/* |
114 |
* acpi data storage structure |
115 |
diff -ru usr/src/nv/nv-reg.h usr/src/nv.2419292/nv-reg.h |
116 |
--- usr/src/nv/nv-reg.h 2008-05-19 00:37:01.000000000 -0700 |
117 |
+++ usr/src/nv.2419292/nv-reg.h 2008-05-21 12:07:23.313250167 -0700 |
118 |
@@ -471,6 +471,37 @@ |
119 |
#define __NV_RM_EDGE_INTR_CHECK RMEdgeIntrCheck |
120 |
#define NV_REG_RM_EDGE_INTR_CHECK NV_REG_STRING(__NV_RM_EDGE_INTR_CHECK) |
121 |
|
122 |
+/* |
123 |
+ * Option: UsePageAttributeTable |
124 |
+ * |
125 |
+ * Description: |
126 |
+ * |
127 |
+ * Enable/disable use of the page attribute table (PAT) available in |
128 |
+ * modern x86/x86-64 processors to set the effective memory type of memory |
129 |
+ * mappings to write-combining (WC). If disabled, the driver will fall |
130 |
+ * back to using MTRRs, if possible. |
131 |
+ * |
132 |
+ * If enabled, an x86 processor with PAT support is present and the host |
133 |
+ * system's Linux kernel did not configure one of the PAT entries to |
134 |
+ * indicate the WC memory type, the driver will change the second entry in |
135 |
+ * the PAT from its default (write-through (WT)) to WC at module load |
136 |
+ * time. If the kernel did update one of the PAT entries, the driver will |
137 |
+ * not modify the PAT. |
138 |
+ * |
139 |
+ * In both cases, the driver will honor attempts to map memory with the WC |
140 |
+ * memory type by selecting the appropriate PAT entry using the correct |
141 |
+ * set of PTE flags. |
142 |
+ * |
143 |
+ * Possible values: |
144 |
+ * |
145 |
+ * ~0 = use the NVIDIA driver's default logic (default) |
146 |
+ * 1 = enable use of the PAT for WC mappings. |
147 |
+ * 0 = disable use of the PAT for WC mappings. |
148 |
+ */ |
149 |
+ |
150 |
+#define __NV_USE_PAGE_ATTRIBUTE_TABLE UsePageAttributeTable |
151 |
+#define NV_USE_PAGE_ATTRIBUTE_TABLE NV_REG_STRING(__NV_USE_PAGE_ATTRIBUTE_TABLE) |
152 |
+ |
153 |
|
154 |
|
155 |
#if defined(NV_DEFINE_REGISTRY_KEY_TABLE) |
156 |
@@ -495,6 +526,7 @@ |
157 |
NV_DEFINE_REG_ENTRY(__NV_UPDATE_MEMORY_TYPES, ~0); |
158 |
NV_DEFINE_REG_ENTRY(__NV_USE_VBIOS, 1); |
159 |
NV_DEFINE_REG_ENTRY(__NV_RM_EDGE_INTR_CHECK, 1); |
160 |
+NV_DEFINE_REG_ENTRY(__NV_USE_PAGE_ATTRIBUTE_TABLE, ~0); |
161 |
|
162 |
#if defined(NV_LINUX) |
163 |
NV_DEFINE_REG_STRING_ENTRY(__NV_REGISTRY_DWORDS, NULL); |
164 |
@@ -540,6 +572,7 @@ |
165 |
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_UPDATE_MEMORY_TYPES), |
166 |
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_USE_VBIOS), |
167 |
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_RM_EDGE_INTR_CHECK), |
168 |
+ NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_USE_PAGE_ATTRIBUTE_TABLE), |
169 |
{NULL, NULL, NULL} |
170 |
}; |
171 |
|
172 |
diff -ru usr/src/nv/nv.c usr/src/nv.2419292/nv.c |
173 |
--- usr/src/nv/nv.c 2008-05-19 00:37:01.000000000 -0700 |
174 |
+++ usr/src/nv.2419292/nv.c 2008-05-21 12:07:28.313535114 -0700 |
175 |
@@ -22,10 +22,9 @@ |
176 |
#endif |
177 |
|
178 |
#if defined(KERNEL_2_4) && (defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)) |
179 |
-// weak linking? |
180 |
extern int i2c_add_adapter (struct i2c_adapter *) __attribute__ ((weak)); |
181 |
extern int i2c_del_adapter (struct i2c_adapter *) __attribute__ ((weak)); |
182 |
-#endif // defined(KERNEL_2_4) && (defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)) |
183 |
+#endif |
184 |
|
185 |
/* |
186 |
* our global state; one per device |
187 |
@@ -41,14 +40,7 @@ |
188 |
static struct pm_dev *apm_nv_dev[NV_MAX_DEVICES] = { 0 }; |
189 |
#endif |
190 |
|
191 |
-int nv_pat_enabled = 0; |
192 |
- |
193 |
-#if !defined(NV_BUILD_NV_PAT_SUPPORT) |
194 |
-static int nv_disable_pat = 1; |
195 |
-#else |
196 |
-static int nv_disable_pat = 0; |
197 |
-NV_MODULE_PARAMETER(nv_disable_pat); |
198 |
-#endif |
199 |
+int nv_pat_mode = NV_PAT_MODE_DISABLED; |
200 |
|
201 |
#if defined(NVCPU_X86) || defined(NVCPU_X86_64) |
202 |
NvU64 __nv_supported_pte_mask = ~_PAGE_NX; |
203 |
@@ -611,7 +603,7 @@ |
204 |
nv_state_t *nv; |
205 |
nv_linux_state_t *nvl; |
206 |
|
207 |
- proc_nvidia = create_proc_entry("nvidia", d_flags, proc_root_driver); |
208 |
+ proc_nvidia = create_proc_entry("driver/nvidia", d_flags, NULL); |
209 |
if (!proc_nvidia) |
210 |
goto failed; |
211 |
|
212 |
@@ -863,18 +855,20 @@ |
213 |
static int __nv_enable_pat_support (void); |
214 |
static void __nv_disable_pat_support (void); |
215 |
|
216 |
-#if defined(NV_BUILD_NV_PAT_SUPPORT) |
217 |
+#if defined(NV_ENABLE_PAT_SUPPORT) |
218 |
/* |
219 |
- * Private PAT support for use by the NVIDIA driver. This is an |
220 |
- * interim solution until the kernel offers PAT support. |
221 |
+ * Private PAT support for use by the NVIDIA driver. This is used on |
222 |
+ * kernels that do not modify the PAT to include a write-combining |
223 |
+ * entry. |
224 |
*/ |
225 |
-static int __check_pat_support (void); |
226 |
+static int __determine_pat_mode (void); |
227 |
static void __nv_setup_pat_entries (void *); |
228 |
static void __nv_restore_pat_entries (void *); |
229 |
|
230 |
-#define NV_READ_PAT_ENTRIES(pat1, pat2) rdmsr(IA32_CR_PAT, (pat1), (pat2)) |
231 |
-#define NV_WRITE_PAT_ENTRIES(pat1, pat2) wrmsr(IA32_CR_PAT, (pat1), (pat2)) |
232 |
-#define NV_PAT_ENTRY(pat, index) (((pat) & (0xff<<((index)*8)))>>((index)*8)) |
233 |
+#define NV_READ_PAT_ENTRIES(pat1, pat2) rdmsr(0x277, (pat1), (pat2)) |
234 |
+#define NV_WRITE_PAT_ENTRIES(pat1, pat2) wrmsr(0x277, (pat1), (pat2)) |
235 |
+#define NV_PAT_ENTRY(pat, index) \ |
236 |
+ (((pat) & (0xff << ((index)*8))) >> ((index)*8)) |
237 |
|
238 |
static inline void __nv_disable_caches(unsigned long *cr4) |
239 |
{ |
240 |
@@ -895,39 +889,47 @@ |
241 |
if (cr4 & 0x80) write_cr4(cr4); |
242 |
} |
243 |
|
244 |
-static int __check_pat_support() |
245 |
+static int __determine_pat_mode() |
246 |
{ |
247 |
unsigned int pat1, pat2, i; |
248 |
+ U008 PAT_WC_index; |
249 |
|
250 |
- if (!test_bit(X86_FEATURE_PAT, (volatile unsigned long *)&boot_cpu_data.x86_capability)) |
251 |
+ if (!test_bit(X86_FEATURE_PAT, |
252 |
+ (volatile unsigned long *)&boot_cpu_data.x86_capability)) |
253 |
{ |
254 |
nv_printf(NV_DBG_ERRORS, |
255 |
"NVRM: CPU does not support the PAT, falling back to MTRRs.\n"); |
256 |
- return 0; |
257 |
+ return NV_PAT_MODE_DISABLED; |
258 |
} |
259 |
|
260 |
NV_READ_PAT_ENTRIES(pat1, pat2); |
261 |
+ PAT_WC_index = 0xf; |
262 |
|
263 |
for (i = 0; i < 4; i++) |
264 |
{ |
265 |
- // we plan to mark PAT entry 1 as WC. if it's already marked such, |
266 |
- // that's fine, since it would be no different than us setting it. |
267 |
- if ((i != 1) && NV_PAT_ENTRY(pat1, i) == 1) |
268 |
- { |
269 |
- nv_printf(NV_DBG_ERRORS, "NVRM: PAT index %d already configured for Write-Combining!\n", i); |
270 |
- nv_printf(NV_DBG_ERRORS, "NVRM: Aborting, due to PAT already being configured\n"); |
271 |
- return 0; |
272 |
- } |
273 |
- |
274 |
- if (NV_PAT_ENTRY(pat2, i) == 1) |
275 |
- { |
276 |
- nv_printf(NV_DBG_ERRORS, "NVRM: PAT index %d already configured for Write-Combining!\n", i + 4); |
277 |
- nv_printf(NV_DBG_ERRORS, "NVRM: Aborting, due to PAT already being configured\n"); |
278 |
- return 0; |
279 |
- } |
280 |
+ if (NV_PAT_ENTRY(pat1, i) == 0x01) |
281 |
+ { |
282 |
+ PAT_WC_index = i; |
283 |
+ break; |
284 |
+ } |
285 |
+ |
286 |
+ if (NV_PAT_ENTRY(pat2, i) == 0x01) |
287 |
+ { |
288 |
+ PAT_WC_index = (i + 4); |
289 |
+ break; |
290 |
+ } |
291 |
} |
292 |
|
293 |
- return 1; |
294 |
+ if (PAT_WC_index == 1) |
295 |
+ return NV_PAT_MODE_KERNEL; |
296 |
+ else if (PAT_WC_index != 0xf) |
297 |
+ { |
298 |
+ nv_printf(NV_DBG_ERRORS, |
299 |
+ "NVRM: PAT configuration unsupported, falling back to MTRRs.\n"); |
300 |
+ return NV_PAT_MODE_DISABLED; |
301 |
+ } |
302 |
+ else |
303 |
+ return NV_PAT_MODE_BUILTIN; |
304 |
} |
305 |
|
306 |
static unsigned long orig_pat1, orig_pat2; |
307 |
@@ -978,19 +980,30 @@ |
308 |
__nv_enable_caches(cr4); |
309 |
NV_RESTORE_FLAGS(eflags); |
310 |
} |
311 |
- |
312 |
-#endif /* defined(NV_BUILD_NV_PAT_SUPPORT) */ |
313 |
+#endif |
314 |
|
315 |
static int __nv_enable_pat_support() |
316 |
{ |
317 |
-#if defined(NV_BUILD_NV_PAT_SUPPORT) |
318 |
+#if defined(NV_ENABLE_PAT_SUPPORT) |
319 |
unsigned long pat1, pat2; |
320 |
|
321 |
- if (nv_pat_enabled) |
322 |
+ if (nv_pat_mode != NV_PAT_MODE_DISABLED) |
323 |
return 1; |
324 |
|
325 |
- if (!__check_pat_support()) |
326 |
- return 0; |
327 |
+ nv_pat_mode = __determine_pat_mode(); |
328 |
+ |
329 |
+ switch (nv_pat_mode) |
330 |
+ { |
331 |
+ case NV_PAT_MODE_DISABLED: |
332 |
+ /* avoid the PAT if unavailable/unusable */ |
333 |
+ return 0; |
334 |
+ case NV_PAT_MODE_KERNEL: |
335 |
+ /* inherit the kernel's PAT layout */ |
336 |
+ return 1; |
337 |
+ case NV_PAT_MODE_BUILTIN: |
338 |
+ /* use builtin code to modify the PAT layout */ |
339 |
+ break; |
340 |
+ } |
341 |
|
342 |
NV_READ_PAT_ENTRIES(orig_pat1, orig_pat2); |
343 |
nv_printf(NV_DBG_SETUP, "saved orig pats as 0x%lx 0x%lx\n", orig_pat1, orig_pat2); |
344 |
@@ -1001,31 +1014,28 @@ |
345 |
return 0; |
346 |
} |
347 |
|
348 |
- nv_pat_enabled = 1; |
349 |
- |
350 |
NV_READ_PAT_ENTRIES(pat1, pat2); |
351 |
nv_printf(NV_DBG_SETUP, "changed pats to 0x%lx 0x%lx\n", pat1, pat2); |
352 |
-#endif /* defined(NV_BUILD_NV_PAT_SUPPORT) */ |
353 |
- |
354 |
+#endif |
355 |
return 1; |
356 |
} |
357 |
|
358 |
static void __nv_disable_pat_support() |
359 |
{ |
360 |
-#if defined(NV_BUILD_NV_PAT_SUPPORT) |
361 |
+#if defined(NV_ENABLE_PAT_SUPPORT) |
362 |
unsigned long pat1, pat2; |
363 |
|
364 |
- if (!nv_pat_enabled) |
365 |
+ if (nv_pat_mode != NV_PAT_MODE_BUILTIN) |
366 |
return; |
367 |
|
368 |
if (nv_execute_on_all_cpus(__nv_restore_pat_entries, NULL) != 0) |
369 |
return; |
370 |
|
371 |
- nv_pat_enabled = 0; |
372 |
+ nv_pat_mode = NV_PAT_MODE_DISABLED; |
373 |
|
374 |
NV_READ_PAT_ENTRIES(pat1, pat2); |
375 |
nv_printf(NV_DBG_SETUP, "restored orig pats as 0x%lx 0x%lx\n", pat1, pat2); |
376 |
-#endif /* defined(NV_BUILD_NV_PAT_SUPPORT) */ |
377 |
+#endif |
378 |
} |
379 |
|
380 |
#if defined(NV_CHANGE_PAGE_ATTR_BUG_PRESENT) |
381 |
@@ -1273,7 +1283,7 @@ |
382 |
#endif |
383 |
} |
384 |
|
385 |
-#if defined(NV_BUILD_NV_PAT_SUPPORT) && defined(CONFIG_HOTPLUG_CPU) |
386 |
+#if defined(NV_ENABLE_PAT_SUPPORT) && defined(CONFIG_HOTPLUG_CPU) |
387 |
static int |
388 |
nv_kern_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) |
389 |
{ |
390 |
@@ -1305,8 +1315,7 @@ |
391 |
.notifier_call = nv_kern_cpu_callback, |
392 |
.priority = 0 |
393 |
}; |
394 |
- |
395 |
-#endif /* defined(NV_BUILD_NV_PAT_SUPPORT) && defined(CONFIG_HOTPLUG_CPU) */ |
396 |
+#endif |
397 |
|
398 |
|
399 |
/*** |
400 |
@@ -1315,7 +1324,7 @@ |
401 |
|
402 |
static int __init nvidia_init_module(void) |
403 |
{ |
404 |
- int rc; |
405 |
+ int rc, disable_pat = 0; |
406 |
U032 i, count, data; |
407 |
nv_state_t *nv = NV_STATE_PTR(&nv_ctl_device); |
408 |
nv_stack_t *sp = NULL; |
409 |
@@ -1443,18 +1452,6 @@ |
410 |
nv_printf(NV_DBG_ERRORS, "NVRM: pte cache allocation failed\n"); |
411 |
goto failed; |
412 |
} |
413 |
- |
414 |
-#if defined(NV_BUILD_NV_PAT_SUPPORT) && defined(CONFIG_HOTPLUG_CPU) |
415 |
- if (!nv_disable_pat) |
416 |
- { |
417 |
- if (register_hotcpu_notifier(&nv_hotcpu_nfb) != 0) |
418 |
- { |
419 |
- rc = -EIO; |
420 |
- nv_printf(NV_DBG_ERRORS, "NVRM: CPU hotplug notifier registration failed!\n"); |
421 |
- goto failed; |
422 |
- } |
423 |
- } |
424 |
-#endif |
425 |
|
426 |
#if defined(NV_SG_MAP_BUFFERS) |
427 |
rm_read_registry_dword(sp, nv, "NVreg", "RemapLimit", &nv_remap_limit); |
428 |
@@ -1532,8 +1529,30 @@ |
429 |
|
430 |
nvos_proc_add_warning_file("README", __README_warning); |
431 |
|
432 |
- if (!nv_disable_pat) |
433 |
+ rc = rm_read_registry_dword(sp, nv, |
434 |
+ "NVreg", NV_USE_PAGE_ATTRIBUTE_TABLE, &data); |
435 |
+ if ((rc == 0) && ((int)data != ~0)) |
436 |
+ { |
437 |
+ disable_pat = (data == 0); |
438 |
+ } |
439 |
+ |
440 |
+ if (!disable_pat) |
441 |
+ { |
442 |
__nv_enable_pat_support(); |
443 |
+#if defined(NV_ENABLE_PAT_SUPPORT) && defined(CONFIG_HOTPLUG_CPU) |
444 |
+ if (nv_pat_mode == NV_PAT_MODE_BUILTIN) |
445 |
+ { |
446 |
+ if (register_hotcpu_notifier(&nv_hotcpu_nfb) != 0) |
447 |
+ { |
448 |
+ __nv_disable_pat_support(); |
449 |
+ rc = -EIO; |
450 |
+ nv_printf(NV_DBG_ERRORS, |
451 |
+ "NVRM: CPU hotplug notifier registration failed!\n"); |
452 |
+ goto failed; |
453 |
+ } |
454 |
+ } |
455 |
+#endif |
456 |
+ } |
457 |
else |
458 |
{ |
459 |
nv_printf(NV_DBG_ERRORS, |
460 |
@@ -1686,10 +1705,10 @@ |
461 |
rm_unregister_compatible_ioctls(sp); |
462 |
#endif |
463 |
|
464 |
- if (nv_pat_enabled) |
465 |
+ if (nv_pat_mode == NV_PAT_MODE_BUILTIN) |
466 |
{ |
467 |
__nv_disable_pat_support(); |
468 |
-#if defined(NV_BUILD_NV_PAT_SUPPORT) && defined(CONFIG_HOTPLUG_CPU) |
469 |
+#if defined(NV_ENABLE_PAT_SUPPORT) && defined(CONFIG_HOTPLUG_CPU) |
470 |
unregister_hotcpu_notifier(&nv_hotcpu_nfb); |
471 |
#endif |
472 |
} |
473 |
@@ -1825,6 +1844,8 @@ |
474 |
} |
475 |
} |
476 |
|
477 |
+#if !defined(NV_VM_INSERT_PAGE_PRESENT) |
478 |
+static |
479 |
struct page *nv_kern_vma_nopage( |
480 |
struct vm_area_struct *vma, |
481 |
unsigned long address, |
482 |
@@ -1835,22 +1856,21 @@ |
483 |
#endif |
484 |
) |
485 |
{ |
486 |
-#if !defined(NV_VM_INSERT_PAGE_PRESENT) |
487 |
struct page *page; |
488 |
|
489 |
page = pfn_to_page(vma->vm_pgoff); |
490 |
get_page(page); |
491 |
|
492 |
return page; |
493 |
-#else |
494 |
- return NOPAGE_SIGBUS; |
495 |
-#endif |
496 |
} |
497 |
+#endif |
498 |
|
499 |
struct vm_operations_struct nv_vm_ops = { |
500 |
.open = nv_kern_vma_open, |
501 |
.close = nv_kern_vma_release, /* "close" */ |
502 |
+#if !defined(NV_VM_INSERT_PAGE_PRESENT) |
503 |
.nopage = nv_kern_vma_nopage, |
504 |
+#endif |
505 |
}; |
506 |
|
507 |
static nv_file_private_t * |
508 |
@@ -1864,7 +1884,7 @@ |
509 |
|
510 |
memset(nvfp, 0, sizeof(nv_file_private_t)); |
511 |
|
512 |
- sema_init(&nvfp->sp_lock, 1); |
513 |
+ NV_INIT_MUTEX(&nvfp->sp_lock); |
514 |
|
515 |
// initialize this file's event queue |
516 |
init_waitqueue_head(&nvfp->waitqueue); |
517 |
@@ -2214,11 +2234,12 @@ |
518 |
break; |
519 |
#if defined(NVCPU_X86) || defined(NVCPU_X86_64) |
520 |
case NV_MEMORY_WRITECOMBINED: |
521 |
-#if defined(NV_BUILD_NV_PAT_SUPPORT) |
522 |
- if (nv_pat_enabled && |
523 |
- (memory_type != NV_MEMORY_TYPE_REGISTERS)) |
524 |
+#if defined(NV_ENABLE_PAT_SUPPORT) |
525 |
+ if ((nv_pat_mode != NV_PAT_MODE_DISABLED) && |
526 |
+ (memory_type != NV_MEMORY_TYPE_REGISTERS)) |
527 |
{ |
528 |
- *prot = pgprot_writecombined(*prot); |
529 |
+ pgprot_val(*prot) &= ~(_PAGE_PSE | _PAGE_PCD | _PAGE_PWT); |
530 |
+ *prot = __pgprot(pgprot_val(*prot) | _PAGE_PWT); |
531 |
break; |
532 |
} |
533 |
#endif |
534 |
@@ -2242,7 +2263,6 @@ |
535 |
return 1; |
536 |
#endif |
537 |
case NV_MEMORY_CACHED: |
538 |
- //case NV_MEMORY_WRITEBACK: |
539 |
#if !defined(NVCPU_X86) && !defined(NVCPU_X86_64) |
540 |
if (memory_type != NV_MEMORY_TYPE_REGISTERS) |
541 |
break; |
542 |
@@ -2264,8 +2284,6 @@ |
543 |
if (memory_type == NV_MEMORY_TYPE_SYSTEM) |
544 |
break; |
545 |
#endif |
546 |
- //case NV_MEMORY_WRITETHRU: |
547 |
- //case NV_MEMORY_WRITEPROTECT: |
548 |
default: |
549 |
if(nv_ext_encode_caching(prot, cache_type, memory_type) == 0) |
550 |
return 0; |
551 |
@@ -3502,6 +3520,10 @@ |
552 |
BOOL kern |
553 |
) |
554 |
{ |
555 |
+#if defined(NV_SET_PAGES_UC_PRESENT) && defined(NVCPU_X86) |
556 |
+ nv_printf(NV_DBG_ERRORS, |
557 |
+ "NVRM: can't translate address in nv_get_phys_address()!\n"); |
558 |
+#else |
559 |
struct mm_struct *mm; |
560 |
pgd_t *pgd = NULL; |
561 |
pmd_t *pmd = NULL; |
562 |
@@ -3514,15 +3536,7 @@ |
563 |
down_read(&mm->mmap_sem); |
564 |
} |
565 |
else |
566 |
- { |
567 |
-#if defined(NV_SET_PAGES_UC_PRESENT) && defined(NVCPU_X86) |
568 |
- nv_printf(NV_DBG_ERRORS, |
569 |
- "NVRM: can't translate KVA in nv_get_phys_address()!\n"); |
570 |
- return 0; |
571 |
-#else |
572 |
mm = NULL; |
573 |
-#endif |
574 |
- } |
575 |
|
576 |
pgd = NV_PGD_OFFSET(address, kern, mm); |
577 |
if (!NV_PGD_PRESENT(pgd)) |
578 |
@@ -3550,6 +3564,7 @@ |
579 |
failed: |
580 |
if (!kern) |
581 |
up_read(&mm->mmap_sem); |
582 |
+#endif |
583 |
return 0; |
584 |
} |
585 |
|
586 |
@@ -3790,8 +3805,9 @@ |
587 |
|
588 |
nv_init_lock(nvl->rm_lock); |
589 |
|
590 |
- sema_init(&nvl->ldata_lock, 1); |
591 |
- sema_init(&nvl->at_lock, 1); |
592 |
+ NV_INIT_MUTEX(&nvl->ldata_lock); |
593 |
+ NV_INIT_MUTEX(&nvl->at_lock); |
594 |
+ |
595 |
NV_ATOMIC_SET(nvl->usage_count, 0); |
596 |
|
597 |
nvl->rm_lock_cpu = -1; |
598 |
diff -ru usr/src/nv/os-agp.c usr/src/nv.2419292/os-agp.c |
599 |
--- usr/src/nv/os-agp.c 2008-05-19 00:37:01.000000000 -0700 |
600 |
+++ usr/src/nv.2419292/os-agp.c 2008-05-21 12:07:30.437656163 -0700 |
601 |
@@ -115,7 +115,7 @@ |
602 |
goto release; |
603 |
} |
604 |
|
605 |
- if (!nv_pat_enabled) |
606 |
+ if (nv_pat_mode == NV_PAT_MODE_DISABLED) |
607 |
{ |
608 |
#ifdef CONFIG_MTRR |
609 |
/* |
610 |
@@ -175,7 +175,7 @@ |
611 |
|
612 |
failed: |
613 |
#ifdef CONFIG_MTRR |
614 |
- if (!nv_pat_enabled) |
615 |
+ if (nv_pat_mode == NV_PAT_MODE_DISABLED) |
616 |
mtrr_del(-1, agp_info.aper_base, agp_info.aper_size << 20); |
617 |
#endif |
618 |
release: |
619 |
@@ -205,7 +205,7 @@ |
620 |
nvl = NV_GET_NVL_FROM_NV_STATE(nv); |
621 |
|
622 |
#ifdef CONFIG_MTRR |
623 |
- if (!nv_pat_enabled) |
624 |
+ if (nv_pat_mode == NV_PAT_MODE_DISABLED) |
625 |
mtrr_del(-1, nv->agp.address, nv->agp.size); |
626 |
#endif |
627 |
|
628 |
diff -ru usr/src/nv/os-interface.c usr/src/nv.2419292/os-interface.c |
629 |
--- usr/src/nv/os-interface.c 2008-05-19 00:37:01.000000000 -0700 |
630 |
+++ usr/src/nv.2419292/os-interface.c 2008-05-21 12:07:33.365823028 -0700 |
631 |
@@ -1355,7 +1355,7 @@ |
632 |
|
633 |
BOOL NV_API_CALL os_pat_supported(void) |
634 |
{ |
635 |
- return nv_pat_enabled; |
636 |
+ return (nv_pat_mode != NV_PAT_MODE_DISABLED); |
637 |
} |
638 |
|
639 |
void NV_API_CALL os_dump_stack() |
640 |
|
641 |
|
642 |
|
643 |
-- |
644 |
gentoo-commits@l.g.o mailing list |