Gentoo Archives: gentoo-commits

From: "Ryan Hill (dirtyepic)" <dirtyepic@g.o>
To: gentoo-commits@l.g.o
Subject: [gentoo-commits] gentoo commit in src/patchsets/gcc/4.3.6/gentoo: 00_all_gcc-4.1-alpha-mieee-default.patch 00_all_gcc-trampolinewarn.patch 01_all_gcc-4.1-alpha-asm-mcpu.patch 03_all_gcc43-java-nomulti.patch 05_all_pr40010-manpages.patch 08_all_gcc-4.1-cross-compile.patch 10_all_gcc-default-format-security.patch 10_all_gcc-default-fortify-source.patch 11_all_gcc-netbsd-symbolic.patch 14_all_gcc-sparc64-bsd.patch 15_all_gcc-libgomp-no-werror.patch 18_all_904-flatten-switch-stmt-00.patch 20_all_mudflap-setuid-env.patch 20_all_s390-gcc-4.3.2-z10-complete.patch 40_all_gcc-4.4-libiberty.h-asprintf.patch 45_all_arm-pic-ssp-segv-pr35965.patch 46_all_armel-hilo-union-class.patch 47_all_arm-unbreak-armv4t.patch 48_all_gfortran-armel-updates.patch 49_all_arm_v7-config.patch 51_all_gcc-3.4-libiberty-pic.patch 53_all_gcc4-superh-default-multilib.patch 61_all_gcc4-ia64-noteGNUstack.patch 61_all_gcc43-pr24170.patch 62_all_gcc4-noteGNUstack.patch 66_all_gcc43-pr25343.patch 68_all_gc c43-pr37661.patch 70_all_gcc43-libjava-headers.patch 73_all_sh-libgcc-stacks.patch 74_all_sh-pr24836.patch 75_all_mips-r10k-cache-barriers.patch 76_all_mips-r10k-scheduling-support.patch 77_all_mips-r10k-support-for-atomic-memory-fixes.patch 78_all_mips-constant-addr.patch 79_all_arm_PR37436.patch 80_all_sparc-biarch.patch 90_all_gcc-freebsd.patch 91_all_gcc-freebsd.patch README.history
Date: Fri, 01 Jul 2011 07:18:13
Message-Id: 20110701071743.2275D20054@flycatcher.gentoo.org
1 dirtyepic 11/07/01 07:17:43
2
3 Added: 00_all_gcc-4.1-alpha-mieee-default.patch
4 00_all_gcc-trampolinewarn.patch
5 01_all_gcc-4.1-alpha-asm-mcpu.patch
6 03_all_gcc43-java-nomulti.patch
7 05_all_pr40010-manpages.patch
8 08_all_gcc-4.1-cross-compile.patch
9 10_all_gcc-default-format-security.patch
10 10_all_gcc-default-fortify-source.patch
11 11_all_gcc-netbsd-symbolic.patch
12 14_all_gcc-sparc64-bsd.patch
13 15_all_gcc-libgomp-no-werror.patch
14 18_all_904-flatten-switch-stmt-00.patch
15 20_all_mudflap-setuid-env.patch
16 20_all_s390-gcc-4.3.2-z10-complete.patch
17 40_all_gcc-4.4-libiberty.h-asprintf.patch
18 45_all_arm-pic-ssp-segv-pr35965.patch
19 46_all_armel-hilo-union-class.patch
20 47_all_arm-unbreak-armv4t.patch
21 48_all_gfortran-armel-updates.patch
22 49_all_arm_v7-config.patch
23 51_all_gcc-3.4-libiberty-pic.patch
24 53_all_gcc4-superh-default-multilib.patch
25 61_all_gcc4-ia64-noteGNUstack.patch
26 61_all_gcc43-pr24170.patch
27 62_all_gcc4-noteGNUstack.patch
28 66_all_gcc43-pr25343.patch
29 68_all_gcc43-pr37661.patch
30 70_all_gcc43-libjava-headers.patch
31 73_all_sh-libgcc-stacks.patch
32 74_all_sh-pr24836.patch
33 75_all_mips-r10k-cache-barriers.patch
34 76_all_mips-r10k-scheduling-support.patch
35 77_all_mips-r10k-support-for-atomic-memory-fixes.patch
36 78_all_mips-constant-addr.patch
37 79_all_arm_PR37436.patch 80_all_sparc-biarch.patch
38 90_all_gcc-freebsd.patch 91_all_gcc-freebsd.patch
39 README.history
40 Log:
41 Initial 4.3.6 patchset based on latest 4.3.5 patchset.
42
43 Revision Changes Path
44 1.1 src/patchsets/gcc/4.3.6/gentoo/00_all_gcc-4.1-alpha-mieee-default.patch
45
46 file : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/00_all_gcc-4.1-alpha-mieee-default.patch?rev=1.1&view=markup
47 plain: http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/00_all_gcc-4.1-alpha-mieee-default.patch?rev=1.1&content-type=text/plain
48
49 Index: 00_all_gcc-4.1-alpha-mieee-default.patch
50 ===================================================================
51 Set the default behavior on alpha to use -mieee since the large majority of
52 time we want this (bad/weird things can happen with packages built without
53 -mieee).
54
55 To satisfy those people who may not want -mieee forced on them all the time,
56 we also provide -mno-ieee.
57
58 Patch by Mike Frysinger <vapier@g.o>
59
60 --- gcc-4.3.0/gcc/config/alpha/alpha.h
61 +++ gcc-4.3.0/gcc/config/alpha/alpha.h
62 @@ -95,6 +95,8 @@
63 while (0)
64 #endif
65
66 +#define CPP_SPEC "%{!no-ieee:-mieee}"
67 +
68 #define WORD_SWITCH_TAKES_ARG(STR) \
69 (!strcmp (STR, "rpath") || DEFAULT_WORD_SWITCH_TAKES_ARG(STR))
70
71 --- gcc-4.3.0/gcc/config/alpha/alpha.opt
72 +++ gcc-4.3.0/gcc/config/alpha/alpha.opt
73 @@ -39,7 +39,7 @@
74 Request IEEE-conformant math library routines (OSF/1)
75
76 mieee
77 -Target Report RejectNegative Mask(IEEE)
78 +Target Report Mask(IEEE)
79 Emit IEEE-conformant code, without inexact exceptions
80
81 mieee-with-inexact
82
83
84
85 1.1 src/patchsets/gcc/4.3.6/gentoo/00_all_gcc-trampolinewarn.patch
86
87 file : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/00_all_gcc-trampolinewarn.patch?rev=1.1&view=markup
88 plain: http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/00_all_gcc-trampolinewarn.patch?rev=1.1&content-type=text/plain
89
90 Index: 00_all_gcc-trampolinewarn.patch
91 ===================================================================
92 This trivial patch causes gcc to emit a warning whenever
93 it generates a trampoline. These are otherwise hard to
94 locate. It is rigged to default ON - to have it default
95 to OFF remove the text 'Init(1)' from the common.opt
96 patch, leaving just 'Common Var(warn_trampolines)'.
97 Kevin F. Quinn <kevquinn@g.o> 17 Jan 2006
98
99 --- gcc/gcc/common.opt
100 +++ gcc/gcc/common.opt
101 @@ -141,6 +141,10 @@
102 Common Var(warn_system_headers)
103 Do not suppress warnings from system headers
104
105 +Wtrampolines
106 +Common Var(warn_trampolines) Init(1)
107 +Warn whenever a trampoline is generated
108 +
109 Wuninitialized
110 Common Var(warn_uninitialized)
111 Warn about uninitialized automatic variables
112 --- gcc/gcc/builtins.c
113 +++ gcc/gcc/builtins.c
114 @@ -5224,6 +5224,9 @@
115 #endif
116 trampolines_created = 1;
117 INITIALIZE_TRAMPOLINE (r_tramp, r_func, r_chain);
118 +
119 + if (warn_trampolines)
120 + warning (OPT_Wtrampolines, "generating trampoline in object (requires executable stack)");
121
122 return const0_rtx;
123 }
124
125
126
127 1.1 src/patchsets/gcc/4.3.6/gentoo/01_all_gcc-4.1-alpha-asm-mcpu.patch
128
129 file : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/01_all_gcc-4.1-alpha-asm-mcpu.patch?rev=1.1&view=markup
130 plain: http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/01_all_gcc-4.1-alpha-asm-mcpu.patch?rev=1.1&content-type=text/plain
131
132 Index: 01_all_gcc-4.1-alpha-asm-mcpu.patch
133 ===================================================================
134 http://bugs.gentoo.org/170146
135 http://gcc.gnu.org/ml/gcc-patches/2009-11/msg00403.html
136
137 alpha: turn -mcpu=<cpu> into -m<cpu> for assembler all the time
138
139 --- gcc-x/gcc/config/alpha/elf.h
140 +++ gcc-x/gcc/config/alpha/elf.h
141 @@ -46,7 +46,7 @@
142 #define CC1_SPEC "%{G*}"
143
144 #undef ASM_SPEC
145 -#define ASM_SPEC "%{G*} %{relax:-relax} %{!gstabs*:-no-mdebug}%{gstabs*:-mdebug}"
146 +#define ASM_SPEC "%{G*} %{relax:-relax} %{!gstabs*:-no-mdebug}%{gstabs*:-mdebug} %{mcpu=*:-m%*}"
147
148 #undef IDENT_ASM_OP
149 #define IDENT_ASM_OP "\t.ident\t"
150
151
152
153 1.1 src/patchsets/gcc/4.3.6/gentoo/03_all_gcc43-java-nomulti.patch
154
155 file : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/03_all_gcc43-java-nomulti.patch?rev=1.1&view=markup
156 plain: http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/03_all_gcc43-java-nomulti.patch?rev=1.1&content-type=text/plain
157
158 Index: 03_all_gcc43-java-nomulti.patch
159 ===================================================================
160 --- libjava/configure.ac.jj 2007-12-07 17:55:50.000000000 +0100
161 +++ libjava/configure.ac 2007-12-07 18:36:56.000000000 +0100
162 @@ -82,6 +82,13 @@ AC_ARG_ENABLE(java-maintainer-mode,
163 [allow rebuilding of .class and .h files]))
164 AM_CONDITIONAL(JAVA_MAINTAINER_MODE, test "$enable_java_maintainer_mode" = yes)
165
166 +AC_ARG_ENABLE(libjava-multilib,
167 + AS_HELP_STRING([--enable-libjava-multilib], [build libjava as multilib]))
168 +if test "$enable_libjava_multilib" = no; then
169 + multilib=no
170 + ac_configure_args="$ac_configure_args --disable-multilib"
171 +fi
172 +
173 # It may not be safe to run linking tests in AC_PROG_CC/AC_PROG_CXX.
174 GCC_NO_EXECUTABLES
175
176 --- libjava/configure.jj 2007-12-07 17:55:50.000000000 +0100
177 +++ libjava/configure 2007-12-07 18:39:58.000000000 +0100
178 @@ -1018,6 +1018,8 @@ Optional Features:
179 --enable-gconf-peer compile GConf native peers for util.preferences
180 --enable-java-maintainer-mode
181 allow rebuilding of .class and .h files
182 + --enable-libjava-multilib
183 + build libjava as multilib
184 --disable-dependency-tracking speeds up one-time build
185 --enable-dependency-tracking do not reject slow dependency extractors
186 --enable-maintainer-mode enable make rules and dependencies not useful
187 @@ -1848,6 +1850,16 @@ else
188 fi
189
190
191 +# Check whether --enable-libjava-multilib was given.
192 +if test "${enable_libjava_multilib+set}" = set; then
193 + enableval=$enable_libjava_multilib;
194 +fi
195 +
196 +if test "$enable_libjava_multilib" = no; then
197 + multilib=no
198 + ac_configure_args="$ac_configure_args --disable-multilib"
199 +fi
200 +
201 # It may not be safe to run linking tests in AC_PROG_CC/AC_PROG_CXX.
202
203
204
205
206
207 1.1 src/patchsets/gcc/4.3.6/gentoo/05_all_pr40010-manpages.patch
208
209 file : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/05_all_pr40010-manpages.patch?rev=1.1&view=markup
210 plain: http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/05_all_pr40010-manpages.patch?rev=1.1&content-type=text/plain
211
212 Index: 05_all_pr40010-manpages.patch
213 ===================================================================
214 Fix manpage generation w/ parallel builds.
215
216 https://bugs.gentoo.org/256608
217 http://gcc.gnu.org/PR40010
218
219 --- a/gcc/Makefile.in
220 +++ b/gcc/Makefile.in
221 @@ -3808,7 +3808,7 @@ cpp.pod: cpp.texi cppenv.texi cppopts.texi
222 # These next rules exist because the output name is not the same as
223 # the input name, so our implicit %.pod rule will not work.
224
225 -gcc.pod: invoke.texi cppenv.texi cppopts.texi
226 +gcc.pod: invoke.texi cppenv.texi cppopts.texi gcc-vers.texi
227 $(STAMP) $@
228 -$(TEXI2POD) $< > $@
229 gfdl.pod: fdl.texi
230
231
232
233 1.1 src/patchsets/gcc/4.3.6/gentoo/08_all_gcc-4.1-cross-compile.patch
234
235 file : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/08_all_gcc-4.1-cross-compile.patch?rev=1.1&view=markup
236 plain: http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/08_all_gcc-4.1-cross-compile.patch?rev=1.1&content-type=text/plain
237
238 Index: 08_all_gcc-4.1-cross-compile.patch
239 ===================================================================
240 Some notes on the 'bootstrap with or without libc headers' debate:
241 http://linuxfromscratch.org/pipermail/lfs-dev/2005-July/052409.html
242 http://gcc.gnu.org/ml/gcc/2005-07/msg01195.html
243
244 --- gcc/unwind-dw2.c
245 +++ gcc/unwind-dw2.c
246 @@ -253,9 +253,11 @@
247 }
248 #endif
249
250 +#ifndef inhibit_libc
251 #ifdef MD_UNWIND_SUPPORT
252 #include MD_UNWIND_SUPPORT
253 #endif
254 +#endif
255
256 /* Extract any interesting information from the CIE for the translation
257 unit F belongs to. Return a pointer to the byte after the augmentation,
258 --- gcc/configure
259 +++ gcc/configure
260 @@ -12857,7 +12857,7 @@ then
261 | powerpc*-*-*,powerpc64*-*-*)
262 CROSS="$CROSS -DNATIVE_CROSS" ;;
263 esac
264 -elif test "x$TARGET_SYSTEM_ROOT" != x; then
265 +elif test "x$TARGET_SYSTEM_ROOT" != x -o $build != $host; then
266 SYSTEM_HEADER_DIR=$build_system_header_dir
267 fi
268
269 --- gcc/configure.ac
270 +++ gcc/configure.ac
271 @@ -1717,7 +1717,7 @@ then
272 | powerpc*-*-*,powerpc64*-*-*)
273 CROSS="$CROSS -DNATIVE_CROSS" ;;
274 esac
275 -elif test "x$TARGET_SYSTEM_ROOT" != x; then
276 +elif test "x$TARGET_SYSTEM_ROOT" != x -o $build != $host; then
277 SYSTEM_HEADER_DIR=$build_system_header_dir
278 fi
279
280
281
282
283 1.1 src/patchsets/gcc/4.3.6/gentoo/10_all_gcc-default-format-security.patch
284
285 file : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/10_all_gcc-default-format-security.patch?rev=1.1&view=markup
286 plain: http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/10_all_gcc-default-format-security.patch?rev=1.1&content-type=text/plain
287
288 Index: 10_all_gcc-default-format-security.patch
289 ===================================================================
290 ripped from Debian
291
292 # DP: Turn on -Wformat -Wformat-security by default for C, C++, ObjC, ObjC++.
293
294 --- gcc/c-common.c
295 +++ gcc/c-common.c
296 @@ -277,7 +277,7 @@
297 /* Warn about format/argument anomalies in calls to formatted I/O functions
298 (*printf, *scanf, strftime, strfmon, etc.). */
299
300 -int warn_format;
301 +int warn_format = 1;
302
303 /* Warn about using __null (as NULL in C++) as sentinel. For code compiled
304 with GCC this doesn't matter as __null is guaranteed to have the right
305 --- gcc/c.opt
306 +++ gcc/c.opt
307 @@ -228,7 +228,7 @@
308 Warn about format strings that contain NUL bytes
309
310 Wformat-security
311 -C ObjC C++ ObjC++ Var(warn_format_security) Warning
312 +C ObjC C++ ObjC++ Var(warn_format_security) Init(1) Warning
313 Warn about possible security problems with format functions
314
315 Wformat-y2k
316 --- gcc/doc/invoke.texi
317 +++ gcc/doc/invoke.texi
318 @@ -2802,6 +2802,9 @@
319 @option{-Wformat-nonliteral}, @option{-Wformat-security}, and
320 @option{-Wformat=2} are available, but are not included in @option{-Wall}.
321
322 +NOTE: In Gentoo, this option is enabled by default for C, C++, ObjC, ObjC++.
323 +To disable, use @option{-Wformat=0}.
324 +
325 @item -Wformat-y2k
326 @opindex Wformat-y2k
327 @opindex Wno-format-y2k
328 @@ -2849,6 +2852,11 @@
329 in future warnings may be added to @option{-Wformat-security} that are not
330 included in @option{-Wformat-nonliteral}.)
331
332 +NOTE: In Gentoo, this option is enabled by default for C, C++, ObjC, ObjC++.
333 +To disable, use @option{-Wno-format-security}, or disable all format warnings
334 +with @option{-Wformat=0}. To make format security warnings fatal, specify
335 +@option{-Werror=format-security}.
336 +
337 @item -Wformat=2
338 @opindex Wformat=2
339 @opindex Wno-format=2
340
341
342
343 1.1 src/patchsets/gcc/4.3.6/gentoo/10_all_gcc-default-fortify-source.patch
344
345 file : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/10_all_gcc-default-fortify-source.patch?rev=1.1&view=markup
346 plain: http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/10_all_gcc-default-fortify-source.patch?rev=1.1&content-type=text/plain
347
348 Index: 10_all_gcc-default-fortify-source.patch
349 ===================================================================
350 ripped from Debian
351
352 # DP: Turn on -D_FORTIFY_SOURCE=2 by default for C, C++, ObjC, ObjC++.
353
354 --- gcc/doc/invoke.texi
355 +++ gcc/doc/invoke.texi
356 @@ -5204,6 +5204,11 @@
357 Please note the warning under @option{-fgcse} about
358 invoking @option{-O2} on programs that use computed gotos.
359
360 +NOTE: In Gentoo, @option{-D_FORTIFY_SOURCE=2} is set by default, and is
361 +activated when @option{-O} is set to 2 or higher. This enables additional
362 +compile-time and run-time checks for several libc functions. To disable,
363 +specify either @option{-U_FORTIFY_SOURCE} or @option{-D_FORTIFY_SOURCE=0}.
364 +
365 @item -O3
366 @opindex O3
367 Optimize yet more. @option{-O3} turns on all optimizations specified by
368 --- gcc/gcc.c
369 +++ gcc/gcc.c
370 @@ -802,6 +802,7 @@
371 %{H} %C %{D*&U*&A*} %{i*} %Z %i\
372 %{fmudflap:-D_MUDFLAP -include mf-runtime.h}\
373 %{fmudflapth:-D_MUDFLAP -D_MUDFLAPTH -include mf-runtime.h}\
374 + %{!D_FORTIFY_SOURCE:%{!D_FORTIFY_SOURCE=*:%{!U_FORTIFY_SOURCE:-D_FORTIFY_SOURCE=2}}}\
375 %{E|M|MM:%W{o*}}";
376
377 /* This contains cpp options which are common with cc1_options and are passed
378
379
380
381 1.1 src/patchsets/gcc/4.3.6/gentoo/11_all_gcc-netbsd-symbolic.patch
382
383 file : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/11_all_gcc-netbsd-symbolic.patch?rev=1.1&view=markup
384 plain: http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/11_all_gcc-netbsd-symbolic.patch?rev=1.1&content-type=text/plain
385
386 Index: 11_all_gcc-netbsd-symbolic.patch
387 ===================================================================
388 http://bugs.gentoo.org/122698
389
390 --- gcc/config/netbsd-elf.h
391 +++ gcc/config/netbsd-elf.h
392 @@ -83,6 +83,7 @@
393 #define NETBSD_LINK_SPEC_ELF \
394 "%{assert*} %{R*} %{rpath*} \
395 %{shared:-shared} \
396 + %{symbolic:-Bsymbolic} \
397 %{!shared: \
398 -dc -dp \
399 %{!nostdlib: \
400
401
402
403 1.1 src/patchsets/gcc/4.3.6/gentoo/14_all_gcc-sparc64-bsd.patch
404
405 file : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/14_all_gcc-sparc64-bsd.patch?rev=1.1&view=markup
406 plain: http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/14_all_gcc-sparc64-bsd.patch?rev=1.1&content-type=text/plain
407
408 Index: 14_all_gcc-sparc64-bsd.patch
409 ===================================================================
410 --- a/gcc/config/sparc/freebsd.h 2006-02-02 19:55:09 +0000
411 +++ b/gcc/config/sparc/freebsd.h 2007-09-06 23:55:21 +0100
412 @@ -26,9 +26,22 @@
413 /* FreeBSD needs the platform name (sparc64) defined.
414 Emacs needs to know if the arch is 64 or 32-bits. */
415
416 -#undef CPP_CPU64_DEFAULT_SPEC
417 -#define CPP_CPU64_DEFAULT_SPEC \
418 - "-D__sparc64__ -D__sparc_v9__ -D__sparcv9 -D__arch64__"
419 +#undef FBSD_TARGET_CPU_CPP_BUILTINS
420 +#define FBSD_TARGET_CPU_CPP_BUILTINS() \
421 + do \
422 + { \
423 + if (TARGET_ARCH64) \
424 + { \
425 + builtin_define ("__sparc64__"); \
426 + builtin_define ("__sparc_v9__"); \
427 + builtin_define ("__sparcv9"); \
428 + } \
429 + else \
430 + builtin_define ("__sparc"); \
431 + builtin_define ("__sparc__"); \
432 + } \
433 + while (0)
434 +
435
436 #define LINK_SPEC "%(link_arch) \
437 %{!mno-relax:%{!r:-relax}} \
438
439
440
441 1.1 src/patchsets/gcc/4.3.6/gentoo/15_all_gcc-libgomp-no-werror.patch
442
443 file : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/15_all_gcc-libgomp-no-werror.patch?rev=1.1&view=markup
444 plain: http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/15_all_gcc-libgomp-no-werror.patch?rev=1.1&content-type=text/plain
445
446 Index: 15_all_gcc-libgomp-no-werror.patch
447 ===================================================================
448 libgomp does not respect --disable-werror
449
450 http://bugs.gentoo.org/229059
451 http://gcc.gnu.org/PR38436
452
453 --- gcc-4.3.2/libgomp/configure
454 +++ gcc-4.3.2/libgomp/configure
455 @@ -3297,7 +3297,7 @@
456
457 # Add -Wall -Werror if we are using GCC.
458 if test "x$GCC" = "xyes"; then
459 - XCFLAGS="$XCFLAGS -Wall -Werror"
460 + XCFLAGS="$XCFLAGS -Wall"
461 fi
462
463 # Find other programs we need.
464
465
466
467 1.1 src/patchsets/gcc/4.3.6/gentoo/18_all_904-flatten-switch-stmt-00.patch
468
469 file : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/18_all_904-flatten-switch-stmt-00.patch?rev=1.1&view=markup
470 plain: http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/18_all_904-flatten-switch-stmt-00.patch?rev=1.1&content-type=text/plain
471
472 Index: 18_all_904-flatten-switch-stmt-00.patch
473 ===================================================================
474 http://gcc.gnu.org/ml/gcc-patches/2007-04/msg00927.html
475
476 Hi,
477
478 The attached patch makes sure that we create smaller object code for
479 simple switch statements. We just make sure to flatten the switch
480 statement into an if-else chain, basically.
481
482 This fixes a size-regression as compared to gcc-3.4, as can be seen
483 below.
484
485 2007-04-15 Bernhard Fischer <..>
486
487 * stmt.c (expand_case): Do not create a complex binary tree when
488 optimizing for size but rather use the simple ordered list.
489 (emit_case_nodes): do not emit jumps to the default_label when
490 optimizing for size.
491
492 Not regtested so far.
493 Comments?
494
495 Attached is the test switch.c mentioned below.
496
497 $ for i in 2.95 3.3 3.4 4.0 4.1 4.2.orig-HEAD 4.3.orig-HEAD 4.3-HEAD;do
498 gcc-$i -DCHAIN -Os -o switch-CHAIN-$i.o -c switch.c ;done
499 $ for i in 2.95 3.3 3.4 4.0 4.1 4.2.orig-HEAD 4.3.orig-HEAD 4.3-HEAD;do
500 gcc-$i -UCHAIN -Os -o switch-$i.o -c switch.c ;done
501
502 $ size switch-*.o
503 text data bss dec hex filename
504 169 0 0 169 a9 switch-2.95.o
505 115 0 0 115 73 switch-3.3.o
506 103 0 0 103 67 switch-3.4.o
507 124 0 0 124 7c switch-4.0.o
508 124 0 0 124 7c switch-4.1.o
509 124 0 0 124 7c switch-4.2.orig-HEAD.o
510 95 0 0 95 5f switch-4.3-HEAD.o
511 124 0 0 124 7c switch-4.3.orig-HEAD.o
512 166 0 0 166 a6 switch-CHAIN-2.95.o
513 111 0 0 111 6f switch-CHAIN-3.3.o
514 95 0 0 95 5f switch-CHAIN-3.4.o
515 95 0 0 95 5f switch-CHAIN-4.0.o
516 95 0 0 95 5f switch-CHAIN-4.1.o
517 95 0 0 95 5f switch-CHAIN-4.2.orig-HEAD.o
518 95 0 0 95 5f switch-CHAIN-4.3-HEAD.o
519 95 0 0 95 5f switch-CHAIN-4.3.orig-HEAD.o
520
521
522 Content-Type: text/x-diff; charset=us-ascii
523 Content-Disposition: attachment; filename="gcc-4.3.gcc-flatten-switch-stmt.00.diff"
524
525 Index: gcc-4.2.0/gcc/stmt.c
526 ===================================================================
527 --- gcc-4.2.0.orig/gcc/stmt.c (revision 123843)
528 +++ gcc-4.2.0/gcc/stmt.c (working copy)
529 @@ -2517,7 +2517,11 @@ expand_case (tree exp)
530 use_cost_table
531 = (TREE_CODE (orig_type) != ENUMERAL_TYPE
532 && estimate_case_costs (case_list));
533 - balance_case_nodes (&case_list, NULL);
534 + /* When optimizing for size, we want a straight list to avoid
535 + jumps as much as possible. This basically creates an if-else
536 + chain. */
537 + if (!optimize_size)
538 + balance_case_nodes (&case_list, NULL);
539 emit_case_nodes (index, case_list, default_label, index_type);
540 emit_jump (default_label);
541 }
542 @@ -3075,6 +3079,7 @@ emit_case_nodes (rtx index, case_node_pt
543 {
544 if (!node_has_low_bound (node, index_type))
545 {
546 + if (!optimize_size) /* don't jl to the .default_label. */
547 emit_cmp_and_jump_insns (index,
548 convert_modes
549 (mode, imode,
550
551
552 Content-Type: text/x-csrc; charset=us-ascii
553 Content-Disposition: attachment; filename="switch.c"
554
555 int
556 commutative_tree_code (int code)
557 {
558 #define CASE(val, ret) case val:/* __asm__("# val="#val ",ret="#ret);*/ return ret;
559 #ifndef CHAIN
560 switch (code)
561 {
562 # if 1
563 CASE(1,3)
564 CASE(3,2)
565 CASE(5,8)
566 CASE(7,1)
567 CASE(33,4)
568 CASE(44,9)
569 CASE(55,10)
570 CASE(66,-1)
571 CASE(77,99)
572 CASE(666,0)
573 # else
574 case 1:
575 return 3;
576 case 3:
577 return 2;
578 case 5:
579 return 8;
580 case 7:
581 return 1;
582 case 33:
583 return 4;
584 case 44:
585 return 9;
586 case 55:
587 return 10;
588 case 66:
589 return -1;
590 case 77:
591 return 99;
592 case 666:
593 return 0;
594 # endif
595 default:
596 break;
597 }
598 return 4711;
599
600 #else
601 if (code == 1)
602 return 3;
603 else if (code == 3)
604 return 2;
605 else if (code == 5)
606 return 8;
607 else if (code == 7)
608 return 1;
609 else if (code == 33)
610 return 4;
611 else if (code == 44)
612 return 9;
613 else if (code == 55)
614 return 10;
615 else if (code == 66)
616 return -1;
617 else if (code == 77)
618 return 99;
619 else if (code == 666)
620 return 0;
621 else
622 return 4711;
623 #endif
624 }
625
626
627 --AhhlLboLdkugWU4S--
628
629
630
631
632 1.1 src/patchsets/gcc/4.3.6/gentoo/20_all_mudflap-setuid-env.patch
633
634 file : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/20_all_mudflap-setuid-env.patch?rev=1.1&view=markup
635 plain: http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/20_all_mudflap-setuid-env.patch?rev=1.1&content-type=text/plain
636
637 Index: 20_all_mudflap-setuid-env.patch
638 ===================================================================
639 mudflap accepts options via $MUDFLAP_OPTIONS even when running setuid.
640
641 -viol-gdb option invokes programs upon error detection which is bad.
642 Note that NULL ptr derefs which are unexploitable in userspace programs,
643 then become exploitable.
644
645 http://gcc.gnu.org/PR41433
646 https://bugs.gentoo.org/335290
647
648 --- a/libmudflap/mf-runtime.c
649 +++ b/libmudflap/mf-runtime.c
650 @@ -303,6 +303,14 @@ __mf_set_default_options ()
651 #ifdef LIBMUDFLAPTH
652 __mf_opts.thread_stack = 0;
653 #endif
654 +
655 + /* PR41443: Beware that the above flags will be applied to
656 + setuid/setgid binaries, and cannot be overriden with
657 + $MUDFLAP_OPTIONS. So the defaults must be non-exploitable.
658 +
659 + Should we consider making the default violation_mode something
660 + harsher than viol_nop? OTOH, glibc's MALLOC_CHECK_ is disabled
661 + by default for these same programs. */
662 }
663
664 static struct mudoption
665 @@ -442,7 +450,7 @@ __mf_usage ()
666 "This is a %s%sGCC \"mudflap\" memory-checked binary.\n"
667 "Mudflap is Copyright (C) 2002-2010 Free Software Foundation, Inc.\n"
668 "\n"
669 - "The mudflap code can be controlled by an environment variable:\n"
670 + "Unless setuid, a program's mudflap options be set by an environment variable:\n"
671 "\n"
672 "$ export MUDFLAP_OPTIONS='<options>'\n"
673 "$ <mudflapped_program>\n"
674 @@ -705,7 +713,8 @@ __mf_init ()
675
676 __mf_set_default_options ();
677
678 - ov = getenv ("MUDFLAP_OPTIONS");
679 + if (getuid () == geteuid () && getgid () == getegid ()) /* PR41433, not setuid */
680 + ov = getenv ("MUDFLAP_OPTIONS");
681 if (ov)
682 {
683 int rc = __mfu_set_options (ov);
684
685
686
687 1.1 src/patchsets/gcc/4.3.6/gentoo/20_all_s390-gcc-4.3.2-z10-complete.patch
688
689 file : http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/20_all_s390-gcc-4.3.2-z10-complete.patch?rev=1.1&view=markup
690 plain: http://sources.gentoo.org/viewvc.cgi/gentoo/src/patchsets/gcc/4.3.6/gentoo/20_all_s390-gcc-4.3.2-z10-complete.patch?rev=1.1&content-type=text/plain
691
692 Index: 20_all_s390-gcc-4.3.2-z10-complete.patch
693 ===================================================================
694 http://www.ibm.com/developerworks/linux/linux390/toolchain.html#gcc-4.3.2
695
696 This patch enables gcc 4.3.2 to generate code using the new IBM System
697 z10 hardware instructions and provides z10 specific instructions
698 scheduling. When the -march=z10 option is specified, gcc makes use of
699 the z10 instruction extension facility to generate faster executables
700 which are limited to run on a z10 or higher. z10 specific instruction
701 scheduling is enabled by default when using the -march=z10 option but
702 can also be requested separately using the -mtune=z10 option.
703
704 Index: gcc/doc/tm.texi
705 ===================================================================
706 --- gcc/doc/tm.texi (revision 141434)
707 +++ gcc/doc/tm.texi (working copy)
708 @@ -5297,6 +5297,17 @@
709 Format}.
710 @end defmac
711
712 +@defmac TARGET_MEM_CONSTRAINT
713 +A single character to be used instead of the default @code{'m'}
714 +character for general memory addresses. This defines the constraint
715 +letter which matches the memory addresses accepted by
716 +@code{GO_IF_LEGITIMATE_ADDRESS_P}. Define this macro if you want to
717 +support new address formats in your back end without changing the
718 +semantics of the @code{'m'} constraint. This is necessary in order to
719 +preserve functionality of inline assembly constructs using the
720 +@code{'m'} constraint.
721 +@end defmac
722 +
723 @defmac FIND_BASE_TERM (@var{x})
724 A C expression to determine the base term of address @var{x}.
725 This macro is used in only one place: `find_base_term' in alias.c.
726 Index: gcc/doc/md.texi
727 ===================================================================
728 --- gcc/doc/md.texi (revision 141434)
729 +++ gcc/doc/md.texi (working copy)
730 @@ -1050,6 +1050,7 @@
731 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
732 * Class Preferences:: Constraints guide which hard register to put things in.
733 * Modifiers:: More precise control over effects of constraints.
734 +* Disable Insn Alternatives:: Disable insn alternatives using the @code{enabled} attribute.
735 * Machine Constraints:: Existing constraints for some particular machines.
736 * Define Constraints:: How to define machine-specific constraints.
737 * C Constraint Interface:: How to test constraints from C code.
738 @@ -1085,6 +1086,8 @@
739 @item @samp{m}
740 A memory operand is allowed, with any kind of address that the machine
741 supports in general.
742 +Note that the letter used for the general memory constraint can be
743 +re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
744
745 @cindex offsettable address
746 @cindex @samp{o} in constraint
747 @@ -3091,6 +3094,99 @@
748 @end table
749
750 @ifset INTERNALS
751 +@node Disable Insn Alternatives
752 +@subsection Disable insn alternatives using the @code{enabled} attribute
753 +@cindex enabled
754 +
755 +The @code{enabled} insn attribute may be used to disable certain insn
756 +alternatives for machine-specific reasons. This is useful when adding
757 +new instructions to an existing pattern which are only available for
758 +certain cpu architecture levels as specified with the @code{-march=}
759 +option.
760 +
761 +If an insn alternative is disabled, then it will never be used. The
762 +compiler treats the constraints for the disabled alternative as
763 +unsatisfiable.
764 +
765 +In order to make use of the @code{enabled} attribute a back end has to add
766 +in the machine description files:
767 +
768 +@enumerate
769 +@item
770 +A definition of the @code{enabled} insn attribute. The attribute is
771 +defined as usual using the @code{define_attr} command. This
772 +definition should be based on other insn attributes and/or target flags.
773 +The @code{enabled} attribute is a numeric attribute and should evaluate to
774 +@code{(const_int 1)} for an enabled alternative and to
775 +@code{(const_int 0)} otherwise.
776 +@item
777 +A definition of another insn attribute used to describe for what
778 +reason an insn alternative might be available or
779 +not. E.g. @code{cpu_facility} as in the example below.
780 +@item
781 +An assignement for the second attribute to each insn definition
782 +combining instructions which are not all available under the same
783 +circumstances. (Note: It obviously only makes sense for definitions
784 +with more than one alternative. Otherwise the insn pattern should be
785 +disabled or enabled using the insn condition.)
786 +@end enumerate
787 +
788 +E.g. the following two patterns could easily be merged using the @code{enabled}
789 +attribute:
790 +
791 +@smallexample
792 +
793 +(define_insn "*movdi_old"
794 + [(set (match_operand:DI 0 "register_operand" "=d")
795 + (match_operand:DI 1 "register_operand" " d"))]
796 + "!TARGET_NEW"
797 + "lgr %0,%1")
798 +
799 +(define_insn "*movdi_new"
800 + [(set (match_operand:DI 0 "register_operand" "=d,f,d")
801 + (match_operand:DI 1 "register_operand" " d,d,f"))]
802 + "TARGET_NEW"
803 + "@@
804 + lgr %0,%1
805 + ldgr %0,%1
806 + lgdr %0,%1")
807 +
808 +@end smallexample
809 +
810 +to:
811 +
812 +@smallexample
813 +
814 +(define_insn "*movdi_combined"
815 + [(set (match_operand:DI 0 "register_operand" "=d,f,d")
816 + (match_operand:DI 1 "register_operand" " d,d,f"))]
817 + ""
818 + "@@
819 + lgr %0,%1
820 + ldgr %0,%1
821 + lgdr %0,%1"
822 + [(set_attr "cpu_facility" "*,new,new")])
823 +
824 +@end smallexample
825 +
826 +with the @code{enabled} attribute defined like this:
827 +
828 +@smallexample
829 +
830 +(define_attr "cpu_facility" "standard,new" (const_string "standard"))
831 +
832 +(define_attr "enabled" ""
833 + (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
834 + (and (eq_attr "cpu_facility" "new")
835 + (ne (symbol_ref "TARGET_NEW") (const_int 0)))
836 + (const_int 1)]
837 + (const_int 0)))
838 +
839 +@end smallexample
840 +
841 +@end ifset
842 +
843 +@ifset INTERNALS
844 @node Define Constraints
845 @subsection Defining Machine-Specific Constraints
846 @cindex defining constraints
847 @@ -6514,6 +6610,22 @@
848 defined and the function to obtain the attribute's value will return
849 @code{int}.
850
851 +There are attributes which are tied to a specific meaning. These
852 +attributes are not free to use for other purposes:
853 +
854 +@table @code
855 +@item length
856 +The @code{length} attribute is used to calculate the length of emitted
857 +code chunks. This is especially important when verifying branch
858 +distances. @xref{Insn Lengths}.
859 +
860 +@item enabled
861 +The @code{enabled} attribute can be defined to prevent certain
862 +alternatives of an insn definition from being used during code
863 +generation. @xref{Disable Insn Alternatives}.
864 +
865 +@end table
866 +
867 @end ifset
868 @ifset INTERNALS
869 @node Expressions
870 Index: gcc/postreload.c
871 ===================================================================
872 --- gcc/postreload.c (revision 141434)
873 +++ gcc/postreload.c (working copy)
874 @@ -542,12 +542,12 @@
875 case '*': case '%':
876 case '0': case '1': case '2': case '3': case '4':
877 case '5': case '6': case '7': case '8': case '9':
878 - case 'm': case '<': case '>': case 'V': case 'o':
879 + case '<': case '>': case 'V': case 'o':
880 case 'E': case 'F': case 'G': case 'H':
881 case 's': case 'i': case 'n':
882 case 'I': case 'J': case 'K': case 'L':
883 case 'M': case 'N': case 'O': case 'P':
884 - case 'p': case 'X':
885 + case 'p': case 'X': case TARGET_MEM_CONSTRAINT:
886 /* These don't say anything we care about. */
887 break;
888
889 Index: gcc/defaults.h
890 ===================================================================
891 --- gcc/defaults.h (revision 141434)
892 +++ gcc/defaults.h (working copy)
893 @@ -902,6 +902,10 @@
894 #define LEGITIMATE_PIC_OPERAND_P(X) 1
895 #endif
896
897 +#ifndef TARGET_MEM_CONSTRAINT
898 +#define TARGET_MEM_CONSTRAINT 'm'
899 +#endif
900 +
901 #ifndef REVERSIBLE_CC_MODE
902 #define REVERSIBLE_CC_MODE(MODE) 0
903 #endif
904 Index: gcc/reload.c
905 ===================================================================
906 --- gcc/reload.c (revision 141434)
907 +++ gcc/reload.c (working copy)
908 @@ -2544,7 +2544,7 @@
909 int noperands;
910 /* These start out as the constraints for the insn
911 and they are chewed up as we consider alternatives. */
912 - char *constraints[MAX_RECOG_OPERANDS];
913 + const char *constraints[MAX_RECOG_OPERANDS];
914 /* These are the preferred classes for an operand, or NO_REGS if it isn't
915 a register. */
916 enum reg_class preferred_class[MAX_RECOG_OPERANDS];
917 @@ -2651,7 +2651,8 @@
918
919 memcpy (operand_mode, recog_data.operand_mode,
920 noperands * sizeof (enum machine_mode));
921 - memcpy (constraints, recog_data.constraints, noperands * sizeof (char *));
922 + memcpy (constraints, recog_data.constraints,
923 + noperands * sizeof (const char *));
924
925 commutative = -1;
926
927 @@ -2662,8 +2663,9 @@
928
929 for (i = 0; i < noperands; i++)
930 {
931 - char *p;
932 + const char *p;
933 int c;
934 + char *end;
935
936 substed_operand[i] = recog_data.operand[i];
937 p = constraints[i];
938 @@ -2707,7 +2709,8 @@
939 case '0': case '1': case '2': case '3': case '4':
940 case '5': case '6': case '7': case '8': case '9':
941 {
942 - c = strtoul (p - 1, &p, 10);
943 + c = strtoul (p - 1, &end, 10);
944 + p = end;
945
946 operands_match[c][i]
947 = operands_match_p (recog_data.operand[c],
948 @@ -2935,11 +2938,21 @@
949 a bad register class to only count 1/3 as much. */
950 int reject = 0;
951
952 + if (!recog_data.alternative_enabled_p[this_alternative_number])
953 + {
954 + int i;
955 +
956 + for (i = 0; i < recog_data.n_operands; i++)
957 + constraints[i] = skip_alternative (constraints[i]);
958 +
959 + continue;
960 + }
961 +
962 this_earlyclobber = 0;
963
964 for (i = 0; i < noperands; i++)
965 {
966 - char *p = constraints[i];
967 + const char *p = constraints[i];
968 char *end;
969 int len;
970 int win = 0;
971 @@ -3203,7 +3216,7 @@
972 badop = 0;
973 break;
974
975 - case 'm':
976 + case TARGET_MEM_CONSTRAINT:
977 if (force_reload)
978 break;
979 if (MEM_P (operand)
980 @@ -3738,7 +3751,7 @@
981 address_reloaded[commutative + 1] = t;
982
983 memcpy (constraints, recog_data.constraints,
984 - noperands * sizeof (char *));
985 + noperands * sizeof (const char *));
986 goto try_swapped;
987 }
988 else
989 @@ -4555,7 +4568,7 @@
990 while (*constraint++ != ',');
991 altnum--;
992 }
993 - /* Scan the requested alternative for 'm' or 'o'.
994 + /* Scan the requested alternative for TARGET_MEM_CONSTRAINT or 'o'.
995 If one of them is present, this alternative accepts the result of
996 passing a constant-pool reference through find_reloads_toplev.
997
998 @@ -4566,7 +4579,7 @@
999 for (; (c = *constraint) && c != ',' && c != '#';
1000 constraint += CONSTRAINT_LEN (c, constraint))
1001 {
1002 - if (c == 'm' || c == 'o')
1003 + if (c == TARGET_MEM_CONSTRAINT || c == 'o')
1004 return true;
1005 #ifdef EXTRA_CONSTRAINT_STR
1006 if (EXTRA_MEMORY_CONSTRAINT (c, constraint)
1007 Index: gcc/genoutput.c
1008 ===================================================================
1009 --- gcc/genoutput.c (revision 141434)
1010 +++ gcc/genoutput.c (working copy)
1011 @@ -1122,7 +1122,10 @@
1012 unsigned int namelen = strlen (name);
1013 struct constraint_data **iter, **slot, *new;
1014
1015 - if (strchr (indep_constraints, name[0]))
1016 + /* The 'm' constraint is special here since that constraint letter
1017 + can be overridden by the back end by defining the
1018 + TARGET_MEM_CONSTRAINT macro. */
1019 + if (strchr (indep_constraints, name[0]) && name[0] != 'm')
1020 {
1021 if (name[1] == '\0')
1022 message_with_line (lineno, "constraint letter '%s' cannot be "
1023 Index: gcc/recog.c
1024 ===================================================================
1025 --- gcc/recog.c (revision 141434)
1026 +++ gcc/recog.c (working copy)
1027 @@ -60,6 +60,14 @@
1028 #endif
1029 #endif
1030
1031 +#ifndef HAVE_ATTR_enabled
1032 +static inline bool
1033 +get_attr_enabled (rtx insn ATTRIBUTE_UNUSED)
1034 +{
1035 + return true;
1036 +}
1037 +#endif
1038 +
1039 static void validate_replace_rtx_1 (rtx *, rtx, rtx, rtx);
1040 static void validate_replace_src_1 (rtx *, void *);
1041 static rtx split_insn (rtx);
1042 @@ -1550,7 +1558,7 @@
1043 result = 1;
1044 break;
1045
1046 - case 'm':
1047 + case TARGET_MEM_CONSTRAINT:
1048 case 'V': /* non-offsettable */
1049 if (memory_operand (op, VOIDmode))
1050 result = 1;
1051 @@ -1684,16 +1692,14 @@
1052 result = 1;
1053 }
1054 #ifdef EXTRA_CONSTRAINT_STR
1055 + else if (EXTRA_MEMORY_CONSTRAINT (c, constraint))
1056 + /* Every memory operand can be reloaded to fit. */
1057 + result = result || memory_operand (op, VOIDmode);
1058 + else if (EXTRA_ADDRESS_CONSTRAINT (c, constraint))
1059 + /* Every address operand can be reloaded to fit. */
1060 + result = result || address_operand (op, VOIDmode);
1061 else if (EXTRA_CONSTRAINT_STR (op, c, constraint))
1062 result = 1;
1063 - else if (EXTRA_MEMORY_CONSTRAINT (c, constraint)
1064 - /* Every memory operand can be reloaded to fit. */
1065 - && memory_operand (op, VOIDmode))
1066 - result = 1;
1067 - else if (EXTRA_ADDRESS_CONSTRAINT (c, constraint)
1068 - /* Every address operand can be reloaded to fit. */
1069 - && address_operand (op, VOIDmode))
1070 - result = 1;
1071 #endif
1072 break;
1073 }
1074 @@ -1927,11 +1933,9 @@
1075 int noperands;
1076 rtx body = PATTERN (insn);
1077
1078 - recog_data.insn = NULL;
1079 recog_data.n_operands = 0;
1080 recog_data.n_alternatives = 0;
1081 recog_data.n_dups = 0;
1082 - which_alternative = -1;
1083
1084 switch (GET_CODE (body))
1085 {
1086 @@ -2011,6 +2015,22 @@
1087 : OP_IN);
1088
1089 gcc_assert (recog_data.n_alternatives <= MAX_RECOG_ALTERNATIVES);
1090 +
1091 + if (INSN_CODE (insn) < 0)
1092 + for (i = 0; i < recog_data.n_alternatives; i++)
1093 + recog_data.alternative_enabled_p[i] = true;
1094 + else
1095 + {
1096 + recog_data.insn = insn;
1097 + for (i = 0; i < recog_data.n_alternatives; i++)
1098 + {
1099 + which_alternative = i;
1100 + recog_data.alternative_enabled_p[i] = get_attr_enabled (insn);
1101 + }
1102 + }
1103 +
1104 + recog_data.insn = NULL;
1105 + which_alternative = -1;
1106 }
1107
1108 /* After calling extract_insn, you can use this function to extract some
1109 @@ -2040,6 +2060,12 @@
1110 op_alt[j].matches = -1;
1111 op_alt[j].matched = -1;
1112
1113 + if (!recog_data.alternative_enabled_p[j])
1114 + {
1115 + p = skip_alternative (p);
1116 + continue;
1117 + }
1118 +
1119 if (*p == '\0' || *p == ',')
1120 {
1121 op_alt[j].anything_ok = 1;
1122 @@ -2089,7 +2115,7 @@
1123 }
1124 continue;
1125
1126 - case 'm':
1127 + case TARGET_MEM_CONSTRAINT:
1128 op_alt[j].memory_ok = 1;
1129 break;
1130 case '<':
1131 @@ -2209,6 +2235,17 @@
1132 int lose = 0;
1133 funny_match_index = 0;
1134
1135 + if (!recog_data.alternative_enabled_p[which_alternative])
1136 + {
1137 + int i;
1138 +
1139 + for (i = 0; i < recog_data.n_operands; i++)
1140 + constraints[i] = skip_alternative (constraints[i]);
1141 +
1142 + which_alternative++;
1143 + continue;
1144 + }
1145 +
1146 for (opno = 0; opno < recog_data.n_operands; opno++)
1147 {
1148 rtx op = recog_data.operand[opno];
1149 @@ -2362,7 +2399,7 @@
1150 win = 1;
1151 break;
1152
1153 - case 'm':
1154 + case TARGET_MEM_CONSTRAINT:
1155 /* Memory operands must be valid, to the extent
1156 required by STRICT. */
1157 if (MEM_P (op))
1158 Index: gcc/recog.h
1159 ===================================================================
1160 --- gcc/recog.h (revision 141434)
1161 +++ gcc/recog.h (working copy)
1162 @@ -50,7 +50,8 @@
1163
1164 /* Nonzero if '&' was found in the constraint string. */
1165 unsigned int earlyclobber:1;
1166 - /* Nonzero if 'm' was found in the constraint string. */
1167 + /* Nonzero if TARGET_MEM_CONSTRAINT was found in the constraint
1168 + string. */
1169 unsigned int memory_ok:1;
1170 /* Nonzero if 'o' was found in the constraint string. */
1171 unsigned int offmem_ok:1;
1172 @@ -142,6 +143,19 @@
1173 }
1174 #endif
1175
1176 +/* Skip chars until the next ',' or the end of the string. This is
1177 + useful to skip alternatives in a constraint string. */
1178 +static inline const char *
1179 +skip_alternative (const char *p)
1180 +{
1181 + const char *r = p;
1182 + while (*r != '\0' && *r != ',')
1183 + r++;
1184 + if (*r == ',')
1185 + r++;
1186 + return r;
1187 +}
1188 +
1189 /* Nonzero means volatile operands are recognized. */
1190 extern int volatile_ok;
1191
1192 @@ -201,6 +215,12 @@
1193 /* The number of alternatives in the constraints for the insn. */
1194 char n_alternatives;
1195
1196 + /* Specifies whether an insn alternative is enabled using the
1197 + `enabled' attribute in the insn pattern definition. For back
1198 + ends not using the `enabled' attribute the array fields are
1199 + always set to `true' in expand_insn. */
1200 + bool alternative_enabled_p [MAX_RECOG_ALTERNATIVES];
1201 +
1202 /* In case we are caching, hold insn data was generated for. */
1203 rtx insn;
1204 };
1205 Index: gcc/genpreds.c
1206 ===================================================================
1207 --- gcc/genpreds.c (revision 141434)
1208 +++ gcc/genpreds.c (working copy)
1209 @@ -690,8 +690,11 @@
1210 for (iter_ = first_constraint; iter_; iter_ = iter_->next_textual)
1211
1212 /* These letters, and all names beginning with them, are reserved for
1213 - generic constraints. */
1214 -static const char generic_constraint_letters[] = "EFVXgimnoprs";
1215 + generic constraints.
1216 + The 'm' constraint is not mentioned here since that constraint
1217 + letter can be overridden by the back end by defining the
1218 + TARGET_MEM_CONSTRAINT macro. */
1219 +static const char generic_constraint_letters[] = "EFVXginoprs";
1220
1221 /* Machine-independent code expects that constraints with these
1222 (initial) letters will allow only (a subset of all) CONST_INTs. */
1223 Index: gcc/regclass.c
1224 ===================================================================
1225 --- gcc/regclass.c (revision 141434)
1226 +++ gcc/regclass.c (working copy)
1227 @@ -1141,8 +1141,9 @@
1228 record_address_regs (GET_MODE (recog_data.operand[i]),
1229 XEXP (recog_data.operand[i], 0),
1230 0, MEM, SCRATCH, frequency * 2);
1231 - else if (constraints[i][0] == 'p'
1232 - || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], constraints[i]))
1233 + else if (recog_data.alternative_enabled_p[0]
1234 + && (constraints[i][0] == 'p'
1235 + || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], constraints[i])))
1236 record_address_regs (VOIDmode, recog_data.operand[i], 0, ADDRESS,
1237 SCRATCH, frequency * 2);
1238 }
1239 @@ -1699,7 +1700,7 @@
1240 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1241 break;
1242
1243 - case 'm': case 'o': case 'V':
1244 + case TARGET_MEM_CONSTRAINT: case 'o': case 'V':
1245 /* It doesn't seem worth distinguishing between offsettable
1246 and non-offsettable addresses here. */
1247 allows_mem[i] = 1;
1248 @@ -1930,6 +1931,9 @@
1249 if (alt_fail)
1250 continue;
1251
1252 + if (!recog_data.alternative_enabled_p[alt])
1253 + continue;
1254 +
1255 /* Finally, update the costs with the information we've calculated
1256 about this alternative. */
1257
1258 Index: gcc/config.gcc
1259 ===================================================================
1260 --- gcc/config.gcc (revision 141434)
1261 +++ gcc/config.gcc (working copy)
1262 @@ -3155,7 +3155,7 @@
1263 for which in arch tune; do
1264 eval "val=\$with_$which"
1265 case ${val} in
1266 - "" | g5 | g6 | z900 | z990 | z9-109 | z9-ec)
1267 + "" | g5 | g6 | z900 | z990 | z9-109 | z9-ec | z10)
1268 # OK
1269 ;;
1270 *)
1271 Index: gcc/config/s390/s390.c
1272 ===================================================================
1273 --- gcc/config/s390/s390.c (revision 141434)
1274 +++ gcc/config/s390/s390.c (working copy)
1275 @@ -1,8 +1,9 @@
1276 /* Subroutines used for code generation on IBM S/390 and zSeries
1277 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
1278 - 2007 Free Software Foundation, Inc.
1279 + 2007, 2008 Free Software Foundation, Inc.
1280 Contributed by Hartmut Penner (hpenner@××××××.com) and
1281 - Ulrich Weigand (uweigand@××××××.com).
1282 + Ulrich Weigand (uweigand@××××××.com) and
1283 + Andreas Krebbel (Andreas.Krebbel@××××××.com).
1284
1285 This file is part of GCC.
1286
1287 @@ -188,6 +189,38 @@
1288 COSTS_N_INSNS (24), /* DSGR */
1289 };
1290
1291 +static const
1292 +struct processor_costs z10_cost =
1293 +{
1294 + COSTS_N_INSNS (10), /* M */
1295 + COSTS_N_INSNS (10), /* MGHI */
1296 + COSTS_N_INSNS (10), /* MH */
1297 + COSTS_N_INSNS (10), /* MHI */
1298 + COSTS_N_INSNS (10), /* ML */
1299 + COSTS_N_INSNS (10), /* MR */
1300 + COSTS_N_INSNS (10), /* MS */
1301 + COSTS_N_INSNS (10), /* MSG */
1302 + COSTS_N_INSNS (10), /* MSGF */
1303 + COSTS_N_INSNS (10), /* MSGFR */
1304 + COSTS_N_INSNS (10), /* MSGR */
1305 + COSTS_N_INSNS (10), /* MSR */
1306 + COSTS_N_INSNS (10), /* multiplication in DFmode */
1307 + COSTS_N_INSNS (50), /* MXBR */
1308 + COSTS_N_INSNS (120), /* SQXBR */
1309 + COSTS_N_INSNS (52), /* SQDBR */
1310 + COSTS_N_INSNS (38), /* SQEBR */
1311 + COSTS_N_INSNS (10), /* MADBR */
1312 + COSTS_N_INSNS (10), /* MAEBR */
1313 + COSTS_N_INSNS (111), /* DXBR */
1314 + COSTS_N_INSNS (39), /* DDBR */
1315 + COSTS_N_INSNS (32), /* DEBR */
1316 + COSTS_N_INSNS (160), /* DLGR */
1317 + COSTS_N_INSNS (71), /* DLR */
1318 + COSTS_N_INSNS (71), /* DR */
1319 + COSTS_N_INSNS (71), /* DSGFR */
1320 + COSTS_N_INSNS (71), /* DSGR */
1321 +};
1322 +
1323 extern int reload_completed;
1324
1325 /* Save information from a "cmpxx" operation until the branch or scc is
1326 @@ -1029,6 +1062,41 @@
1327 }
1328 }
1329
1330 +
1331 +/* Return branch condition mask to implement a compare and branch
1332 + specified by CODE. Return -1 for invalid comparisons. */
1333 +
1334 +int
1335 +s390_compare_and_branch_condition_mask (rtx code)
1336 +{
1337 + const int CC0 = 1 << 3;
1338 + const int CC1 = 1 << 2;
1339 + const int CC2 = 1 << 1;
1340 +
1341 + switch (GET_CODE (code))
1342 + {
1343 + case EQ:
1344 + return CC0;
1345 + case NE:
1346 + return CC1 | CC2;
1347 + case LT:
1348 + case LTU:
1349 + return CC1;
1350 + case GT:
1351 + case GTU:
1352 + return CC2;
1353 + case LE:
1354 + case LEU:
1355 + return CC0 | CC1;
1356 + case GE:
1357 + case GEU:
1358 + return CC0 | CC2;
1359 + default:
1360 + gcc_unreachable ();
1361 + }
1362 + return -1;
1363 +}
1364 +
1365 /* If INV is false, return assembler mnemonic string to implement
1366 a branch specified by CODE. If INV is true, return mnemonic
1367 for the corresponding inverted branch. */
1368 @@ -1036,6 +1104,8 @@
1369 static const char *
1370 s390_branch_condition_mnemonic (rtx code, int inv)
1371 {
1372 + int mask;
1373 +
1374 static const char *const mnemonic[16] =
1375 {
1376 NULL, "o", "h", "nle",
1377 @@ -1044,7 +1114,13 @@
1378 "le", "nh", "no", NULL
1379 };
1380
1381 - int mask = s390_branch_condition_mask (code);
1382 + if (GET_CODE (XEXP (code, 0)) == REG
1383 + && REGNO (XEXP (code, 0)) == CC_REGNUM
1384 + && XEXP (code, 1) == const0_rtx)
1385 + mask = s390_branch_condition_mask (code);
1386 + else
1387 + mask = s390_compare_and_branch_condition_mask (code);
1388 +
1389 gcc_assert (mask >= 0);
1390
1391 if (inv)
1392 @@ -1121,6 +1197,67 @@
1393 return part == -1 ? -1 : n_parts - 1 - part;
1394 }
1395
1396 +/* Return true if IN contains a contiguous bitfield in the lower SIZE
1397 + bits and no other bits are set in IN. POS and LENGTH can be used
1398 + to obtain the start position and the length of the bitfield.
1399 +
1400 + POS gives the position of the first bit of the bitfield counting
1401 + from the lowest order bit starting with zero. In order to use this
1402 + value for S/390 instructions this has to be converted to "bits big
1403 + endian" style. */
1404 +
1405 +bool
1406 +s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1407 + int *pos, int *length)
1408 +{
1409 + int tmp_pos = 0;
1410 + int tmp_length = 0;
1411 + int i;
1412 + unsigned HOST_WIDE_INT mask = 1ULL;
1413 + bool contiguous = false;
1414 +
1415 + for (i = 0; i < size; mask <<= 1, i++)
1416 + {
1417 + if (contiguous)
1418 + {
1419 + if (mask & in)
1420 + tmp_length++;
1421 + else
1422 + break;
1423 + }
1424 + else
1425 + {
1426 + if (mask & in)
1427 + {
1428 + contiguous = true;
1429 + tmp_length++;
1430 + }
1431 + else
1432 + tmp_pos++;
1433 + }
1434 + }
1435 +
1436 + if (!tmp_length)
1437 + return false;
1438 +
1439 + /* Calculate a mask for all bits beyond the contiguous bits. */
1440 + mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1441 +
1442 + if (mask & in)
1443 + return false;
1444 +
1445 + if (tmp_length + tmp_pos - 1 > size)
1446 + return false;
1447 +
1448 + if (length)
1449 + *length = tmp_length;
1450 +
1451 + if (pos)
1452 + *pos = tmp_pos;
1453 +
1454 + return true;
1455 +}
1456 +
1457 /* Check whether we can (and want to) split a double-word
1458 move in mode MODE from SRC to DST into two single-word
1459 moves, moving the subword FIRST_SUBWORD first. */
1460 @@ -1365,6 +1502,8 @@
1461 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1462 {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1463 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
1464 + {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH
1465 + | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10},
1466 };
1467 size_t i;
1468
1469 @@ -1472,13 +1611,21 @@
1470 }
1471
1472 /* Set processor cost function. */
1473 - if (s390_tune == PROCESSOR_2094_Z9_109)
1474 - s390_cost = &z9_109_cost;
1475 - else if (s390_tune == PROCESSOR_2084_Z990)
1476 - s390_cost = &z990_cost;
1477 - else
1478 - s390_cost = &z900_cost;
1479 -
1480 + switch (s390_tune)
1481 + {
1482 + case PROCESSOR_2084_Z990:
1483 + s390_cost = &z990_cost;
1484 + break;
1485 + case PROCESSOR_2094_Z9_109:
1486 + s390_cost = &z9_109_cost;
1487 + break;
1488 + case PROCESSOR_2097_Z10:
1489 + s390_cost = &z10_cost;
1490 + break;
1491 + default:
1492 + s390_cost = &z900_cost;
1493 + }
1494 +
1495 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1496 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1497 "in combination");
1498 @@ -1992,11 +2139,10 @@
1499 return 0;
1500 if (GET_CODE (op) != MEM)
1501 return 0;
1502 - /* Any invalid address here will be fixed up by reload,
1503 - so accept it for the most generic constraint. */
1504 - if (s390_decompose_address (XEXP (op, 0), &addr)
1505 - && s390_short_displacement (addr.disp))
1506 + if (!s390_decompose_address (XEXP (op, 0), &addr))
1507 return 0;
1508 + if (s390_short_displacement (addr.disp))
1509 + return 0;
1510 break;
1511
1512 case 'U':
1513 @@ -2012,11 +2158,10 @@
1514 case 'W':
1515 if (!TARGET_LONG_DISPLACEMENT)
1516 return 0;
1517 - /* Any invalid address here will be fixed up by reload,
1518 - so accept it for the most generic constraint. */
1519 - if (s390_decompose_address (op, &addr)
1520 - && s390_short_displacement (addr.disp))
1521 + if (!s390_decompose_address (op, &addr))
1522 return 0;
1523 + if (s390_short_displacement (addr.disp))
1524 + return 0;
1525 break;
1526
1527 case 'Y':
1528 @@ -2651,6 +2796,132 @@
1529 return class;
1530 }
1531
1532 +/* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
1533 + and return these parts in SYMREF and ADDEND. You can pass NULL in
1534 + SYMREF and/or ADDEND if you are not interested in these values. */
1535 +
1536 +static bool
1537 +s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
1538 +{
1539 + HOST_WIDE_INT tmpaddend = 0;
1540 +
1541 + if (GET_CODE (addr) == CONST)
1542 + addr = XEXP (addr, 0);
1543 +
1544 + if (GET_CODE (addr) == PLUS)
1545 + {
1546 + if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
1547 + && CONST_INT_P (XEXP (addr, 1)))
1548 + {
1549 + tmpaddend = INTVAL (XEXP (addr, 1));
1550 + addr = XEXP (addr, 0);
1551 + }
1552 + else
1553 + return false;
1554 + }
1555 + else
1556 + if (GET_CODE (addr) != SYMBOL_REF)
1557 + return false;
1558 +
1559 + if (symref)
1560 + *symref = addr;
1561 + if (addend)
1562 + *addend = tmpaddend;
1563 +
1564 + return true;
1565 +}
1566 +
1567 +/* Return true if ADDR is SYMBOL_REF + addend with addend being a
1568 + multiple of ALIGNMENT and the SYMBOL_REF being naturally
1569 + aligned. */
1570 +
1571 +bool
1572 +s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
1573 +{
1574 + HOST_WIDE_INT addend;
1575 + rtx symref;
1576 +
1577 + if (!s390_symref_operand_p (addr, &symref, &addend))
1578 + return false;
1579 +
1580 + return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
1581 + && !(addend & (alignment - 1)));
1582 +}
1583 +
1584 +/* ADDR is moved into REG using larl. If ADDR isn't a valid larl
1585 + operand SCRATCH is used to reload the even part of the address and
1586 + adding one. */
1587 +
1588 +void
1589 +s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
1590 +{
1591 + HOST_WIDE_INT addend;
1592 + rtx symref;
1593 +
1594 + if (!s390_symref_operand_p (addr, &symref, &addend))
1595 + gcc_unreachable ();
1596 +
1597 + if (!(addend & 1))
1598 + /* Easy case. The addend is even so larl will do fine. */
1599 + emit_move_insn (reg, addr);
1600 + else
1601 + {
1602 + /* We can leave the scratch register untouched if the target
1603 + register is a valid base register. */
1604 + if (REGNO (reg) < FIRST_PSEUDO_REGISTER
1605 + && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
1606 + scratch = reg;
1607 +
1608 + gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
1609 + gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
1610 +
1611 + if (addend != 1)
1612 + emit_move_insn (scratch,
1613 + gen_rtx_CONST (Pmode,
1614 + gen_rtx_PLUS (Pmode, symref,
1615 + GEN_INT (addend - 1))));
1616 + else
1617 + emit_move_insn (scratch, symref);
1618 +
1619 + /* Increment the address using la in order to avoid clobbering cc. */
1620 + emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
1621 + }
1622 +}
1623 +
1624 +/* Generate what is necessary to move between REG and MEM using
1625 + SCRATCH. The direction is given by TOMEM. */
1626 +
1627 +void
1628 +s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
1629 +{
1630 + /* Reload might have pulled a constant out of the literal pool.
1631 + Force it back in. */
1632 + if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
1633 + || GET_CODE (mem) == CONST)
1634 + mem = force_const_mem (GET_MODE (reg), mem);
1635 +
1636 + gcc_assert (MEM_P (mem));
1637 +
1638 + /* For a load from memory we can leave the scratch register
1639 + untouched if the target register is a valid base register. */
1640 + if (!tomem
1641 + && REGNO (reg) < FIRST_PSEUDO_REGISTER
1642 + && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
1643 + && GET_MODE (reg) == GET_MODE (scratch))
1644 + scratch = reg;
1645 +
1646 + /* Load address into scratch register. Since we can't have a
1647 + secondary reload for a secondary reload we have to cover the case
1648 + where larl would need a secondary reload here as well. */
1649 + s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
1650 +
1651 + /* Now we can use a standard load/store to do the move. */
1652 + if (tomem)
1653 + emit_move_insn (replace_equiv_address (mem, scratch), reg);
1654 + else
1655 + emit_move_insn (reg, replace_equiv_address (mem, scratch));
1656 +}
1657 +
1658 /* Inform reload about cases where moving X with a mode MODE to a register in
1659 CLASS requires an extra scratch or immediate register. Return the class
1660 needed for the immediate register. */
1661 @@ -2663,6 +2934,60 @@
1662 if (reg_classes_intersect_p (CC_REGS, class))
1663 return GENERAL_REGS;
1664
1665 + if (TARGET_Z10)
1666 + {
1667 + /* On z10 several optimizer steps may generate larl operands with
1668 + an odd addend. */
1669 + if (in_p
1670 + && s390_symref_operand_p (x, NULL, NULL)
1671 + && mode == Pmode
1672 + && !s390_check_symref_alignment (x, 2))
1673 + sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
1674 + : CODE_FOR_reloadsi_larl_odd_addend_z10);
1675 +
1676 + /* On z10 we need a scratch register when moving QI, TI or floating
1677 + point mode values from or to a memory location with a SYMBOL_REF
1678 + or if the symref addend of a SI or DI move is not aligned to the
1679 + width of the access. */
1680 + if (MEM_P (x)
1681 + && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
1682 + && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
1683 + || (!TARGET_64BIT && mode == DImode)
1684 + || ((mode == HImode || mode == SImode || mode == DImode)
1685 + && (!s390_check_symref_alignment (XEXP (x, 0),
1686 + GET_MODE_SIZE (mode))))))
1687 + {
1688 +#define __SECONDARY_RELOAD_CASE(M,m) \
1689 + case M##mode: \
1690 + if (TARGET_64BIT) \
1691 + sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
1692 + CODE_FOR_reload##m##di_tomem_z10; \
1693 + else \
1694 + sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
1695 + CODE_FOR_reload##m##si_tomem_z10; \
1696 + break;
1697 +
1698 + switch (GET_MODE (x))
1699 + {
1700 + __SECONDARY_RELOAD_CASE (QI, qi);
1701 + __SECONDARY_RELOAD_CASE (HI, hi);
1702 + __SECONDARY_RELOAD_CASE (SI, si);
1703 + __SECONDARY_RELOAD_CASE (DI, di);
1704 + __SECONDARY_RELOAD_CASE (TI, ti);
1705 + __SECONDARY_RELOAD_CASE (SF, sf);
1706 + __SECONDARY_RELOAD_CASE (DF, df);
1707 + __SECONDARY_RELOAD_CASE (TF, tf);
1708 + __SECONDARY_RELOAD_CASE (SD, sd);
1709 + __SECONDARY_RELOAD_CASE (DD, dd);
1710 + __SECONDARY_RELOAD_CASE (TD, td);
1711 +
1712 + default:
1713 + gcc_unreachable ();
1714 + }
1715 +#undef __SECONDARY_RELOAD_CASE
1716 + }
1717 + }
1718 +
1719 /* We need a scratch register when loading a PLUS expression which
1720 is not a legitimate operand of the LOAD ADDRESS instruction. */
1721 if (in_p && s390_plus_operand (x, mode))
1722 @@ -2769,10 +3094,16 @@
1723 STRICT specifies whether strict register checking applies. */
1724
1725 bool
1726 -legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1727 - rtx addr, int strict)
1728 +legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
1729 {
1730 struct s390_address ad;
1731 +
1732 + if (TARGET_Z10
1733 + && larl_operand (addr, VOIDmode)
1734 + && (mode == VOIDmode
1735 + || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
1736 + return true;
1737 +
1738 if (!s390_decompose_address (addr, &ad))
1739 return false;
1740
1741 @@ -4010,14 +4341,31 @@
1742 return false;
1743 }
1744
1745 -/* Expand code for the insv template. Return true if successful, false else. */
1746 +/* Expand code for the insv template. Return true if successful. */
1747
1748 -bool
1749 +bool
1750 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
1751 {
1752 int bitsize = INTVAL (op1);
1753 int bitpos = INTVAL (op2);
1754
1755 + /* On z10 we can use the risbg instruction to implement insv. */
1756 + if (TARGET_Z10
1757 + && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
1758 + || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
1759 + {
1760 + rtx op;
1761 + rtx clobber;
1762 +
1763 + op = gen_rtx_SET (GET_MODE(src),
1764 + gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
1765 + src);
1766 + clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1767 + emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
1768 +
1769 + return true;
1770 + }
1771 +
1772 /* We need byte alignment. */
1773 if (bitsize % BITS_PER_UNIT)
1774 return false;
1775 @@ -4554,6 +4902,13 @@
1776 {
1777 struct s390_address ad;
1778
1779 + if (s390_symref_operand_p (addr, NULL, NULL))
1780 + {
1781 + gcc_assert (TARGET_Z10);
1782 + output_addr_const (file, addr);
1783 + return;
1784 + }
1785 +
1786 if (!s390_decompose_address (addr, &ad)
1787 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
1788 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
1789 @@ -4587,6 +4942,7 @@
1790 'Y': print shift count operand.
1791
1792 'b': print integer X as if it's an unsigned byte.
1793 + 'c': print integer X as if it's an signed byte.
1794 'x': print integer X as if it's an unsigned halfword.
1795 'h': print integer X as if it's a signed halfword.
1796 'i': print the first nonzero HImode part of X.
1797 @@ -4732,6 +5088,8 @@
1798 case CONST_INT:
1799 if (code == 'b')
1800 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
1801 + else if (code == 'c')
1802 + fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
1803 else if (code == 'x')
1804 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
1805 else if (code == 'h')
1806 @@ -4891,6 +5249,7 @@
1807 return 0;
1808 }
1809
1810 +
1811 /* A C statement (sans semicolon) to update the integer scheduling priority
1812 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
1813 reduce the priority to execute INSN later. Do not define this macro if
1814 @@ -4930,10 +5289,16 @@
1815 static int
1816 s390_issue_rate (void)
1817 {
1818 - if (s390_tune == PROCESSOR_2084_Z990
1819 - || s390_tune == PROCESSOR_2094_Z9_109)
1820 - return 3;
1821 - return 1;
1822 + switch (s390_tune)
1823 + {
1824 + case PROCESSOR_2084_Z990:
1825 + case PROCESSOR_2094_Z9_109:
1826 + return 3;
1827 + case PROCESSOR_2097_Z10:
1828 + return 2;
1829 + default:
1830 + return 1;
1831 + }
1832 }
1833
1834 static int
1835 @@ -8515,11 +8880,30 @@
1836 {
1837 default_encode_section_info (decl, rtl, first);
1838
1839 - /* If a variable has a forced alignment to < 2 bytes, mark it with
1840 - SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL operand. */
1841 - if (TREE_CODE (decl) == VAR_DECL
1842 - && DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
1843 - SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
1844 + if (TREE_CODE (decl) == VAR_DECL)
1845 + {
1846 + /* If a variable has a forced alignment to < 2 bytes, mark it
1847 + with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
1848 + operand. */
1849 + if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
1850 + SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
1851 + if (!DECL_SIZE (decl)
1852 + || !DECL_ALIGN (decl)
1853 + || !host_integerp (DECL_SIZE (decl), 0)
1854 + || (DECL_ALIGN (decl) <= 64
1855 + && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
1856 + SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
1857 + }
1858 +
1859 + /* Literal pool references don't have a decl so they are handled
1860 + differently here. We rely on the information in the MEM_ALIGN
1861 + entry to decide upon natural alignment. */
1862 + if (MEM_P (rtl)
1863 + && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
1864 + && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
1865 + && (MEM_ALIGN (rtl) == 0
1866 + || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
1867 + SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
1868 }
1869
1870 /* Output thunk to FILE that implements a C++ virtual function call (with
1871 Index: gcc/config/s390/predicates.md
1872 ===================================================================
1873 --- gcc/config/s390/predicates.md (revision 141434)
1874 +++ gcc/config/s390/predicates.md (working copy)
1875 @@ -1,5 +1,5 @@
1876 ;; Predicate definitions for S/390 and zSeries.
1877 -;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
1878 +;; Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
1879 ;; Contributed by Hartmut Penner (hpenner@××××××.com) and
1880 ;; Ulrich Weigand (uweigand@××××××.com).
1881 ;;
1882 @@ -110,7 +110,7 @@
1883 if (GET_CODE (op) == LABEL_REF)
1884 return true;
1885 if (GET_CODE (op) == SYMBOL_REF)
1886 - return ((SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_ALIGN1) == 0
1887 + return (!SYMBOL_REF_ALIGN1_P (op)
1888 && SYMBOL_REF_TLS_MODEL (op) == 0
1889 && (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
1890
1891 @@ -172,6 +172,18 @@
1892 return (s390_branch_condition_mask (op) >= 0);
1893 })
1894
1895 +(define_predicate "s390_signed_integer_comparison"
1896 + (match_code "eq, ne, lt, gt, le, ge")
1897 +{
1898 + return (s390_compare_and_branch_condition_mask (op) >= 0);
1899 +})
1900 +
1901 +(define_predicate "s390_unsigned_integer_comparison"
1902 + (match_code "eq, ne, ltu, gtu, leu, geu")
1903 +{
1904 + return (s390_compare_and_branch_condition_mask (op) >= 0);
1905 +})
1906 +
1907 ;; Return nonzero if OP is a valid comparison operator
1908 ;; for an ALC condition.
1909
1910 Index: gcc/config/s390/s390.h
1911 ===================================================================
1912 --- gcc/config/s390/s390.h (revision 141434)
1913 +++ gcc/config/s390/s390.h (working copy)
1914 @@ -1,8 +1,9 @@
1915 /* Definitions of target machine for GNU compiler, for IBM S/390
1916 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
1917 - 2007 Free Software Foundation, Inc.
1918 + 2007, 2008 Free Software Foundation, Inc.
1919 Contributed by Hartmut Penner (hpenner@××××××.com) and
1920 Ulrich Weigand (uweigand@××××××.com).
1921 + Andreas Krebbel (Andreas.Krebbel@××××××.com)
1922
1923 This file is part of GCC.
1924
1925 @@ -40,6 +41,7 @@
1926 PROCESSOR_2064_Z900,
1927 PROCESSOR_2084_Z990,
1928 PROCESSOR_2094_Z9_109,
1929 + PROCESSOR_2097_Z10,
1930 PROCESSOR_max
1931 };
1932
1933 @@ -51,7 +53,8 @@
1934 PF_ZARCH = 2,
1935 PF_LONG_DISPLACEMENT = 4,
1936 PF_EXTIMM = 8,
1937 - PF_DFP = 16
1938 + PF_DFP = 16,
1939 + PF_Z10 = 32
1940 };
1941
1942 extern enum processor_type s390_tune;
1943 @@ -60,6 +63,10 @@
1944 extern enum processor_type s390_arch;
1945 extern enum processor_flags s390_arch_flags;
1946
1947 +/* These flags indicate that the generated code should run on a cpu
1948 + providing the respective hardware facility regardless of the
1949 + current cpu mode (ESA or z/Architecture). */
1950 +
1951 #define TARGET_CPU_IEEE_FLOAT \
1952 (s390_arch_flags & PF_IEEE_FLOAT)
1953 #define TARGET_CPU_ZARCH \
1954 @@ -70,13 +77,21 @@
1955 (s390_arch_flags & PF_EXTIMM)
1956 #define TARGET_CPU_DFP \
1957 (s390_arch_flags & PF_DFP)
1958 +#define TARGET_CPU_Z10 \
1959 + (s390_arch_flags & PF_Z10)
1960
1961 +/* These flags indicate that the generated code should run on a cpu
1962 + providing the respective hardware facility when run in
1963 + z/Architecture mode. */
1964 +
1965 #define TARGET_LONG_DISPLACEMENT \
1966 (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT)
1967 #define TARGET_EXTIMM \
1968 (TARGET_ZARCH && TARGET_CPU_EXTIMM)
1969 #define TARGET_DFP \
1970 - (TARGET_ZARCH && TARGET_CPU_DFP)
1971 + (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT)
1972 +#define TARGET_Z10 \
1973 + (TARGET_ZARCH && TARGET_CPU_Z10)
1974
1975 /* Run-time target specification. */
1976
1977 @@ -485,11 +500,14 @@
1978 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1979 s390_preferred_reload_class ((X), (CLASS))
1980
1981 -/* We need secondary memory to move data between GPRs and FPRs. */
1982 +/* We need secondary memory to move data between GPRs and FPRs. With
1983 + DFP the ldgr lgdr instructions are available. But these
1984 + instructions do not handle GPR pairs so it is not possible for 31
1985 + bit. */
1986 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1987 ((CLASS1) != (CLASS2) \
1988 && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS) \
1989 - && (!TARGET_DFP || GET_MODE_SIZE (MODE) != 8))
1990 + && (!TARGET_DFP || !TARGET_64BIT || GET_MODE_SIZE (MODE) != 8))
1991
1992 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit
1993 because the movsi and movsf patterns don't handle r/f moves. */
1994 @@ -688,6 +706,13 @@
1995 /* Maximum number of registers that can appear in a valid memory address. */
1996 #define MAX_REGS_PER_ADDRESS 2
1997
1998 +/* This definition replaces the formerly used 'm' constraint with a
1999 +different constraint letter in order to avoid changing semantics of
2000 +the 'm' constraint when accepting new address formats in
2001 +legitimate_address_p. The constraint letter defined here must not be
2002 +used in insn definitions or inline assemblies. */
2003 +#define TARGET_MEM_CONSTRAINT 'e'
2004 +
2005 /* S/390 has no mode dependent addresses. */
2006 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
2007
2008 @@ -954,7 +979,12 @@
2009 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1)
2010
2011 /* Machine-specific symbol_ref flags. */
2012 -#define SYMBOL_FLAG_ALIGN1 (SYMBOL_FLAG_MACH_DEP << 0)
2013 +#define SYMBOL_FLAG_ALIGN1 (SYMBOL_FLAG_MACH_DEP << 0)
2014 +#define SYMBOL_REF_ALIGN1_P(X) \
2015 + ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN1))
2016 +#define SYMBOL_FLAG_NOT_NATURALLY_ALIGNED (SYMBOL_FLAG_MACH_DEP << 1)
2017 +#define SYMBOL_REF_NOT_NATURALLY_ALIGNED_P(X) \
2018 + ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_NOT_NATURALLY_ALIGNED))
2019
2020 /* Check whether integer displacement is in range. */
2021 #define DISP_IN_RANGE(d) \
2022 Index: gcc/config/s390/2084.md
2023 ===================================================================
2024 --- gcc/config/s390/2084.md (revision 141434)
2025 +++ gcc/config/s390/2084.md (working copy)
2026 @@ -243,7 +243,7 @@
2027
2028 (define_insn_reservation "x_itof" 7
2029 (and (eq_attr "cpu" "z990,z9_109")
2030 - (eq_attr "type" "itof"))
2031 + (eq_attr "type" "itoftf,itofdf,itofsf"))
2032 "x_e1_t*3,x-wr-fp")
2033
2034 (define_bypass 1 "x_fsimpdf" "x_fstoredf")
2035 Index: gcc/config/s390/s390.md
2036 ===================================================================
2037 --- gcc/config/s390/s390.md (revision 141434)
2038 +++ gcc/config/s390/s390.md (working copy)
2039 @@ -1,8 +1,9 @@
2040 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2041 -;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
2042 +;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
2043 ;; Free Software Foundation, Inc.
2044 ;; Contributed by Hartmut Penner (hpenner@××××××.com) and
2045 -;; Ulrich Weigand (uweigand@××××××.com).
2046 +;; Ulrich Weigand (uweigand@××××××.com) and
2047 +;; Andreas Krebbel (Andreas.Krebbel@××××××.com)
2048
2049 ;; This file is part of GCC.
2050
2051 @@ -38,6 +39,7 @@
2052 ;; %Y: print shift count operand.
2053 ;;
2054 ;; %b: print integer X as if it's an unsigned byte.
2055 +;; %c: print integer X as if it's an signed byte.
2056 ;; %x: print integer X as if it's an unsigned halfword.
2057 ;; %h: print integer X as if it's a signed halfword.
2058 ;; %i: print the first nonzero HImode part of X.
2059 @@ -189,7 +191,7 @@
2060 ;; Used to determine defaults for length and other attribute values.
2061
2062 (define_attr "op_type"
2063 - "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR"
2064 + "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
2065 (const_string "NN"))
2066
2067 ;; Instruction type attribute used for scheduling.
2068 @@ -200,8 +202,12 @@
2069 branch,jsr,fsimptf,fsimpdf,fsimpsf,
2070 floadtf,floaddf,floadsf,fstoredf,fstoresf,
2071 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
2072 - ftoi,itof,fsqrttf,fsqrtdf,fsqrtsf,
2073 - ftrunctf,ftruncdf,other"
2074 + ftoi,fsqrttf,fsqrtdf,fsqrtsf,
2075 + ftrunctf,ftruncdf, ftruncsd, ftruncdd,
2076 + itoftf, itofdf, itofsf, itofdd, itoftd,
2077 + fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
2078 + fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
2079 + ftoidfp, other"
2080 (cond [(eq_attr "op_type" "NN") (const_string "other")
2081 (eq_attr "op_type" "SS") (const_string "cs")]
2082 (const_string "integer")))
2083 @@ -215,11 +221,36 @@
2084 (const_string "reg")
2085 (const_string "agen")))
2086
2087 +;; Properties concerning Z10 execution grouping and value forwarding.
2088 +;; z10_super: instruction is superscalar.
2089 +;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
2090 +;; z10_fwd: The instruction reads the value of an operand and stores it into a
2091 +;; target register. It can forward this value to a second instruction that reads
2092 +;; the same register if that second instruction is issued in the same group.
2093 +;; z10_rec: The instruction is in the T pipeline and reads a register. If the
2094 +;; instruction in the S pipe writes to the register, then the T instruction
2095 +;; can immediately read the new value.
2096 +;; z10_fr: union of Z10_fwd and z10_rec.
2097 +;; z10_c: second operand of instruction is a register and read with complemented bits.
2098 +;; z10_cobra: its a compare and branch instruction
2099 +;;
2100 +;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
2101 +
2102 +
2103 +(define_attr "z10prop" "none,
2104 + z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
2105 + z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
2106 + z10_rec,
2107 + z10_fr, z10_fr_A3, z10_fr_E1,
2108 + z10_c, z10_cobra"
2109 + (const_string "none"))
2110 +
2111 +
2112 ;; Length in bytes.
2113
2114 (define_attr "length" ""
2115 - (cond [(eq_attr "op_type" "E,RR") (const_int 2)
2116 - (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI") (const_int 4)]
2117 + (cond [(eq_attr "op_type" "E,RR") (const_int 2)
2118 + (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
2119 (const_int 6)))
2120
2121
2122 @@ -228,9 +259,41 @@
2123 ;; distinguish between g5 and g6, but there are differences between the two
2124 ;; CPUs could in theory be modeled.
2125
2126 -(define_attr "cpu" "g5,g6,z900,z990,z9_109"
2127 +(define_attr "cpu" "g5,g6,z900,z990,z9_109,z10"
2128 (const (symbol_ref "s390_tune")))
2129
2130 +(define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10"
2131 + (const_string "standard"))
2132 +
2133 +(define_attr "enabled" ""
2134 + (cond [(eq_attr "cpu_facility" "standard")
2135 + (const_int 1)
2136 +
2137 + (and (eq_attr "cpu_facility" "ieee")
2138 + (ne (symbol_ref "TARGET_CPU_IEEE_FLOAT") (const_int 0)))
2139 + (const_int 1)
2140 +
2141 + (and (eq_attr "cpu_facility" "zarch")
2142 + (ne (symbol_ref "TARGET_ZARCH") (const_int 0)))
2143 + (const_int 1)
2144 +
2145 + (and (eq_attr "cpu_facility" "longdisp")
2146 + (ne (symbol_ref "TARGET_LONG_DISPLACEMENT") (const_int 0)))
2147 + (const_int 1)
2148 +
2149 + (and (eq_attr "cpu_facility" "extimm")
2150 + (ne (symbol_ref "TARGET_EXTIMM") (const_int 0)))
2151 + (const_int 1)
2152 +
2153 + (and (eq_attr "cpu_facility" "dfp")
2154 + (ne (symbol_ref "TARGET_DFP") (const_int 0)))
2155 + (const_int 1)
2156 +
2157 + (and (eq_attr "cpu_facility" "z10")
2158 + (ne (symbol_ref "TARGET_Z10") (const_int 0)))
2159 + (const_int 1)]
2160 + (const_int 0)))
2161 +
2162 ;; Pipeline description for z900. For lack of anything better,
2163 ;; this description is also used for the g5 and g6.
2164 (include "2064.md")
2165 @@ -238,6 +301,9 @@
2166 ;; Pipeline description for z990, z9-109 and z9-ec.
2167 (include "2084.md")
2168
2169 +;; Pipeline description for z10
2170 +(include "2097.md")
2171 +
2172 ;; Predicates
2173 (include "predicates.md")
2174
2175 @@ -254,6 +320,7 @@
2176 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
2177 (SD "TARGET_HARD_DFP")])
2178 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
2179 +(define_mode_iterator FPALL [TF DF SF TD DD SD])
2180 (define_mode_iterator BFP [TF DF SF])
2181 (define_mode_iterator DFP [TD DD])
2182 (define_mode_iterator DFP_ALL [TD DD SD])
2183 @@ -283,6 +350,7 @@
2184 ;; This mode iterator allows the integer patterns to be defined from the
2185 ;; same template.
2186 (define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI])
2187 +(define_mode_iterator INTALL [TI DI SI HI QI])
2188
2189 ;; This iterator allows to unify all 'bCOND' expander patterns.
2190 (define_code_iterator COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
2191 @@ -352,12 +420,6 @@
2192 ;; modes and to an empty string for bfp modes.
2193 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
2194
2195 -;; Although it is imprecise for z9-ec we handle all dfp instructions like
2196 -;; bfp regarding the pipeline description.
2197 -(define_mode_attr bfp [(TF "tf") (DF "df") (SF "sf")
2198 - (TD "tf") (DD "df") (SD "sf")])
2199 -
2200 -
2201 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
2202 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
2203 ;; version only operates on one register.
2204 @@ -367,13 +429,13 @@
2205 ;; version only operates on one register. The DImode version needs an additional
2206 ;; register for the assembler output.
2207 (define_mode_attr 1 [(DI "%1,") (SI "")])
2208 -
2209 -;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
2210 +
2211 +;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
2212 ;; 'ashift' and "srdl" in 'lshiftrt'.
2213 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
2214
2215 ;; In SHIFT templates, this attribute holds the correct standard name for the
2216 -;; pattern itself and the corresponding function calls.
2217 +;; pattern itself and the corresponding function calls.
2218 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
2219
2220 ;; This attribute handles differences in the instruction 'type' and will result
2221 @@ -425,7 +487,6 @@
2222 ;; Maximum unsigned integer that fits in MODE.
2223 (define_mode_attr max_uint [(HI "65535") (QI "255")])
2224
2225 -
2226 ;;
2227 ;;- Compare instructions.
2228 ;;
2229 @@ -464,7 +525,8 @@
2230 "@
2231 tm\t%S0,%b1
2232 tmy\t%S0,%b1"
2233 - [(set_attr "op_type" "SI,SIY")])
2234 + [(set_attr "op_type" "SI,SIY")
2235 + (set_attr "z10prop" "z10_super,z10_super")])
2236
2237 (define_insn "*tmdi_reg"
2238 [(set (reg CC_REGNUM)
2239 @@ -480,7 +542,8 @@
2240 tmhl\t%0,%i1
2241 tmlh\t%0,%i1
2242 tmll\t%0,%i1"
2243 - [(set_attr "op_type" "RI")])
2244 + [(set_attr "op_type" "RI")
2245 + (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
2246
2247 (define_insn "*tmsi_reg"
2248 [(set (reg CC_REGNUM)
2249 @@ -511,19 +574,25 @@
2250
2251 (define_insn "*tstdi_sign"
2252 [(set (reg CC_REGNUM)
2253 - (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
2254 - (const_int 32)) (const_int 32))
2255 - (match_operand:DI 1 "const0_operand" "")))
2256 - (set (match_operand:DI 2 "register_operand" "=d")
2257 + (compare
2258 + (ashiftrt:DI
2259 + (ashift:DI
2260 + (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
2261 + (const_int 32)) (const_int 32))
2262 + (match_operand:DI 1 "const0_operand" "")))
2263 + (set (match_operand:DI 2 "register_operand" "=d,d")
2264 (sign_extend:DI (match_dup 0)))]
2265 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
2266 - "ltgfr\t%2,%0"
2267 - [(set_attr "op_type" "RRE")])
2268 + "ltgfr\t%2,%0
2269 + ltgf\t%2,%0"
2270 + [(set_attr "op_type" "RRE,RXY")
2271 + (set_attr "cpu_facility" "*,z10")
2272 + (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
2273
2274 ; ltr, lt, ltgr, ltg
2275 (define_insn "*tst<mode>_extimm"
2276 [(set (reg CC_REGNUM)
2277 - (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
2278 + (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
2279 (match_operand:GPR 1 "const0_operand" "")))
2280 (set (match_operand:GPR 2 "register_operand" "=d,d")
2281 (match_dup 0))]
2282 @@ -531,19 +600,21 @@
2283 "@
2284 lt<g>r\t%2,%0
2285 lt<g>\t%2,%0"
2286 - [(set_attr "op_type" "RR<E>,RXY")])
2287 + [(set_attr "op_type" "RR<E>,RXY")
2288 + (set_attr "z10prop" "z10_fr_E1,z10_fr_A3") ])
2289
2290 ; ltr, lt, ltgr, ltg
2291 (define_insn "*tst<mode>_cconly_extimm"
2292 [(set (reg CC_REGNUM)
2293 - (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
2294 + (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
2295 (match_operand:GPR 1 "const0_operand" "")))
2296 (clobber (match_scratch:GPR 2 "=X,d"))]
2297 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
2298 "@
2299 lt<g>r\t%0,%0
2300 lt<g>\t%2,%0"
2301 - [(set_attr "op_type" "RR<E>,RXY")])
2302 + [(set_attr "op_type" "RR<E>,RXY")
2303 + (set_attr "z10prop" "z10_fr_E1,z10_fr_A3")])
2304
2305 (define_insn "*tstdi"
2306 [(set (reg CC_REGNUM)
2307 @@ -553,7 +624,8 @@
2308 (match_dup 0))]
2309 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
2310 "ltgr\t%2,%0"
2311 - [(set_attr "op_type" "RRE")])
2312 + [(set_attr "op_type" "RRE")
2313 + (set_attr "z10prop" "z10_fr_E1")])
2314
2315 (define_insn "*tstsi"
2316 [(set (reg CC_REGNUM)
2317 @@ -566,7 +638,8 @@
2318 ltr\t%2,%0
2319 icm\t%2,15,%S0
2320 icmy\t%2,15,%S0"
2321 - [(set_attr "op_type" "RR,RS,RSY")])
2322 + [(set_attr "op_type" "RR,RS,RSY")
2323 + (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
2324
2325 (define_insn "*tstsi_cconly"
2326 [(set (reg CC_REGNUM)
2327 @@ -578,7 +651,8 @@
2328 ltr\t%0,%0
2329 icm\t%2,15,%S0
2330 icmy\t%2,15,%S0"
2331 - [(set_attr "op_type" "RR,RS,RSY")])
2332 + [(set_attr "op_type" "RR,RS,RSY")
2333 + (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
2334
2335 (define_insn "*tstdi_cconly_31"
2336 [(set (reg CC_REGNUM)
2337 @@ -596,7 +670,8 @@
2338 (match_operand:GPR 1 "const0_operand" "")))]
2339 "s390_match_ccmode(insn, CCSmode)"
2340 "lt<g>r\t%0,%0"
2341 - [(set_attr "op_type" "RR<E>")])
2342 + [(set_attr "op_type" "RR<E>")
2343 + (set_attr "z10prop" "z10_fr_E1")])
2344
2345 ; tst(hi|qi) instruction pattern(s).
2346
2347 @@ -611,7 +686,8 @@
2348 icm\t%2,<icm_lo>,%S0
2349 icmy\t%2,<icm_lo>,%S0
2350 tml\t%0,<max_uint>"
2351 - [(set_attr "op_type" "RS,RSY,RI")])
2352 + [(set_attr "op_type" "RS,RSY,RI")
2353 + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
2354
2355 (define_insn "*tsthiCCT_cconly"
2356 [(set (reg CC_REGNUM)
2357 @@ -623,7 +699,8 @@
2358 icm\t%2,3,%S0
2359 icmy\t%2,3,%S0
2360 tml\t%0,65535"
2361 - [(set_attr "op_type" "RS,RSY,RI")])
2362 + [(set_attr "op_type" "RS,RSY,RI")
2363 + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
2364
2365 (define_insn "*tstqiCCT_cconly"
2366 [(set (reg CC_REGNUM)
2367 @@ -634,7 +711,8 @@
2368 cli\t%S0,0
2369 cliy\t%S0,0
2370 tml\t%0,255"
2371 - [(set_attr "op_type" "SI,SIY,RI")])
2372 + [(set_attr "op_type" "SI,SIY,RI")
2373 + (set_attr "z10prop" "z10_super,z10_super,*")])
2374
2375 (define_insn "*tst<mode>"
2376 [(set (reg CC_REGNUM)
2377 @@ -646,7 +724,8 @@
2378 "@
2379 icm\t%2,<icm_lo>,%S0
2380 icmy\t%2,<icm_lo>,%S0"
2381 - [(set_attr "op_type" "RS,RSY")])
2382 + [(set_attr "op_type" "RS,RSY")
2383 + (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2384
2385 (define_insn "*tst<mode>_cconly"
2386 [(set (reg CC_REGNUM)
2387 @@ -657,7 +736,8 @@
2388 "@
2389 icm\t%2,<icm_lo>,%S0
2390 icmy\t%2,<icm_lo>,%S0"
2391 - [(set_attr "op_type" "RS,RSY")])
2392 + [(set_attr "op_type" "RS,RSY")
2393 + (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2394
2395
2396 ; Compare (equality) instructions
2397 @@ -665,7 +745,7 @@
2398 (define_insn "*cmpdi_cct"
2399 [(set (reg CC_REGNUM)
2400 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
2401 - (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))]
2402 + (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
2403 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
2404 "@
2405 cgr\t%0,%1
2406 @@ -673,7 +753,8 @@
2407 cgfi\t%0,%1
2408 cg\t%0,%1
2409 #"
2410 - [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")])
2411 + [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
2412 + (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
2413
2414 (define_insn "*cmpsi_cct"
2415 [(set (reg CC_REGNUM)
2416 @@ -687,97 +768,174 @@
2417 c\t%0,%1
2418 cy\t%0,%1
2419 #"
2420 - [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")])
2421 + [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
2422 + (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super,z10_super,*")])
2423
2424 -
2425 ; Compare (signed) instructions
2426
2427 (define_insn "*cmpdi_ccs_sign"
2428 [(set (reg CC_REGNUM)
2429 - (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
2430 - (match_operand:DI 0 "register_operand" "d,d")))]
2431 + (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
2432 + "d,RT,b"))
2433 + (match_operand:DI 0 "register_operand" "d, d,d")))]
2434 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
2435 "@
2436 cgfr\t%0,%1
2437 - cgf\t%0,%1"
2438 - [(set_attr "op_type" "RRE,RXY")])
2439 + cgf\t%0,%1
2440 + cgfrl\t%0,%1"
2441 + [(set_attr "op_type" "RRE,RXY,RIL")
2442 + (set_attr "z10prop" "z10_c,*,*")
2443 + (set_attr "type" "*,*,larl")])
2444
2445 +
2446 +
2447 (define_insn "*cmpsi_ccs_sign"
2448 [(set (reg CC_REGNUM)
2449 - (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
2450 - (match_operand:SI 0 "register_operand" "d,d")))]
2451 + (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
2452 + (match_operand:SI 0 "register_operand" "d,d,d")))]
2453 "s390_match_ccmode(insn, CCSRmode)"
2454 "@
2455 ch\t%0,%1
2456 - chy\t%0,%1"
2457 - [(set_attr "op_type" "RX,RXY")])
2458 + chy\t%0,%1
2459 + chrl\t%0,%1"
2460 + [(set_attr "op_type" "RX,RXY,RIL")
2461 + (set_attr "cpu_facility" "*,*,z10")
2462 + (set_attr "type" "*,*,larl")])
2463
2464 -; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg
2465 +(define_insn "*cmphi_ccs_z10"
2466 + [(set (reg CC_REGNUM)
2467 + (compare (match_operand:HI 0 "s_operand" "Q")
2468 + (match_operand:HI 1 "immediate_operand" "K")))]
2469 + "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
2470 + "chhsi\t%0,%1"
2471 + [(set_attr "op_type" "SIL")])
2472 +
2473 +(define_insn "*cmpdi_ccs_signhi_rl"
2474 + [(set (reg CC_REGNUM)
2475 + (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
2476 + (match_operand:GPR 0 "register_operand" "d,d")))]
2477 + "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
2478 + "@
2479 + cgh\t%0,%1
2480 + cghrl\t%0,%1"
2481 + [(set_attr "op_type" "RXY,RIL")
2482 + (set_attr "type" "*,larl")])
2483 +
2484 +; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
2485 (define_insn "*cmp<mode>_ccs"
2486 [(set (reg CC_REGNUM)
2487 - (compare (match_operand:GPR 0 "register_operand" "d,d,d,d,d")
2488 - (match_operand:GPR 1 "general_operand" "d,K,Os,R,T")))]
2489 + (compare (match_operand:GPR 0 "nonimmediate_operand"
2490 + "d,d,Q, d,d,d,d")
2491 + (match_operand:GPR 1 "general_operand"
2492 + "d,K,K,Os,R,T,b")))]
2493 "s390_match_ccmode(insn, CCSmode)"
2494 "@
2495 c<g>r\t%0,%1
2496 c<g>hi\t%0,%h1
2497 + c<g>hsi\t%0,%h1
2498 c<g>fi\t%0,%1
2499 c<g>\t%0,%1
2500 - c<y>\t%0,%1"
2501 - [(set_attr "op_type" "RR<E>,RI,RIL,RX<Y>,RXY")])
2502 + c<y>\t%0,%1
2503 + c<g>rl\t%0,%1"
2504 + [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
2505 + (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
2506 + (set_attr "type" "*,*,*,*,*,*,larl")
2507 + (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
2508
2509
2510 ; Compare (unsigned) instructions
2511
2512 +(define_insn "*cmpsi_ccu_zerohi_rlsi"
2513 + [(set (reg CC_REGNUM)
2514 + (compare (zero_extend:SI (mem:HI (match_operand:SI 1
2515 + "larl_operand" "X")))
2516 + (match_operand:SI 0 "register_operand" "d")))]
2517 + "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
2518 + "clhrl\t%0,%1"
2519 + [(set_attr "op_type" "RIL")
2520 + (set_attr "type" "larl")])
2521 +
2522 +; clhrl, clghrl
2523 +(define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
2524 + [(set (reg CC_REGNUM)
2525 + (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
2526 + "larl_operand" "X")))
2527 + (match_operand:GPR 0 "register_operand" "d")))]
2528 + "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
2529 + "cl<g>hrl\t%0,%1"