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commit: 16261751801f082e769f9ef9aa70a2b84cc459ae |
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Author: Andreas K. Hüttel <dilfridge <AT> gentoo <DOT> org> |
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AuthorDate: Sun Feb 27 15:56:12 2022 +0000 |
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Commit: Andreas K. Hüttel <dilfridge <AT> gentoo <DOT> org> |
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CommitDate: Sun Feb 27 15:56:12 2022 +0000 |
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URL: https://gitweb.gentoo.org/proj/releng.git/commit/?id=16261751 |
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|
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Fix upload filename |
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|
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Signed-off-by: Andreas K. Hüttel <dilfridge <AT> gentoo.org> |
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|
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tools/catalyst-auto-qemu-riscv.conf | 2 +- |
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1 file changed, 1 insertion(+), 1 deletion(-) |
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|
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diff --git a/tools/catalyst-auto-qemu-riscv.conf b/tools/catalyst-auto-qemu-riscv.conf |
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index 6af25e4b..0bf8f877 100644 |
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--- a/tools/catalyst-auto-qemu-riscv.conf |
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+++ b/tools/catalyst-auto-qemu-riscv.conf |
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@@ -57,7 +57,7 @@ post_build() { |
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;; |
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stage3*musl.spec) |
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pushd "${BUILD_SRCDIR_BASE}/builds/musl" >/dev/null |
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- upload stage3-rv64_$(echo ${spec}|sed -e 's:^stage3-::g' -e 's:\.spec$::g')-${TIMESTAMP}*.xz* |
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+ upload stage3-rv64_$(echo ${spec}|sed -e 's:^stage3-::g' -e 's:-:_:g' -e 's:\.spec$::g')-${TIMESTAMP}*.xz* |
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popd >/dev/null |
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;; |
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*) |
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