Gentoo Archives: gentoo-commits

From: Mike Pagano <mpagano@g.o>
To: gentoo-commits@l.g.o
Subject: [gentoo-commits] proj/linux-patches:4.20 commit in: /
Date: Fri, 22 Feb 2019 15:20:25
Message-Id: 1550848733.ee51be5f1cb825aa5845a9badc02fdc43e501c96.mpagano@gentoo
1 commit: ee51be5f1cb825aa5845a9badc02fdc43e501c96
2 Author: Mike Pagano <mpagano <AT> gentoo <DOT> org>
3 AuthorDate: Fri Feb 22 15:18:53 2019 +0000
4 Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org>
5 CommitDate: Fri Feb 22 15:18:53 2019 +0000
6 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=ee51be5f
7
8 proj/linux-patches: Add fixed cpu opt. patch for gcc >= v8
9
10 Signed-off-by: Mike Pagano <mpagano <AT> gentoo.org>
11
12 0000_README | 4 +
13 5011_enable-cpu-optimizations-for-gcc8.patch | 569 +++++++++++++++++++++++++++
14 2 files changed, 573 insertions(+)
15
16 diff --git a/0000_README b/0000_README
17 index b93c0f3..068574e 100644
18 --- a/0000_README
19 +++ b/0000_README
20 @@ -114,3 +114,7 @@ Desc: Add Gentoo Linux support config settings and defaults.
21 Patch: 5010_enable-additional-cpu-optimizations-for-gcc-4.9.patch
22 From: https://github.com/graysky2/kernel_gcc_patch/
23 Desc: Kernel patch enables gcc >= v4.13 optimizations for additional CPUs.
24 +
25 +Patch: 5011_enable-cpu-optimizations-for-gcc8.patch
26 +From: https://github.com/graysky2/kernel_gcc_patch/
27 +Desc: Kernel patch for >= gccv8 enables kernel >= v4.13 optimizations for additional CPUs.
28
29 diff --git a/5011_enable-cpu-optimizations-for-gcc8.patch b/5011_enable-cpu-optimizations-for-gcc8.patch
30 new file mode 100644
31 index 0000000..bfd2065
32 --- /dev/null
33 +++ b/5011_enable-cpu-optimizations-for-gcc8.patch
34 @@ -0,0 +1,569 @@
35 +WARNING
36 +This patch works with gcc versions 8.1+ and with kernel version 4.13+ and should
37 +NOT be applied when compiling on older versions of gcc due to key name changes
38 +of the march flags introduced with the version 4.9 release of gcc.[1]
39 +
40 +Use the older version of this patch hosted on the same github for older
41 +versions of gcc.
42 +
43 +FEATURES
44 +This patch adds additional CPU options to the Linux kernel accessible under:
45 + Processor type and features --->
46 + Processor family --->
47 +
48 +The expanded microarchitectures include:
49 +* AMD Improved K8-family
50 +* AMD K10-family
51 +* AMD Family 10h (Barcelona)
52 +* AMD Family 14h (Bobcat)
53 +* AMD Family 16h (Jaguar)
54 +* AMD Family 15h (Bulldozer)
55 +* AMD Family 15h (Piledriver)
56 +* AMD Family 15h (Steamroller)
57 +* AMD Family 15h (Excavator)
58 +* AMD Family 17h (Zen)
59 +* Intel Silvermont low-power processors
60 +* Intel 1st Gen Core i3/i5/i7 (Nehalem)
61 +* Intel 1.5 Gen Core i3/i5/i7 (Westmere)
62 +* Intel 2nd Gen Core i3/i5/i7 (Sandybridge)
63 +* Intel 3rd Gen Core i3/i5/i7 (Ivybridge)
64 +* Intel 4th Gen Core i3/i5/i7 (Haswell)
65 +* Intel 5th Gen Core i3/i5/i7 (Broadwell)
66 +* Intel 6th Gen Core i3/i5/i7 (Skylake)
67 +* Intel 6th Gen Core i7/i9 (Skylake X)
68 +* Intel 8th Gen Core i3/i5/i7 (Cannon Lake)
69 +* Intel 8th Gen Core i7/i9 (Ice Lake)
70 +
71 +It also offers to compile passing the 'native' option which, "selects the CPU
72 +to generate code for at compilation time by determining the processor type of
73 +the compiling machine. Using -march=native enables all instruction subsets
74 +supported by the local machine and will produce code optimized for the local
75 +machine under the constraints of the selected instruction set."[3]
76 +
77 +MINOR NOTES
78 +This patch also changes 'atom' to 'bonnell' in accordance with the gcc v4.9
79 +changes. Note that upstream is using the deprecated 'match=atom' flags when I
80 +believe it should use the newer 'march=bonnell' flag for atom processors.[2]
81 +
82 +It is not recommended to compile on Atom-CPUs with the 'native' option.[4] The
83 +recommendation is to use the 'atom' option instead.
84 +
85 +BENEFITS
86 +Small but real speed increases are measurable using a make endpoint comparing
87 +a generic kernel to one built with one of the respective microarchs.
88 +
89 +See the following experimental evidence supporting this statement:
90 +https://github.com/graysky2/kernel_gcc_patch
91 +
92 +REQUIREMENTS
93 +linux version >=4.20
94 +gcc version >=8.1
95 +
96 +ACKNOWLEDGMENTS
97 +This patch builds on the seminal work by Jeroen.[5]
98 +
99 +REFERENCES
100 +1. https://gcc.gnu.org/gcc-4.9/changes.html
101 +2. https://bugzilla.kernel.org/show_bug.cgi?id=77461
102 +3. https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
103 +4. https://github.com/graysky2/kernel_gcc_patch/issues/15
104 +5. http://www.linuxforge.net/docs/linux/linux-gcc.php
105 +
106 +--- a/arch/x86/Makefile_32.cpu 2019-02-22 09:22:03.426937735 -0500
107 ++++ b/arch/x86/Makefile_32.cpu 2019-02-22 09:37:58.680968580 -0500
108 +@@ -23,7 +23,18 @@ cflags-$(CONFIG_MK6) += -march=k6
109 + # Please note, that patches that add -march=athlon-xp and friends are pointless.
110 + # They make zero difference whatsosever to performance at this time.
111 + cflags-$(CONFIG_MK7) += -march=athlon
112 ++cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native)
113 + cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8,-march=athlon)
114 ++cflags-$(CONFIG_MK8SSE3) += $(call cc-option,-march=k8-sse3,-march=athlon)
115 ++cflags-$(CONFIG_MK10) += $(call cc-option,-march=amdfam10,-march=athlon)
116 ++cflags-$(CONFIG_MBARCELONA) += $(call cc-option,-march=barcelona,-march=athlon)
117 ++cflags-$(CONFIG_MBOBCAT) += $(call cc-option,-march=btver1,-march=athlon)
118 ++cflags-$(CONFIG_MJAGUAR) += $(call cc-option,-march=btver2,-march=athlon)
119 ++cflags-$(CONFIG_MBULLDOZER) += $(call cc-option,-march=bdver1,-march=athlon)
120 ++cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-march=bdver2,-march=athlon)
121 ++cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-march=bdver3,-march=athlon)
122 ++cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4,-march=athlon)
123 ++cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1,-march=athlon)
124 + cflags-$(CONFIG_MCRUSOE) += -march=i686 -falign-functions=0 -falign-jumps=0 -falign-loops=0
125 + cflags-$(CONFIG_MEFFICEON) += -march=i686 $(call tune,pentium3) -falign-functions=0 -falign-jumps=0 -falign-loops=0
126 + cflags-$(CONFIG_MWINCHIPC6) += $(call cc-option,-march=winchip-c6,-march=i586)
127 +@@ -32,9 +43,20 @@ cflags-$(CONFIG_MCYRIXIII) += $(call cc-
128 + cflags-$(CONFIG_MVIAC3_2) += $(call cc-option,-march=c3-2,-march=i686)
129 + cflags-$(CONFIG_MVIAC7) += -march=i686
130 + cflags-$(CONFIG_MCORE2) += -march=i686 $(call tune,core2)
131 +-cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom,$(call cc-option,-march=core2,-march=i686)) \
132 +- $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic))
133 +-
134 ++cflags-$(CONFIG_MNEHALEM) += -march=i686 $(call tune,nehalem)
135 ++cflags-$(CONFIG_MWESTMERE) += -march=i686 $(call tune,westmere)
136 ++cflags-$(CONFIG_MSILVERMONT) += -march=i686 $(call tune,silvermont)
137 ++cflags-$(CONFIG_MSANDYBRIDGE) += -march=i686 $(call tune,sandybridge)
138 ++cflags-$(CONFIG_MIVYBRIDGE) += -march=i686 $(call tune,ivybridge)
139 ++cflags-$(CONFIG_MHASWELL) += -march=i686 $(call tune,haswell)
140 ++cflags-$(CONFIG_MBROADWELL) += -march=i686 $(call tune,broadwell)
141 ++cflags-$(CONFIG_MSKYLAKE) += -march=i686 $(call tune,skylake)
142 ++cflags-$(CONFIG_MSKYLAKEX) += -march=i686 $(call tune,skylake-avx512)
143 ++cflags-$(CONFIG_MCANNONLAKE) += -march=i686 $(call tune,cannonlake)
144 ++cflags-$(CONFIG_MICELAKE) += -march=i686 $(call tune,icelake)
145 ++cflags-$(CONFIG_MATOM) += $(call cc-option,-march=bonnell,$(call cc-option,-march=core2,-march=i686)) \
146 ++ $(call cc-option,-mtune=bonnell,$(call cc-option,-mtune=generic))
147 ++
148 + # AMD Elan support
149 + cflags-$(CONFIG_MELAN) += -march=i486
150 +
151 +--- a/arch/x86/Kconfig.cpu 2019-02-22 09:22:11.576958595 -0500
152 ++++ b/arch/x86/Kconfig.cpu 2019-02-22 09:34:16.490003911 -0500
153 +@@ -116,6 +116,7 @@ config MPENTIUMM
154 + config MPENTIUM4
155 + bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
156 + depends on X86_32
157 ++ select X86_P6_NOP
158 + ---help---
159 + Select this for Intel Pentium 4 chips. This includes the
160 + Pentium 4, Pentium D, P4-based Celeron and Xeon, and
161 +@@ -150,7 +151,7 @@ config MPENTIUM4
162 +
163 +
164 + config MK6
165 +- bool "K6/K6-II/K6-III"
166 ++ bool "AMD K6/K6-II/K6-III"
167 + depends on X86_32
168 + ---help---
169 + Select this for an AMD K6-family processor. Enables use of
170 +@@ -158,7 +159,7 @@ config MK6
171 + flags to GCC.
172 +
173 + config MK7
174 +- bool "Athlon/Duron/K7"
175 ++ bool "AMD Athlon/Duron/K7"
176 + depends on X86_32
177 + ---help---
178 + Select this for an AMD Athlon K7-family processor. Enables use of
179 +@@ -166,11 +167,81 @@ config MK7
180 + flags to GCC.
181 +
182 + config MK8
183 +- bool "Opteron/Athlon64/Hammer/K8"
184 ++ bool "AMD Opteron/Athlon64/Hammer/K8"
185 + ---help---
186 + Select this for an AMD Opteron or Athlon64 Hammer-family processor.
187 + Enables use of some extended instructions, and passes appropriate
188 + optimization flags to GCC.
189 ++config MK8SSE3
190 ++ bool "AMD Opteron/Athlon64/Hammer/K8 with SSE3"
191 ++ ---help---
192 ++ Select this for improved AMD Opteron or Athlon64 Hammer-family processors.
193 ++ Enables use of some extended instructions, and passes appropriate
194 ++ optimization flags to GCC.
195 ++
196 ++config MK10
197 ++ bool "AMD 61xx/7x50/PhenomX3/X4/II/K10"
198 ++ ---help---
199 ++ Select this for an AMD 61xx Eight-Core Magny-Cours, Athlon X2 7x50,
200 ++ Phenom X3/X4/II, Athlon II X2/X3/X4, or Turion II-family processor.
201 ++ Enables use of some extended instructions, and passes appropriate
202 ++ optimization flags to GCC.
203 ++
204 ++config MBARCELONA
205 ++ bool "AMD Barcelona"
206 ++ ---help---
207 ++ Select this for AMD Family 10h Barcelona processors.
208 ++
209 ++ Enables -march=barcelona
210 ++
211 ++config MBOBCAT
212 ++ bool "AMD Bobcat"
213 ++ ---help---
214 ++ Select this for AMD Family 14h Bobcat processors.
215 ++
216 ++ Enables -march=btver1
217 ++
218 ++config MJAGUAR
219 ++ bool "AMD Jaguar"
220 ++ ---help---
221 ++ Select this for AMD Family 16h Jaguar processors.
222 ++
223 ++ Enables -march=btver2
224 ++
225 ++config MBULLDOZER
226 ++ bool "AMD Bulldozer"
227 ++ ---help---
228 ++ Select this for AMD Family 15h Bulldozer processors.
229 ++
230 ++ Enables -march=bdver1
231 ++
232 ++config MPILEDRIVER
233 ++ bool "AMD Piledriver"
234 ++ ---help---
235 ++ Select this for AMD Family 15h Piledriver processors.
236 ++
237 ++ Enables -march=bdver2
238 ++
239 ++config MSTEAMROLLER
240 ++ bool "AMD Steamroller"
241 ++ ---help---
242 ++ Select this for AMD Family 15h Steamroller processors.
243 ++
244 ++ Enables -march=bdver3
245 ++
246 ++config MEXCAVATOR
247 ++ bool "AMD Excavator"
248 ++ ---help---
249 ++ Select this for AMD Family 15h Excavator processors.
250 ++
251 ++ Enables -march=bdver4
252 ++
253 ++config MZEN
254 ++ bool "AMD Zen"
255 ++ ---help---
256 ++ Select this for AMD Family 17h Zen processors.
257 ++
258 ++ Enables -march=znver1
259 +
260 + config MCRUSOE
261 + bool "Crusoe"
262 +@@ -253,6 +324,7 @@ config MVIAC7
263 +
264 + config MPSC
265 + bool "Intel P4 / older Netburst based Xeon"
266 ++ select X86_P6_NOP
267 + depends on X86_64
268 + ---help---
269 + Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
270 +@@ -262,23 +334,126 @@ config MPSC
271 + using the cpu family field
272 + in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.
273 +
274 ++config MATOM
275 ++ bool "Intel Atom"
276 ++ select X86_P6_NOP
277 ++ ---help---
278 ++
279 ++ Select this for the Intel Atom platform. Intel Atom CPUs have an
280 ++ in-order pipelining architecture and thus can benefit from
281 ++ accordingly optimized code. Use a recent GCC with specific Atom
282 ++ support in order to fully benefit from selecting this option.
283 ++
284 + config MCORE2
285 +- bool "Core 2/newer Xeon"
286 ++ bool "Intel Core 2"
287 ++ select X86_P6_NOP
288 ++
289 + ---help---
290 +
291 + Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and
292 + 53xx) CPUs. You can distinguish newer from older Xeons by the CPU
293 + family in /proc/cpuinfo. Newer ones have 6 and older ones 15
294 + (not a typo)
295 ++ Enables -march=core2
296 +
297 +-config MATOM
298 +- bool "Intel Atom"
299 ++config MNEHALEM
300 ++ bool "Intel Nehalem"
301 ++ select X86_P6_NOP
302 + ---help---
303 +
304 +- Select this for the Intel Atom platform. Intel Atom CPUs have an
305 +- in-order pipelining architecture and thus can benefit from
306 +- accordingly optimized code. Use a recent GCC with specific Atom
307 +- support in order to fully benefit from selecting this option.
308 ++ Select this for 1st Gen Core processors in the Nehalem family.
309 ++
310 ++ Enables -march=nehalem
311 ++
312 ++config MWESTMERE
313 ++ bool "Intel Westmere"
314 ++ select X86_P6_NOP
315 ++ ---help---
316 ++
317 ++ Select this for the Intel Westmere formerly Nehalem-C family.
318 ++
319 ++ Enables -march=westmere
320 ++
321 ++config MSILVERMONT
322 ++ bool "Intel Silvermont"
323 ++ select X86_P6_NOP
324 ++ ---help---
325 ++
326 ++ Select this for the Intel Silvermont platform.
327 ++
328 ++ Enables -march=silvermont
329 ++
330 ++config MSANDYBRIDGE
331 ++ bool "Intel Sandy Bridge"
332 ++ select X86_P6_NOP
333 ++ ---help---
334 ++
335 ++ Select this for 2nd Gen Core processors in the Sandy Bridge family.
336 ++
337 ++ Enables -march=sandybridge
338 ++
339 ++config MIVYBRIDGE
340 ++ bool "Intel Ivy Bridge"
341 ++ select X86_P6_NOP
342 ++ ---help---
343 ++
344 ++ Select this for 3rd Gen Core processors in the Ivy Bridge family.
345 ++
346 ++ Enables -march=ivybridge
347 ++
348 ++config MHASWELL
349 ++ bool "Intel Haswell"
350 ++ select X86_P6_NOP
351 ++ ---help---
352 ++
353 ++ Select this for 4th Gen Core processors in the Haswell family.
354 ++
355 ++ Enables -march=haswell
356 ++
357 ++config MBROADWELL
358 ++ bool "Intel Broadwell"
359 ++ select X86_P6_NOP
360 ++ ---help---
361 ++
362 ++ Select this for 5th Gen Core processors in the Broadwell family.
363 ++
364 ++ Enables -march=broadwell
365 ++
366 ++config MSKYLAKE
367 ++ bool "Intel Skylake"
368 ++ select X86_P6_NOP
369 ++ ---help---
370 ++
371 ++ Select this for 6th Gen Core processors in the Skylake family.
372 ++
373 ++ Enables -march=skylake
374 ++
375 ++config MSKYLAKEX
376 ++ bool "Intel Skylake X"
377 ++ select X86_P6_NOP
378 ++ ---help---
379 ++
380 ++ Select this for 6th Gen Core processors in the Skylake X family.
381 ++
382 ++ Enables -march=skylake-avx512
383 ++
384 ++config MCANNONLAKE
385 ++ bool "Intel Cannon Lake"
386 ++ select X86_P6_NOP
387 ++ ---help---
388 ++
389 ++ Select this for 8th Gen Core processors
390 ++
391 ++ Enables -march=cannonlake
392 ++
393 ++config MICELAKE
394 ++ bool "Intel Ice Lake"
395 ++ select X86_P6_NOP
396 ++ ---help---
397 ++
398 ++ Select this for 8th Gen Core processors in the Ice Lake family.
399 ++
400 ++ Enables -march=icelake
401 +
402 + config GENERIC_CPU
403 + bool "Generic-x86-64"
404 +@@ -287,6 +462,19 @@ config GENERIC_CPU
405 + Generic x86-64 CPU.
406 + Run equally well on all x86-64 CPUs.
407 +
408 ++config MNATIVE
409 ++ bool "Native optimizations autodetected by GCC"
410 ++ ---help---
411 ++
412 ++ GCC 4.2 and above support -march=native, which automatically detects
413 ++ the optimum settings to use based on your processor. -march=native
414 ++ also detects and applies additional settings beyond -march specific
415 ++ to your CPU, (eg. -msse4). Unless you have a specific reason not to
416 ++ (e.g. distcc cross-compiling), you should probably be using
417 ++ -march=native rather than anything listed below.
418 ++
419 ++ Enables -march=native
420 ++
421 + endchoice
422 +
423 + config X86_GENERIC
424 +@@ -311,7 +499,7 @@ config X86_INTERNODE_CACHE_SHIFT
425 + config X86_L1_CACHE_SHIFT
426 + int
427 + default "7" if MPENTIUM4 || MPSC
428 +- default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
429 ++ default "6" if MK7 || MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MJAGUAR || MPENTIUMM || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MNATIVE || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
430 + default "4" if MELAN || M486 || MGEODEGX1
431 + default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
432 +
433 +@@ -329,39 +517,40 @@ config X86_ALIGNMENT_16
434 +
435 + config X86_INTEL_USERCOPY
436 + def_bool y
437 +- depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2
438 ++ depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK8SSE3 || MK7 || MEFFICEON || MCORE2 || MK10 || MBARCELONA || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MNATIVE
439 +
440 + config X86_USE_PPRO_CHECKSUM
441 + def_bool y
442 +- depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM
443 ++ depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MK10 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MATOM || MNATIVE
444 +
445 + config X86_USE_3DNOW
446 + def_bool y
447 + depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML
448 +
449 +-#
450 +-# P6_NOPs are a relatively minor optimization that require a family >=
451 +-# 6 processor, except that it is broken on certain VIA chips.
452 +-# Furthermore, AMD chips prefer a totally different sequence of NOPs
453 +-# (which work on all CPUs). In addition, it looks like Virtual PC
454 +-# does not understand them.
455 +-#
456 +-# As a result, disallow these if we're not compiling for X86_64 (these
457 +-# NOPs do work on all x86-64 capable chips); the list of processors in
458 +-# the right-hand clause are the cores that benefit from this optimization.
459 +-#
460 + config X86_P6_NOP
461 +- def_bool y
462 +- depends on X86_64
463 +- depends on (MCORE2 || MPENTIUM4 || MPSC)
464 ++ default n
465 ++ bool "Support for P6_NOPs on Intel chips"
466 ++ depends on (MCORE2 || MPENTIUM4 || MPSC || MATOM || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MNATIVE)
467 ++ ---help---
468 ++ P6_NOPs are a relatively minor optimization that require a family >=
469 ++ 6 processor, except that it is broken on certain VIA chips.
470 ++ Furthermore, AMD chips prefer a totally different sequence of NOPs
471 ++ (which work on all CPUs). In addition, it looks like Virtual PC
472 ++ does not understand them.
473 ++
474 ++ As a result, disallow these if we're not compiling for X86_64 (these
475 ++ NOPs do work on all x86-64 capable chips); the list of processors in
476 ++ the right-hand clause are the cores that benefit from this optimization.
477 +
478 ++ Say Y if you have Intel CPU newer than Pentium Pro, N otherwise.
479 ++
480 + config X86_TSC
481 + def_bool y
482 +- depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64
483 ++ depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MNATIVE || MATOM) || X86_64
484 +
485 + config X86_CMPXCHG64
486 + def_bool y
487 +- depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586TSC || M586MMX || MATOM || MGEODE_LX || MGEODEGX1 || MK6 || MK7 || MK8
488 ++ depends on (MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MJAGUAR || MK7 || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MNATIVE || MATOM || MGEODE_LX)
489 +
490 + # this should be set for all -march=.. options where the compiler
491 + # generates cmov.
492 +--- a/arch/x86/Makefile 2019-02-22 09:21:58.196924367 -0500
493 ++++ b/arch/x86/Makefile 2019-02-22 09:36:27.310577832 -0500
494 +@@ -118,13 +118,46 @@ else
495 + KBUILD_CFLAGS += $(call cc-option,-mskip-rax-setup)
496 +
497 + # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu)
498 ++ cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native)
499 + cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8)
500 ++ cflags-$(CONFIG_MK8SSE3) += $(call cc-option,-march=k8-sse3,-mtune=k8)
501 ++ cflags-$(CONFIG_MK10) += $(call cc-option,-march=amdfam10)
502 ++ cflags-$(CONFIG_MBARCELONA) += $(call cc-option,-march=barcelona)
503 ++ cflags-$(CONFIG_MBOBCAT) += $(call cc-option,-march=btver1)
504 ++ cflags-$(CONFIG_MJAGUAR) += $(call cc-option,-march=btver2)
505 ++ cflags-$(CONFIG_MBULLDOZER) += $(call cc-option,-march=bdver1)
506 ++ cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-march=bdver2)
507 ++ cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-march=bdver3)
508 ++ cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4)
509 ++ cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1)
510 + cflags-$(CONFIG_MPSC) += $(call cc-option,-march=nocona)
511 +
512 + cflags-$(CONFIG_MCORE2) += \
513 +- $(call cc-option,-march=core2,$(call cc-option,-mtune=generic))
514 +- cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom) \
515 +- $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic))
516 ++ $(call cc-option,-march=core2,$(call cc-option,-mtune=core2))
517 ++ cflags-$(CONFIG_MNEHALEM) += \
518 ++ $(call cc-option,-march=nehalem,$(call cc-option,-mtune=nehalem))
519 ++ cflags-$(CONFIG_MWESTMERE) += \
520 ++ $(call cc-option,-march=westmere,$(call cc-option,-mtune=westmere))
521 ++ cflags-$(CONFIG_MSILVERMONT) += \
522 ++ $(call cc-option,-march=silvermont,$(call cc-option,-mtune=silvermont))
523 ++ cflags-$(CONFIG_MSANDYBRIDGE) += \
524 ++ $(call cc-option,-march=sandybridge,$(call cc-option,-mtune=sandybridge))
525 ++ cflags-$(CONFIG_MIVYBRIDGE) += \
526 ++ $(call cc-option,-march=ivybridge,$(call cc-option,-mtune=ivybridge))
527 ++ cflags-$(CONFIG_MHASWELL) += \
528 ++ $(call cc-option,-march=haswell,$(call cc-option,-mtune=haswell))
529 ++ cflags-$(CONFIG_MBROADWELL) += \
530 ++ $(call cc-option,-march=broadwell,$(call cc-option,-mtune=broadwell))
531 ++ cflags-$(CONFIG_MSKYLAKE) += \
532 ++ $(call cc-option,-march=skylake,$(call cc-option,-mtune=skylake))
533 ++ cflags-$(CONFIG_MSKYLAKEX) += \
534 ++ $(call cc-option,-march=skylake-avx512,$(call cc-option,-mtune=skylake-avx512))
535 ++ cflags-$(CONFIG_MCANNONLAKE) += \
536 ++ $(call cc-option,-march=cannonlake,$(call cc-option,-mtune=cannonlake))
537 ++ cflags-$(CONFIG_MICELAKE) += \
538 ++ $(call cc-option,-march=icelake,$(call cc-option,-mtune=icelake))
539 ++ cflags-$(CONFIG_MATOM) += $(call cc-option,-march=bonnell) \
540 ++ $(call cc-option,-mtune=bonnell,$(call cc-option,-mtune=generic))
541 + cflags-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=generic)
542 + KBUILD_CFLAGS += $(cflags-y)
543 +
544 +--- a/arch/x86/include/asm/module.h 2019-02-22 09:22:26.726997480 -0500
545 ++++ b/arch/x86/include/asm/module.h 2019-02-22 09:40:04.231493392 -0500
546 +@@ -25,6 +25,30 @@ struct mod_arch_specific {
547 + #define MODULE_PROC_FAMILY "586MMX "
548 + #elif defined CONFIG_MCORE2
549 + #define MODULE_PROC_FAMILY "CORE2 "
550 ++#elif defined CONFIG_MNATIVE
551 ++#define MODULE_PROC_FAMILY "NATIVE "
552 ++#elif defined CONFIG_MNEHALEM
553 ++#define MODULE_PROC_FAMILY "NEHALEM "
554 ++#elif defined CONFIG_MWESTMERE
555 ++#define MODULE_PROC_FAMILY "WESTMERE "
556 ++#elif defined CONFIG_MSILVERMONT
557 ++#define MODULE_PROC_FAMILY "SILVERMONT "
558 ++#elif defined CONFIG_MSANDYBRIDGE
559 ++#define MODULE_PROC_FAMILY "SANDYBRIDGE "
560 ++#elif defined CONFIG_MIVYBRIDGE
561 ++#define MODULE_PROC_FAMILY "IVYBRIDGE "
562 ++#elif defined CONFIG_MHASWELL
563 ++#define MODULE_PROC_FAMILY "HASWELL "
564 ++#elif defined CONFIG_MBROADWELL
565 ++#define MODULE_PROC_FAMILY "BROADWELL "
566 ++#elif defined CONFIG_MSKYLAKE
567 ++#define MODULE_PROC_FAMILY "SKYLAKE "
568 ++#elif defined CONFIG_MSKYLAKEX
569 ++#define MODULE_PROC_FAMILY "SKYLAKEX "
570 ++#elif defined CONFIG_MCANNONLAKE
571 ++#define MODULE_PROC_FAMILY "CANNONLAKE "
572 ++#elif defined CONFIG_MICELAKE
573 ++#define MODULE_PROC_FAMILY "ICELAKE "
574 + #elif defined CONFIG_MATOM
575 + #define MODULE_PROC_FAMILY "ATOM "
576 + #elif defined CONFIG_M686
577 +@@ -43,6 +67,26 @@ struct mod_arch_specific {
578 + #define MODULE_PROC_FAMILY "K7 "
579 + #elif defined CONFIG_MK8
580 + #define MODULE_PROC_FAMILY "K8 "
581 ++#elif defined CONFIG_MK8SSE3
582 ++#define MODULE_PROC_FAMILY "K8SSE3 "
583 ++#elif defined CONFIG_MK10
584 ++#define MODULE_PROC_FAMILY "K10 "
585 ++#elif defined CONFIG_MBARCELONA
586 ++#define MODULE_PROC_FAMILY "BARCELONA "
587 ++#elif defined CONFIG_MBOBCAT
588 ++#define MODULE_PROC_FAMILY "BOBCAT "
589 ++#elif defined CONFIG_MBULLDOZER
590 ++#define MODULE_PROC_FAMILY "BULLDOZER "
591 ++#elif defined CONFIG_MPILEDRIVER
592 ++#define MODULE_PROC_FAMILY "PILEDRIVER "
593 ++#elif defined CONFIG_MSTEAMROLLER
594 ++#define MODULE_PROC_FAMILY "STEAMROLLER "
595 ++#elif defined CONFIG_MJAGUAR
596 ++#define MODULE_PROC_FAMILY "JAGUAR "
597 ++#elif defined CONFIG_MEXCAVATOR
598 ++#define MODULE_PROC_FAMILY "EXCAVATOR "
599 ++#elif defined CONFIG_MZEN
600 ++#define MODULE_PROC_FAMILY "ZEN "
601 + #elif defined CONFIG_MELAN
602 + #define MODULE_PROC_FAMILY "ELAN "
603 + #elif defined CONFIG_MCRUSOE