1 |
halcy0n 09/04/26 18:17:59 |
2 |
|
3 |
Modified: README.history |
4 |
Added: 78_all_arm-PR37436.patch |
5 |
Log: |
6 |
Releasing patchset with fixes for arm; bug #265367 and bug #261111 |
7 |
|
8 |
Revision Changes Path |
9 |
1.14 src/patchsets/gcc/4.3.2/gentoo/README.history |
10 |
|
11 |
file : http://sources.gentoo.org/viewcvs.py/gentoo/src/patchsets/gcc/4.3.2/gentoo/README.history?rev=1.14&view=markup |
12 |
plain: http://sources.gentoo.org/viewcvs.py/gentoo/src/patchsets/gcc/4.3.2/gentoo/README.history?rev=1.14&content-type=text/plain |
13 |
diff : http://sources.gentoo.org/viewcvs.py/gentoo/src/patchsets/gcc/4.3.2/gentoo/README.history?r1=1.13&r2=1.14 |
14 |
|
15 |
Index: README.history |
16 |
=================================================================== |
17 |
RCS file: /var/cvsroot/gentoo/src/patchsets/gcc/4.3.2/gentoo/README.history,v |
18 |
retrieving revision 1.13 |
19 |
retrieving revision 1.14 |
20 |
diff -u -r1.13 -r1.14 |
21 |
--- README.history 27 Jan 2009 18:42:43 -0000 1.13 |
22 |
+++ README.history 26 Apr 2009 18:17:59 -0000 1.14 |
23 |
@@ -1,3 +1,7 @@ |
24 |
+1.7 26.04.2009 |
25 |
+ + 67_all_gcc43-pr35964.patch |
26 |
+ + 78_all_arm-PR37436.patch |
27 |
+ |
28 |
1.6 27.01.2008 |
29 |
+ 46_all_armel-hilo-union-class.patch |
30 |
+ 47_all_arm-unbreak-armv4t.patch |
31 |
|
32 |
|
33 |
|
34 |
1.1 src/patchsets/gcc/4.3.2/gentoo/78_all_arm-PR37436.patch |
35 |
|
36 |
file : http://sources.gentoo.org/viewcvs.py/gentoo/src/patchsets/gcc/4.3.2/gentoo/78_all_arm-PR37436.patch?rev=1.1&view=markup |
37 |
plain: http://sources.gentoo.org/viewcvs.py/gentoo/src/patchsets/gcc/4.3.2/gentoo/78_all_arm-PR37436.patch?rev=1.1&content-type=text/plain |
38 |
|
39 |
Index: 78_all_arm-PR37436.patch |
40 |
=================================================================== |
41 |
Backport from gcc-4.4 to fix bug #265367 |
42 |
|
43 |
http://gcc.gnu.org/PR37436 |
44 |
|
45 |
Index: gcc/config/arm/arm.c |
46 |
=================================================================== |
47 |
--- gcc/config/arm/arm.c (revision 142777) |
48 |
+++ gcc/config/arm/arm.c (revision 142778) |
49 |
@@ -3844,6 +3844,7 @@ |
50 |
rtx xop1 = XEXP (x, 1); |
51 |
|
52 |
return ((arm_address_register_rtx_p (xop0, strict_p) |
53 |
+ && GET_CODE(xop1) == CONST_INT |
54 |
&& arm_legitimate_index_p (mode, xop1, outer, strict_p)) |
55 |
|| (arm_address_register_rtx_p (xop1, strict_p) |
56 |
&& arm_legitimate_index_p (mode, xop0, outer, strict_p))); |
57 |
Index: gcc/config/arm/predicates.md |
58 |
=================================================================== |
59 |
--- gcc/config/arm/predicates.md (revision 142777) |
60 |
+++ gcc/config/arm/predicates.md (revision 142778) |
61 |
@@ -234,6 +234,10 @@ |
62 |
(match_test "arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND, |
63 |
0)"))) |
64 |
|
65 |
+(define_special_predicate "arm_reg_or_extendqisi_mem_op" |
66 |
+ (ior (match_operand 0 "arm_extendqisi_mem_op") |
67 |
+ (match_operand 0 "s_register_operand"))) |
68 |
+ |
69 |
(define_predicate "power_of_two_operand" |
70 |
(match_code "const_int") |
71 |
{ |
72 |
Index: gcc/config/arm/arm.md |
73 |
=================================================================== |
74 |
--- gcc/config/arm/arm.md (revision 142777) |
75 |
+++ gcc/config/arm/arm.md (revision 142778) |
76 |
@@ -4299,7 +4299,7 @@ |
77 |
|
78 |
(define_expand "extendqihi2" |
79 |
[(set (match_dup 2) |
80 |
- (ashift:SI (match_operand:QI 1 "general_operand" "") |
81 |
+ (ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "") |
82 |
(const_int 24))) |
83 |
(set (match_operand:HI 0 "s_register_operand" "") |
84 |
(ashiftrt:SI (match_dup 2) |
85 |
@@ -4324,7 +4324,7 @@ |
86 |
|
87 |
(define_insn "*arm_extendqihi_insn" |
88 |
[(set (match_operand:HI 0 "s_register_operand" "=r") |
89 |
- (sign_extend:HI (match_operand:QI 1 "memory_operand" "Uq")))] |
90 |
+ (sign_extend:HI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))] |
91 |
"TARGET_ARM && arm_arch4" |
92 |
"ldr%(sb%)\\t%0, %1" |
93 |
[(set_attr "type" "load_byte") |
94 |
@@ -4335,7 +4335,7 @@ |
95 |
|
96 |
(define_expand "extendqisi2" |
97 |
[(set (match_dup 2) |
98 |
- (ashift:SI (match_operand:QI 1 "general_operand" "") |
99 |
+ (ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "") |
100 |
(const_int 24))) |
101 |
(set (match_operand:SI 0 "s_register_operand" "") |
102 |
(ashiftrt:SI (match_dup 2) |
103 |
@@ -4367,7 +4367,7 @@ |
104 |
|
105 |
(define_insn "*arm_extendqisi" |
106 |
[(set (match_operand:SI 0 "s_register_operand" "=r") |
107 |
- (sign_extend:SI (match_operand:QI 1 "memory_operand" "Uq")))] |
108 |
+ (sign_extend:SI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))] |
109 |
"TARGET_ARM && arm_arch4 && !arm_arch6" |
110 |
"ldr%(sb%)\\t%0, %1" |
111 |
[(set_attr "type" "load_byte") |
112 |
@@ -4378,7 +4378,8 @@ |
113 |
|
114 |
(define_insn "*arm_extendqisi_v6" |
115 |
[(set (match_operand:SI 0 "s_register_operand" "=r,r") |
116 |
- (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,Uq")))] |
117 |
+ (sign_extend:SI |
118 |
+ (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "r,Uq")))] |
119 |
"TARGET_ARM && arm_arch6" |
120 |
"@ |
121 |
sxtb%?\\t%0, %1 |