[gentoo-commits] linux-patches r1696 - genpatches-2.6/trunk/2.6.33

[Mike Pagano (mpagano)]

Author: mpagano
Date: 2010-04-27 13:06:02 +0000 (Tue, 27 Apr 2010)
New Revision: 1696

Added:
   genpatches-2.6/trunk/2.6.33/1002_linux-2.6.33.3.patch
Modified:
   genpatches-2.6/trunk/2.6.33/0000_README
Log:
Linux patch 2.6.33.3

Modified: genpatches-2.6/trunk/2.6.33/0000_README
===================================================================
--- genpatches-2.6/trunk/2.6.33/0000_README	2010-04-25 00:23:19 UTC (rev 1695)
+++ genpatches-2.6/trunk/2.6.33/0000_README	2010-04-27 13:06:02 UTC (rev 1696)
@@ -47,6 +47,10 @@
 From:   http://www.kernel.org
 Desc:   Linux 2.6.33.2
 
+Patch:  1002_linux-2.6.33.3.patch
+From:   http://www.kernel.org
+Desc:   Linux 2.6.33.3
+
 Patch:  4100_dm-bbr.patch
 From:   EVMS 2.5.2
 Desc:   Bad block relocation support for LiveCD users

Added: genpatches-2.6/trunk/2.6.33/1002_linux-2.6.33.3.patch
===================================================================
--- genpatches-2.6/trunk/2.6.33/1002_linux-2.6.33.3.patch	                        (rev 0)
+++ genpatches-2.6/trunk/2.6.33/1002_linux-2.6.33.3.patch	2010-04-27 13:06:02 UTC (rev 1696)
@@ -0,0 +1,5184 @@
+diff --git a/Documentation/i2c/busses/i2c-i801 b/Documentation/i2c/busses/i2c-i801
+index 81c0c59..e1bb5b2 100644
+--- a/Documentation/i2c/busses/i2c-i801
++++ b/Documentation/i2c/busses/i2c-i801
+@@ -15,7 +15,8 @@ Supported adapters:
+   * Intel 82801I (ICH9)
+   * Intel EP80579 (Tolapai)
+   * Intel 82801JI (ICH10)
+-  * Intel PCH
++  * Intel 3400/5 Series (PCH)
++  * Intel Cougar Point (PCH)
+    Datasheets: Publicly available at the Intel website
+ 
+ Authors: 
+diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
+index 6b84a04..cbeb6e0 100644
+--- a/arch/arm/boot/compressed/head.S
++++ b/arch/arm/boot/compressed/head.S
+@@ -172,7 +172,7 @@ not_angel:
+ 		adr	r0, LC0
+  ARM(		ldmia	r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp})
+  THUMB(		ldmia	r0, {r1, r2, r3, r4, r5, r6, r11, ip}	)
+- THUMB(		ldr	sp, [r0, #28]				)
++ THUMB(		ldr	sp, [r0, #32]				)
+ 		subs	r0, r0, r1		@ calculate the delta offset
+ 
+ 						@ if delta is zero, we are
+diff --git a/arch/ia64/kvm/kvm-ia64.c b/arch/ia64/kvm/kvm-ia64.c
+index 5fdeec5..d76279a 100644
+--- a/arch/ia64/kvm/kvm-ia64.c
++++ b/arch/ia64/kvm/kvm-ia64.c
+@@ -1794,7 +1794,8 @@ static int kvm_ia64_sync_dirty_log(struct kvm *kvm,
+ {
+ 	struct kvm_memory_slot *memslot;
+ 	int r, i;
+-	long n, base;
++	long base;
++	unsigned long n;
+ 	unsigned long *dirty_bitmap = (unsigned long *)(kvm->arch.vm_base +
+ 			offsetof(struct kvm_vm_data, kvm_mem_dirty_log));
+ 
+@@ -1807,7 +1808,7 @@ static int kvm_ia64_sync_dirty_log(struct kvm *kvm,
+ 	if (!memslot->dirty_bitmap)
+ 		goto out;
+ 
+-	n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
++	n = kvm_dirty_bitmap_bytes(memslot);
+ 	base = memslot->base_gfn / BITS_PER_LONG;
+ 
+ 	for (i = 0; i < n/sizeof(long); ++i) {
+@@ -1823,7 +1824,7 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
+ 		struct kvm_dirty_log *log)
+ {
+ 	int r;
+-	int n;
++	unsigned long n;
+ 	struct kvm_memory_slot *memslot;
+ 	int is_dirty = 0;
+ 
+@@ -1841,7 +1842,7 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
+ 	if (is_dirty) {
+ 		kvm_flush_remote_tlbs(kvm);
+ 		memslot = &kvm->memslots[log->slot];
+-		n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
++		n = kvm_dirty_bitmap_bytes(memslot);
+ 		memset(memslot->dirty_bitmap, 0, n);
+ 	}
+ 	r = 0;
+diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
+index 3e294bd..e6dc595 100644
+--- a/arch/powerpc/kvm/book3s.c
++++ b/arch/powerpc/kvm/book3s.c
+@@ -848,7 +848,8 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
+ 	struct kvm_vcpu *vcpu;
+ 	ulong ga, ga_end;
+ 	int is_dirty = 0;
+-	int r, n;
++	int r;
++	unsigned long n;
+ 
+ 	down_write(&kvm->slots_lock);
+ 
+@@ -866,7 +867,7 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
+ 		kvm_for_each_vcpu(n, vcpu, kvm)
+ 			kvmppc_mmu_pte_pflush(vcpu, ga, ga_end);
+ 
+-		n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
++		n = kvm_dirty_bitmap_bytes(memslot);
+ 		memset(memslot->dirty_bitmap, 0, n);
+ 	}
+ 
+diff --git a/arch/powerpc/platforms/pseries/offline_states.h b/arch/powerpc/platforms/pseries/offline_states.h
+index 22574e0..202d869 100644
+--- a/arch/powerpc/platforms/pseries/offline_states.h
++++ b/arch/powerpc/platforms/pseries/offline_states.h
+@@ -9,10 +9,30 @@ enum cpu_state_vals {
+ 	CPU_MAX_OFFLINE_STATES
+ };
+ 
++#ifdef CONFIG_HOTPLUG_CPU
+ extern enum cpu_state_vals get_cpu_current_state(int cpu);
+ extern void set_cpu_current_state(int cpu, enum cpu_state_vals state);
+-extern enum cpu_state_vals get_preferred_offline_state(int cpu);
+ extern void set_preferred_offline_state(int cpu, enum cpu_state_vals state);
+ extern void set_default_offline_state(int cpu);
++#else
++static inline enum cpu_state_vals get_cpu_current_state(int cpu)
++{
++	return CPU_STATE_ONLINE;
++}
++
++static inline void set_cpu_current_state(int cpu, enum cpu_state_vals state)
++{
++}
++
++static inline void set_preferred_offline_state(int cpu, enum cpu_state_vals state)
++{
++}
++
++static inline void set_default_offline_state(int cpu)
++{
++}
++#endif
++
++extern enum cpu_state_vals get_preferred_offline_state(int cpu);
+ extern int start_secondary(void);
+ #endif
+diff --git a/arch/s390/mm/vmem.c b/arch/s390/mm/vmem.c
+index 300ab01..5f91a38 100644
+--- a/arch/s390/mm/vmem.c
++++ b/arch/s390/mm/vmem.c
+@@ -70,12 +70,8 @@ static pte_t __ref *vmem_pte_alloc(void)
+ 		pte = alloc_bootmem(PTRS_PER_PTE * sizeof(pte_t));
+ 	if (!pte)
+ 		return NULL;
+-	if (MACHINE_HAS_HPAGE)
+-		clear_table((unsigned long *) pte, _PAGE_TYPE_EMPTY | _PAGE_CO,
+-			    PTRS_PER_PTE * sizeof(pte_t));
+-	else
+-		clear_table((unsigned long *) pte, _PAGE_TYPE_EMPTY,
+-			    PTRS_PER_PTE * sizeof(pte_t));
++	clear_table((unsigned long *) pte, _PAGE_TYPE_EMPTY,
++		    PTRS_PER_PTE * sizeof(pte_t));
+ 	return pte;
+ }
+ 
+@@ -116,8 +112,7 @@ static int vmem_add_mem(unsigned long start, unsigned long size, int ro)
+ 		if (MACHINE_HAS_HPAGE && !(address & ~HPAGE_MASK) &&
+ 		    (address + HPAGE_SIZE <= start + size) &&
+ 		    (address >= HPAGE_SIZE)) {
+-			pte_val(pte) |= _SEGMENT_ENTRY_LARGE |
+-					_SEGMENT_ENTRY_CO;
++			pte_val(pte) |= _SEGMENT_ENTRY_LARGE;
+ 			pmd_val(*pm_dir) = pte_val(pte);
+ 			address += HPAGE_SIZE - PAGE_SIZE;
+ 			continue;
+diff --git a/arch/sh/include/asm/elf.h b/arch/sh/include/asm/elf.h
+index ac04255..ce830fa 100644
+--- a/arch/sh/include/asm/elf.h
++++ b/arch/sh/include/asm/elf.h
+@@ -211,7 +211,9 @@ extern void __kernel_vsyscall;
+ 
+ #define VSYSCALL_AUX_ENT					\
+ 	if (vdso_enabled)					\
+-		NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_BASE);
++		NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_BASE);	\
++	else							\
++		NEW_AUX_ENT(AT_IGNORE, 0);
+ #else
+ #define VSYSCALL_AUX_ENT
+ #endif /* CONFIG_VSYSCALL */
+@@ -219,7 +221,7 @@ extern void __kernel_vsyscall;
+ #ifdef CONFIG_SH_FPU
+ #define FPU_AUX_ENT	NEW_AUX_ENT(AT_FPUCW, FPSCR_INIT)
+ #else
+-#define FPU_AUX_ENT
++#define FPU_AUX_ENT	NEW_AUX_ENT(AT_IGNORE, 0)
+ #endif
+ 
+ extern int l1i_cache_shape, l1d_cache_shape, l2_cache_shape;
+diff --git a/arch/sh/kernel/smp.c b/arch/sh/kernel/smp.c
+index 983e079..1d19c19 100644
+--- a/arch/sh/kernel/smp.c
++++ b/arch/sh/kernel/smp.c
+@@ -69,6 +69,7 @@ asmlinkage void __cpuinit start_secondary(void)
+ 	unsigned int cpu;
+ 	struct mm_struct *mm = &init_mm;
+ 
++	enable_mmu();
+ 	atomic_inc(&mm->mm_count);
+ 	atomic_inc(&mm->mm_users);
+ 	current->active_mm = mm;
+diff --git a/arch/sparc/kernel/ptrace_32.c b/arch/sparc/kernel/ptrace_32.c
+index 7e3dfd9..e608f39 100644
+--- a/arch/sparc/kernel/ptrace_32.c
++++ b/arch/sparc/kernel/ptrace_32.c
+@@ -65,6 +65,7 @@ static int genregs32_get(struct task_struct *target,
+ 			*k++ = regs->u_regs[pos++];
+ 
+ 		reg_window = (unsigned long __user *) regs->u_regs[UREG_I6];
++		reg_window -= 16;
+ 		for (; count > 0 && pos < 32; count--) {
+ 			if (get_user(*k++, &reg_window[pos++]))
+ 				return -EFAULT;
+@@ -76,6 +77,7 @@ static int genregs32_get(struct task_struct *target,
+ 		}
+ 
+ 		reg_window = (unsigned long __user *) regs->u_regs[UREG_I6];
++		reg_window -= 16;
+ 		for (; count > 0 && pos < 32; count--) {
+ 			if (get_user(reg, &reg_window[pos++]) ||
+ 			    put_user(reg, u++))
+@@ -141,6 +143,7 @@ static int genregs32_set(struct task_struct *target,
+ 			regs->u_regs[pos++] = *k++;
+ 
+ 		reg_window = (unsigned long __user *) regs->u_regs[UREG_I6];
++		reg_window -= 16;
+ 		for (; count > 0 && pos < 32; count--) {
+ 			if (put_user(*k++, &reg_window[pos++]))
+ 				return -EFAULT;
+@@ -153,6 +156,7 @@ static int genregs32_set(struct task_struct *target,
+ 		}
+ 
+ 		reg_window = (unsigned long __user *) regs->u_regs[UREG_I6];
++		reg_window -= 16;
+ 		for (; count > 0 && pos < 32; count--) {
+ 			if (get_user(reg, u++) ||
+ 			    put_user(reg, &reg_window[pos++]))
+diff --git a/arch/sparc/kernel/ptrace_64.c b/arch/sparc/kernel/ptrace_64.c
+index 2f6524d..aa90da0 100644
+--- a/arch/sparc/kernel/ptrace_64.c
++++ b/arch/sparc/kernel/ptrace_64.c
+@@ -492,6 +492,7 @@ static int genregs32_get(struct task_struct *target,
+ 			*k++ = regs->u_regs[pos++];
+ 
+ 		reg_window = (compat_ulong_t __user *) regs->u_regs[UREG_I6];
++		reg_window -= 16;
+ 		if (target == current) {
+ 			for (; count > 0 && pos < 32; count--) {
+ 				if (get_user(*k++, &reg_window[pos++]))
+@@ -516,6 +517,7 @@ static int genregs32_get(struct task_struct *target,
+ 		}
+ 
+ 		reg_window = (compat_ulong_t __user *) regs->u_regs[UREG_I6];
++		reg_window -= 16;
+ 		if (target == current) {
+ 			for (; count > 0 && pos < 32; count--) {
+ 				if (get_user(reg, &reg_window[pos++]) ||
+@@ -599,6 +601,7 @@ static int genregs32_set(struct task_struct *target,
+ 			regs->u_regs[pos++] = *k++;
+ 
+ 		reg_window = (compat_ulong_t __user *) regs->u_regs[UREG_I6];
++		reg_window -= 16;
+ 		if (target == current) {
+ 			for (; count > 0 && pos < 32; count--) {
+ 				if (put_user(*k++, &reg_window[pos++]))
+@@ -625,6 +628,7 @@ static int genregs32_set(struct task_struct *target,
+ 		}
+ 
+ 		reg_window = (compat_ulong_t __user *) regs->u_regs[UREG_I6];
++		reg_window -= 16;
+ 		if (target == current) {
+ 			for (; count > 0 && pos < 32; count--) {
+ 				if (get_user(reg, u++) ||
+diff --git a/arch/um/sys-x86_64/Makefile b/arch/um/sys-x86_64/Makefile
+index 2201e9c..c1ea9eb 100644
+--- a/arch/um/sys-x86_64/Makefile
++++ b/arch/um/sys-x86_64/Makefile
+@@ -8,7 +8,8 @@ obj-y = bug.o bugs.o delay.o fault.o ldt.o mem.o ptrace.o ptrace_user.o \
+ 	setjmp.o signal.o stub.o stub_segv.o syscalls.o syscall_table.o \
+ 	sysrq.o ksyms.o tls.o
+ 
+-subarch-obj-y = lib/csum-partial_64.o lib/memcpy_64.o lib/thunk_64.o
++subarch-obj-y = lib/csum-partial_64.o lib/memcpy_64.o lib/thunk_64.o \
++		lib/rwsem_64.o
+ subarch-obj-$(CONFIG_MODULES) += kernel/module.o
+ 
+ ldt-y = ../sys-i386/ldt.o
+diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
+index f20ddf8..a198293 100644
+--- a/arch/x86/Kconfig.cpu
++++ b/arch/x86/Kconfig.cpu
+@@ -319,7 +319,7 @@ config X86_L1_CACHE_SHIFT
+ 
+ config X86_XADD
+ 	def_bool y
+-	depends on X86_32 && !M386
++	depends on X86_64 || !M386
+ 
+ config X86_PPRO_FENCE
+ 	bool "PentiumPro memory ordering errata workaround"
+diff --git a/arch/x86/include/asm/rwsem.h b/arch/x86/include/asm/rwsem.h
+index ca7517d..606ede1 100644
+--- a/arch/x86/include/asm/rwsem.h
++++ b/arch/x86/include/asm/rwsem.h
+@@ -41,6 +41,7 @@
+ #include <linux/list.h>
+ #include <linux/spinlock.h>
+ #include <linux/lockdep.h>
++#include <asm/asm.h>
+ 
+ struct rwsem_waiter;
+ 
+@@ -55,17 +56,28 @@ extern asmregparm struct rw_semaphore *
+ 
+ /*
+  * the semaphore definition
++ *
++ * The bias values and the counter type limits the number of
++ * potential readers/writers to 32767 for 32 bits and 2147483647
++ * for 64 bits.
+  */
+ 
+-#define RWSEM_UNLOCKED_VALUE		0x00000000
+-#define RWSEM_ACTIVE_BIAS		0x00000001
+-#define RWSEM_ACTIVE_MASK		0x0000ffff
+-#define RWSEM_WAITING_BIAS		(-0x00010000)
++#ifdef CONFIG_X86_64
++# define RWSEM_ACTIVE_MASK		0xffffffffL
++#else
++# define RWSEM_ACTIVE_MASK		0x0000ffffL
++#endif
++
++#define RWSEM_UNLOCKED_VALUE		0x00000000L
++#define RWSEM_ACTIVE_BIAS		0x00000001L
++#define RWSEM_WAITING_BIAS		(-RWSEM_ACTIVE_MASK-1)
+ #define RWSEM_ACTIVE_READ_BIAS		RWSEM_ACTIVE_BIAS
+ #define RWSEM_ACTIVE_WRITE_BIAS		(RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
+ 
++typedef signed long rwsem_count_t;
++
+ struct rw_semaphore {
+-	signed long		count;
++	rwsem_count_t		count;
+ 	spinlock_t		wait_lock;
+ 	struct list_head	wait_list;
+ #ifdef CONFIG_DEBUG_LOCK_ALLOC
+@@ -105,7 +117,7 @@ do {								\
+ static inline void __down_read(struct rw_semaphore *sem)
+ {
+ 	asm volatile("# beginning down_read\n\t"
+-		     LOCK_PREFIX "  incl      (%%eax)\n\t"
++		     LOCK_PREFIX _ASM_INC "(%1)\n\t"
+ 		     /* adds 0x00000001, returns the old value */
+ 		     "  jns        1f\n"
+ 		     "  call call_rwsem_down_read_failed\n"
+@@ -121,14 +133,14 @@ static inline void __down_read(struct rw_semaphore *sem)
+  */
+ static inline int __down_read_trylock(struct rw_semaphore *sem)
+ {
+-	__s32 result, tmp;
++	rwsem_count_t result, tmp;
+ 	asm volatile("# beginning __down_read_trylock\n\t"
+-		     "  movl      %0,%1\n\t"
++		     "  mov          %0,%1\n\t"
+ 		     "1:\n\t"
+-		     "  movl	     %1,%2\n\t"
+-		     "  addl      %3,%2\n\t"
++		     "  mov          %1,%2\n\t"
++		     "  add          %3,%2\n\t"
+ 		     "  jle	     2f\n\t"
+-		     LOCK_PREFIX "  cmpxchgl  %2,%0\n\t"
++		     LOCK_PREFIX "  cmpxchg  %2,%0\n\t"
+ 		     "  jnz	     1b\n\t"
+ 		     "2:\n\t"
+ 		     "# ending __down_read_trylock\n\t"
+@@ -143,13 +155,13 @@ static inline int __down_read_trylock(struct rw_semaphore *sem)
+  */
+ static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
+ {
+-	int tmp;
++	rwsem_count_t tmp;
+ 
+ 	tmp = RWSEM_ACTIVE_WRITE_BIAS;
+ 	asm volatile("# beginning down_write\n\t"
+-		     LOCK_PREFIX "  xadd      %%edx,(%%eax)\n\t"
++		     LOCK_PREFIX "  xadd      %1,(%2)\n\t"
+ 		     /* subtract 0x0000ffff, returns the old value */
+-		     "  testl     %%edx,%%edx\n\t"
++		     "  test      %1,%1\n\t"
+ 		     /* was the count 0 before? */
+ 		     "  jz        1f\n"
+ 		     "  call call_rwsem_down_write_failed\n"
+@@ -170,9 +182,9 @@ static inline void __down_write(struct rw_semaphore *sem)
+  */
+ static inline int __down_write_trylock(struct rw_semaphore *sem)
+ {
+-	signed long ret = cmpxchg(&sem->count,
+-				  RWSEM_UNLOCKED_VALUE,
+-				  RWSEM_ACTIVE_WRITE_BIAS);
++	rwsem_count_t ret = cmpxchg(&sem->count,
++				    RWSEM_UNLOCKED_VALUE,
++				    RWSEM_ACTIVE_WRITE_BIAS);
+ 	if (ret == RWSEM_UNLOCKED_VALUE)
+ 		return 1;
+ 	return 0;
+@@ -183,9 +195,9 @@ static inline int __down_write_trylock(struct rw_semaphore *sem)
+  */
+ static inline void __up_read(struct rw_semaphore *sem)
+ {
+-	__s32 tmp = -RWSEM_ACTIVE_READ_BIAS;
++	rwsem_count_t tmp = -RWSEM_ACTIVE_READ_BIAS;
+ 	asm volatile("# beginning __up_read\n\t"
+-		     LOCK_PREFIX "  xadd      %%edx,(%%eax)\n\t"
++		     LOCK_PREFIX "  xadd      %1,(%2)\n\t"
+ 		     /* subtracts 1, returns the old value */
+ 		     "  jns        1f\n\t"
+ 		     "  call call_rwsem_wake\n"
+@@ -201,18 +213,18 @@ static inline void __up_read(struct rw_semaphore *sem)
+  */
+ static inline void __up_write(struct rw_semaphore *sem)
+ {
++	rwsem_count_t tmp;
+ 	asm volatile("# beginning __up_write\n\t"
+-		     "  movl      %2,%%edx\n\t"
+-		     LOCK_PREFIX "  xaddl     %%edx,(%%eax)\n\t"
++		     LOCK_PREFIX "  xadd      %1,(%2)\n\t"
+ 		     /* tries to transition
+ 			0xffff0001 -> 0x00000000 */
+ 		     "  jz       1f\n"
+ 		     "  call call_rwsem_wake\n"
+ 		     "1:\n\t"
+ 		     "# ending __up_write\n"
+-		     : "+m" (sem->count)
+-		     : "a" (sem), "i" (-RWSEM_ACTIVE_WRITE_BIAS)
+-		     : "memory", "cc", "edx");
++		     : "+m" (sem->count), "=d" (tmp)
++		     : "a" (sem), "1" (-RWSEM_ACTIVE_WRITE_BIAS)
++		     : "memory", "cc");
+ }
+ 
+ /*
+@@ -221,33 +233,38 @@ static inline void __up_write(struct rw_semaphore *sem)
+ static inline void __downgrade_write(struct rw_semaphore *sem)
+ {
+ 	asm volatile("# beginning __downgrade_write\n\t"
+-		     LOCK_PREFIX "  addl      %2,(%%eax)\n\t"
+-		     /* transitions 0xZZZZ0001 -> 0xYYYY0001 */
++		     LOCK_PREFIX _ASM_ADD "%2,(%1)\n\t"
++		     /*
++		      * transitions 0xZZZZ0001 -> 0xYYYY0001 (i386)
++		      *     0xZZZZZZZZ00000001 -> 0xYYYYYYYY00000001 (x86_64)
++		      */
+ 		     "  jns       1f\n\t"
+ 		     "  call call_rwsem_downgrade_wake\n"
+ 		     "1:\n\t"
+ 		     "# ending __downgrade_write\n"
+ 		     : "+m" (sem->count)
+-		     : "a" (sem), "i" (-RWSEM_WAITING_BIAS)
++		     : "a" (sem), "er" (-RWSEM_WAITING_BIAS)
+ 		     : "memory", "cc");
+ }
+ 
+ /*
+  * implement atomic add functionality
+  */
+-static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
++static inline void rwsem_atomic_add(rwsem_count_t delta,
++				    struct rw_semaphore *sem)
+ {
+-	asm volatile(LOCK_PREFIX "addl %1,%0"
++	asm volatile(LOCK_PREFIX _ASM_ADD "%1,%0"
+ 		     : "+m" (sem->count)
+-		     : "ir" (delta));
++		     : "er" (delta));
+ }
+ 
+ /*
+  * implement exchange and add functionality
+  */
+-static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
++static inline rwsem_count_t rwsem_atomic_update(rwsem_count_t delta,
++						struct rw_semaphore *sem)
+ {
+-	int tmp = delta;
++	rwsem_count_t tmp = delta;
+ 
+ 	asm volatile(LOCK_PREFIX "xadd %0,%1"
+ 		     : "+r" (tmp), "+m" (sem->count)
+diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h
+index 1e79678..4cfc908 100644
+--- a/arch/x86/include/asm/smp.h
++++ b/arch/x86/include/asm/smp.h
+@@ -135,6 +135,8 @@ int native_cpu_disable(void);
+ void native_cpu_die(unsigned int cpu);
+ void native_play_dead(void);
+ void play_dead_common(void);
++void wbinvd_on_cpu(int cpu);
++int wbinvd_on_all_cpus(void);
+ 
+ void native_send_call_func_ipi(const struct cpumask *mask);
+ void native_send_call_func_single_ipi(int cpu);
+@@ -147,6 +149,13 @@ static inline int num_booting_cpus(void)
+ {
+ 	return cpumask_weight(cpu_callout_mask);
+ }
++#else /* !CONFIG_SMP */
++#define wbinvd_on_cpu(cpu)     wbinvd()
++static inline int wbinvd_on_all_cpus(void)
++{
++	wbinvd();
++	return 0;
++}
+ #endif /* CONFIG_SMP */
+ 
+ extern unsigned disabled_cpus __cpuinitdata;
+diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c
+index adb0ba0..2e77516 100644
+--- a/arch/x86/kernel/amd_iommu.c
++++ b/arch/x86/kernel/amd_iommu.c
+@@ -2298,7 +2298,7 @@ static void cleanup_domain(struct protection_domain *domain)
+ 	list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
+ 		struct device *dev = dev_data->dev;
+ 
+-		do_detach(dev);
++		__detach_device(dev);
+ 		atomic_set(&dev_data->bind, 0);
+ 	}
+ 
+@@ -2379,9 +2379,7 @@ static void amd_iommu_domain_destroy(struct iommu_domain *dom)
+ 
+ 	free_pagetable(domain);
+ 
+-	domain_id_free(domain->id);
+-
+-	kfree(domain);
++	protection_domain_free(domain);
+ 
+ 	dom->priv = NULL;
+ }
+diff --git a/arch/x86/kernel/amd_iommu_init.c b/arch/x86/kernel/amd_iommu_init.c
+index 9dc91b4..883d619 100644
+--- a/arch/x86/kernel/amd_iommu_init.c
++++ b/arch/x86/kernel/amd_iommu_init.c
+@@ -1288,6 +1288,8 @@ static int __init amd_iommu_init(void)
+ 	if (ret)
+ 		goto free;
+ 
++	enable_iommus();
++
+ 	if (iommu_pass_through)
+ 		ret = amd_iommu_init_passthrough();
+ 	else
+@@ -1300,8 +1302,6 @@ static int __init amd_iommu_init(void)
+ 
+ 	amd_iommu_init_notifier();
+ 
+-	enable_iommus();
+-
+ 	if (iommu_pass_through)
+ 		goto out;
+ 
+@@ -1315,6 +1315,7 @@ out:
+ 	return ret;
+ 
+ free:
++	disable_iommus();
+ 
+ 	amd_iommu_uninit_devices();
+ 
+diff --git a/arch/x86/kernel/aperture_64.c b/arch/x86/kernel/aperture_64.c
+index f147a95..19f2c70 100644
+--- a/arch/x86/kernel/aperture_64.c
++++ b/arch/x86/kernel/aperture_64.c
+@@ -394,6 +394,7 @@ void __init gart_iommu_hole_init(void)
+ 	for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
+ 		int bus;
+ 		int dev_base, dev_limit;
++		u32 ctl;
+ 
+ 		bus = bus_dev_ranges[i].bus;
+ 		dev_base = bus_dev_ranges[i].dev_base;
+@@ -407,7 +408,19 @@ void __init gart_iommu_hole_init(void)
+ 			gart_iommu_aperture = 1;
+ 			x86_init.iommu.iommu_init = gart_iommu_init;
+ 
+-			aper_order = (read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL) >> 1) & 7;
++			ctl = read_pci_config(bus, slot, 3,
++					      AMD64_GARTAPERTURECTL);
++
++			/*
++			 * Before we do anything else disable the GART. It may
++			 * still be enabled if we boot into a crash-kernel here.
++			 * Reconfiguring the GART while it is enabled could have
++			 * unknown side-effects.
++			 */
++			ctl &= ~GARTEN;
++			write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
++
++			aper_order = (ctl >> 1) & 7;
+ 			aper_size = (32 * 1024 * 1024) << aper_order;
+ 			aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
+ 			aper_base <<= 25;
+diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
+index dfca210..d4df517 100644
+--- a/arch/x86/kernel/apic/apic.c
++++ b/arch/x86/kernel/apic/apic.c
+@@ -1640,8 +1640,10 @@ int __init APIC_init_uniprocessor(void)
+ 	}
+ #endif
+ 
++#ifndef CONFIG_SMP
+ 	enable_IR_x2apic();
+ 	default_setup_apic_routing();
++#endif
+ 
+ 	verify_local_APIC();
+ 	connect_bsp_APIC();
+diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
+index fc6c8ef..d440123 100644
+--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
++++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
+@@ -18,6 +18,7 @@
+ #include <asm/processor.h>
+ #include <linux/smp.h>
+ #include <asm/k8.h>
++#include <asm/smp.h>
+ 
+ #define LVL_1_INST	1
+ #define LVL_1_DATA	2
+@@ -150,7 +151,8 @@ struct _cpuid4_info {
+ 	union _cpuid4_leaf_ebx ebx;
+ 	union _cpuid4_leaf_ecx ecx;
+ 	unsigned long size;
+-	unsigned long can_disable;
++	bool can_disable;
++	unsigned int l3_indices;
+ 	DECLARE_BITMAP(shared_cpu_map, NR_CPUS);
+ };
+ 
+@@ -160,7 +162,8 @@ struct _cpuid4_info_regs {
+ 	union _cpuid4_leaf_ebx ebx;
+ 	union _cpuid4_leaf_ecx ecx;
+ 	unsigned long size;
+-	unsigned long can_disable;
++	bool can_disable;
++	unsigned int l3_indices;
+ };
+ 
+ unsigned short			num_cache_leaves;
+@@ -290,6 +293,36 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
+ 		(ebx->split.ways_of_associativity + 1) - 1;
+ }
+ 
++struct _cache_attr {
++	struct attribute attr;
++	ssize_t (*show)(struct _cpuid4_info *, char *);
++	ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
++};
++
++#ifdef CONFIG_CPU_SUP_AMD
++static unsigned int __cpuinit amd_calc_l3_indices(void)
++{
++	/*
++	 * We're called over smp_call_function_single() and therefore
++	 * are on the correct cpu.
++	 */
++	int cpu = smp_processor_id();
++	int node = cpu_to_node(cpu);
++	struct pci_dev *dev = node_to_k8_nb_misc(node);
++	unsigned int sc0, sc1, sc2, sc3;
++	u32 val = 0;
++
++	pci_read_config_dword(dev, 0x1C4, &val);
++
++	/* calculate subcache sizes */
++	sc0 = !(val & BIT(0));
++	sc1 = !(val & BIT(4));
++	sc2 = !(val & BIT(8))  + !(val & BIT(9));
++	sc3 = !(val & BIT(12)) + !(val & BIT(13));
++
++	return (max(max(max(sc0, sc1), sc2), sc3) << 10) - 1;
++}
++
+ static void __cpuinit
+ amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
+ {
+@@ -299,12 +332,103 @@ amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
+ 	if (boot_cpu_data.x86 == 0x11)
+ 		return;
+ 
+-	/* see erratum #382 */
+-	if ((boot_cpu_data.x86 == 0x10) && (boot_cpu_data.x86_model < 0x8))
++	/* see errata #382 and #388 */
++	if ((boot_cpu_data.x86 == 0x10) &&
++	    ((boot_cpu_data.x86_model < 0x8) ||
++	     (boot_cpu_data.x86_mask  < 0x1)))
+ 		return;
+ 
+-	this_leaf->can_disable = 1;
++	this_leaf->can_disable = true;
++	this_leaf->l3_indices  = amd_calc_l3_indices();
++}
++
++static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
++				  unsigned int index)
++{
++	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
++	int node = amd_get_nb_id(cpu);
++	struct pci_dev *dev = node_to_k8_nb_misc(node);
++	unsigned int reg = 0;
++
++	if (!this_leaf->can_disable)
++		return -EINVAL;
++
++	if (!dev)
++		return -EINVAL;
++
++	pci_read_config_dword(dev, 0x1BC + index * 4, &reg);
++	return sprintf(buf, "0x%08x\n", reg);
++}
++
++#define SHOW_CACHE_DISABLE(index)					\
++static ssize_t								\
++show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf)	\
++{									\
++	return show_cache_disable(this_leaf, buf, index);		\
++}
++SHOW_CACHE_DISABLE(0)
++SHOW_CACHE_DISABLE(1)
++
++static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
++	const char *buf, size_t count, unsigned int index)
++{
++	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
++	int node = amd_get_nb_id(cpu);
++	struct pci_dev *dev = node_to_k8_nb_misc(node);
++	unsigned long val = 0;
++
++#define SUBCACHE_MASK	(3UL << 20)
++#define SUBCACHE_INDEX	0xfff
++
++	if (!this_leaf->can_disable)
++		return -EINVAL;
++
++	if (!capable(CAP_SYS_ADMIN))
++		return -EPERM;
++
++	if (!dev)
++		return -EINVAL;
++
++	if (strict_strtoul(buf, 10, &val) < 0)
++		return -EINVAL;
++
++	/* do not allow writes outside of allowed bits */
++	if ((val & ~(SUBCACHE_MASK | SUBCACHE_INDEX)) ||
++	    ((val & SUBCACHE_INDEX) > this_leaf->l3_indices))
++		return -EINVAL;
++
++	val |= BIT(30);
++	pci_write_config_dword(dev, 0x1BC + index * 4, val);
++	/*
++	 * We need to WBINVD on a core on the node containing the L3 cache which
++	 * indices we disable therefore a simple wbinvd() is not sufficient.
++	 */
++	wbinvd_on_cpu(cpu);
++	pci_write_config_dword(dev, 0x1BC + index * 4, val | BIT(31));
++	return count;
++}
++
++#define STORE_CACHE_DISABLE(index)					\
++static ssize_t								\
++store_cache_disable_##index(struct _cpuid4_info *this_leaf,		\
++			    const char *buf, size_t count)		\
++{									\
++	return store_cache_disable(this_leaf, buf, count, index);	\
+ }
++STORE_CACHE_DISABLE(0)
++STORE_CACHE_DISABLE(1)
++
++static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
++		show_cache_disable_0, store_cache_disable_0);
++static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
++		show_cache_disable_1, store_cache_disable_1);
++
++#else	/* CONFIG_CPU_SUP_AMD */
++static void __cpuinit
++amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
++{
++};
++#endif /* CONFIG_CPU_SUP_AMD */
+ 
+ static int
+ __cpuinit cpuid4_cache_lookup_regs(int index,
+@@ -711,82 +835,6 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
+ #define to_object(k)	container_of(k, struct _index_kobject, kobj)
+ #define to_attr(a)	container_of(a, struct _cache_attr, attr)
+ 
+-static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
+-				  unsigned int index)
+-{
+-	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
+-	int node = cpu_to_node(cpu);
+-	struct pci_dev *dev = node_to_k8_nb_misc(node);
+-	unsigned int reg = 0;
+-
+-	if (!this_leaf->can_disable)
+-		return -EINVAL;
+-
+-	if (!dev)
+-		return -EINVAL;
+-
+-	pci_read_config_dword(dev, 0x1BC + index * 4, &reg);
+-	return sprintf(buf, "%x\n", reg);
+-}
+-
+-#define SHOW_CACHE_DISABLE(index)					\
+-static ssize_t								\
+-show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf)  	\
+-{									\
+-	return show_cache_disable(this_leaf, buf, index);		\
+-}
+-SHOW_CACHE_DISABLE(0)
+-SHOW_CACHE_DISABLE(1)
+-
+-static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
+-	const char *buf, size_t count, unsigned int index)
+-{
+-	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
+-	int node = cpu_to_node(cpu);
+-	struct pci_dev *dev = node_to_k8_nb_misc(node);
+-	unsigned long val = 0;
+-	unsigned int scrubber = 0;
+-
+-	if (!this_leaf->can_disable)
+-		return -EINVAL;
+-
+-	if (!capable(CAP_SYS_ADMIN))
+-		return -EPERM;
+-
+-	if (!dev)
+-		return -EINVAL;
+-
+-	if (strict_strtoul(buf, 10, &val) < 0)
+-		return -EINVAL;
+-
+-	val |= 0xc0000000;
+-
+-	pci_read_config_dword(dev, 0x58, &scrubber);
+-	scrubber &= ~0x1f000000;
+-	pci_write_config_dword(dev, 0x58, scrubber);
+-
+-	pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
+-	wbinvd();
+-	pci_write_config_dword(dev, 0x1BC + index * 4, val);
+-	return count;
+-}
+-
+-#define STORE_CACHE_DISABLE(index)					\
+-static ssize_t								\
+-store_cache_disable_##index(struct _cpuid4_info *this_leaf,	     	\
+-			    const char *buf, size_t count)		\
+-{									\
+-	return store_cache_disable(this_leaf, buf, count, index);	\
+-}
+-STORE_CACHE_DISABLE(0)
+-STORE_CACHE_DISABLE(1)
+-
+-struct _cache_attr {
+-	struct attribute attr;
+-	ssize_t (*show)(struct _cpuid4_info *, char *);
+-	ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
+-};
+-
+ #define define_one_ro(_name) \
+ static struct _cache_attr _name = \
+ 	__ATTR(_name, 0444, show_##_name, NULL)
+@@ -801,23 +849,28 @@ define_one_ro(size);
+ define_one_ro(shared_cpu_map);
+ define_one_ro(shared_cpu_list);
+ 
+-static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
+-		show_cache_disable_0, store_cache_disable_0);
+-static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
+-		show_cache_disable_1, store_cache_disable_1);
++#define DEFAULT_SYSFS_CACHE_ATTRS	\
++	&type.attr,			\
++	&level.attr,			\
++	&coherency_line_size.attr,	\
++	&physical_line_partition.attr,	\
++	&ways_of_associativity.attr,	\
++	&number_of_sets.attr,		\
++	&size.attr,			\
++	&shared_cpu_map.attr,		\
++	&shared_cpu_list.attr
+ 
+ static struct attribute *default_attrs[] = {
+-	&type.attr,
+-	&level.attr,
+-	&coherency_line_size.attr,
+-	&physical_line_partition.attr,
+-	&ways_of_associativity.attr,
+-	&number_of_sets.attr,
+-	&size.attr,
+-	&shared_cpu_map.attr,
+-	&shared_cpu_list.attr,
++	DEFAULT_SYSFS_CACHE_ATTRS,
++	NULL
++};
++
++static struct attribute *default_l3_attrs[] = {
++	DEFAULT_SYSFS_CACHE_ATTRS,
++#ifdef CONFIG_CPU_SUP_AMD
+ 	&cache_disable_0.attr,
+ 	&cache_disable_1.attr,
++#endif
+ 	NULL
+ };
+ 
+@@ -908,6 +961,7 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
+ 	unsigned int cpu = sys_dev->id;
+ 	unsigned long i, j;
+ 	struct _index_kobject *this_object;
++	struct _cpuid4_info   *this_leaf;
+ 	int retval;
+ 
+ 	retval = cpuid4_cache_sysfs_init(cpu);
+@@ -926,6 +980,14 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
+ 		this_object = INDEX_KOBJECT_PTR(cpu, i);
+ 		this_object->cpu = cpu;
+ 		this_object->index = i;
++
++		this_leaf = CPUID4_INFO_IDX(cpu, i);
++
++		if (this_leaf->can_disable)
++			ktype_cache.default_attrs = default_l3_attrs;
++		else
++			ktype_cache.default_attrs = default_attrs;
++
+ 		retval = kobject_init_and_add(&(this_object->kobj),
+ 					      &ktype_cache,
+ 					      per_cpu(ici_cache_kobject, cpu),
+diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
+index 98819b3..c7ca8e2 100644
+--- a/arch/x86/kernel/cpu/perf_event.c
++++ b/arch/x86/kernel/cpu/perf_event.c
+@@ -245,6 +245,97 @@ static u64 __read_mostly hw_cache_event_ids
+ 				[PERF_COUNT_HW_CACHE_OP_MAX]
+ 				[PERF_COUNT_HW_CACHE_RESULT_MAX];
+ 
++static const u64 westmere_hw_cache_event_ids
++				[PERF_COUNT_HW_CACHE_MAX]
++				[PERF_COUNT_HW_CACHE_OP_MAX]
++				[PERF_COUNT_HW_CACHE_RESULT_MAX] =
++{
++ [ C(L1D) ] = {
++	[ C(OP_READ) ] = {
++		[ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
++		[ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
++	},
++	[ C(OP_WRITE) ] = {
++		[ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
++		[ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
++	},
++	[ C(OP_PREFETCH) ] = {
++		[ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
++		[ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
++	},
++ },
++ [ C(L1I ) ] = {
++	[ C(OP_READ) ] = {
++		[ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
++		[ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
++	},
++	[ C(OP_WRITE) ] = {
++		[ C(RESULT_ACCESS) ] = -1,
++		[ C(RESULT_MISS)   ] = -1,
++	},
++	[ C(OP_PREFETCH) ] = {
++		[ C(RESULT_ACCESS) ] = 0x0,
++		[ C(RESULT_MISS)   ] = 0x0,
++	},
++ },
++ [ C(LL  ) ] = {
++	[ C(OP_READ) ] = {
++		[ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS               */
++		[ C(RESULT_MISS)   ] = 0x0224, /* L2_RQSTS.LD_MISS             */
++	},
++	[ C(OP_WRITE) ] = {
++		[ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS                */
++		[ C(RESULT_MISS)   ] = 0x0824, /* L2_RQSTS.RFO_MISS            */
++	},
++	[ C(OP_PREFETCH) ] = {
++		[ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference                */
++		[ C(RESULT_MISS)   ] = 0x412e, /* LLC Misses                   */
++	},
++ },
++ [ C(DTLB) ] = {
++	[ C(OP_READ) ] = {
++		[ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
++		[ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
++	},
++	[ C(OP_WRITE) ] = {
++		[ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
++		[ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
++	},
++	[ C(OP_PREFETCH) ] = {
++		[ C(RESULT_ACCESS) ] = 0x0,
++		[ C(RESULT_MISS)   ] = 0x0,
++	},
++ },
++ [ C(ITLB) ] = {
++	[ C(OP_READ) ] = {
++		[ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
++		[ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.ANY              */
++	},
++	[ C(OP_WRITE) ] = {
++		[ C(RESULT_ACCESS) ] = -1,
++		[ C(RESULT_MISS)   ] = -1,
++	},
++	[ C(OP_PREFETCH) ] = {
++		[ C(RESULT_ACCESS) ] = -1,
++		[ C(RESULT_MISS)   ] = -1,
++	},
++ },
++ [ C(BPU ) ] = {
++	[ C(OP_READ) ] = {
++		[ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
++		[ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
++	},
++	[ C(OP_WRITE) ] = {
++		[ C(RESULT_ACCESS) ] = -1,
++		[ C(RESULT_MISS)   ] = -1,
++	},
++	[ C(OP_PREFETCH) ] = {
++		[ C(RESULT_ACCESS) ] = -1,
++		[ C(RESULT_MISS)   ] = -1,
++	},
++ },
++};
++
+ static __initconst u64 nehalem_hw_cache_event_ids
+ 				[PERF_COUNT_HW_CACHE_MAX]
+ 				[PERF_COUNT_HW_CACHE_OP_MAX]
+@@ -2118,6 +2209,7 @@ static __init int intel_pmu_init(void)
+ 	 * Install the hw-cache-events table:
+ 	 */
+ 	switch (boot_cpu_data.x86_model) {
++
+ 	case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
+ 	case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
+ 	case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
+@@ -2129,7 +2221,9 @@ static __init int intel_pmu_init(void)
+ 		event_constraints = intel_core_event_constraints;
+ 		break;
+ 	default:
+-	case 26:
++	case 26: /* 45 nm nehalem, "Bloomfield" */
++	case 30: /* 45 nm nehalem, "Lynnfield" */
++	case 46: /* 45 nm nehalem-ex, "Beckton" */
+ 		memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
+ 		       sizeof(hw_cache_event_ids));
+ 
+@@ -2142,6 +2236,14 @@ static __init int intel_pmu_init(void)
+ 
+ 		pr_cont("Atom events, ");
+ 		break;
++
++	case 37: /* 32 nm nehalem, "Clarkdale" */
++	case 44: /* 32 nm nehalem, "Gulftown" */
++		memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
++		       sizeof(hw_cache_event_ids));
++
++		pr_cont("Westmere events, ");
++		break;
+ 	}
+ 	return 0;
+ }
+diff --git a/arch/x86/kernel/crash.c b/arch/x86/kernel/crash.c
+index a4849c1..ebd4c51 100644
+--- a/arch/x86/kernel/crash.c
++++ b/arch/x86/kernel/crash.c
+@@ -27,7 +27,6 @@
+ #include <asm/cpu.h>
+ #include <asm/reboot.h>
+ #include <asm/virtext.h>
+-#include <asm/x86_init.h>
+ 
+ #if defined(CONFIG_SMP) && defined(CONFIG_X86_LOCAL_APIC)
+ 
+@@ -103,10 +102,5 @@ void native_machine_crash_shutdown(struct pt_regs *regs)
+ #ifdef CONFIG_HPET_TIMER
+ 	hpet_disable();
+ #endif
+-
+-#ifdef CONFIG_X86_64
+-	x86_platform.iommu_shutdown();
+-#endif
+-
+ 	crash_save_cpu(regs, safe_smp_processor_id());
+ }
+diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
+index ad80a1c..773afc9 100644
+--- a/arch/x86/kernel/hpet.c
++++ b/arch/x86/kernel/hpet.c
+@@ -399,9 +399,15 @@ static int hpet_next_event(unsigned long delta,
+ 	 * then we might have a real hardware problem. We can not do
+ 	 * much about it here, but at least alert the user/admin with
+ 	 * a prominent warning.
++	 * An erratum on some chipsets (ICH9,..), results in comparator read
++	 * immediately following a write returning old value. Workaround
++	 * for this is to read this value second time, when first
++	 * read returns old value.
+ 	 */
+-	WARN_ONCE(hpet_readl(HPET_Tn_CMP(timer)) != cnt,
++	if (unlikely((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt)) {
++		WARN_ONCE(hpet_readl(HPET_Tn_CMP(timer)) != cnt,
+ 		  KERN_WARNING "hpet: compare register read back failed.\n");
++	}
+ 
+ 	return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
+ }
+diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c
+index bfba601..b2258ca 100644
+--- a/arch/x86/kernel/kgdb.c
++++ b/arch/x86/kernel/kgdb.c
+@@ -618,8 +618,8 @@ int kgdb_arch_init(void)
+ 	 * portion of kgdb because this operation requires mutexs to
+ 	 * complete.
+ 	 */
++	hw_breakpoint_init(&attr);
+ 	attr.bp_addr = (unsigned long)kgdb_arch_init;
+-	attr.type = PERF_TYPE_BREAKPOINT;
+ 	attr.bp_len = HW_BREAKPOINT_LEN_1;
+ 	attr.bp_type = HW_BREAKPOINT_W;
+ 	attr.disabled = 1;
+diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
+index a2c1edd..e81030f 100644
+--- a/arch/x86/kernel/mpparse.c
++++ b/arch/x86/kernel/mpparse.c
+@@ -664,7 +664,7 @@ static void __init smp_reserve_memory(struct mpf_intel *mpf)
+ {
+ 	unsigned long size = get_mpc_size(mpf->physptr);
+ 
+-	reserve_early(mpf->physptr, mpf->physptr+size, "MP-table mpc");
++	reserve_early_overlap_ok(mpf->physptr, mpf->physptr+size, "MP-table mpc");
+ }
+ 
+ static int __init smp_scan_config(unsigned long base, unsigned long length)
+@@ -693,7 +693,7 @@ static int __init smp_scan_config(unsigned long base, unsigned long length)
+ 			       mpf, (u64)virt_to_phys(mpf));
+ 
+ 			mem = virt_to_phys(mpf);
+-			reserve_early(mem, mem + sizeof(*mpf), "MP-table mpf");
++			reserve_early_overlap_ok(mem, mem + sizeof(*mpf), "MP-table mpf");
+ 			if (mpf->physptr)
+ 				smp_reserve_memory(mpf);
+ 
+diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c
+index 34de53b..4f41b29 100644
+--- a/arch/x86/kernel/pci-gart_64.c
++++ b/arch/x86/kernel/pci-gart_64.c
+@@ -564,6 +564,9 @@ static void enable_gart_translations(void)
+ 
+ 		enable_gart_translation(dev, __pa(agp_gatt_table));
+ 	}
++
++	/* Flush the GART-TLB to remove stale entries */
++	k8_flush_garts();
+ }
+ 
+ /*
+diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
+index 89a49fb..28c3d81 100644
+--- a/arch/x86/kvm/mmu.c
++++ b/arch/x86/kvm/mmu.c
+@@ -1502,8 +1502,8 @@ static int mmu_zap_unsync_children(struct kvm *kvm,
+ 		for_each_sp(pages, sp, parents, i) {
+ 			kvm_mmu_zap_page(kvm, sp);
+ 			mmu_pages_clear_parents(&parents);
++			zapped++;
+ 		}
+-		zapped += pages.nr;
+ 		kvm_mmu_pages_init(parent, &parents, &pages);
+ 	}
+ 
+@@ -1554,14 +1554,16 @@ void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
+ 	 */
+ 
+ 	if (used_pages > kvm_nr_mmu_pages) {
+-		while (used_pages > kvm_nr_mmu_pages) {
++		while (used_pages > kvm_nr_mmu_pages &&
++			!list_empty(&kvm->arch.active_mmu_pages)) {
+ 			struct kvm_mmu_page *page;
+ 
+ 			page = container_of(kvm->arch.active_mmu_pages.prev,
+ 					    struct kvm_mmu_page, link);
+-			kvm_mmu_zap_page(kvm, page);
++			used_pages -= kvm_mmu_zap_page(kvm, page);
+ 			used_pages--;
+ 		}
++		kvm_nr_mmu_pages = used_pages;
+ 		kvm->arch.n_free_mmu_pages = 0;
+ 	}
+ 	else
+@@ -1608,7 +1610,8 @@ static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
+ 		    && !sp->role.invalid) {
+ 			pgprintk("%s: zap %lx %x\n",
+ 				 __func__, gfn, sp->role.word);
+-			kvm_mmu_zap_page(kvm, sp);
++			if (kvm_mmu_zap_page(kvm, sp))
++				nn = bucket->first;
+ 		}
+ 	}
+ }
+diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
+index 1d9b338..d42e191 100644
+--- a/arch/x86/kvm/svm.c
++++ b/arch/x86/kvm/svm.c
+@@ -698,29 +698,28 @@ static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
+ 	if (err)
+ 		goto free_svm;
+ 
++	err = -ENOMEM;
+ 	page = alloc_page(GFP_KERNEL);
+-	if (!page) {
+-		err = -ENOMEM;
++	if (!page)
+ 		goto uninit;
+-	}
+ 
+-	err = -ENOMEM;
+ 	msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
+ 	if (!msrpm_pages)
+-		goto uninit;
++		goto free_page1;
+ 
+ 	nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
+ 	if (!nested_msrpm_pages)
+-		goto uninit;
+-
+-	svm->msrpm = page_address(msrpm_pages);
+-	svm_vcpu_init_msrpm(svm->msrpm);
++		goto free_page2;
+ 
+ 	hsave_page = alloc_page(GFP_KERNEL);
+ 	if (!hsave_page)
+-		goto uninit;
++		goto free_page3;
++
+ 	svm->nested.hsave = page_address(hsave_page);
+ 
++	svm->msrpm = page_address(msrpm_pages);
++	svm_vcpu_init_msrpm(svm->msrpm);
++
+ 	svm->nested.msrpm = page_address(nested_msrpm_pages);
+ 
+ 	svm->vmcb = page_address(page);
+@@ -737,6 +736,12 @@ static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
+ 
+ 	return &svm->vcpu;
+ 
++free_page3:
++	__free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
++free_page2:
++	__free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
++free_page1:
++	__free_page(page);
+ uninit:
+ 	kvm_vcpu_uninit(&svm->vcpu);
+ free_svm:
+diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
+index 8a8e139..3acbe19 100644
+--- a/arch/x86/kvm/vmx.c
++++ b/arch/x86/kvm/vmx.c
+@@ -61,6 +61,8 @@ module_param_named(unrestricted_guest,
+ static int __read_mostly emulate_invalid_guest_state = 0;
+ module_param(emulate_invalid_guest_state, bool, S_IRUGO);
+ 
++#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
++
+ /*
+  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
+  * ple_gap:    upper bound on the amount of time between two successive
+@@ -115,7 +117,7 @@ struct vcpu_vmx {
+ 	} host_state;
+ 	struct {
+ 		int vm86_active;
+-		u8 save_iopl;
++		ulong save_rflags;
+ 		struct kvm_save_segment {
+ 			u16 selector;
+ 			unsigned long base;
+@@ -787,18 +789,23 @@ static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
+ 
+ static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
+ {
+-	unsigned long rflags;
++	unsigned long rflags, save_rflags;
+ 
+ 	rflags = vmcs_readl(GUEST_RFLAGS);
+-	if (to_vmx(vcpu)->rmode.vm86_active)
+-		rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
++	if (to_vmx(vcpu)->rmode.vm86_active) {
++		rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
++		save_rflags = to_vmx(vcpu)->rmode.save_rflags;
++		rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
++	}
+ 	return rflags;
+ }
+ 
+ static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
+ {
+-	if (to_vmx(vcpu)->rmode.vm86_active)
++	if (to_vmx(vcpu)->rmode.vm86_active) {
++		to_vmx(vcpu)->rmode.save_rflags = rflags;
+ 		rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
++	}
+ 	vmcs_writel(GUEST_RFLAGS, rflags);
+ }
+ 
+@@ -1431,8 +1438,8 @@ static void enter_pmode(struct kvm_vcpu *vcpu)
+ 	vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
+ 
+ 	flags = vmcs_readl(GUEST_RFLAGS);
+-	flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
+-	flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
++	flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
++	flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
+ 	vmcs_writel(GUEST_RFLAGS, flags);
+ 
+ 	vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
+@@ -1501,8 +1508,7 @@ static void enter_rmode(struct kvm_vcpu *vcpu)
+ 	vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
+ 
+ 	flags = vmcs_readl(GUEST_RFLAGS);
+-	vmx->rmode.save_iopl
+-		= (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
++	vmx->rmode.save_rflags = flags;
+ 
+ 	flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
+ 
+@@ -2719,6 +2725,12 @@ static int handle_rmode_exception(struct kvm_vcpu *vcpu,
+ 		kvm_queue_exception(vcpu, vec);
+ 		return 1;
+ 	case BP_VECTOR:
++		/*
++		 * Update instruction length as we may reinject the exception
++		 * from user space while in guest debugging mode.
++		 */
++		to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
++			vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
+ 		if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
+ 			return 0;
+ 		/* fall through */
+@@ -2841,6 +2853,13 @@ static int handle_exception(struct kvm_vcpu *vcpu)
+ 		kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
+ 		/* fall through */
+ 	case BP_VECTOR:
++		/*
++		 * Update instruction length as we may reinject #BP from
++		 * user space while in guest debugging mode. Reading it for
++		 * #DB as well causes no harm, it is not used in that case.
++		 */
++		vmx->vcpu.arch.event_exit_inst_len =
++			vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
+ 		kvm_run->exit_reason = KVM_EXIT_DEBUG;
+ 		kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
+ 		kvm_run->debug.arch.exception = ex_no;
+diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
+index e900908..dd78927 100644
+--- a/arch/x86/kvm/x86.c
++++ b/arch/x86/kvm/x86.c
+@@ -384,21 +384,16 @@ out:
+ void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
+ {
+ 	if (cr0 & CR0_RESERVED_BITS) {
+-		printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
+-		       cr0, vcpu->arch.cr0);
+ 		kvm_inject_gp(vcpu, 0);
+ 		return;
+ 	}
+ 
+ 	if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
+-		printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
+ 		kvm_inject_gp(vcpu, 0);
+ 		return;
+ 	}
+ 
+ 	if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
+-		printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
+-		       "and a clear PE flag\n");
+ 		kvm_inject_gp(vcpu, 0);
+ 		return;
+ 	}
+@@ -409,15 +404,11 @@ void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
+ 			int cs_db, cs_l;
+ 
+ 			if (!is_pae(vcpu)) {
+-				printk(KERN_DEBUG "set_cr0: #GP, start paging "
+-				       "in long mode while PAE is disabled\n");
+ 				kvm_inject_gp(vcpu, 0);
+ 				return;
+ 			}
+ 			kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
+ 			if (cs_l) {
+-				printk(KERN_DEBUG "set_cr0: #GP, start paging "
+-				       "in long mode while CS.L == 1\n");
+ 				kvm_inject_gp(vcpu, 0);
+ 				return;
+ 
+@@ -425,8 +416,6 @@ void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
+ 		} else
+ #endif
+ 		if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
+-			printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
+-			       "reserved bits\n");
+ 			kvm_inject_gp(vcpu, 0);
+ 			return;
+ 		}
+@@ -453,28 +442,23 @@ void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
+ 	unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
+ 
+ 	if (cr4 & CR4_RESERVED_BITS) {
+-		printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
+ 		kvm_inject_gp(vcpu, 0);
+ 		return;
+ 	}
+ 
+ 	if (is_long_mode(vcpu)) {
+ 		if (!(cr4 & X86_CR4_PAE)) {
+-			printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
+-			       "in long mode\n");
+ 			kvm_inject_gp(vcpu, 0);
+ 			return;
+ 		}
+ 	} else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
+ 		   && ((cr4 ^ old_cr4) & pdptr_bits)
+ 		   && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
+-		printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
+ 		kvm_inject_gp(vcpu, 0);
+ 		return;
+ 	}
+ 
+ 	if (cr4 & X86_CR4_VMXE) {
+-		printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
+ 		kvm_inject_gp(vcpu, 0);
+ 		return;
+ 	}
+@@ -495,21 +479,16 @@ void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
+ 
+ 	if (is_long_mode(vcpu)) {
+ 		if (cr3 & CR3_L_MODE_RESERVED_BITS) {
+-			printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
+ 			kvm_inject_gp(vcpu, 0);
+ 			return;
+ 		}
+ 	} else {
+ 		if (is_pae(vcpu)) {
+ 			if (cr3 & CR3_PAE_RESERVED_BITS) {
+-				printk(KERN_DEBUG
+-				       "set_cr3: #GP, reserved bits\n");
+ 				kvm_inject_gp(vcpu, 0);
+ 				return;
+ 			}
+ 			if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
+-				printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
+-				       "reserved bits\n");
+ 				kvm_inject_gp(vcpu, 0);
+ 				return;
+ 			}
+@@ -541,7 +520,6 @@ EXPORT_SYMBOL_GPL(kvm_set_cr3);
+ void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
+ {
+ 	if (cr8 & CR8_RESERVED_BITS) {
+-		printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
+ 		kvm_inject_gp(vcpu, 0);
+ 		return;
+ 	}
+@@ -595,15 +573,12 @@ static u32 emulated_msrs[] = {
+ static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
+ {
+ 	if (efer & efer_reserved_bits) {
+-		printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
+-		       efer);
+ 		kvm_inject_gp(vcpu, 0);
+ 		return;
+ 	}
+ 
+ 	if (is_paging(vcpu)
+ 	    && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
+-		printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
+ 		kvm_inject_gp(vcpu, 0);
+ 		return;
+ 	}
+@@ -613,7 +588,6 @@ static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
+ 
+ 		feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
+ 		if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
+-			printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
+ 			kvm_inject_gp(vcpu, 0);
+ 			return;
+ 		}
+@@ -624,7 +598,6 @@ static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
+ 
+ 		feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
+ 		if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
+-			printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
+ 			kvm_inject_gp(vcpu, 0);
+ 			return;
+ 		}
+@@ -913,9 +886,13 @@ static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
+ 		if (msr >= MSR_IA32_MC0_CTL &&
+ 		    msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
+ 			u32 offset = msr - MSR_IA32_MC0_CTL;
+-			/* only 0 or all 1s can be written to IA32_MCi_CTL */
++			/* only 0 or all 1s can be written to IA32_MCi_CTL
++			 * some Linux kernels though clear bit 10 in bank 4 to
++			 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
++			 * this to avoid an uncatched #GP in the guest
++			 */
+ 			if ((offset & 0x3) == 0 &&
+-			    data != 0 && data != ~(u64)0)
++			    data != 0 && (data | (1 << 10)) != ~(u64)0)
+ 				return -1;
+ 			vcpu->arch.mce_banks[offset] = data;
+ 			break;
+@@ -2366,7 +2343,7 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
+ 				      struct kvm_dirty_log *log)
+ {
+ 	int r;
+-	int n;
++	unsigned long n;
+ 	struct kvm_memory_slot *memslot;
+ 	int is_dirty = 0;
+ 
+@@ -2382,7 +2359,7 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
+ 		kvm_mmu_slot_remove_write_access(kvm, log->slot);
+ 		spin_unlock(&kvm->mmu_lock);
+ 		memslot = &kvm->memslots[log->slot];
+-		n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
++		n = kvm_dirty_bitmap_bytes(memslot);
+ 		memset(memslot->dirty_bitmap, 0, n);
+ 	}
+ 	r = 0;
+@@ -4599,6 +4576,7 @@ int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
+ 	int ret = 0;
+ 	u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
+ 	u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
++	u32 desc_limit;
+ 
+ 	old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
+ 
+@@ -4621,7 +4599,10 @@ int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
+ 		}
+ 	}
+ 
+-	if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
++	desc_limit = get_desc_limit(&nseg_desc);
++	if (!nseg_desc.p ||
++	    ((desc_limit < 0x67 && (nseg_desc.type & 8)) ||
++	     desc_limit < 0x2b)) {
+ 		kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
+ 		return 1;
+ 	}
+diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
+index cffd754..ddef409 100644
+--- a/arch/x86/lib/Makefile
++++ b/arch/x86/lib/Makefile
+@@ -14,7 +14,7 @@ $(obj)/inat.o: $(obj)/inat-tables.c
+ 
+ clean-files := inat-tables.c
+ 
+-obj-$(CONFIG_SMP) += msr-smp.o
++obj-$(CONFIG_SMP) += msr-smp.o cache-smp.o
+ 
+ lib-y := delay.o
+ lib-y += thunk_$(BITS).o
+@@ -39,4 +39,5 @@ else
+         lib-y += thunk_64.o clear_page_64.o copy_page_64.o
+         lib-y += memmove_64.o memset_64.o
+         lib-y += copy_user_64.o rwlock_64.o copy_user_nocache_64.o
++	lib-$(CONFIG_RWSEM_XCHGADD_ALGORITHM) += rwsem_64.o
+ endif
+diff --git a/arch/x86/lib/cache-smp.c b/arch/x86/lib/cache-smp.c
+new file mode 100644
+index 0000000..a3c6688
+--- /dev/null
++++ b/arch/x86/lib/cache-smp.c
+@@ -0,0 +1,19 @@
++#include <linux/smp.h>
++#include <linux/module.h>
++
++static void __wbinvd(void *dummy)
++{
++	wbinvd();
++}
++
++void wbinvd_on_cpu(int cpu)
++{
++	smp_call_function_single(cpu, __wbinvd, NULL, 1);
++}
++EXPORT_SYMBOL(wbinvd_on_cpu);
++
++int wbinvd_on_all_cpus(void)
++{
++	return on_each_cpu(__wbinvd, NULL, 1);
++}
++EXPORT_SYMBOL(wbinvd_on_all_cpus);
+diff --git a/arch/x86/lib/rwsem_64.S b/arch/x86/lib/rwsem_64.S
+new file mode 100644
+index 0000000..15acecf
+--- /dev/null
++++ b/arch/x86/lib/rwsem_64.S
+@@ -0,0 +1,81 @@
++/*
++ * x86-64 rwsem wrappers
++ *
++ * This interfaces the inline asm code to the slow-path
++ * C routines. We need to save the call-clobbered regs
++ * that the asm does not mark as clobbered, and move the
++ * argument from %rax to %rdi.
++ *
++ * NOTE! We don't need to save %rax, because the functions
++ * will always return the semaphore pointer in %rax (which
++ * is also the input argument to these helpers)
++ *
++ * The following can clobber %rdx because the asm clobbers it:
++ *   call_rwsem_down_write_failed
++ *   call_rwsem_wake
++ * but %rdi, %rsi, %rcx, %r8-r11 always need saving.
++ */
++
++#include <linux/linkage.h>
++#include <asm/rwlock.h>
++#include <asm/alternative-asm.h>
++#include <asm/frame.h>
++#include <asm/dwarf2.h>
++
++#define save_common_regs \
++	pushq %rdi; \
++	pushq %rsi; \
++	pushq %rcx; \
++	pushq %r8; \
++	pushq %r9; \
++	pushq %r10; \
++	pushq %r11
++
++#define restore_common_regs \
++	popq %r11; \
++	popq %r10; \
++	popq %r9; \
++	popq %r8; \
++	popq %rcx; \
++	popq %rsi; \
++	popq %rdi
++
++/* Fix up special calling conventions */
++ENTRY(call_rwsem_down_read_failed)
++	save_common_regs
++	pushq %rdx
++	movq %rax,%rdi
++	call rwsem_down_read_failed
++	popq %rdx
++	restore_common_regs
++	ret
++	ENDPROC(call_rwsem_down_read_failed)
++
++ENTRY(call_rwsem_down_write_failed)
++	save_common_regs
++	movq %rax,%rdi
++	call rwsem_down_write_failed
++	restore_common_regs
++	ret
++	ENDPROC(call_rwsem_down_write_failed)
++
++ENTRY(call_rwsem_wake)
++	decw %dx    /* do nothing if still outstanding active readers */
++	jnz 1f
++	save_common_regs
++	movq %rax,%rdi
++	call rwsem_wake
++	restore_common_regs
++1:	ret
++	ENDPROC(call_rwsem_wake)
++
++/* Fix up special calling conventions */
++ENTRY(call_rwsem_downgrade_wake)
++	save_common_regs
++	pushq %rdx
++	movq %rax,%rdi
++	call rwsem_downgrade_wake
++	popq %rdx
++	restore_common_regs
++	ret
++	ENDPROC(call_rwsem_downgrade_wake)
+diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c
+index 0696d50..b02f6d8 100644
+--- a/arch/x86/pci/irq.c
++++ b/arch/x86/pci/irq.c
+@@ -590,6 +590,8 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route
+ 	case PCI_DEVICE_ID_INTEL_ICH10_1:
+ 	case PCI_DEVICE_ID_INTEL_ICH10_2:
+ 	case PCI_DEVICE_ID_INTEL_ICH10_3:
++	case PCI_DEVICE_ID_INTEL_CPT_LPC1:
++	case PCI_DEVICE_ID_INTEL_CPT_LPC2:
+ 		r->name = "PIIX/ICH";
+ 		r->get = pirq_piix_get;
+ 		r->set = pirq_piix_set;
+diff --git a/arch/x86/power/hibernate_asm_32.S b/arch/x86/power/hibernate_asm_32.S
+index b641388..ad47dae 100644
+--- a/arch/x86/power/hibernate_asm_32.S
++++ b/arch/x86/power/hibernate_asm_32.S
+@@ -27,10 +27,17 @@ ENTRY(swsusp_arch_suspend)
+ 	ret
+ 
+ ENTRY(restore_image)
++	movl	mmu_cr4_features, %ecx
+ 	movl	resume_pg_dir, %eax
+ 	subl	$__PAGE_OFFSET, %eax
+ 	movl	%eax, %cr3
+ 
++	jecxz	1f	# cr4 Pentium and higher, skip if zero
++	andl	$~(X86_CR4_PGE), %ecx
++	movl	%ecx, %cr4;  # turn off PGE
++	movl	%cr3, %eax;  # flush TLB
++	movl	%eax, %cr3
++1:
+ 	movl	restore_pblist, %edx
+ 	.p2align 4,,7
+ 
+@@ -54,16 +61,8 @@ done:
+ 	movl	$swapper_pg_dir, %eax
+ 	subl	$__PAGE_OFFSET, %eax
+ 	movl	%eax, %cr3
+-	/* Flush TLB, including "global" things (vmalloc) */
+ 	movl	mmu_cr4_features, %ecx
+ 	jecxz	1f	# cr4 Pentium and higher, skip if zero
+-	movl	%ecx, %edx
+-	andl	$~(X86_CR4_PGE), %edx
+-	movl	%edx, %cr4;  # turn off PGE
+-1:
+-	movl	%cr3, %eax;  # flush TLB
+-	movl	%eax, %cr3
+-	jecxz	1f	# cr4 Pentium and higher, skip if zero
+ 	movl	%ecx, %cr4;  # turn PGE back on
+ 1:
+ 
+diff --git a/drivers/acpi/acpica/exprep.c b/drivers/acpi/acpica/exprep.c
+index 52fec07..83b6252 100644
+--- a/drivers/acpi/acpica/exprep.c
++++ b/drivers/acpi/acpica/exprep.c
+@@ -468,6 +468,23 @@ acpi_status acpi_ex_prep_field_value(struct acpi_create_field_info *info)
+ 
+ 		acpi_ut_add_reference(obj_desc->field.region_obj);
+ 
++		/* allow full data read from EC address space */
++		if (obj_desc->field.region_obj->region.space_id ==
++			ACPI_ADR_SPACE_EC) {
++			if (obj_desc->common_field.bit_length > 8) {
++				unsigned width =
++					ACPI_ROUND_BITS_UP_TO_BYTES(
++					obj_desc->common_field.bit_length);
++				// access_bit_width is u8, don't overflow it
++				if (width > 8)
++					width = 8;
++				obj_desc->common_field.access_byte_width =
++							width;
++				obj_desc->common_field.access_bit_width =
++							8 * width;
++			}
++		}
++
+ 		ACPI_DEBUG_PRINT((ACPI_DB_BFIELD,
+ 				  "RegionField: BitOff %X, Off %X, Gran %X, Region %p\n",
+ 				  obj_desc->field.start_field_bit_offset,
+diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c
+index d6471bb..fc67d11 100644
+--- a/drivers/acpi/ec.c
++++ b/drivers/acpi/ec.c
+@@ -589,12 +589,12 @@ static u32 acpi_ec_gpe_handler(void *data)
+ 
+ static acpi_status
+ acpi_ec_space_handler(u32 function, acpi_physical_address address,
+-		      u32 bits, acpi_integer *value,
++		      u32 bits, acpi_integer *value64,
+ 		      void *handler_context, void *region_context)
+ {
+ 	struct acpi_ec *ec = handler_context;
+-	int result = 0, i;
+-	u8 temp = 0;
++	int result = 0, i, bytes = bits / 8;
++	u8 *value = (u8 *)value64;
+ 
+ 	if ((address > 0xFF) || !value || !handler_context)
+ 		return AE_BAD_PARAMETER;
+@@ -602,32 +602,15 @@ acpi_ec_space_handler(u32 function, acpi_physical_address address,
+ 	if (function != ACPI_READ && function != ACPI_WRITE)
+ 		return AE_BAD_PARAMETER;
+ 
+-	if (bits != 8 && acpi_strict)
+-		return AE_BAD_PARAMETER;
+-
+-	if (EC_FLAGS_MSI)
++	if (EC_FLAGS_MSI || bits > 8)
+ 		acpi_ec_burst_enable(ec);
+ 
+-	if (function == ACPI_READ) {
+-		result = acpi_ec_read(ec, address, &temp);
+-		*value = temp;
+-	} else {
+-		temp = 0xff & (*value);
+-		result = acpi_ec_write(ec, address, temp);
+-	}
+-
+-	for (i = 8; unlikely(bits - i > 0); i += 8) {
+-		++address;
+-		if (function == ACPI_READ) {
+-			result = acpi_ec_read(ec, address, &temp);
+-			(*value) |= ((acpi_integer)temp) << i;
+-		} else {
+-			temp = 0xff & ((*value) >> i);
+-			result = acpi_ec_write(ec, address, temp);
+-		}
+-	}
++	for (i = 0; i < bytes; ++i, ++address, ++value)
++		result = (function == ACPI_READ) ?
++			acpi_ec_read(ec, address, value) :
++			acpi_ec_write(ec, address, *value);
+ 
+-	if (EC_FLAGS_MSI)
++	if (EC_FLAGS_MSI || bits > 8)
+ 		acpi_ec_burst_disable(ec);
+ 
+ 	switch (result) {
+diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
+index 9e2feb6..462200d 100644
+--- a/drivers/ata/ahci.c
++++ b/drivers/ata/ahci.c
+@@ -570,6 +570,12 @@ static const struct pci_device_id ahci_pci_tbl[] = {
+ 	{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
+ 	{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
++	{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
++	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
++	{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
++	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
++	{ PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
++	{ PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
+ 
+ 	/* JMicron 360/1/3/5/6, match class to avoid IDE function */
+ 	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
+index 6f3f225..b5f614b 100644
+--- a/drivers/ata/ata_piix.c
++++ b/drivers/ata/ata_piix.c
+@@ -291,6 +291,14 @@ static const struct pci_device_id piix_pci_tbl[] = {
+ 	{ 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
+ 	/* SATA Controller IDE (PCH) */
+ 	{ 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
++	/* SATA Controller IDE (CPT) */
++	{ 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
++	/* SATA Controller IDE (CPT) */
++	{ 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
++	/* SATA Controller IDE (CPT) */
++	{ 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
++	/* SATA Controller IDE (CPT) */
++	{ 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
+ 	{ }	/* terminate list */
+ };
+ 
+diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
+index 6728328..2401c9c 100644
+--- a/drivers/ata/libata-core.c
++++ b/drivers/ata/libata-core.c
+@@ -4348,6 +4348,9 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
+ 	{ "HTS541080G9SA00",    "MB4OC60D",     ATA_HORKAGE_NONCQ, },
+ 	{ "HTS541010G9SA00",    "MBZOC60D",     ATA_HORKAGE_NONCQ, },
+ 
++	/* https://bugzilla.kernel.org/show_bug.cgi?id=15573 */
++	{ "C300-CTFDDAC128MAG",	"0001",		ATA_HORKAGE_NONCQ, },
++
+ 	/* devices which puke on READ_NATIVE_MAX */
+ 	{ "HDS724040KLSA80",	"KFAOA20N",	ATA_HORKAGE_BROKEN_HPA, },
+ 	{ "WDC WD3200JD-00KLB0", "WD-WCAMR1130137", ATA_HORKAGE_BROKEN_HPA },
+diff --git a/drivers/ata/pata_via.c b/drivers/ata/pata_via.c
+index be7c395..ad64750 100644
+--- a/drivers/ata/pata_via.c
++++ b/drivers/ata/pata_via.c
+@@ -697,6 +697,7 @@ static const struct pci_device_id via[] = {
+ 	{ PCI_VDEVICE(VIA, 0x3164), },
+ 	{ PCI_VDEVICE(VIA, 0x5324), },
+ 	{ PCI_VDEVICE(VIA, 0xC409), VIA_IDFLAG_SINGLE },
++	{ PCI_VDEVICE(VIA, 0x9001), VIA_IDFLAG_SINGLE },
+ 
+ 	{ },
+ };
+diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
+index 3999a5f..8a713f1 100644
+--- a/drivers/char/agp/intel-agp.c
++++ b/drivers/char/agp/intel-agp.c
+@@ -8,6 +8,7 @@
+ #include <linux/kernel.h>
+ #include <linux/pagemap.h>
+ #include <linux/agp_backend.h>
++#include <asm/smp.h>
+ #include "agp.h"
+ 
+ /*
+@@ -815,12 +816,6 @@ static void intel_i830_setup_flush(void)
+ 		intel_i830_fini_flush();
+ }
+ 
+-static void
+-do_wbinvd(void *null)
+-{
+-	wbinvd();
+-}
+-
+ /* The chipset_flush interface needs to get data that has already been
+  * flushed out of the CPU all the way out to main memory, because the GPU
+  * doesn't snoop those buffers.
+@@ -837,12 +832,10 @@ static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
+ 
+ 	memset(pg, 0, 1024);
+ 
+-	if (cpu_has_clflush) {
++	if (cpu_has_clflush)
+ 		clflush_cache_range(pg, 1024);
+-	} else {
+-		if (on_each_cpu(do_wbinvd, NULL, 1) != 0)
+-			printk(KERN_ERR "Timed out waiting for cache flush.\n");
+-	}
++	else if (wbinvd_on_all_cpus() != 0)
++		printk(KERN_ERR "Timed out waiting for cache flush.\n");
+ }
+ 
+ /* The intel i830 automatically initializes the agp aperture during POST.
+diff --git a/drivers/char/raw.c b/drivers/char/raw.c
+index 64acd05..9abc3a1 100644
+--- a/drivers/char/raw.c
++++ b/drivers/char/raw.c
+@@ -247,6 +247,7 @@ static const struct file_operations raw_fops = {
+ 	.aio_read = 	generic_file_aio_read,
+ 	.write	=	do_sync_write,
+ 	.aio_write =	blkdev_aio_write,
++	.fsync	=	block_fsync,
+ 	.open	=	raw_open,
+ 	.release=	raw_release,
+ 	.ioctl	=	raw_ioctl,
+diff --git a/drivers/char/tty_io.c b/drivers/char/tty_io.c
+index dcb9083..76253cf 100644
+--- a/drivers/char/tty_io.c
++++ b/drivers/char/tty_io.c
+@@ -1423,6 +1423,8 @@ static void release_one_tty(struct work_struct *work)
+ 	list_del_init(&tty->tty_files);
+ 	file_list_unlock();
+ 
++	put_pid(tty->pgrp);
++	put_pid(tty->session);
+ 	free_tty_struct(tty);
+ }
+ 
+diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
+index 7d0f00a..99907c3 100644
+--- a/drivers/gpu/drm/drm_crtc_helper.c
++++ b/drivers/gpu/drm/drm_crtc_helper.c
+@@ -104,6 +104,7 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector,
+ 	if (connector->status == connector_status_disconnected) {
+ 		DRM_DEBUG_KMS("%s is disconnected\n",
+ 			  drm_get_connector_name(connector));
++		drm_mode_connector_update_edid_property(connector, NULL);
+ 		goto prune;
+ 	}
+ 
+diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
+index ab6c973..bfd0e4a 100644
+--- a/drivers/gpu/drm/drm_edid.c
++++ b/drivers/gpu/drm/drm_edid.c
+@@ -85,6 +85,8 @@ static struct edid_quirk {
+ 
+ 	/* Envision Peripherals, Inc. EN-7100e */
+ 	{ "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
++	/* Envision EN2028 */
++	{ "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
+ 
+ 	/* Funai Electronics PM36B */
+ 	{ "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
+@@ -707,15 +709,6 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
+ 	mode->vsync_end = mode->vsync_start + vsync_pulse_width;
+ 	mode->vtotal = mode->vdisplay + vblank;
+ 
+-	/* perform the basic check for the detailed timing */
+-	if (mode->hsync_end > mode->htotal ||
+-		mode->vsync_end > mode->vtotal) {
+-		drm_mode_destroy(dev, mode);
+-		DRM_DEBUG_KMS("Incorrect detailed timing. "
+-				"Sync is beyond the blank.\n");
+-		return NULL;
+-	}
+-
+ 	/* Some EDIDs have bogus h/vtotal values */
+ 	if (mode->hsync_end > mode->htotal)
+ 		mode->htotal = mode->hsync_end + 1;
+diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
+index 08d14df..4804872 100644
+--- a/drivers/gpu/drm/drm_fops.c
++++ b/drivers/gpu/drm/drm_fops.c
+@@ -140,14 +140,16 @@ int drm_open(struct inode *inode, struct file *filp)
+ 		spin_unlock(&dev->count_lock);
+ 	}
+ out:
+-	mutex_lock(&dev->struct_mutex);
+-	if (minor->type == DRM_MINOR_LEGACY) {
+-		BUG_ON((dev->dev_mapping != NULL) &&
+-			(dev->dev_mapping != inode->i_mapping));
+-		if (dev->dev_mapping == NULL)
+-			dev->dev_mapping = inode->i_mapping;
++	if (!retcode) {
++		mutex_lock(&dev->struct_mutex);
++		if (minor->type == DRM_MINOR_LEGACY) {
++			if (dev->dev_mapping == NULL)
++				dev->dev_mapping = inode->i_mapping;
++			else if (dev->dev_mapping != inode->i_mapping)
++				retcode = -ENODEV;
++		}
++		mutex_unlock(&dev->struct_mutex);
+ 	}
+-	mutex_unlock(&dev->struct_mutex);
+ 
+ 	return retcode;
+ }
+diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
+index 93031a7..1238bc9 100644
+--- a/drivers/gpu/drm/i915/intel_lvds.c
++++ b/drivers/gpu/drm/i915/intel_lvds.c
+@@ -899,6 +899,14 @@ static const struct dmi_system_id intel_no_lvds[] = {
+ 			DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
+ 		},
+ 	},
++	{
++		.callback = intel_no_lvds_dmi_callback,
++		.ident = "Clientron U800",
++		.matches = {
++			DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
++			DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
++		},
++	},
+ 
+ 	{ }	/* terminating entry */
+ };
+diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
+index d75788f..b1f929d 100644
+--- a/drivers/gpu/drm/radeon/atom.c
++++ b/drivers/gpu/drm/radeon/atom.c
+@@ -881,11 +881,16 @@ static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
+ 	uint8_t attr = U8((*ptr)++), shift;
+ 	uint32_t saved, dst;
+ 	int dptr = *ptr;
++	uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
+ 	SDEBUG("   dst: ");
+ 	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
++	/* op needs to full dst value */
++	dst = saved;
+ 	shift = atom_get_src(ctx, attr, ptr);
+ 	SDEBUG("   shift: %d\n", shift);
+ 	dst <<= shift;
++	dst &= atom_arg_mask[dst_align];
++	dst >>= atom_arg_shift[dst_align];
+ 	SDEBUG("   dst: ");
+ 	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+ }
+@@ -895,11 +900,16 @@ static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
+ 	uint8_t attr = U8((*ptr)++), shift;
+ 	uint32_t saved, dst;
+ 	int dptr = *ptr;
++	uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
+ 	SDEBUG("   dst: ");
+ 	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
++	/* op needs to full dst value */
++	dst = saved;
+ 	shift = atom_get_src(ctx, attr, ptr);
+ 	SDEBUG("   shift: %d\n", shift);
+ 	dst >>= shift;
++	dst &= atom_arg_mask[dst_align];
++	dst >>= atom_arg_shift[dst_align];
+ 	SDEBUG("   dst: ");
+ 	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+ }
+diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
+index 43b55a0..5bdfaf2 100644
+--- a/drivers/gpu/drm/radeon/r300.c
++++ b/drivers/gpu/drm/radeon/r300.c
+@@ -364,11 +364,12 @@ void r300_gpu_init(struct radeon_device *rdev)
+ 
+ 	r100_hdp_reset(rdev);
+ 	/* FIXME: rv380 one pipes ? */
+-	if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
++	if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
++	    (rdev->family == CHIP_R350)) {
+ 		/* r300,r350 */
+ 		rdev->num_gb_pipes = 2;
+ 	} else {
+-		/* rv350,rv370,rv380 */
++		/* rv350,rv370,rv380,r300 AD */
+ 		rdev->num_gb_pipes = 1;
+ 	}
+ 	rdev->num_z_pipes = 1;
+diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
+index e7b1944..81b832e 100644
+--- a/drivers/gpu/drm/radeon/radeon_combios.c
++++ b/drivers/gpu/drm/radeon/radeon_combios.c
+@@ -670,7 +670,9 @@ struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
+ 			dac = RBIOS8(dac_info + 0x3) & 0xf;
+ 			p_dac->ps2_pdac_adj = (bg << 8) | (dac);
+ 		}
+-		found = 1;
++		/* if the values are all zeros, use the table */
++		if (p_dac->ps2_pdac_adj)
++			found = 1;
+ 	}
+ 
+ out:
+@@ -812,7 +814,9 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
+ 			bg = RBIOS8(dac_info + 0x10) & 0xf;
+ 			dac = RBIOS8(dac_info + 0x11) & 0xf;
+ 			tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
+-			found = 1;
++			/* if the values are all zeros, use the table */
++			if (tv_dac->ps2_tvdac_adj)
++				found = 1;
+ 		} else if (rev > 1) {
+ 			bg = RBIOS8(dac_info + 0xc) & 0xf;
+ 			dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
+@@ -825,7 +829,9 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
+ 			bg = RBIOS8(dac_info + 0xe) & 0xf;
+ 			dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
+ 			tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
+-			found = 1;
++			/* if the values are all zeros, use the table */
++			if (tv_dac->ps2_tvdac_adj)
++				found = 1;
+ 		}
+ 		tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
+ 	}
+@@ -842,7 +848,9 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
+ 				    (bg << 16) | (dac << 20);
+ 				tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
+ 				tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
+-				found = 1;
++				/* if the values are all zeros, use the table */
++				if (tv_dac->ps2_tvdac_adj)
++					found = 1;
+ 			} else {
+ 				bg = RBIOS8(dac_info + 0x4) & 0xf;
+ 				dac = RBIOS8(dac_info + 0x5) & 0xf;
+@@ -850,7 +858,9 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
+ 				    (bg << 16) | (dac << 20);
+ 				tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
+ 				tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
+-				found = 1;
++				/* if the values are all zeros, use the table */
++				if (tv_dac->ps2_tvdac_adj)
++					found = 1;
+ 			}
+ 		} else {
+ 			DRM_INFO("No TV DAC info found in BIOS\n");
+diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
+index 65f8194..2bdfbcd 100644
+--- a/drivers/gpu/drm/radeon/radeon_connectors.c
++++ b/drivers/gpu/drm/radeon/radeon_connectors.c
+@@ -162,12 +162,14 @@ radeon_connector_analog_encoder_conflict_solve(struct drm_connector *connector,
+ {
+ 	struct drm_device *dev = connector->dev;
+ 	struct drm_connector *conflict;
++	struct radeon_connector *radeon_conflict;
+ 	int i;
+ 
+ 	list_for_each_entry(conflict, &dev->mode_config.connector_list, head) {
+ 		if (conflict == connector)
+ 			continue;
+ 
++		radeon_conflict = to_radeon_connector(conflict);
+ 		for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
+ 			if (conflict->encoder_ids[i] == 0)
+ 				break;
+@@ -177,6 +179,9 @@ radeon_connector_analog_encoder_conflict_solve(struct drm_connector *connector,
+ 				if (conflict->status != connector_status_connected)
+ 					continue;
+ 
++				if (radeon_conflict->use_digital)
++					continue;
++
+ 				if (priority == true) {
+ 					DRM_INFO("1: conflicting encoders switching off %s\n", drm_get_connector_name(conflict));
+ 					DRM_INFO("in favor of %s\n", drm_get_connector_name(connector));
+@@ -315,7 +320,7 @@ int radeon_connector_set_property(struct drm_connector *connector, struct drm_pr
+ 		radeon_encoder = to_radeon_encoder(encoder);
+ 		if (!radeon_encoder->enc_priv)
+ 			return 0;
+-		if (rdev->is_atom_bios) {
++		if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) {
+ 			struct radeon_encoder_atom_dac *dac_int;
+ 			dac_int = radeon_encoder->enc_priv;
+ 			dac_int->tv_std = val;
+diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
+index 06123ba..f129bbb 100644
+--- a/drivers/gpu/drm/radeon/radeon_cp.c
++++ b/drivers/gpu/drm/radeon/radeon_cp.c
+@@ -417,8 +417,9 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
+ 	return -EBUSY;
+ }
+ 
+-static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
++static void radeon_init_pipes(struct drm_device *dev)
+ {
++	drm_radeon_private_t *dev_priv = dev->dev_private;
+ 	uint32_t gb_tile_config, gb_pipe_sel = 0;
+ 
+ 	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
+@@ -436,11 +437,12 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
+ 		dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
+ 	} else {
+ 		/* R3xx */
+-		if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
++		if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
++		     dev->pdev->device != 0x4144) ||
+ 		    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
+ 			dev_priv->num_gb_pipes = 2;
+ 		} else {
+-			/* R3Vxx */
++			/* RV3xx/R300 AD */
+ 			dev_priv->num_gb_pipes = 1;
+ 		}
+ 	}
+@@ -736,7 +738,7 @@ static int radeon_do_engine_reset(struct drm_device * dev)
+ 
+ 	/* setup the raster pipes */
+ 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
+-	    radeon_init_pipes(dev_priv);
++	    radeon_init_pipes(dev);
+ 
+ 	/* Reset the CP ring */
+ 	radeon_do_cp_reset(dev_priv);
+diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
+index e9d0850..9933c2c 100644
+--- a/drivers/gpu/drm/radeon/radeon_cs.c
++++ b/drivers/gpu/drm/radeon/radeon_cs.c
+@@ -193,11 +193,13 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
+ 		radeon_bo_list_fence(&parser->validated, parser->ib->fence);
+ 	}
+ 	radeon_bo_list_unreserve(&parser->validated);
+-	for (i = 0; i < parser->nrelocs; i++) {
+-		if (parser->relocs[i].gobj) {
+-			mutex_lock(&parser->rdev->ddev->struct_mutex);
+-			drm_gem_object_unreference(parser->relocs[i].gobj);
+-			mutex_unlock(&parser->rdev->ddev->struct_mutex);
++	if (parser->relocs != NULL) {
++		for (i = 0; i < parser->nrelocs; i++) {
++			if (parser->relocs[i].gobj) {
++				mutex_lock(&parser->rdev->ddev->struct_mutex);
++				drm_gem_object_unreference(parser->relocs[i].gobj);
++				mutex_unlock(&parser->rdev->ddev->struct_mutex);
++			}
+ 		}
+ 	}
+ 	kfree(parser->track);
+@@ -246,7 +248,8 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
+ 	}
+ 	r = radeon_cs_parser_relocs(&parser);
+ 	if (r) {
+-		DRM_ERROR("Failed to parse relocation !\n");
++		if (r != -ERESTARTSYS)
++			DRM_ERROR("Failed to parse relocation %d!\n", r);
+ 		radeon_cs_parser_fini(&parser, r);
+ 		mutex_unlock(&rdev->cs_mutex);
+ 		return r;
+diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
+index 768b150..509ba3f 100644
+--- a/drivers/gpu/drm/radeon/radeon_device.c
++++ b/drivers/gpu/drm/radeon/radeon_device.c
+@@ -655,6 +655,14 @@ int radeon_device_init(struct radeon_device *rdev,
+ 		return r;
+ 	radeon_check_arguments(rdev);
+ 
++	/* all of the newer IGP chips have an internal gart
++	 * However some rs4xx report as AGP, so remove that here.
++	 */
++	if ((rdev->family >= CHIP_RS400) &&
++	    (rdev->flags & RADEON_IS_IGP)) {
++		rdev->flags &= ~RADEON_IS_AGP;
++	}
++
+ 	if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
+ 		radeon_agp_disable(rdev);
+ 	}
+diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
+index 3c91724..7626bd5 100644
+--- a/drivers/gpu/drm/radeon/radeon_encoders.c
++++ b/drivers/gpu/drm/radeon/radeon_encoders.c
+@@ -1276,8 +1276,12 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
+ 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
+ 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+ 		atombios_dac_setup(encoder, ATOM_ENABLE);
+-		if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
+-			atombios_tv_setup(encoder, ATOM_ENABLE);
++		if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
++			if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
++				atombios_tv_setup(encoder, ATOM_ENABLE);
++			else
++				atombios_tv_setup(encoder, ATOM_DISABLE);
++		}
+ 		break;
+ 	}
+ 	atombios_apply_encoder_quirks(encoder, adjusted_mode);
+diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
+index 417684d..f2ed27c 100644
+--- a/drivers/gpu/drm/radeon/radeon_legacy_tv.c
++++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
+@@ -57,6 +57,10 @@
+ #define NTSC_TV_PLL_N_14 693
+ #define NTSC_TV_PLL_P_14 7
+ 
++#define PAL_TV_PLL_M_14 19
++#define PAL_TV_PLL_N_14 353
++#define PAL_TV_PLL_P_14 5
++
+ #define VERT_LEAD_IN_LINES 2
+ #define FRAC_BITS 0xe
+ #define FRAC_MASK 0x3fff
+@@ -205,9 +209,24 @@ static const struct radeon_tv_mode_constants available_tv_modes[] = {
+ 		630627,             /* defRestart */
+ 		347,                /* crtcPLL_N */
+ 		14,                 /* crtcPLL_M */
+-			8,                  /* crtcPLL_postDiv */
++		8,                  /* crtcPLL_postDiv */
+ 		1022,               /* pixToTV */
+ 	},
++	{ /* PAL timing for 14 Mhz ref clk */
++		800,                /* horResolution */
++		600,                /* verResolution */
++		TV_STD_PAL,         /* standard */
++		1131,               /* horTotal */
++		742,                /* verTotal */
++		813,                /* horStart */
++		840,                /* horSyncStart */
++		633,                /* verSyncStart */
++		708369,             /* defRestart */
++		211,                /* crtcPLL_N */
++		9,                  /* crtcPLL_M */
++		8,                  /* crtcPLL_postDiv */
++		759,                /* pixToTV */
++	},
+ };
+ 
+ #define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes)
+@@ -242,7 +261,7 @@ static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(stru
+ 		if (pll->reference_freq == 2700)
+ 			const_ptr = &available_tv_modes[1];
+ 		else
+-			const_ptr = &available_tv_modes[1]; /* FIX ME */
++			const_ptr = &available_tv_modes[3];
+ 	}
+ 	return const_ptr;
+ }
+@@ -685,9 +704,9 @@ void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
+ 			n = PAL_TV_PLL_N_27;
+ 			p = PAL_TV_PLL_P_27;
+ 		} else {
+-			m = PAL_TV_PLL_M_27;
+-			n = PAL_TV_PLL_N_27;
+-			p = PAL_TV_PLL_P_27;
++			m = PAL_TV_PLL_M_14;
++			n = PAL_TV_PLL_N_14;
++			p = PAL_TV_PLL_P_14;
+ 		}
+ 	}
+ 
+diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
+index c381856..a27c09f 100644
+--- a/drivers/gpu/drm/radeon/rs600.c
++++ b/drivers/gpu/drm/radeon/rs600.c
+@@ -175,7 +175,7 @@ void rs600_gart_tlb_flush(struct radeon_device *rdev)
+ 	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
+ 
+ 	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
+-	tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
++	tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
+ 	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
+ 
+ 	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
+diff --git a/drivers/hid/hid-gyration.c b/drivers/hid/hid-gyration.c
+index cab13e8..62416e6 100644
+--- a/drivers/hid/hid-gyration.c
++++ b/drivers/hid/hid-gyration.c
+@@ -53,10 +53,13 @@ static int gyration_input_mapping(struct hid_device *hdev, struct hid_input *hi,
+ static int gyration_event(struct hid_device *hdev, struct hid_field *field,
+ 		struct hid_usage *usage, __s32 value)
+ {
+-	struct input_dev *input = field->hidinput->input;
++
++	if (!(hdev->claimed & HID_CLAIMED_INPUT) || !field->hidinput)
++		return 0;
+ 
+ 	if ((usage->hid & HID_USAGE_PAGE) == HID_UP_GENDESK &&
+ 			(usage->hid & 0xff) == 0x82) {
++		struct input_dev *input = field->hidinput->input;
+ 		input_event(input, usage->type, usage->code, 1);
+ 		input_sync(input);
+ 		input_event(input, usage->type, usage->code, 0);
+diff --git a/drivers/hwmon/sht15.c b/drivers/hwmon/sht15.c
+index 864a371..fbc997e 100644
+--- a/drivers/hwmon/sht15.c
++++ b/drivers/hwmon/sht15.c
+@@ -302,13 +302,13 @@ error_ret:
+  **/
+ static inline int sht15_calc_temp(struct sht15_data *data)
+ {
+-	int d1 = 0;
++	int d1 = temppoints[0].d1;
+ 	int i;
+ 
+-	for (i = 1; i < ARRAY_SIZE(temppoints); i++)
++	for (i = ARRAY_SIZE(temppoints) - 1; i > 0; i--)
+ 		/* Find pointer to interpolate */
+ 		if (data->supply_uV > temppoints[i - 1].vdd) {
+-			d1 = (data->supply_uV/1000 - temppoints[i - 1].vdd)
++			d1 = (data->supply_uV - temppoints[i - 1].vdd)
+ 				* (temppoints[i].d1 - temppoints[i - 1].d1)
+ 				/ (temppoints[i].vdd - temppoints[i - 1].vdd)
+ 				+ temppoints[i - 1].d1;
+@@ -541,7 +541,12 @@ static int __devinit sht15_probe(struct platform_device *pdev)
+ /* If a regulator is available, query what the supply voltage actually is!*/
+ 	data->reg = regulator_get(data->dev, "vcc");
+ 	if (!IS_ERR(data->reg)) {
+-		data->supply_uV = regulator_get_voltage(data->reg);
++		int voltage;
++
++		voltage = regulator_get_voltage(data->reg);
++		if (voltage)
++			data->supply_uV = voltage;
++
+ 		regulator_enable(data->reg);
+ 		/* setup a notifier block to update this if another device
+ 		 *  causes the voltage to change */
+diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
+index 5f318ce..cb9f95c 100644
+--- a/drivers/i2c/busses/Kconfig
++++ b/drivers/i2c/busses/Kconfig
+@@ -77,7 +77,7 @@ config I2C_AMD8111
+ 	  will be called i2c-amd8111.
+ 
+ config I2C_I801
+-	tristate "Intel 82801 (ICH)"
++	tristate "Intel 82801 (ICH/PCH)"
+ 	depends on PCI
+ 	help
+ 	  If you say yes to this option, support will be included for the Intel
+@@ -97,7 +97,8 @@ config I2C_I801
+ 	    ICH9
+ 	    Tolapai
+ 	    ICH10
+-	    PCH
++	    3400/5 Series (PCH)
++	    Cougar Point (PCH)
+ 
+ 	  This driver can also be built as a module.  If so, the module
+ 	  will be called i2c-i801.
+diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
+index 5574be2..e361da7 100644
+--- a/drivers/i2c/busses/i2c-i801.c
++++ b/drivers/i2c/busses/i2c-i801.c
+@@ -41,7 +41,8 @@
+   Tolapai               0x5032     32     hard     yes     yes     yes
+   ICH10                 0x3a30     32     hard     yes     yes     yes
+   ICH10                 0x3a60     32     hard     yes     yes     yes
+-  PCH                   0x3b30     32     hard     yes     yes     yes
++  3400/5 Series (PCH)   0x3b30     32     hard     yes     yes     yes
++  Cougar Point (PCH)    0x1c22     32     hard     yes     yes     yes
+ 
+   Features supported by this driver:
+   Software PEC                     no
+@@ -580,6 +581,7 @@ static struct pci_device_id i801_ids[] = {
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PCH_SMBUS) },
++	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CPT_SMBUS) },
+ 	{ 0, }
+ };
+ 
+@@ -709,6 +711,7 @@ static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id
+ 	case PCI_DEVICE_ID_INTEL_ICH10_4:
+ 	case PCI_DEVICE_ID_INTEL_ICH10_5:
+ 	case PCI_DEVICE_ID_INTEL_PCH_SMBUS:
++	case PCI_DEVICE_ID_INTEL_CPT_SMBUS:
+ 		i801_features |= FEATURE_I2C_BLOCK_READ;
+ 		/* fall through */
+ 	case PCI_DEVICE_ID_INTEL_82801DB_3:
+diff --git a/drivers/infiniband/ulp/ipoib/ipoib_cm.c b/drivers/infiniband/ulp/ipoib/ipoib_cm.c
+index 30bdf42..f8302c2 100644
+--- a/drivers/infiniband/ulp/ipoib/ipoib_cm.c
++++ b/drivers/infiniband/ulp/ipoib/ipoib_cm.c
+@@ -752,6 +752,8 @@ void ipoib_cm_send(struct net_device *dev, struct sk_buff *skb, struct ipoib_cm_
+ 		if (++priv->tx_outstanding == ipoib_sendq_size) {
+ 			ipoib_dbg(priv, "TX ring 0x%x full, stopping kernel net queue\n",
+ 				  tx->qp->qp_num);
++			if (ib_req_notify_cq(priv->send_cq, IB_CQ_NEXT_COMP))
++				ipoib_warn(priv, "request notify on send CQ failed\n");
+ 			netif_stop_queue(dev);
+ 		}
+ 	}
+diff --git a/drivers/input/sparse-keymap.c b/drivers/input/sparse-keymap.c
+index fbd3987..e8d65b3 100644
+--- a/drivers/input/sparse-keymap.c
++++ b/drivers/input/sparse-keymap.c
+@@ -161,7 +161,7 @@ int sparse_keymap_setup(struct input_dev *dev,
+ 	return 0;
+ 
+  err_out:
+-	kfree(keymap);
++	kfree(map);
+ 	return error;
+ 
+ }
+diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c
+index 072f33b..e53ddc5 100644
+--- a/drivers/input/tablet/wacom_sys.c
++++ b/drivers/input/tablet/wacom_sys.c
+@@ -644,13 +644,15 @@ static int wacom_resume(struct usb_interface *intf)
+ 	int rv;
+ 
+ 	mutex_lock(&wacom->lock);
+-	if (wacom->open) {
++
++	/* switch to wacom mode first */