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commit: 3e9b25c208079a6f5463930e65512a557caa9d9b |
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Author: Mike Pagano <mpagano <AT> gentoo <DOT> org> |
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AuthorDate: Sat Jan 29 17:47:39 2022 +0000 |
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Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org> |
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CommitDate: Sat Jan 29 17:47:39 2022 +0000 |
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URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=3e9b25c2 |
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|
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Linux patch 4.4.301 |
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|
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Signed-off-by: Mike Pagano <mpagano <AT> gentoo.org> |
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|
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0000_README | 4 ++ |
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1300_linux-4.4.301.patch | 180 +++++++++++++++++++++++++++++++++++++++++++++++ |
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2 files changed, 184 insertions(+) |
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|
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diff --git a/0000_README b/0000_README |
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index 53822338..c28b7561 100644 |
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--- a/0000_README |
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+++ b/0000_README |
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@@ -1243,6 +1243,10 @@ Patch: 1299_linux-4.4.300.patch |
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From: http://www.kernel.org |
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Desc: Linux 4.4.300 |
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|
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+Patch: 1300_linux-4.4.301.patch |
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+From: http://www.kernel.org |
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+Desc: Linux 4.4.301 |
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+ |
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Patch: 1500_XATTR_USER_PREFIX.patch |
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From: https://bugs.gentoo.org/show_bug.cgi?id=470644 |
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Desc: Support for namespace user.pax.* on tmpfs. |
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|
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diff --git a/1300_linux-4.4.301.patch b/1300_linux-4.4.301.patch |
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new file mode 100644 |
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index 00000000..5ccaefc1 |
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--- /dev/null |
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+++ b/1300_linux-4.4.301.patch |
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@@ -0,0 +1,180 @@ |
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+diff --git a/Makefile b/Makefile |
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+index 29bb2f87dd2ad..3bf23154499e6 100644 |
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+--- a/Makefile |
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++++ b/Makefile |
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+@@ -1,6 +1,6 @@ |
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+ VERSION = 4 |
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+ PATCHLEVEL = 4 |
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+-SUBLEVEL = 300 |
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++SUBLEVEL = 301 |
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+ EXTRAVERSION = |
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+ NAME = Blurry Fish Butt |
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+ |
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+diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h |
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+index adbbcaf14af67..8d7d102af52f4 100644 |
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+--- a/drivers/gpu/drm/i915/i915_drv.h |
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++++ b/drivers/gpu/drm/i915/i915_drv.h |
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+@@ -1719,6 +1719,8 @@ struct drm_i915_private { |
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+ |
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+ struct intel_uncore uncore; |
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+ |
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++ struct mutex tlb_invalidate_lock; |
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++ |
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+ struct i915_virtual_gpu vgpu; |
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+ |
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+ struct intel_guc guc; |
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+@@ -2066,6 +2068,9 @@ struct drm_i915_gem_object { |
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+ */ |
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+ unsigned int active:I915_NUM_RINGS; |
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+ |
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++ unsigned long flags; |
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++#define I915_BO_WAS_BOUND_BIT 0 |
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++ |
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+ /** |
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+ * This is set if the object has been written to since last bound |
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+ * to the GTT |
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+diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c |
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+index f56af0aaafde5..ffce88930371e 100644 |
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+--- a/drivers/gpu/drm/i915/i915_gem.c |
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++++ b/drivers/gpu/drm/i915/i915_gem.c |
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+@@ -2212,6 +2212,85 @@ i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
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+ kfree(obj->pages); |
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+ } |
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+ |
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++#define _wait_for_us(COND, US, W) ({ \ |
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++ unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \ |
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++ int ret__; \ |
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++ for (;;) { \ |
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++ bool expired__ = time_after(jiffies, timeout__); \ |
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++ if (COND) { \ |
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++ ret__ = 0; \ |
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++ break; \ |
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++ } \ |
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++ if (expired__) { \ |
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++ ret__ = -ETIMEDOUT; \ |
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++ break; \ |
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++ } \ |
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++ usleep_range((W), (W)*2); \ |
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++ } \ |
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++ ret__; \ |
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++}) |
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++ |
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++static int |
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++__intel_wait_for_register_fw(struct drm_i915_private *dev_priv, |
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++ u32 reg, |
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++ const u32 mask, |
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++ const u32 value, |
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++ const unsigned int timeout_us, |
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++ const unsigned int timeout_ms) |
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++{ |
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++#define done ((I915_READ_FW(reg) & mask) == value) |
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++ int ret = _wait_for_us(done, timeout_us, 2); |
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++ if (ret) |
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++ ret = wait_for(done, timeout_ms); |
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++ return ret; |
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++#undef done |
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++} |
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++ |
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++static void invalidate_tlbs(struct drm_i915_private *dev_priv) |
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++{ |
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++ static const u32 gen8_regs[] = { |
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++ [RCS] = GEN8_RTCR, |
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++ [VCS] = GEN8_M1TCR, |
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++ [VCS2] = GEN8_M2TCR, |
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++ [VECS] = GEN8_VTCR, |
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++ [BCS] = GEN8_BTCR, |
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++ }; |
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++ enum intel_ring_id id; |
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++ |
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++ if (INTEL_INFO(dev_priv)->gen < 8) |
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++ return; |
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++ |
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++ mutex_lock(&dev_priv->tlb_invalidate_lock); |
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++ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
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++ |
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++ for (id = 0; id < I915_NUM_RINGS; id++) { |
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++ struct intel_engine_cs *engine = &dev_priv->ring[id]; |
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++ /* |
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++ * HW architecture suggest typical invalidation time at 40us, |
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++ * with pessimistic cases up to 100us and a recommendation to |
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++ * cap at 1ms. We go a bit higher just in case. |
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++ */ |
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++ const unsigned int timeout_us = 100; |
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++ const unsigned int timeout_ms = 4; |
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++ |
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++ if (!intel_ring_initialized(engine)) |
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++ continue; |
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++ |
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++ if (WARN_ON_ONCE(id >= ARRAY_SIZE(gen8_regs) || !gen8_regs[id])) |
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++ continue; |
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++ |
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++ I915_WRITE_FW(gen8_regs[id], 1); |
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++ if (__intel_wait_for_register_fw(dev_priv, |
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++ gen8_regs[id], 1, 0, |
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++ timeout_us, timeout_ms)) |
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++ DRM_ERROR_RATELIMITED("%s TLB invalidation did not complete in %ums!\n", |
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++ engine->name, timeout_ms); |
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++ } |
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++ |
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++ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
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++ mutex_unlock(&dev_priv->tlb_invalidate_lock); |
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++} |
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++ |
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+ int |
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+ i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
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+ { |
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+@@ -2230,6 +2309,14 @@ i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
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+ * lists early. */ |
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+ list_del(&obj->global_list); |
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+ |
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++ if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, &obj->flags)) { |
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++ struct drm_i915_private *i915 = to_i915(obj->base.dev); |
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++ |
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++ intel_runtime_pm_get(i915); |
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++ invalidate_tlbs(i915); |
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++ intel_runtime_pm_put(i915); |
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++ } |
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++ |
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+ ops->put_pages(obj); |
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+ obj->pages = NULL; |
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+ |
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+@@ -5050,6 +5137,8 @@ i915_gem_load(struct drm_device *dev) |
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+ i915_gem_shrinker_init(dev_priv); |
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+ |
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+ mutex_init(&dev_priv->fb_tracking.lock); |
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++ |
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++ mutex_init(&dev_priv->tlb_invalidate_lock); |
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+ } |
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+ |
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+ void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
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+diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c |
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+index 65a53ee398b8e..b2bb0b268ea9c 100644 |
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+--- a/drivers/gpu/drm/i915/i915_gem_gtt.c |
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++++ b/drivers/gpu/drm/i915/i915_gem_gtt.c |
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+@@ -3538,6 +3538,9 @@ int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, |
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+ |
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+ vma->bound |= bind_flags; |
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+ |
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++ if (vma->obj) |
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++ set_bit(I915_BO_WAS_BOUND_BIT, &vma->obj->flags); |
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++ |
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+ return 0; |
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+ } |
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+ |
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+diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h |
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+index 603d8cdfc5f1f..33a9b80da5dc8 100644 |
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+--- a/drivers/gpu/drm/i915/i915_reg.h |
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++++ b/drivers/gpu/drm/i915/i915_reg.h |
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+@@ -1592,6 +1592,12 @@ enum skl_disp_power_wells { |
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+ |
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+ #define GEN7_TLB_RD_ADDR 0x4700 |
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+ |
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++#define GEN8_RTCR 0x4260 |
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++#define GEN8_M1TCR 0x4264 |
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++#define GEN8_M2TCR 0x4268 |
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++#define GEN8_BTCR 0x426c |
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++#define GEN8_VTCR 0x4270 |
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++ |
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+ #if 0 |
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+ #define PRB0_TAIL 0x02030 |
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+ #define PRB0_HEAD 0x02034 |