Gentoo Archives: gentoo-commits

From: Mike Pagano <mpagano@g.o>
To: gentoo-commits@l.g.o
Subject: [gentoo-commits] proj/linux-patches:4.4 commit in: /
Date: Sat, 29 Jan 2022 17:47:53
Message-Id: 1643478459.3e9b25c208079a6f5463930e65512a557caa9d9b.mpagano@gentoo
1 commit: 3e9b25c208079a6f5463930e65512a557caa9d9b
2 Author: Mike Pagano <mpagano <AT> gentoo <DOT> org>
3 AuthorDate: Sat Jan 29 17:47:39 2022 +0000
4 Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org>
5 CommitDate: Sat Jan 29 17:47:39 2022 +0000
6 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=3e9b25c2
7
8 Linux patch 4.4.301
9
10 Signed-off-by: Mike Pagano <mpagano <AT> gentoo.org>
11
12 0000_README | 4 ++
13 1300_linux-4.4.301.patch | 180 +++++++++++++++++++++++++++++++++++++++++++++++
14 2 files changed, 184 insertions(+)
15
16 diff --git a/0000_README b/0000_README
17 index 53822338..c28b7561 100644
18 --- a/0000_README
19 +++ b/0000_README
20 @@ -1243,6 +1243,10 @@ Patch: 1299_linux-4.4.300.patch
21 From: http://www.kernel.org
22 Desc: Linux 4.4.300
23
24 +Patch: 1300_linux-4.4.301.patch
25 +From: http://www.kernel.org
26 +Desc: Linux 4.4.301
27 +
28 Patch: 1500_XATTR_USER_PREFIX.patch
29 From: https://bugs.gentoo.org/show_bug.cgi?id=470644
30 Desc: Support for namespace user.pax.* on tmpfs.
31
32 diff --git a/1300_linux-4.4.301.patch b/1300_linux-4.4.301.patch
33 new file mode 100644
34 index 00000000..5ccaefc1
35 --- /dev/null
36 +++ b/1300_linux-4.4.301.patch
37 @@ -0,0 +1,180 @@
38 +diff --git a/Makefile b/Makefile
39 +index 29bb2f87dd2ad..3bf23154499e6 100644
40 +--- a/Makefile
41 ++++ b/Makefile
42 +@@ -1,6 +1,6 @@
43 + VERSION = 4
44 + PATCHLEVEL = 4
45 +-SUBLEVEL = 300
46 ++SUBLEVEL = 301
47 + EXTRAVERSION =
48 + NAME = Blurry Fish Butt
49 +
50 +diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
51 +index adbbcaf14af67..8d7d102af52f4 100644
52 +--- a/drivers/gpu/drm/i915/i915_drv.h
53 ++++ b/drivers/gpu/drm/i915/i915_drv.h
54 +@@ -1719,6 +1719,8 @@ struct drm_i915_private {
55 +
56 + struct intel_uncore uncore;
57 +
58 ++ struct mutex tlb_invalidate_lock;
59 ++
60 + struct i915_virtual_gpu vgpu;
61 +
62 + struct intel_guc guc;
63 +@@ -2066,6 +2068,9 @@ struct drm_i915_gem_object {
64 + */
65 + unsigned int active:I915_NUM_RINGS;
66 +
67 ++ unsigned long flags;
68 ++#define I915_BO_WAS_BOUND_BIT 0
69 ++
70 + /**
71 + * This is set if the object has been written to since last bound
72 + * to the GTT
73 +diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
74 +index f56af0aaafde5..ffce88930371e 100644
75 +--- a/drivers/gpu/drm/i915/i915_gem.c
76 ++++ b/drivers/gpu/drm/i915/i915_gem.c
77 +@@ -2212,6 +2212,85 @@ i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
78 + kfree(obj->pages);
79 + }
80 +
81 ++#define _wait_for_us(COND, US, W) ({ \
82 ++ unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
83 ++ int ret__; \
84 ++ for (;;) { \
85 ++ bool expired__ = time_after(jiffies, timeout__); \
86 ++ if (COND) { \
87 ++ ret__ = 0; \
88 ++ break; \
89 ++ } \
90 ++ if (expired__) { \
91 ++ ret__ = -ETIMEDOUT; \
92 ++ break; \
93 ++ } \
94 ++ usleep_range((W), (W)*2); \
95 ++ } \
96 ++ ret__; \
97 ++})
98 ++
99 ++static int
100 ++__intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
101 ++ u32 reg,
102 ++ const u32 mask,
103 ++ const u32 value,
104 ++ const unsigned int timeout_us,
105 ++ const unsigned int timeout_ms)
106 ++{
107 ++#define done ((I915_READ_FW(reg) & mask) == value)
108 ++ int ret = _wait_for_us(done, timeout_us, 2);
109 ++ if (ret)
110 ++ ret = wait_for(done, timeout_ms);
111 ++ return ret;
112 ++#undef done
113 ++}
114 ++
115 ++static void invalidate_tlbs(struct drm_i915_private *dev_priv)
116 ++{
117 ++ static const u32 gen8_regs[] = {
118 ++ [RCS] = GEN8_RTCR,
119 ++ [VCS] = GEN8_M1TCR,
120 ++ [VCS2] = GEN8_M2TCR,
121 ++ [VECS] = GEN8_VTCR,
122 ++ [BCS] = GEN8_BTCR,
123 ++ };
124 ++ enum intel_ring_id id;
125 ++
126 ++ if (INTEL_INFO(dev_priv)->gen < 8)
127 ++ return;
128 ++
129 ++ mutex_lock(&dev_priv->tlb_invalidate_lock);
130 ++ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
131 ++
132 ++ for (id = 0; id < I915_NUM_RINGS; id++) {
133 ++ struct intel_engine_cs *engine = &dev_priv->ring[id];
134 ++ /*
135 ++ * HW architecture suggest typical invalidation time at 40us,
136 ++ * with pessimistic cases up to 100us and a recommendation to
137 ++ * cap at 1ms. We go a bit higher just in case.
138 ++ */
139 ++ const unsigned int timeout_us = 100;
140 ++ const unsigned int timeout_ms = 4;
141 ++
142 ++ if (!intel_ring_initialized(engine))
143 ++ continue;
144 ++
145 ++ if (WARN_ON_ONCE(id >= ARRAY_SIZE(gen8_regs) || !gen8_regs[id]))
146 ++ continue;
147 ++
148 ++ I915_WRITE_FW(gen8_regs[id], 1);
149 ++ if (__intel_wait_for_register_fw(dev_priv,
150 ++ gen8_regs[id], 1, 0,
151 ++ timeout_us, timeout_ms))
152 ++ DRM_ERROR_RATELIMITED("%s TLB invalidation did not complete in %ums!\n",
153 ++ engine->name, timeout_ms);
154 ++ }
155 ++
156 ++ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
157 ++ mutex_unlock(&dev_priv->tlb_invalidate_lock);
158 ++}
159 ++
160 + int
161 + i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
162 + {
163 +@@ -2230,6 +2309,14 @@ i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
164 + * lists early. */
165 + list_del(&obj->global_list);
166 +
167 ++ if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, &obj->flags)) {
168 ++ struct drm_i915_private *i915 = to_i915(obj->base.dev);
169 ++
170 ++ intel_runtime_pm_get(i915);
171 ++ invalidate_tlbs(i915);
172 ++ intel_runtime_pm_put(i915);
173 ++ }
174 ++
175 + ops->put_pages(obj);
176 + obj->pages = NULL;
177 +
178 +@@ -5050,6 +5137,8 @@ i915_gem_load(struct drm_device *dev)
179 + i915_gem_shrinker_init(dev_priv);
180 +
181 + mutex_init(&dev_priv->fb_tracking.lock);
182 ++
183 ++ mutex_init(&dev_priv->tlb_invalidate_lock);
184 + }
185 +
186 + void i915_gem_release(struct drm_device *dev, struct drm_file *file)
187 +diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
188 +index 65a53ee398b8e..b2bb0b268ea9c 100644
189 +--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
190 ++++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
191 +@@ -3538,6 +3538,9 @@ int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
192 +
193 + vma->bound |= bind_flags;
194 +
195 ++ if (vma->obj)
196 ++ set_bit(I915_BO_WAS_BOUND_BIT, &vma->obj->flags);
197 ++
198 + return 0;
199 + }
200 +
201 +diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
202 +index 603d8cdfc5f1f..33a9b80da5dc8 100644
203 +--- a/drivers/gpu/drm/i915/i915_reg.h
204 ++++ b/drivers/gpu/drm/i915/i915_reg.h
205 +@@ -1592,6 +1592,12 @@ enum skl_disp_power_wells {
206 +
207 + #define GEN7_TLB_RD_ADDR 0x4700
208 +
209 ++#define GEN8_RTCR 0x4260
210 ++#define GEN8_M1TCR 0x4264
211 ++#define GEN8_M2TCR 0x4268
212 ++#define GEN8_BTCR 0x426c
213 ++#define GEN8_VTCR 0x4270
214 ++
215 + #if 0
216 + #define PRB0_TAIL 0x02030
217 + #define PRB0_HEAD 0x02034