Gentoo Archives: gentoo-commits

From: Mike Pagano <mpagano@g.o>
To: gentoo-commits@l.g.o
Subject: [gentoo-commits] proj/linux-patches:5.10 commit in: /
Date: Wed, 30 Dec 2020 12:54:24
Message-Id: 1609332844.b6de6417a82978446b2e3e3bec49271f305452e6.mpagano@gentoo
1 commit: b6de6417a82978446b2e3e3bec49271f305452e6
2 Author: Mike Pagano <mpagano <AT> gentoo <DOT> org>
3 AuthorDate: Wed Dec 30 12:54:04 2020 +0000
4 Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org>
5 CommitDate: Wed Dec 30 12:54:04 2020 +0000
6 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=b6de6417
7
8 Linux patch 5.10.4
9
10 Signed-off-by: Mike Pagano <mpagano <AT> gentoo.org>
11
12 0000_README | 4 +
13 1003_linux-5.10.4.patch | 23858 ++++++++++++++++++++++++++++++++++++++++++++++
14 2 files changed, 23862 insertions(+)
15
16 diff --git a/0000_README b/0000_README
17 index 025c3da..ce1d3f7 100644
18 --- a/0000_README
19 +++ b/0000_README
20 @@ -55,6 +55,10 @@ Patch: 1002_linux-5.10.3.patch
21 From: http://www.kernel.org
22 Desc: Linux 5.10.3
23
24 +Patch: 1003_linux-5.10.4.patch
25 +From: http://www.kernel.org
26 +Desc: Linux 5.10.4
27 +
28 Patch: 1500_XATTR_USER_PREFIX.patch
29 From: https://bugs.gentoo.org/show_bug.cgi?id=470644
30 Desc: Support for namespace user.pax.* on tmpfs.
31
32 diff --git a/1003_linux-5.10.4.patch b/1003_linux-5.10.4.patch
33 new file mode 100644
34 index 0000000..a623431
35 --- /dev/null
36 +++ b/1003_linux-5.10.4.patch
37 @@ -0,0 +1,23858 @@
38 +diff --git a/Documentation/locking/seqlock.rst b/Documentation/locking/seqlock.rst
39 +index a334b584f2b34..64405e5da63e4 100644
40 +--- a/Documentation/locking/seqlock.rst
41 ++++ b/Documentation/locking/seqlock.rst
42 +@@ -89,7 +89,7 @@ Read path::
43 +
44 + .. _seqcount_locktype_t:
45 +
46 +-Sequence counters with associated locks (``seqcount_LOCKTYPE_t``)
47 ++Sequence counters with associated locks (``seqcount_LOCKNAME_t``)
48 + -----------------------------------------------------------------
49 +
50 + As discussed at :ref:`seqcount_t`, sequence count write side critical
51 +@@ -115,27 +115,26 @@ The following sequence counters with associated locks are defined:
52 + - ``seqcount_mutex_t``
53 + - ``seqcount_ww_mutex_t``
54 +
55 +-The plain seqcount read and write APIs branch out to the specific
56 +-seqcount_LOCKTYPE_t implementation at compile-time. This avoids kernel
57 +-API explosion per each new seqcount LOCKTYPE.
58 ++The sequence counter read and write APIs can take either a plain
59 ++seqcount_t or any of the seqcount_LOCKNAME_t variants above.
60 +
61 +-Initialization (replace "LOCKTYPE" with one of the supported locks)::
62 ++Initialization (replace "LOCKNAME" with one of the supported locks)::
63 +
64 + /* dynamic */
65 +- seqcount_LOCKTYPE_t foo_seqcount;
66 +- seqcount_LOCKTYPE_init(&foo_seqcount, &lock);
67 ++ seqcount_LOCKNAME_t foo_seqcount;
68 ++ seqcount_LOCKNAME_init(&foo_seqcount, &lock);
69 +
70 + /* static */
71 +- static seqcount_LOCKTYPE_t foo_seqcount =
72 +- SEQCNT_LOCKTYPE_ZERO(foo_seqcount, &lock);
73 ++ static seqcount_LOCKNAME_t foo_seqcount =
74 ++ SEQCNT_LOCKNAME_ZERO(foo_seqcount, &lock);
75 +
76 + /* C99 struct init */
77 + struct {
78 +- .seq = SEQCNT_LOCKTYPE_ZERO(foo.seq, &lock),
79 ++ .seq = SEQCNT_LOCKNAME_ZERO(foo.seq, &lock),
80 + } foo;
81 +
82 + Write path: same as in :ref:`seqcount_t`, while running from a context
83 +-with the associated LOCKTYPE lock acquired.
84 ++with the associated write serialization lock acquired.
85 +
86 + Read path: same as in :ref:`seqcount_t`.
87 +
88 +diff --git a/Documentation/x86/topology.rst b/Documentation/x86/topology.rst
89 +index e29739904e37e..7f58010ea86af 100644
90 +--- a/Documentation/x86/topology.rst
91 ++++ b/Documentation/x86/topology.rst
92 +@@ -41,6 +41,8 @@ Package
93 + Packages contain a number of cores plus shared resources, e.g. DRAM
94 + controller, shared caches etc.
95 +
96 ++Modern systems may also use the term 'Die' for package.
97 ++
98 + AMD nomenclature for package is 'Node'.
99 +
100 + Package-related topology information in the kernel:
101 +@@ -53,11 +55,18 @@ Package-related topology information in the kernel:
102 +
103 + The number of dies in a package. This information is retrieved via CPUID.
104 +
105 ++ - cpuinfo_x86.cpu_die_id:
106 ++
107 ++ The physical ID of the die. This information is retrieved via CPUID.
108 ++
109 + - cpuinfo_x86.phys_proc_id:
110 +
111 + The physical ID of the package. This information is retrieved via CPUID
112 + and deduced from the APIC IDs of the cores in the package.
113 +
114 ++ Modern systems use this value for the socket. There may be multiple
115 ++ packages within a socket. This value may differ from cpu_die_id.
116 ++
117 + - cpuinfo_x86.logical_proc_id:
118 +
119 + The logical ID of the package. As we do not trust BIOSes to enumerate the
120 +diff --git a/Makefile b/Makefile
121 +index a72bc404123d5..1e50d6af932ab 100644
122 +--- a/Makefile
123 ++++ b/Makefile
124 +@@ -1,7 +1,7 @@
125 + # SPDX-License-Identifier: GPL-2.0
126 + VERSION = 5
127 + PATCHLEVEL = 10
128 +-SUBLEVEL = 3
129 ++SUBLEVEL = 4
130 + EXTRAVERSION =
131 + NAME = Kleptomaniac Octopus
132 +
133 +diff --git a/arch/Kconfig b/arch/Kconfig
134 +index ba4e966484ab5..ddd4641446bdd 100644
135 +--- a/arch/Kconfig
136 ++++ b/arch/Kconfig
137 +@@ -143,6 +143,22 @@ config UPROBES
138 + managed by the kernel and kept transparent to the probed
139 + application. )
140 +
141 ++config HAVE_64BIT_ALIGNED_ACCESS
142 ++ def_bool 64BIT && !HAVE_EFFICIENT_UNALIGNED_ACCESS
143 ++ help
144 ++ Some architectures require 64 bit accesses to be 64 bit
145 ++ aligned, which also requires structs containing 64 bit values
146 ++ to be 64 bit aligned too. This includes some 32 bit
147 ++ architectures which can do 64 bit accesses, as well as 64 bit
148 ++ architectures without unaligned access.
149 ++
150 ++ This symbol should be selected by an architecture if 64 bit
151 ++ accesses are required to be 64 bit aligned in this way even
152 ++ though it is not a 64 bit architecture.
153 ++
154 ++ See Documentation/unaligned-memory-access.txt for more
155 ++ information on the topic of unaligned memory accesses.
156 ++
157 + config HAVE_EFFICIENT_UNALIGNED_ACCESS
158 + bool
159 + help
160 +diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
161 +index caa27322a0ab7..3a392983ac079 100644
162 +--- a/arch/arm/boot/compressed/head.S
163 ++++ b/arch/arm/boot/compressed/head.S
164 +@@ -116,7 +116,7 @@
165 + /*
166 + * Debug print of the final appended DTB location
167 + */
168 +- .macro dbgadtb, begin, end
169 ++ .macro dbgadtb, begin, size
170 + #ifdef DEBUG
171 + kputc #'D'
172 + kputc #'T'
173 +@@ -129,7 +129,7 @@
174 + kputc #'('
175 + kputc #'0'
176 + kputc #'x'
177 +- kphex \end, 8 /* End of appended DTB */
178 ++ kphex \size, 8 /* Size of appended DTB */
179 + kputc #')'
180 + kputc #'\n'
181 + #endif
182 +diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
183 +index 654648b05c7c2..aeccedd125740 100644
184 +--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
185 ++++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
186 +@@ -266,11 +266,6 @@
187 + reg = <0x11000 0x100>;
188 + };
189 +
190 +-&i2c1 {
191 +- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
192 +- reg = <0x11100 0x100>;
193 +-};
194 +-
195 + &mpic {
196 + reg = <0x20a00 0x2d0>, <0x21070 0x58>;
197 + };
198 +diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
199 +index 2d44d9ad4e400..e6ad821a86359 100644
200 +--- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
201 ++++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
202 +@@ -82,11 +82,6 @@
203 + status = "okay";
204 + };
205 +
206 +-&vuart {
207 +- // VUART Host Console
208 +- status = "okay";
209 +-};
210 +-
211 + &uart1 {
212 + // Host Console
213 + status = "okay";
214 +diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts
215 +index 1deb30ec912cf..6e9baf3bba531 100644
216 +--- a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts
217 ++++ b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts
218 +@@ -22,9 +22,9 @@
219 + #size-cells = <1>;
220 + ranges;
221 +
222 +- vga_memory: framebuffer@7f000000 {
223 ++ vga_memory: framebuffer@9f000000 {
224 + no-map;
225 +- reg = <0x7f000000 0x01000000>;
226 ++ reg = <0x9f000000 0x01000000>; /* 16M */
227 + };
228 + };
229 +
230 +diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
231 +index 4d070d6ba09f9..e86c22ce6d123 100644
232 +--- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
233 ++++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
234 +@@ -26,7 +26,7 @@
235 + #size-cells = <1>;
236 + ranges;
237 +
238 +- flash_memory: region@ba000000 {
239 ++ flash_memory: region@b8000000 {
240 + no-map;
241 + reg = <0xb8000000 0x4000000>; /* 64M */
242 + };
243 +diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
244 +index b58220a49cbd8..bf97aaad7be9b 100644
245 +--- a/arch/arm/boot/dts/aspeed-g6.dtsi
246 ++++ b/arch/arm/boot/dts/aspeed-g6.dtsi
247 +@@ -357,7 +357,7 @@
248 + #gpio-cells = <2>;
249 + gpio-controller;
250 + compatible = "aspeed,ast2600-gpio";
251 +- reg = <0x1e780000 0x800>;
252 ++ reg = <0x1e780000 0x400>;
253 + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
254 + gpio-ranges = <&pinctrl 0 0 208>;
255 + ngpios = <208>;
256 +diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts
257 +index eae28b82c7fd0..73b6b1f89de99 100644
258 +--- a/arch/arm/boot/dts/at91-sam9x60ek.dts
259 ++++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
260 +@@ -569,11 +569,14 @@
261 + atmel,pins = <AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
262 + };
263 + };
264 +-}; /* pinctrl */
265 +
266 +-&pmc {
267 +- atmel,osc-bypass;
268 +-};
269 ++ usb1 {
270 ++ pinctrl_usb_default: usb_default {
271 ++ atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
272 ++ AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
273 ++ };
274 ++ };
275 ++}; /* pinctrl */
276 +
277 + &pwm0 {
278 + pinctrl-names = "default";
279 +@@ -684,6 +687,8 @@
280 + atmel,vbus-gpio = <0
281 + &pioD 15 GPIO_ACTIVE_HIGH
282 + &pioD 16 GPIO_ACTIVE_HIGH>;
283 ++ pinctrl-names = "default";
284 ++ pinctrl-0 = <&pinctrl_usb_default>;
285 + status = "okay";
286 + };
287 +
288 +diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
289 +index cf13632edd444..5179258f92470 100644
290 +--- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts
291 ++++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
292 +@@ -242,6 +242,11 @@
293 + atmel,pins =
294 + <AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PE9, conflicts with A9 */
295 + };
296 ++ pinctrl_usb_default: usb_default {
297 ++ atmel,pins =
298 ++ <AT91_PIOE 3 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
299 ++ AT91_PIOE 4 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
300 ++ };
301 + };
302 + };
303 + };
304 +@@ -259,6 +264,8 @@
305 + &pioE 3 GPIO_ACTIVE_LOW
306 + &pioE 4 GPIO_ACTIVE_LOW
307 + >;
308 ++ pinctrl-names = "default";
309 ++ pinctrl-0 = <&pinctrl_usb_default>;
310 + status = "okay";
311 + };
312 +
313 +diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts
314 +index e5974a17374cf..0b3ad1b580b83 100644
315 +--- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts
316 ++++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts
317 +@@ -134,6 +134,11 @@
318 + atmel,pins =
319 + <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
320 + };
321 ++ pinctrl_usb_default: usb_default {
322 ++ atmel,pins =
323 ++ <AT91_PIOE 11 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
324 ++ AT91_PIOE 14 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
325 ++ };
326 + pinctrl_key_gpio: key_gpio_0 {
327 + atmel,pins =
328 + <AT91_PIOE 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
329 +@@ -159,6 +164,8 @@
330 + &pioE 11 GPIO_ACTIVE_HIGH
331 + &pioE 14 GPIO_ACTIVE_HIGH
332 + >;
333 ++ pinctrl-names = "default";
334 ++ pinctrl-0 = <&pinctrl_usb_default>;
335 + status = "okay";
336 + };
337 +
338 +diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
339 +index 5653e70c84b4b..36a42a9fe1957 100644
340 +--- a/arch/arm/boot/dts/at91sam9rl.dtsi
341 ++++ b/arch/arm/boot/dts/at91sam9rl.dtsi
342 +@@ -282,23 +282,26 @@
343 + atmel,adc-use-res = "highres";
344 +
345 + trigger0 {
346 +- trigger-name = "timer-counter-0";
347 ++ trigger-name = "external-rising";
348 + trigger-value = <0x1>;
349 ++ trigger-external;
350 + };
351 ++
352 + trigger1 {
353 +- trigger-name = "timer-counter-1";
354 +- trigger-value = <0x3>;
355 ++ trigger-name = "external-falling";
356 ++ trigger-value = <0x2>;
357 ++ trigger-external;
358 + };
359 +
360 + trigger2 {
361 +- trigger-name = "timer-counter-2";
362 +- trigger-value = <0x5>;
363 ++ trigger-name = "external-any";
364 ++ trigger-value = <0x3>;
365 ++ trigger-external;
366 + };
367 +
368 + trigger3 {
369 +- trigger-name = "external";
370 +- trigger-value = <0x13>;
371 +- trigger-external;
372 ++ trigger-name = "continuous";
373 ++ trigger-value = <0x6>;
374 + };
375 + };
376 +
377 +diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts
378 +index 0c26467de4d03..5963566dbcc9d 100644
379 +--- a/arch/arm/boot/dts/meson8b-odroidc1.dts
380 ++++ b/arch/arm/boot/dts/meson8b-odroidc1.dts
381 +@@ -224,7 +224,7 @@
382 + reg = <0>;
383 +
384 + reset-assert-us = <10000>;
385 +- reset-deassert-us = <30000>;
386 ++ reset-deassert-us = <80000>;
387 + reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
388 +
389 + interrupt-parent = <&gpio_intc>;
390 +diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
391 +index cc498191ddd1d..8f4eb1ed45816 100644
392 +--- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
393 ++++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
394 +@@ -81,7 +81,7 @@
395 + reg = <0>;
396 +
397 + reset-assert-us = <10000>;
398 +- reset-deassert-us = <30000>;
399 ++ reset-deassert-us = <80000>;
400 + reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
401 + };
402 + };
403 +diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
404 +index cfa85aa3da085..6afa8fd7c412d 100644
405 +--- a/arch/arm/boot/dts/omap4-panda-es.dts
406 ++++ b/arch/arm/boot/dts/omap4-panda-es.dts
407 +@@ -46,7 +46,7 @@
408 +
409 + button_pins: pinmux_button_pins {
410 + pinctrl-single,pins = <
411 +- OMAP4_IOPAD(0x11b, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */
412 ++ OMAP4_IOPAD(0x0fc, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */
413 + >;
414 + };
415 + };
416 +diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
417 +index 2ddc85dff8ce9..2c4952427296e 100644
418 +--- a/arch/arm/boot/dts/sama5d2.dtsi
419 ++++ b/arch/arm/boot/dts/sama5d2.dtsi
420 +@@ -656,6 +656,7 @@
421 + clocks = <&pmc PMC_TYPE_PERIPHERAL 51>;
422 + #address-cells = <1>;
423 + #size-cells = <1>;
424 ++ no-memory-wc;
425 + ranges = <0 0xf8044000 0x1420>;
426 + };
427 +
428 +@@ -724,7 +725,7 @@
429 +
430 + can0: can@f8054000 {
431 + compatible = "bosch,m_can";
432 +- reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
433 ++ reg = <0xf8054000 0x4000>, <0x210000 0x1c00>;
434 + reg-names = "m_can", "message_ram";
435 + interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
436 + <64 IRQ_TYPE_LEVEL_HIGH 7>;
437 +@@ -1130,7 +1131,7 @@
438 +
439 + can1: can@fc050000 {
440 + compatible = "bosch,m_can";
441 +- reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
442 ++ reg = <0xfc050000 0x4000>, <0x210000 0x3800>;
443 + reg-names = "m_can", "message_ram";
444 + interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
445 + <65 IRQ_TYPE_LEVEL_HIGH 7>;
446 +@@ -1140,7 +1141,7 @@
447 + assigned-clocks = <&pmc PMC_TYPE_GCK 57>;
448 + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
449 + assigned-clock-rates = <40000000>;
450 +- bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
451 ++ bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>;
452 + status = "disabled";
453 + };
454 +
455 +diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
456 +index b158771ac0b7d..055334ae3d288 100644
457 +--- a/arch/arm/boot/dts/tegra20-ventana.dts
458 ++++ b/arch/arm/boot/dts/tegra20-ventana.dts
459 +@@ -3,6 +3,7 @@
460 +
461 + #include <dt-bindings/input/input.h>
462 + #include "tegra20.dtsi"
463 ++#include "tegra20-cpu-opp.dtsi"
464 +
465 + / {
466 + model = "NVIDIA Tegra20 Ventana evaluation board";
467 +@@ -592,6 +593,16 @@
468 + #clock-cells = <0>;
469 + };
470 +
471 ++ cpus {
472 ++ cpu0: cpu@0 {
473 ++ operating-points-v2 = <&cpu0_opp_table>;
474 ++ };
475 ++
476 ++ cpu@1 {
477 ++ operating-points-v2 = <&cpu0_opp_table>;
478 ++ };
479 ++ };
480 ++
481 + gpio-keys {
482 + compatible = "gpio-keys";
483 +
484 +diff --git a/arch/arm/crypto/aes-ce-core.S b/arch/arm/crypto/aes-ce-core.S
485 +index 4d1707388d941..312428d83eedb 100644
486 +--- a/arch/arm/crypto/aes-ce-core.S
487 ++++ b/arch/arm/crypto/aes-ce-core.S
488 +@@ -386,20 +386,32 @@ ENTRY(ce_aes_ctr_encrypt)
489 + .Lctrloop4x:
490 + subs r4, r4, #4
491 + bmi .Lctr1x
492 +- add r6, r6, #1
493 ++
494 ++ /*
495 ++ * NOTE: the sequence below has been carefully tweaked to avoid
496 ++ * a silicon erratum that exists in Cortex-A57 (#1742098) and
497 ++ * Cortex-A72 (#1655431) cores, where AESE/AESMC instruction pairs
498 ++ * may produce an incorrect result if they take their input from a
499 ++ * register of which a single 32-bit lane has been updated the last
500 ++ * time it was modified. To work around this, the lanes of registers
501 ++ * q0-q3 below are not manipulated individually, and the different
502 ++ * counter values are prepared by successive manipulations of q7.
503 ++ */
504 ++ add ip, r6, #1
505 + vmov q0, q7
506 ++ rev ip, ip
507 ++ add lr, r6, #2
508 ++ vmov s31, ip @ set lane 3 of q1 via q7
509 ++ add ip, r6, #3
510 ++ rev lr, lr
511 + vmov q1, q7
512 +- rev ip, r6
513 +- add r6, r6, #1
514 ++ vmov s31, lr @ set lane 3 of q2 via q7
515 ++ rev ip, ip
516 + vmov q2, q7
517 +- vmov s7, ip
518 +- rev ip, r6
519 +- add r6, r6, #1
520 ++ vmov s31, ip @ set lane 3 of q3 via q7
521 ++ add r6, r6, #4
522 + vmov q3, q7
523 +- vmov s11, ip
524 +- rev ip, r6
525 +- add r6, r6, #1
526 +- vmov s15, ip
527 ++
528 + vld1.8 {q4-q5}, [r1]!
529 + vld1.8 {q6}, [r1]!
530 + vld1.8 {q15}, [r1]!
531 +diff --git a/arch/arm/crypto/aes-neonbs-glue.c b/arch/arm/crypto/aes-neonbs-glue.c
532 +index bda8bf17631e1..f70af1d0514b9 100644
533 +--- a/arch/arm/crypto/aes-neonbs-glue.c
534 ++++ b/arch/arm/crypto/aes-neonbs-glue.c
535 +@@ -19,7 +19,7 @@ MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@××××××.org>");
536 + MODULE_LICENSE("GPL v2");
537 +
538 + MODULE_ALIAS_CRYPTO("ecb(aes)");
539 +-MODULE_ALIAS_CRYPTO("cbc(aes)");
540 ++MODULE_ALIAS_CRYPTO("cbc(aes)-all");
541 + MODULE_ALIAS_CRYPTO("ctr(aes)");
542 + MODULE_ALIAS_CRYPTO("xts(aes)");
543 +
544 +@@ -191,7 +191,8 @@ static int cbc_init(struct crypto_skcipher *tfm)
545 + struct aesbs_cbc_ctx *ctx = crypto_skcipher_ctx(tfm);
546 + unsigned int reqsize;
547 +
548 +- ctx->enc_tfm = crypto_alloc_skcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
549 ++ ctx->enc_tfm = crypto_alloc_skcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC |
550 ++ CRYPTO_ALG_NEED_FALLBACK);
551 + if (IS_ERR(ctx->enc_tfm))
552 + return PTR_ERR(ctx->enc_tfm);
553 +
554 +@@ -441,7 +442,8 @@ static struct skcipher_alg aes_algs[] = { {
555 + .base.cra_blocksize = AES_BLOCK_SIZE,
556 + .base.cra_ctxsize = sizeof(struct aesbs_cbc_ctx),
557 + .base.cra_module = THIS_MODULE,
558 +- .base.cra_flags = CRYPTO_ALG_INTERNAL,
559 ++ .base.cra_flags = CRYPTO_ALG_INTERNAL |
560 ++ CRYPTO_ALG_NEED_FALLBACK,
561 +
562 + .min_keysize = AES_MIN_KEY_SIZE,
563 + .max_keysize = AES_MAX_KEY_SIZE,
564 +diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
565 +index 55a47df047738..1c9e6d1452c5b 100644
566 +--- a/arch/arm/kernel/entry-armv.S
567 ++++ b/arch/arm/kernel/entry-armv.S
568 +@@ -252,31 +252,10 @@ __und_svc:
569 + #else
570 + svc_entry
571 + #endif
572 +- @
573 +- @ call emulation code, which returns using r9 if it has emulated
574 +- @ the instruction, or the more conventional lr if we are to treat
575 +- @ this as a real undefined instruction
576 +- @
577 +- @ r0 - instruction
578 +- @
579 +-#ifndef CONFIG_THUMB2_KERNEL
580 +- ldr r0, [r4, #-4]
581 +-#else
582 +- mov r1, #2
583 +- ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
584 +- cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
585 +- blo __und_svc_fault
586 +- ldrh r9, [r4] @ bottom 16 bits
587 +- add r4, r4, #2
588 +- str r4, [sp, #S_PC]
589 +- orr r0, r9, r0, lsl #16
590 +-#endif
591 +- badr r9, __und_svc_finish
592 +- mov r2, r4
593 +- bl call_fpe
594 +
595 + mov r1, #4 @ PC correction to apply
596 +-__und_svc_fault:
597 ++ THUMB( tst r5, #PSR_T_BIT ) @ exception taken in Thumb mode?
598 ++ THUMB( movne r1, #2 ) @ if so, fix up PC correction
599 + mov r0, sp @ struct pt_regs *regs
600 + bl __und_fault
601 +
602 +diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
603 +index f8904227e7fdc..98c1e68bdfcbb 100644
604 +--- a/arch/arm/kernel/head.S
605 ++++ b/arch/arm/kernel/head.S
606 +@@ -671,12 +671,8 @@ ARM_BE8(rev16 ip, ip)
607 + ldrcc r7, [r4], #4 @ use branch for delay slot
608 + bcc 1b
609 + bx lr
610 +-#else
611 +-#ifdef CONFIG_CPU_ENDIAN_BE8
612 +- moveq r0, #0x00004000 @ set bit 22, mov to mvn instruction
613 + #else
614 + moveq r0, #0x400000 @ set bit 22, mov to mvn instruction
615 +-#endif
616 + b 2f
617 + 1: ldr ip, [r7, r3]
618 + #ifdef CONFIG_CPU_ENDIAN_BE8
619 +@@ -685,7 +681,7 @@ ARM_BE8(rev16 ip, ip)
620 + tst ip, #0x000f0000 @ check the rotation field
621 + orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24
622 + biceq ip, ip, #0x00004000 @ clear bit 22
623 +- orreq ip, ip, r0 @ mask in offset bits 7-0
624 ++ orreq ip, ip, r0, ror #8 @ mask in offset bits 7-0
625 + #else
626 + bic ip, ip, #0x000000ff
627 + tst ip, #0xf00 @ check the rotation field
628 +diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S
629 +index 0186cf9da890b..27b0a1f27fbdf 100644
630 +--- a/arch/arm/vfp/entry.S
631 ++++ b/arch/arm/vfp/entry.S
632 +@@ -37,20 +37,3 @@ ENDPROC(vfp_null_entry)
633 + .align 2
634 + .LCvfp:
635 + .word vfp_vector
636 +-
637 +-@ This code is called if the VFP does not exist. It needs to flag the
638 +-@ failure to the VFP initialisation code.
639 +-
640 +- __INIT
641 +-ENTRY(vfp_testing_entry)
642 +- dec_preempt_count_ti r10, r4
643 +- ldr r0, VFP_arch_address
644 +- str r0, [r0] @ set to non-zero value
645 +- ret r9 @ we have handled the fault
646 +-ENDPROC(vfp_testing_entry)
647 +-
648 +- .align 2
649 +-VFP_arch_address:
650 +- .word VFP_arch
651 +-
652 +- __FINIT
653 +diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
654 +index 4fcff9f59947d..d5837bf05a9a5 100644
655 +--- a/arch/arm/vfp/vfphw.S
656 ++++ b/arch/arm/vfp/vfphw.S
657 +@@ -79,11 +79,6 @@ ENTRY(vfp_support_entry)
658 + DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
659 +
660 + .fpu vfpv2
661 +- ldr r3, [sp, #S_PSR] @ Neither lazy restore nor FP exceptions
662 +- and r3, r3, #MODE_MASK @ are supported in kernel mode
663 +- teq r3, #USR_MODE
664 +- bne vfp_kmode_exception @ Returns through lr
665 +-
666 + VFPFMRX r1, FPEXC @ Is the VFP enabled?
667 + DBGSTR1 "fpexc %08x", r1
668 + tst r1, #FPEXC_EN
669 +diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
670 +index 8c9e7f9f0277d..2cb355c1b5b71 100644
671 +--- a/arch/arm/vfp/vfpmodule.c
672 ++++ b/arch/arm/vfp/vfpmodule.c
673 +@@ -23,6 +23,7 @@
674 + #include <asm/cputype.h>
675 + #include <asm/system_info.h>
676 + #include <asm/thread_notify.h>
677 ++#include <asm/traps.h>
678 + #include <asm/vfp.h>
679 +
680 + #include "vfpinstr.h"
681 +@@ -31,7 +32,6 @@
682 + /*
683 + * Our undef handlers (in entry.S)
684 + */
685 +-asmlinkage void vfp_testing_entry(void);
686 + asmlinkage void vfp_support_entry(void);
687 + asmlinkage void vfp_null_entry(void);
688 +
689 +@@ -42,7 +42,7 @@ asmlinkage void (*vfp_vector)(void) = vfp_null_entry;
690 + * Used in startup: set to non-zero if VFP checks fail
691 + * After startup, holds VFP architecture
692 + */
693 +-unsigned int VFP_arch;
694 ++static unsigned int __initdata VFP_arch;
695 +
696 + /*
697 + * The pointer to the vfpstate structure of the thread which currently
698 +@@ -436,7 +436,7 @@ static void vfp_enable(void *unused)
699 + * present on all CPUs within a SMP complex. Needs to be called prior to
700 + * vfp_init().
701 + */
702 +-void vfp_disable(void)
703 ++void __init vfp_disable(void)
704 + {
705 + if (VFP_arch) {
706 + pr_debug("%s: should be called prior to vfp_init\n", __func__);
707 +@@ -642,7 +642,9 @@ static int vfp_starting_cpu(unsigned int unused)
708 + return 0;
709 + }
710 +
711 +-void vfp_kmode_exception(void)
712 ++#ifdef CONFIG_KERNEL_MODE_NEON
713 ++
714 ++static int vfp_kmode_exception(struct pt_regs *regs, unsigned int instr)
715 + {
716 + /*
717 + * If we reach this point, a floating point exception has been raised
718 +@@ -660,9 +662,51 @@ void vfp_kmode_exception(void)
719 + pr_crit("BUG: unsupported FP instruction in kernel mode\n");
720 + else
721 + pr_crit("BUG: FP instruction issued in kernel mode with FP unit disabled\n");
722 ++ pr_crit("FPEXC == 0x%08x\n", fmrx(FPEXC));
723 ++ return 1;
724 + }
725 +
726 +-#ifdef CONFIG_KERNEL_MODE_NEON
727 ++static struct undef_hook vfp_kmode_exception_hook[] = {{
728 ++ .instr_mask = 0xfe000000,
729 ++ .instr_val = 0xf2000000,
730 ++ .cpsr_mask = MODE_MASK | PSR_T_BIT,
731 ++ .cpsr_val = SVC_MODE,
732 ++ .fn = vfp_kmode_exception,
733 ++}, {
734 ++ .instr_mask = 0xff100000,
735 ++ .instr_val = 0xf4000000,
736 ++ .cpsr_mask = MODE_MASK | PSR_T_BIT,
737 ++ .cpsr_val = SVC_MODE,
738 ++ .fn = vfp_kmode_exception,
739 ++}, {
740 ++ .instr_mask = 0xef000000,
741 ++ .instr_val = 0xef000000,
742 ++ .cpsr_mask = MODE_MASK | PSR_T_BIT,
743 ++ .cpsr_val = SVC_MODE | PSR_T_BIT,
744 ++ .fn = vfp_kmode_exception,
745 ++}, {
746 ++ .instr_mask = 0xff100000,
747 ++ .instr_val = 0xf9000000,
748 ++ .cpsr_mask = MODE_MASK | PSR_T_BIT,
749 ++ .cpsr_val = SVC_MODE | PSR_T_BIT,
750 ++ .fn = vfp_kmode_exception,
751 ++}, {
752 ++ .instr_mask = 0x0c000e00,
753 ++ .instr_val = 0x0c000a00,
754 ++ .cpsr_mask = MODE_MASK,
755 ++ .cpsr_val = SVC_MODE,
756 ++ .fn = vfp_kmode_exception,
757 ++}};
758 ++
759 ++static int __init vfp_kmode_exception_hook_init(void)
760 ++{
761 ++ int i;
762 ++
763 ++ for (i = 0; i < ARRAY_SIZE(vfp_kmode_exception_hook); i++)
764 ++ register_undef_hook(&vfp_kmode_exception_hook[i]);
765 ++ return 0;
766 ++}
767 ++subsys_initcall(vfp_kmode_exception_hook_init);
768 +
769 + /*
770 + * Kernel-side NEON support functions
771 +@@ -708,6 +752,21 @@ EXPORT_SYMBOL(kernel_neon_end);
772 +
773 + #endif /* CONFIG_KERNEL_MODE_NEON */
774 +
775 ++static int __init vfp_detect(struct pt_regs *regs, unsigned int instr)
776 ++{
777 ++ VFP_arch = UINT_MAX; /* mark as not present */
778 ++ regs->ARM_pc += 4;
779 ++ return 0;
780 ++}
781 ++
782 ++static struct undef_hook vfp_detect_hook __initdata = {
783 ++ .instr_mask = 0x0c000e00,
784 ++ .instr_val = 0x0c000a00,
785 ++ .cpsr_mask = MODE_MASK,
786 ++ .cpsr_val = SVC_MODE,
787 ++ .fn = vfp_detect,
788 ++};
789 ++
790 + /*
791 + * VFP support code initialisation.
792 + */
793 +@@ -728,10 +787,11 @@ static int __init vfp_init(void)
794 + * The handler is already setup to just log calls, so
795 + * we just need to read the VFPSID register.
796 + */
797 +- vfp_vector = vfp_testing_entry;
798 ++ register_undef_hook(&vfp_detect_hook);
799 + barrier();
800 + vfpsid = fmrx(FPSID);
801 + barrier();
802 ++ unregister_undef_hook(&vfp_detect_hook);
803 + vfp_vector = vfp_null_entry;
804 +
805 + pr_info("VFP support v0.3: ");
806 +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
807 +index 1b07c8c06eac5..463a72d6bb7c7 100644
808 +--- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
809 ++++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
810 +@@ -340,7 +340,7 @@
811 + eee-broken-1000t;
812 +
813 + reset-assert-us = <10000>;
814 +- reset-deassert-us = <30000>;
815 ++ reset-deassert-us = <80000>;
816 + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
817 +
818 + interrupt-parent = <&gpio_intc>;
819 +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
820 +index 6982632ae6461..39a09661c5f62 100644
821 +--- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
822 ++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
823 +@@ -413,7 +413,7 @@
824 + max-speed = <1000>;
825 +
826 + reset-assert-us = <10000>;
827 +- reset-deassert-us = <30000>;
828 ++ reset-deassert-us = <80000>;
829 + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
830 +
831 + interrupt-parent = <&gpio_intc>;
832 +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi
833 +index 2802ddbb83ac7..feb0885047400 100644
834 +--- a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi
835 ++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi
836 +@@ -264,7 +264,7 @@
837 + max-speed = <1000>;
838 +
839 + reset-assert-us = <10000>;
840 +- reset-deassert-us = <30000>;
841 ++ reset-deassert-us = <80000>;
842 + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
843 +
844 + interrupt-parent = <&gpio_intc>;
845 +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
846 +index 7be3e354093bf..de27beafe9db9 100644
847 +--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
848 ++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
849 +@@ -165,7 +165,7 @@
850 + reg = <0>;
851 +
852 + reset-assert-us = <10000>;
853 +- reset-deassert-us = <30000>;
854 ++ reset-deassert-us = <80000>;
855 + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
856 +
857 + interrupt-parent = <&gpio_intc>;
858 +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
859 +index 70fcfb7b0683d..50de1d01e5655 100644
860 +--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
861 ++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
862 +@@ -200,7 +200,7 @@
863 + reg = <0>;
864 +
865 + reset-assert-us = <10000>;
866 +- reset-deassert-us = <30000>;
867 ++ reset-deassert-us = <80000>;
868 + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
869 +
870 + interrupt-parent = <&gpio_intc>;
871 +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
872 +index 222ee8069cfaa..9b0b81f191f1f 100644
873 +--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
874 ++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
875 +@@ -126,7 +126,7 @@
876 + reg = <0>;
877 +
878 + reset-assert-us = <10000>;
879 +- reset-deassert-us = <30000>;
880 ++ reset-deassert-us = <80000>;
881 + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
882 +
883 + interrupt-parent = <&gpio_intc>;
884 +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi
885 +index ad812854a107f..a350fee1264d7 100644
886 +--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi
887 ++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi
888 +@@ -147,7 +147,7 @@
889 + reg = <0>;
890 +
891 + reset-assert-us = <10000>;
892 +- reset-deassert-us = <30000>;
893 ++ reset-deassert-us = <80000>;
894 + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
895 +
896 + interrupt-parent = <&gpio_intc>;
897 +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
898 +index b08c4537f260d..b2ab05c220903 100644
899 +--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
900 ++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
901 +@@ -82,7 +82,7 @@
902 +
903 + /* External PHY reset is shared with internal PHY Led signal */
904 + reset-assert-us = <10000>;
905 +- reset-deassert-us = <30000>;
906 ++ reset-deassert-us = <80000>;
907 + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
908 +
909 + interrupt-parent = <&gpio_intc>;
910 +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
911 +index bff8ec2c1c70c..62d3e04299b67 100644
912 +--- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
913 ++++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
914 +@@ -194,7 +194,7 @@
915 + reg = <0>;
916 +
917 + reset-assert-us = <10000>;
918 +- reset-deassert-us = <30000>;
919 ++ reset-deassert-us = <80000>;
920 + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
921 +
922 + interrupt-parent = <&gpio_intc>;
923 +@@ -341,7 +341,7 @@
924 + #size-cells = <1>;
925 + compatible = "winbond,w25q16", "jedec,spi-nor";
926 + reg = <0>;
927 +- spi-max-frequency = <3000000>;
928 ++ spi-max-frequency = <104000000>;
929 + };
930 + };
931 +
932 +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
933 +index 83eca3af44ce7..dfa7a37a1281f 100644
934 +--- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
935 ++++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
936 +@@ -112,7 +112,7 @@
937 + max-speed = <1000>;
938 +
939 + reset-assert-us = <10000>;
940 +- reset-deassert-us = <30000>;
941 ++ reset-deassert-us = <80000>;
942 + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
943 + };
944 + };
945 +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
946 +index ea45ae0c71b7f..8edbfe040805c 100644
947 +--- a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
948 ++++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
949 +@@ -64,7 +64,7 @@
950 +
951 + /* External PHY reset is shared with internal PHY Led signal */
952 + reset-assert-us = <10000>;
953 +- reset-deassert-us = <30000>;
954 ++ reset-deassert-us = <80000>;
955 + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
956 +
957 + interrupt-parent = <&gpio_intc>;
958 +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
959 +index c89c9f846fb10..dde7cfe12cffa 100644
960 +--- a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
961 ++++ b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
962 +@@ -114,7 +114,7 @@
963 + max-speed = <1000>;
964 +
965 + reset-assert-us = <10000>;
966 +- reset-deassert-us = <30000>;
967 ++ reset-deassert-us = <80000>;
968 + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
969 + };
970 + };
971 +diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
972 +index 71317f5aada1d..c309517abae32 100644
973 +--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
974 ++++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
975 +@@ -130,7 +130,7 @@
976 + opp-microvolt = <790000>;
977 + };
978 +
979 +- opp-1512000000 {
980 ++ opp-1500000000 {
981 + opp-hz = /bits/ 64 <1500000000>;
982 + opp-microvolt = <800000>;
983 + };
984 +diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
985 +index b9ed6a33e2901..7599e1a00ff51 100644
986 +--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
987 ++++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
988 +@@ -79,8 +79,10 @@
989 + };
990 +
991 + psci {
992 +- compatible = "arm,psci-0.2";
993 ++ compatible = "arm,psci";
994 + method = "smc";
995 ++ cpu_off = <0x84000002>;
996 ++ cpu_on = <0xC4000003>;
997 + };
998 +
999 + soc: soc@0 {
1000 +@@ -481,13 +483,6 @@
1001 + pmu_system_controller: system-controller@105c0000 {
1002 + compatible = "samsung,exynos7-pmu", "syscon";
1003 + reg = <0x105c0000 0x5000>;
1004 +-
1005 +- reboot: syscon-reboot {
1006 +- compatible = "syscon-reboot";
1007 +- regmap = <&pmu_system_controller>;
1008 +- offset = <0x0400>;
1009 +- mask = <0x1>;
1010 +- };
1011 + };
1012 +
1013 + rtc: rtc@10590000 {
1014 +@@ -687,3 +682,4 @@
1015 + };
1016 +
1017 + #include "exynos7-pinctrl.dtsi"
1018 ++#include "arm/exynos-syscon-restart.dtsi"
1019 +diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
1020 +index 8161dd2379712..b3fa4dbeebd52 100644
1021 +--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
1022 ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
1023 +@@ -155,20 +155,10 @@
1024 + };
1025 +
1026 + partition@210000 {
1027 +- reg = <0x210000 0x0f0000>;
1028 ++ reg = <0x210000 0x1d0000>;
1029 + label = "bootloader";
1030 + };
1031 +
1032 +- partition@300000 {
1033 +- reg = <0x300000 0x040000>;
1034 +- label = "DP firmware";
1035 +- };
1036 +-
1037 +- partition@340000 {
1038 +- reg = <0x340000 0x0a0000>;
1039 +- label = "trusted firmware";
1040 +- };
1041 +-
1042 + partition@3e0000 {
1043 + reg = <0x3e0000 0x020000>;
1044 + label = "bootloader environment";
1045 +diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
1046 +index 7a6fb7e1fb82f..33aa0efa2293a 100644
1047 +--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
1048 ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
1049 +@@ -309,7 +309,7 @@
1050 + <0x0 0x20000000 0x0 0x10000000>;
1051 + reg-names = "fspi_base", "fspi_mmap";
1052 + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1053 +- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
1054 ++ clocks = <&clockgen 2 0>, <&clockgen 2 0>;
1055 + clock-names = "fspi_en", "fspi";
1056 + status = "disabled";
1057 + };
1058 +@@ -934,7 +934,7 @@
1059 + ethernet@0,4 {
1060 + compatible = "fsl,enetc-ptp";
1061 + reg = <0x000400 0 0 0 0>;
1062 +- clocks = <&clockgen 4 0>;
1063 ++ clocks = <&clockgen 2 3>;
1064 + little-endian;
1065 + fsl,extts-fifo;
1066 + };
1067 +diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
1068 +index f3a678e0fd99b..bf76ebe463794 100644
1069 +--- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
1070 ++++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
1071 +@@ -146,7 +146,7 @@
1072 + pinctrl-names = "default";
1073 + pinctrl-0 = <&rgmii_pins>;
1074 + phy-mode = "rgmii-id";
1075 +- phy = <&phy1>;
1076 ++ phy-handle = <&phy1>;
1077 + status = "okay";
1078 + };
1079 +
1080 +diff --git a/arch/arm64/boot/dts/marvell/armada-7040.dtsi b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
1081 +index 7a3198cd7a071..2f440711d21d2 100644
1082 +--- a/arch/arm64/boot/dts/marvell/armada-7040.dtsi
1083 ++++ b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
1084 +@@ -15,10 +15,6 @@
1085 + "marvell,armada-ap806";
1086 + };
1087 +
1088 +-&smmu {
1089 +- status = "okay";
1090 +-};
1091 +-
1092 + &cp0_pcie0 {
1093 + iommu-map =
1094 + <0x0 &smmu 0x480 0x20>,
1095 +diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
1096 +index 79e8ce59baa88..22c2d6ebf3818 100644
1097 +--- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi
1098 ++++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
1099 +@@ -15,10 +15,6 @@
1100 + "marvell,armada-ap806";
1101 + };
1102 +
1103 +-&smmu {
1104 +- status = "okay";
1105 +-};
1106 +-
1107 + &cp0_pcie0 {
1108 + iommu-map =
1109 + <0x0 &smmu 0x480 0x20>,
1110 +diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
1111 +index 9cfd961c45eb3..08a914d3a6435 100644
1112 +--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
1113 ++++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
1114 +@@ -363,7 +363,7 @@
1115 + compatible = "mediatek,mt8183-gce";
1116 + reg = <0 0x10238000 0 0x4000>;
1117 + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
1118 +- #mbox-cells = <3>;
1119 ++ #mbox-cells = <2>;
1120 + clocks = <&infracfg CLK_INFRA_GCE>;
1121 + clock-names = "gce";
1122 + };
1123 +diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
1124 +index 93438d2b94696..6946fb210e484 100644
1125 +--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
1126 ++++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
1127 +@@ -378,7 +378,7 @@
1128 + nvidia,schmitt = <TEGRA_PIN_DISABLE>;
1129 + nvidia,lpdr = <TEGRA_PIN_ENABLE>;
1130 + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1131 +- nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
1132 ++ nvidia,io-hv = <TEGRA_PIN_ENABLE>;
1133 + nvidia,tristate = <TEGRA_PIN_DISABLE>;
1134 + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1135 + };
1136 +@@ -390,7 +390,7 @@
1137 + nvidia,schmitt = <TEGRA_PIN_DISABLE>;
1138 + nvidia,lpdr = <TEGRA_PIN_ENABLE>;
1139 + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1140 +- nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
1141 ++ nvidia,io-hv = <TEGRA_PIN_ENABLE>;
1142 + nvidia,tristate = <TEGRA_PIN_DISABLE>;
1143 + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1144 + };
1145 +diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
1146 +index 59e0cbfa22143..cdc1e3d60c58e 100644
1147 +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
1148 ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
1149 +@@ -156,8 +156,8 @@
1150 + no-map;
1151 + };
1152 +
1153 +- tz: tz@48500000 {
1154 +- reg = <0x0 0x48500000 0x0 0x00200000>;
1155 ++ tz: memory@4a600000 {
1156 ++ reg = <0x0 0x4a600000 0x0 0x00400000>;
1157 + no-map;
1158 + };
1159 +
1160 +@@ -167,7 +167,7 @@
1161 + };
1162 +
1163 + q6_region: memory@4ab00000 {
1164 +- reg = <0x0 0x4ab00000 0x0 0x02800000>;
1165 ++ reg = <0x0 0x4ab00000 0x0 0x05500000>;
1166 + no-map;
1167 + };
1168 + };
1169 +diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
1170 +index b18d21e42f596..f7ac4c4033db6 100644
1171 +--- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
1172 ++++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
1173 +@@ -78,6 +78,9 @@
1174 + sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
1175 + scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
1176 +
1177 ++ pinctrl-names = "default";
1178 ++ pinctrl-0 = <&muic_i2c_default>;
1179 ++
1180 + #address-cells = <1>;
1181 + #size-cells = <0>;
1182 +
1183 +@@ -314,6 +317,14 @@
1184 + };
1185 + };
1186 +
1187 ++ muic_i2c_default: muic-i2c-default {
1188 ++ pins = "gpio105", "gpio106";
1189 ++ function = "gpio";
1190 ++
1191 ++ drive-strength = <2>;
1192 ++ bias-disable;
1193 ++ };
1194 ++
1195 + muic_int_default: muic-int-default {
1196 + pins = "gpio12";
1197 + function = "gpio";
1198 +diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
1199 +index 6678f1e8e3958..c71f3afc1cc9f 100644
1200 +--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
1201 ++++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
1202 +@@ -1394,7 +1394,8 @@
1203 + ipa: ipa@1e40000 {
1204 + compatible = "qcom,sc7180-ipa";
1205 +
1206 +- iommus = <&apps_smmu 0x440 0x3>;
1207 ++ iommus = <&apps_smmu 0x440 0x0>,
1208 ++ <&apps_smmu 0x442 0x0>;
1209 + reg = <0 0x1e40000 0 0x7000>,
1210 + <0 0x1e47000 0 0x2000>,
1211 + <0 0x1e04000 0 0x2c000>;
1212 +@@ -2811,7 +2812,7 @@
1213 + interrupt-controller;
1214 + #interrupt-cells = <1>;
1215 +
1216 +- interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
1217 ++ interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
1218 + interconnect-names = "mdp0-mem";
1219 +
1220 + iommus = <&apps_smmu 0x800 0x2>;
1221 +diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
1222 +index 40e8c11f23ab0..f97f354af86f4 100644
1223 +--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
1224 ++++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
1225 +@@ -2141,7 +2141,8 @@
1226 + ipa: ipa@1e40000 {
1227 + compatible = "qcom,sdm845-ipa";
1228 +
1229 +- iommus = <&apps_smmu 0x720 0x3>;
1230 ++ iommus = <&apps_smmu 0x720 0x0>,
1231 ++ <&apps_smmu 0x722 0x0>;
1232 + reg = <0 0x1e40000 0 0x7000>,
1233 + <0 0x1e47000 0 0x2000>,
1234 + <0 0x1e04000 0 0x2c000>;
1235 +diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
1236 +index d03ca31907466..76a8c996d497f 100644
1237 +--- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
1238 ++++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
1239 +@@ -264,23 +264,28 @@
1240 + status = "okay";
1241 + clock-frequency = <400000>;
1242 +
1243 +- hid@15 {
1244 ++ tsel: hid@15 {
1245 + compatible = "hid-over-i2c";
1246 + reg = <0x15>;
1247 + hid-descr-addr = <0x1>;
1248 +
1249 +- interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_RISING>;
1250 ++ interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_HIGH>;
1251 ++
1252 ++ pinctrl-names = "default";
1253 ++ pinctrl-0 = <&i2c3_hid_active>;
1254 + };
1255 +
1256 +- hid@2c {
1257 ++ tsc2: hid@2c {
1258 + compatible = "hid-over-i2c";
1259 + reg = <0x2c>;
1260 + hid-descr-addr = <0x20>;
1261 +
1262 +- interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_RISING>;
1263 ++ interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_HIGH>;
1264 +
1265 + pinctrl-names = "default";
1266 +- pinctrl-0 = <&i2c2_hid_active>;
1267 ++ pinctrl-0 = <&i2c3_hid_active>;
1268 ++
1269 ++ status = "disabled";
1270 + };
1271 + };
1272 +
1273 +@@ -288,15 +293,15 @@
1274 + status = "okay";
1275 + clock-frequency = <400000>;
1276 +
1277 +- hid@10 {
1278 ++ tsc1: hid@10 {
1279 + compatible = "hid-over-i2c";
1280 + reg = <0x10>;
1281 + hid-descr-addr = <0x1>;
1282 +
1283 +- interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>;
1284 ++ interrupts-extended = <&tlmm 125 IRQ_TYPE_LEVEL_LOW>;
1285 +
1286 + pinctrl-names = "default";
1287 +- pinctrl-0 = <&i2c6_hid_active>;
1288 ++ pinctrl-0 = <&i2c5_hid_active>;
1289 + };
1290 + };
1291 +
1292 +@@ -304,7 +309,7 @@
1293 + status = "okay";
1294 + clock-frequency = <400000>;
1295 +
1296 +- hid@5c {
1297 ++ ecsh: hid@5c {
1298 + compatible = "hid-over-i2c";
1299 + reg = <0x5c>;
1300 + hid-descr-addr = <0x1>;
1301 +@@ -312,7 +317,7 @@
1302 + interrupts-extended = <&tlmm 92 IRQ_TYPE_LEVEL_LOW>;
1303 +
1304 + pinctrl-names = "default";
1305 +- pinctrl-0 = <&i2c12_hid_active>;
1306 ++ pinctrl-0 = <&i2c11_hid_active>;
1307 + };
1308 + };
1309 +
1310 +@@ -426,8 +431,8 @@
1311 + &tlmm {
1312 + gpio-reserved-ranges = <0 4>, <81 4>;
1313 +
1314 +- i2c2_hid_active: i2c2-hid-active {
1315 +- pins = <37>;
1316 ++ i2c3_hid_active: i2c2-hid-active {
1317 ++ pins = "gpio37";
1318 + function = "gpio";
1319 +
1320 + input-enable;
1321 +@@ -435,8 +440,8 @@
1322 + drive-strength = <2>;
1323 + };
1324 +
1325 +- i2c6_hid_active: i2c6-hid-active {
1326 +- pins = <125>;
1327 ++ i2c5_hid_active: i2c5-hid-active {
1328 ++ pins = "gpio125";
1329 + function = "gpio";
1330 +
1331 + input-enable;
1332 +@@ -444,8 +449,8 @@
1333 + drive-strength = <2>;
1334 + };
1335 +
1336 +- i2c12_hid_active: i2c12-hid-active {
1337 +- pins = <92>;
1338 ++ i2c11_hid_active: i2c11-hid-active {
1339 ++ pins = "gpio92";
1340 + function = "gpio";
1341 +
1342 + input-enable;
1343 +@@ -454,7 +459,7 @@
1344 + };
1345 +
1346 + wcd_intr_default: wcd_intr_default {
1347 +- pins = <54>;
1348 ++ pins = "gpio54";
1349 + function = "gpio";
1350 +
1351 + input-enable;
1352 +diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts
1353 +index fd194ed7fbc86..98675e1f8204f 100644
1354 +--- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts
1355 ++++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts
1356 +@@ -14,7 +14,7 @@
1357 +
1358 + / {
1359 + model = "Qualcomm Technologies, Inc. SM8250 MTP";
1360 +- compatible = "qcom,sm8250-mtp";
1361 ++ compatible = "qcom,sm8250-mtp", "qcom,sm8250";
1362 +
1363 + aliases {
1364 + serial0 = &uart12;
1365 +diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi
1366 +index 33daa95706840..801ea54b027c4 100644
1367 +--- a/arch/arm64/boot/dts/renesas/cat875.dtsi
1368 ++++ b/arch/arm64/boot/dts/renesas/cat875.dtsi
1369 +@@ -21,7 +21,6 @@
1370 + status = "okay";
1371 +
1372 + phy0: ethernet-phy@0 {
1373 +- rxc-skew-ps = <1500>;
1374 + reg = <0>;
1375 + interrupt-parent = <&gpio2>;
1376 + interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
1377 +diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
1378 +index 178401a34cbf8..b9e46aed53362 100644
1379 +--- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
1380 ++++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
1381 +@@ -23,7 +23,6 @@
1382 + status = "okay";
1383 +
1384 + phy0: ethernet-phy@0 {
1385 +- rxc-skew-ps = <1500>;
1386 + reg = <0>;
1387 + interrupt-parent = <&gpio2>;
1388 + interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
1389 +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
1390 +index b70ffb1c6a630..b76282e704de1 100644
1391 +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
1392 ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
1393 +@@ -334,6 +334,7 @@
1394 + };
1395 +
1396 + &usb20_otg {
1397 ++ dr_mode = "host";
1398 + status = "okay";
1399 + };
1400 +
1401 +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
1402 +index bbdb19a3e85d1..db0d5c8e5f96a 100644
1403 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
1404 ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
1405 +@@ -1237,8 +1237,8 @@
1406 +
1407 + uart0 {
1408 + uart0_xfer: uart0-xfer {
1409 +- rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
1410 +- <1 RK_PB0 1 &pcfg_pull_none>;
1411 ++ rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1412 ++ <1 RK_PB0 1 &pcfg_pull_up>;
1413 + };
1414 +
1415 + uart0_cts: uart0-cts {
1416 +@@ -1256,8 +1256,8 @@
1417 +
1418 + uart1 {
1419 + uart1_xfer: uart1-xfer {
1420 +- rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
1421 +- <3 RK_PA6 4 &pcfg_pull_none>;
1422 ++ rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
1423 ++ <3 RK_PA6 4 &pcfg_pull_up>;
1424 + };
1425 +
1426 + uart1_cts: uart1-cts {
1427 +@@ -1275,15 +1275,15 @@
1428 +
1429 + uart2-0 {
1430 + uart2m0_xfer: uart2m0-xfer {
1431 +- rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
1432 +- <1 RK_PA1 2 &pcfg_pull_none>;
1433 ++ rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
1434 ++ <1 RK_PA1 2 &pcfg_pull_up>;
1435 + };
1436 + };
1437 +
1438 + uart2-1 {
1439 + uart2m1_xfer: uart2m1-xfer {
1440 +- rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
1441 +- <2 RK_PA1 1 &pcfg_pull_none>;
1442 ++ rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
1443 ++ <2 RK_PA1 1 &pcfg_pull_up>;
1444 + };
1445 + };
1446 +
1447 +diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
1448 +index 533525229a8db..b9662205be9bf 100644
1449 +--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
1450 ++++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
1451 +@@ -834,7 +834,7 @@
1452 + };
1453 + };
1454 +
1455 +- dss: dss@04a00000 {
1456 ++ dss: dss@4a00000 {
1457 + compatible = "ti,am65x-dss";
1458 + reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
1459 + <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
1460 +@@ -867,6 +867,8 @@
1461 +
1462 + status = "disabled";
1463 +
1464 ++ dma-coherent;
1465 ++
1466 + dss_ports: ports {
1467 + #address-cells = <1>;
1468 + #size-cells = <0>;
1469 +diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
1470 +index e2a96b2c423c4..c66ded9079be4 100644
1471 +--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
1472 ++++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
1473 +@@ -1278,7 +1278,7 @@
1474 + };
1475 + };
1476 +
1477 +- dss: dss@04a00000 {
1478 ++ dss: dss@4a00000 {
1479 + compatible = "ti,j721e-dss";
1480 + reg =
1481 + <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1482 +diff --git a/arch/arm64/crypto/poly1305-armv8.pl b/arch/arm64/crypto/poly1305-armv8.pl
1483 +index 6e5576d19af8f..cbc980fb02e33 100644
1484 +--- a/arch/arm64/crypto/poly1305-armv8.pl
1485 ++++ b/arch/arm64/crypto/poly1305-armv8.pl
1486 +@@ -840,7 +840,6 @@ poly1305_blocks_neon:
1487 + ldp d14,d15,[sp,#64]
1488 + addp $ACC2,$ACC2,$ACC2
1489 + ldr x30,[sp,#8]
1490 +- .inst 0xd50323bf // autiasp
1491 +
1492 + ////////////////////////////////////////////////////////////////
1493 + // lazy reduction, but without narrowing
1494 +@@ -882,6 +881,7 @@ poly1305_blocks_neon:
1495 + str x4,[$ctx,#8] // set is_base2_26
1496 +
1497 + ldr x29,[sp],#80
1498 ++ .inst 0xd50323bf // autiasp
1499 + ret
1500 + .size poly1305_blocks_neon,.-poly1305_blocks_neon
1501 +
1502 +diff --git a/arch/arm64/crypto/poly1305-core.S_shipped b/arch/arm64/crypto/poly1305-core.S_shipped
1503 +index 8d1c4e420ccdc..fb2822abf63aa 100644
1504 +--- a/arch/arm64/crypto/poly1305-core.S_shipped
1505 ++++ b/arch/arm64/crypto/poly1305-core.S_shipped
1506 +@@ -779,7 +779,6 @@ poly1305_blocks_neon:
1507 + ldp d14,d15,[sp,#64]
1508 + addp v21.2d,v21.2d,v21.2d
1509 + ldr x30,[sp,#8]
1510 +- .inst 0xd50323bf // autiasp
1511 +
1512 + ////////////////////////////////////////////////////////////////
1513 + // lazy reduction, but without narrowing
1514 +@@ -821,6 +820,7 @@ poly1305_blocks_neon:
1515 + str x4,[x0,#8] // set is_base2_26
1516 +
1517 + ldr x29,[sp],#80
1518 ++ .inst 0xd50323bf // autiasp
1519 + ret
1520 + .size poly1305_blocks_neon,.-poly1305_blocks_neon
1521 +
1522 +diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
1523 +index 0cd9f0f75c135..cc060c41adaab 100644
1524 +--- a/arch/arm64/include/asm/kvm_host.h
1525 ++++ b/arch/arm64/include/asm/kvm_host.h
1526 +@@ -214,6 +214,7 @@ enum vcpu_sysreg {
1527 + #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
1528 + #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
1529 + #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
1530 ++#define c2_TTBCR2 (c2_TTBCR + 1) /* Translation Table Base Control R. 2 */
1531 + #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
1532 + #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
1533 + #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
1534 +diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c
1535 +index 52a0638ed967b..ef15c8a2a49dc 100644
1536 +--- a/arch/arm64/kernel/mte.c
1537 ++++ b/arch/arm64/kernel/mte.c
1538 +@@ -189,7 +189,8 @@ long get_mte_ctrl(struct task_struct *task)
1539 +
1540 + switch (task->thread.sctlr_tcf0) {
1541 + case SCTLR_EL1_TCF0_NONE:
1542 +- return PR_MTE_TCF_NONE;
1543 ++ ret |= PR_MTE_TCF_NONE;
1544 ++ break;
1545 + case SCTLR_EL1_TCF0_SYNC:
1546 + ret |= PR_MTE_TCF_SYNC;
1547 + break;
1548 +diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
1549 +index c1fac9836af1a..2b28bf1a53266 100644
1550 +--- a/arch/arm64/kvm/sys_regs.c
1551 ++++ b/arch/arm64/kvm/sys_regs.c
1552 +@@ -1987,6 +1987,7 @@ static const struct sys_reg_desc cp15_regs[] = {
1553 + { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1554 + { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1555 + { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1556 ++ { Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, c2_TTBCR2 },
1557 + { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1558 + { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1559 + { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1560 +diff --git a/arch/m68k/mac/config.c b/arch/m68k/mac/config.c
1561 +index 0ac53d87493c8..2bea1799b8de7 100644
1562 +--- a/arch/m68k/mac/config.c
1563 ++++ b/arch/m68k/mac/config.c
1564 +@@ -777,16 +777,12 @@ static struct resource scc_b_rsrcs[] = {
1565 + struct platform_device scc_a_pdev = {
1566 + .name = "scc",
1567 + .id = 0,
1568 +- .num_resources = ARRAY_SIZE(scc_a_rsrcs),
1569 +- .resource = scc_a_rsrcs,
1570 + };
1571 + EXPORT_SYMBOL(scc_a_pdev);
1572 +
1573 + struct platform_device scc_b_pdev = {
1574 + .name = "scc",
1575 + .id = 1,
1576 +- .num_resources = ARRAY_SIZE(scc_b_rsrcs),
1577 +- .resource = scc_b_rsrcs,
1578 + };
1579 + EXPORT_SYMBOL(scc_b_pdev);
1580 +
1581 +@@ -813,10 +809,15 @@ static void __init mac_identify(void)
1582 +
1583 + /* Set up serial port resources for the console initcall. */
1584 +
1585 +- scc_a_rsrcs[0].start = (resource_size_t) mac_bi_data.sccbase + 2;
1586 +- scc_a_rsrcs[0].end = scc_a_rsrcs[0].start;
1587 +- scc_b_rsrcs[0].start = (resource_size_t) mac_bi_data.sccbase;
1588 +- scc_b_rsrcs[0].end = scc_b_rsrcs[0].start;
1589 ++ scc_a_rsrcs[0].start = (resource_size_t)mac_bi_data.sccbase + 2;
1590 ++ scc_a_rsrcs[0].end = scc_a_rsrcs[0].start;
1591 ++ scc_a_pdev.num_resources = ARRAY_SIZE(scc_a_rsrcs);
1592 ++ scc_a_pdev.resource = scc_a_rsrcs;
1593 ++
1594 ++ scc_b_rsrcs[0].start = (resource_size_t)mac_bi_data.sccbase;
1595 ++ scc_b_rsrcs[0].end = scc_b_rsrcs[0].start;
1596 ++ scc_b_pdev.num_resources = ARRAY_SIZE(scc_b_rsrcs);
1597 ++ scc_b_pdev.resource = scc_b_rsrcs;
1598 +
1599 + switch (macintosh_config->scc_type) {
1600 + case MAC_SCC_PSC:
1601 +diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig
1602 +index 6889f74e06f54..490bb6da74b7e 100644
1603 +--- a/arch/mips/bcm47xx/Kconfig
1604 ++++ b/arch/mips/bcm47xx/Kconfig
1605 +@@ -27,6 +27,7 @@ config BCM47XX_BCMA
1606 + select BCMA
1607 + select BCMA_HOST_SOC
1608 + select BCMA_DRIVER_MIPS
1609 ++ select BCMA_DRIVER_PCI if PCI
1610 + select BCMA_DRIVER_PCI_HOSTMODE if PCI
1611 + select BCMA_DRIVER_GPIO
1612 + default y
1613 +diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
1614 +index ca579deef9391..9d11f68a9e8bb 100644
1615 +--- a/arch/mips/kernel/setup.c
1616 ++++ b/arch/mips/kernel/setup.c
1617 +@@ -498,8 +498,8 @@ static void __init request_crashkernel(struct resource *res)
1618 +
1619 + static void __init check_kernel_sections_mem(void)
1620 + {
1621 +- phys_addr_t start = PFN_PHYS(PFN_DOWN(__pa_symbol(&_text)));
1622 +- phys_addr_t size = PFN_PHYS(PFN_UP(__pa_symbol(&_end))) - start;
1623 ++ phys_addr_t start = __pa_symbol(&_text);
1624 ++ phys_addr_t size = __pa_symbol(&_end) - start;
1625 +
1626 + if (!memblock_is_region_memory(start, size)) {
1627 + pr_info("Kernel sections are not in the memory maps\n");
1628 +diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
1629 +index f8ce6d2dde7b1..e4b364b5da9e7 100644
1630 +--- a/arch/powerpc/boot/Makefile
1631 ++++ b/arch/powerpc/boot/Makefile
1632 +@@ -368,6 +368,8 @@ initrd-y := $(filter-out $(image-y), $(initrd-y))
1633 + targets += $(image-y) $(initrd-y)
1634 + targets += $(foreach x, dtbImage uImage cuImage simpleImage treeImage, \
1635 + $(patsubst $(x).%, dts/%.dtb, $(filter $(x).%, $(image-y))))
1636 ++targets += $(foreach x, dtbImage uImage cuImage simpleImage treeImage, \
1637 ++ $(patsubst $(x).%, dts/fsl/%.dtb, $(filter $(x).%, $(image-y))))
1638 +
1639 + $(addprefix $(obj)/, $(initrd-y)): $(obj)/ramdisk.image.gz
1640 +
1641 +diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
1642 +index 4a4d3afd53406..299ab33505a6c 100644
1643 +--- a/arch/powerpc/include/asm/bitops.h
1644 ++++ b/arch/powerpc/include/asm/bitops.h
1645 +@@ -216,15 +216,34 @@ static inline void arch___clear_bit_unlock(int nr, volatile unsigned long *addr)
1646 + */
1647 + static inline int fls(unsigned int x)
1648 + {
1649 +- return 32 - __builtin_clz(x);
1650 ++ int lz;
1651 ++
1652 ++ if (__builtin_constant_p(x))
1653 ++ return x ? 32 - __builtin_clz(x) : 0;
1654 ++ asm("cntlzw %0,%1" : "=r" (lz) : "r" (x));
1655 ++ return 32 - lz;
1656 + }
1657 +
1658 + #include <asm-generic/bitops/builtin-__fls.h>
1659 +
1660 ++/*
1661 ++ * 64-bit can do this using one cntlzd (count leading zeroes doubleword)
1662 ++ * instruction; for 32-bit we use the generic version, which does two
1663 ++ * 32-bit fls calls.
1664 ++ */
1665 ++#ifdef CONFIG_PPC64
1666 + static inline int fls64(__u64 x)
1667 + {
1668 +- return 64 - __builtin_clzll(x);
1669 ++ int lz;
1670 ++
1671 ++ if (__builtin_constant_p(x))
1672 ++ return x ? 64 - __builtin_clzll(x) : 0;
1673 ++ asm("cntlzd %0,%1" : "=r" (lz) : "r" (x));
1674 ++ return 64 - lz;
1675 + }
1676 ++#else
1677 ++#include <asm-generic/bitops/fls64.h>
1678 ++#endif
1679 +
1680 + #ifdef CONFIG_PPC64
1681 + unsigned int __arch_hweight8(unsigned int w);
1682 +diff --git a/arch/powerpc/include/asm/book3s/32/mmu-hash.h b/arch/powerpc/include/asm/book3s/32/mmu-hash.h
1683 +index 2e277ca0170fb..a8982d52f6b1d 100644
1684 +--- a/arch/powerpc/include/asm/book3s/32/mmu-hash.h
1685 ++++ b/arch/powerpc/include/asm/book3s/32/mmu-hash.h
1686 +@@ -94,6 +94,7 @@ typedef struct {
1687 + } mm_context_t;
1688 +
1689 + void update_bats(void);
1690 ++static inline void cleanup_cpu_mmu_context(void) { };
1691 +
1692 + /* patch sites */
1693 + extern s32 patch__hash_page_A0, patch__hash_page_A1, patch__hash_page_A2;
1694 +diff --git a/arch/powerpc/include/asm/book3s/32/pgtable.h b/arch/powerpc/include/asm/book3s/32/pgtable.h
1695 +index 1376be95e975f..523d3e6e24009 100644
1696 +--- a/arch/powerpc/include/asm/book3s/32/pgtable.h
1697 ++++ b/arch/powerpc/include/asm/book3s/32/pgtable.h
1698 +@@ -524,9 +524,9 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
1699 + if (pte_val(*ptep) & _PAGE_HASHPTE)
1700 + flush_hash_entry(mm, ptep, addr);
1701 + __asm__ __volatile__("\
1702 +- stw%U0%X0 %2,%0\n\
1703 ++ stw%X0 %2,%0\n\
1704 + eieio\n\
1705 +- stw%U0%X0 %L2,%1"
1706 ++ stw%X1 %L2,%1"
1707 + : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
1708 + : "r" (pte) : "memory");
1709 +
1710 +diff --git a/arch/powerpc/include/asm/cpm1.h b/arch/powerpc/include/asm/cpm1.h
1711 +index a116fe9317892..3bdd74739cb88 100644
1712 +--- a/arch/powerpc/include/asm/cpm1.h
1713 ++++ b/arch/powerpc/include/asm/cpm1.h
1714 +@@ -68,6 +68,7 @@ extern void cpm_reset(void);
1715 + #define PROFF_SPI ((uint)0x0180)
1716 + #define PROFF_SCC3 ((uint)0x0200)
1717 + #define PROFF_SMC1 ((uint)0x0280)
1718 ++#define PROFF_DSP1 ((uint)0x02c0)
1719 + #define PROFF_SCC4 ((uint)0x0300)
1720 + #define PROFF_SMC2 ((uint)0x0380)
1721 +
1722 +diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
1723 +index 3d2f94afc13ae..398eba3998790 100644
1724 +--- a/arch/powerpc/include/asm/cputable.h
1725 ++++ b/arch/powerpc/include/asm/cputable.h
1726 +@@ -369,7 +369,7 @@ static inline void cpu_feature_keys_init(void) { }
1727 + CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
1728 + #define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE)
1729 + #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
1730 +- CPU_FTR_MAYBE_CAN_NAP)
1731 ++ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NOEXECUTE)
1732 + #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
1733 + CPU_FTR_MAYBE_CAN_NAP | \
1734 + CPU_FTR_COMMON | CPU_FTR_NOEXECUTE)
1735 +@@ -409,7 +409,6 @@ static inline void cpu_feature_keys_init(void) { }
1736 + CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
1737 + CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
1738 + CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
1739 +-#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
1740 +
1741 + /* 64-bit CPUs */
1742 + #define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \
1743 +@@ -520,8 +519,6 @@ enum {
1744 + CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
1745 + CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
1746 + CPU_FTRS_CLASSIC32 |
1747 +-#else
1748 +- CPU_FTRS_GENERIC_32 |
1749 + #endif
1750 + #ifdef CONFIG_PPC_8xx
1751 + CPU_FTRS_8XX |
1752 +@@ -596,8 +593,6 @@ enum {
1753 + CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
1754 + CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
1755 + CPU_FTRS_CLASSIC32 &
1756 +-#else
1757 +- CPU_FTRS_GENERIC_32 &
1758 + #endif
1759 + #ifdef CONFIG_PPC_8xx
1760 + CPU_FTRS_8XX &
1761 +diff --git a/arch/powerpc/include/asm/nohash/pgtable.h b/arch/powerpc/include/asm/nohash/pgtable.h
1762 +index 6277e7596ae58..ac75f4ab0dba1 100644
1763 +--- a/arch/powerpc/include/asm/nohash/pgtable.h
1764 ++++ b/arch/powerpc/include/asm/nohash/pgtable.h
1765 +@@ -192,9 +192,9 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
1766 + */
1767 + if (IS_ENABLED(CONFIG_PPC32) && IS_ENABLED(CONFIG_PTE_64BIT) && !percpu) {
1768 + __asm__ __volatile__("\
1769 +- stw%U0%X0 %2,%0\n\
1770 ++ stw%X0 %2,%0\n\
1771 + eieio\n\
1772 +- stw%U0%X0 %L2,%1"
1773 ++ stw%X1 %L2,%1"
1774 + : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
1775 + : "r" (pte) : "memory");
1776 + return;
1777 +diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
1778 +index bf0bf1b900d21..fe2ef598e2ead 100644
1779 +--- a/arch/powerpc/kernel/Makefile
1780 ++++ b/arch/powerpc/kernel/Makefile
1781 +@@ -173,6 +173,9 @@ KCOV_INSTRUMENT_cputable.o := n
1782 + KCOV_INSTRUMENT_setup_64.o := n
1783 + KCOV_INSTRUMENT_paca.o := n
1784 +
1785 ++CFLAGS_setup_64.o += -fno-stack-protector
1786 ++CFLAGS_paca.o += -fno-stack-protector
1787 ++
1788 + extra-$(CONFIG_PPC_FPU) += fpu.o
1789 + extra-$(CONFIG_ALTIVEC) += vector.o
1790 + extra-$(CONFIG_PPC64) += entry_64.o
1791 +diff --git a/arch/powerpc/kernel/head_32.h b/arch/powerpc/kernel/head_32.h
1792 +index 7c767765071da..c88e66adecb52 100644
1793 +--- a/arch/powerpc/kernel/head_32.h
1794 ++++ b/arch/powerpc/kernel/head_32.h
1795 +@@ -131,18 +131,28 @@
1796 + #ifdef CONFIG_VMAP_STACK
1797 + mfspr r11, SPRN_SRR0
1798 + mtctr r11
1799 +-#endif
1800 + andi. r11, r9, MSR_PR
1801 +- lwz r11,TASK_STACK-THREAD(r12)
1802 ++ mr r11, r1
1803 ++ lwz r1,TASK_STACK-THREAD(r12)
1804 + beq- 99f
1805 +- addi r11, r11, THREAD_SIZE - INT_FRAME_SIZE
1806 +-#ifdef CONFIG_VMAP_STACK
1807 ++ addi r1, r1, THREAD_SIZE - INT_FRAME_SIZE
1808 + li r10, MSR_KERNEL & ~(MSR_IR | MSR_RI) /* can take DTLB miss */
1809 + mtmsr r10
1810 + isync
1811 ++ tovirt(r12, r12)
1812 ++ stw r11,GPR1(r1)
1813 ++ stw r11,0(r1)
1814 ++ mr r11, r1
1815 ++#else
1816 ++ andi. r11, r9, MSR_PR
1817 ++ lwz r11,TASK_STACK-THREAD(r12)
1818 ++ beq- 99f
1819 ++ addi r11, r11, THREAD_SIZE - INT_FRAME_SIZE
1820 ++ tophys(r11, r11)
1821 ++ stw r1,GPR1(r11)
1822 ++ stw r1,0(r11)
1823 ++ tovirt(r1, r11) /* set new kernel sp */
1824 + #endif
1825 +- tovirt_vmstack r12, r12
1826 +- tophys_novmstack r11, r11
1827 + mflr r10
1828 + stw r10, _LINK(r11)
1829 + #ifdef CONFIG_VMAP_STACK
1830 +@@ -150,9 +160,6 @@
1831 + #else
1832 + mfspr r10,SPRN_SRR0
1833 + #endif
1834 +- stw r1,GPR1(r11)
1835 +- stw r1,0(r11)
1836 +- tovirt_novmstack r1, r11 /* set new kernel sp */
1837 + stw r10,_NIP(r11)
1838 + mfcr r10
1839 + rlwinm r10,r10,0,4,2 /* Clear SO bit in CR */
1840 +diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
1841 +index 1510b2a56669f..2d6581db0c7b6 100644
1842 +--- a/arch/powerpc/kernel/head_64.S
1843 ++++ b/arch/powerpc/kernel/head_64.S
1844 +@@ -417,6 +417,10 @@ generic_secondary_common_init:
1845 + /* From now on, r24 is expected to be logical cpuid */
1846 + mr r24,r5
1847 +
1848 ++ /* Create a temp kernel stack for use before relocation is on. */
1849 ++ ld r1,PACAEMERGSP(r13)
1850 ++ subi r1,r1,STACK_FRAME_OVERHEAD
1851 ++
1852 + /* See if we need to call a cpu state restore handler */
1853 + LOAD_REG_ADDR(r23, cur_cpu_spec)
1854 + ld r23,0(r23)
1855 +@@ -445,10 +449,6 @@ generic_secondary_common_init:
1856 + sync /* order paca.run and cur_cpu_spec */
1857 + isync /* In case code patching happened */
1858 +
1859 +- /* Create a temp kernel stack for use before relocation is on. */
1860 +- ld r1,PACAEMERGSP(r13)
1861 +- subi r1,r1,STACK_FRAME_OVERHEAD
1862 +-
1863 + b __secondary_start
1864 + #endif /* SMP */
1865 +
1866 +@@ -990,7 +990,7 @@ start_here_common:
1867 + bl start_kernel
1868 +
1869 + /* Not reached */
1870 +- trap
1871 ++0: trap
1872 + EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
1873 + .previous
1874 +
1875 +diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
1876 +index 0ad15768d762c..7f5aae3c387d2 100644
1877 +--- a/arch/powerpc/kernel/paca.c
1878 ++++ b/arch/powerpc/kernel/paca.c
1879 +@@ -208,7 +208,7 @@ static struct rtas_args * __init new_rtas_args(int cpu, unsigned long limit)
1880 + struct paca_struct **paca_ptrs __read_mostly;
1881 + EXPORT_SYMBOL(paca_ptrs);
1882 +
1883 +-void __init __nostackprotector initialise_paca(struct paca_struct *new_paca, int cpu)
1884 ++void __init initialise_paca(struct paca_struct *new_paca, int cpu)
1885 + {
1886 + #ifdef CONFIG_PPC_PSERIES
1887 + new_paca->lppaca_ptr = NULL;
1888 +@@ -241,7 +241,7 @@ void __init __nostackprotector initialise_paca(struct paca_struct *new_paca, int
1889 + }
1890 +
1891 + /* Put the paca pointer into r13 and SPRG_PACA */
1892 +-void __nostackprotector setup_paca(struct paca_struct *new_paca)
1893 ++void setup_paca(struct paca_struct *new_paca)
1894 + {
1895 + /* Setup r13 */
1896 + local_paca = new_paca;
1897 +diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
1898 +index 954f41676f692..cccb32cf0e08c 100644
1899 +--- a/arch/powerpc/kernel/rtas.c
1900 ++++ b/arch/powerpc/kernel/rtas.c
1901 +@@ -1030,7 +1030,7 @@ static struct rtas_filter rtas_filters[] __ro_after_init = {
1902 + { "ibm,display-message", -1, 0, -1, -1, -1 },
1903 + { "ibm,errinjct", -1, 2, -1, -1, -1, 1024 },
1904 + { "ibm,close-errinjct", -1, -1, -1, -1, -1 },
1905 +- { "ibm,open-errinct", -1, -1, -1, -1, -1 },
1906 ++ { "ibm,open-errinjct", -1, -1, -1, -1, -1 },
1907 + { "ibm,get-config-addr-info2", -1, -1, -1, -1, -1 },
1908 + { "ibm,get-dynamic-sensor-state", -1, 1, -1, -1, -1 },
1909 + { "ibm,get-indices", -1, 2, 3, -1, -1 },
1910 +diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
1911 +index 808ec9fab6052..da8c71f321ad3 100644
1912 +--- a/arch/powerpc/kernel/setup-common.c
1913 ++++ b/arch/powerpc/kernel/setup-common.c
1914 +@@ -919,8 +919,6 @@ void __init setup_arch(char **cmdline_p)
1915 +
1916 + /* On BookE, setup per-core TLB data structures. */
1917 + setup_tlb_core_data();
1918 +-
1919 +- smp_release_cpus();
1920 + #endif
1921 +
1922 + /* Print various info about the machine that has been gathered so far. */
1923 +@@ -944,6 +942,8 @@ void __init setup_arch(char **cmdline_p)
1924 + exc_lvl_early_init();
1925 + emergency_stack_init();
1926 +
1927 ++ smp_release_cpus();
1928 ++
1929 + initmem_init();
1930 +
1931 + early_memtest(min_low_pfn << PAGE_SHIFT, max_low_pfn << PAGE_SHIFT);
1932 +diff --git a/arch/powerpc/kernel/setup.h b/arch/powerpc/kernel/setup.h
1933 +index 2ec835574cc94..2dd0d9cb5a208 100644
1934 +--- a/arch/powerpc/kernel/setup.h
1935 ++++ b/arch/powerpc/kernel/setup.h
1936 +@@ -8,12 +8,6 @@
1937 + #ifndef __ARCH_POWERPC_KERNEL_SETUP_H
1938 + #define __ARCH_POWERPC_KERNEL_SETUP_H
1939 +
1940 +-#ifdef CONFIG_CC_IS_CLANG
1941 +-#define __nostackprotector
1942 +-#else
1943 +-#define __nostackprotector __attribute__((__optimize__("no-stack-protector")))
1944 +-#endif
1945 +-
1946 + void initialize_cache_info(void);
1947 + void irqstack_early_init(void);
1948 +
1949 +diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
1950 +index 74fd47f46fa58..c28e949cc2229 100644
1951 +--- a/arch/powerpc/kernel/setup_64.c
1952 ++++ b/arch/powerpc/kernel/setup_64.c
1953 +@@ -283,7 +283,7 @@ void __init record_spr_defaults(void)
1954 + * device-tree is not accessible via normal means at this point.
1955 + */
1956 +
1957 +-void __init __nostackprotector early_setup(unsigned long dt_ptr)
1958 ++void __init early_setup(unsigned long dt_ptr)
1959 + {
1960 + static __initdata struct paca_struct boot_paca;
1961 +
1962 +diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
1963 +index 8c2857cbd9609..7d6cf75a7fd80 100644
1964 +--- a/arch/powerpc/kernel/smp.c
1965 ++++ b/arch/powerpc/kernel/smp.c
1966 +@@ -919,7 +919,7 @@ static struct sched_domain_topology_level powerpc_topology[] = {
1967 + { NULL, },
1968 + };
1969 +
1970 +-static int init_big_cores(void)
1971 ++static int __init init_big_cores(void)
1972 + {
1973 + int cpu;
1974 +
1975 +diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
1976 +index 855457ed09b54..b18bce1a209fa 100644
1977 +--- a/arch/powerpc/lib/sstep.c
1978 ++++ b/arch/powerpc/lib/sstep.c
1979 +@@ -1346,6 +1346,9 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1980 + switch (opcode) {
1981 + #ifdef __powerpc64__
1982 + case 1:
1983 ++ if (!cpu_has_feature(CPU_FTR_ARCH_31))
1984 ++ return -1;
1985 ++
1986 + prefix_r = GET_PREFIX_R(word);
1987 + ra = GET_PREFIX_RA(suffix);
1988 + rd = (suffix >> 21) & 0x1f;
1989 +@@ -2733,6 +2736,9 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1990 + }
1991 + break;
1992 + case 1: /* Prefixed instructions */
1993 ++ if (!cpu_has_feature(CPU_FTR_ARCH_31))
1994 ++ return -1;
1995 ++
1996 + prefix_r = GET_PREFIX_R(word);
1997 + ra = GET_PREFIX_RA(suffix);
1998 + op->update_reg = ra;
1999 +@@ -2751,6 +2757,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
2000 + case 41: /* plwa */
2001 + op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
2002 + break;
2003 ++#ifdef CONFIG_VSX
2004 + case 42: /* plxsd */
2005 + op->reg = rd + 32;
2006 + op->type = MKOP(LOAD_VSX, PREFIXED, 8);
2007 +@@ -2791,13 +2798,14 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
2008 + op->element_size = 16;
2009 + op->vsx_flags = VSX_CHECK_VEC;
2010 + break;
2011 ++#endif /* CONFIG_VSX */
2012 + case 56: /* plq */
2013 + op->type = MKOP(LOAD, PREFIXED, 16);
2014 + break;
2015 + case 57: /* pld */
2016 + op->type = MKOP(LOAD, PREFIXED, 8);
2017 + break;
2018 +- case 60: /* stq */
2019 ++ case 60: /* pstq */
2020 + op->type = MKOP(STORE, PREFIXED, 16);
2021 + break;
2022 + case 61: /* pstd */
2023 +diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
2024 +index 0add963a849b3..72e1b51beb10c 100644
2025 +--- a/arch/powerpc/mm/fault.c
2026 ++++ b/arch/powerpc/mm/fault.c
2027 +@@ -303,7 +303,6 @@ static inline void cmo_account_page_fault(void)
2028 + static inline void cmo_account_page_fault(void) { }
2029 + #endif /* CONFIG_PPC_SMLPAR */
2030 +
2031 +-#ifdef CONFIG_PPC_BOOK3S
2032 + static void sanity_check_fault(bool is_write, bool is_user,
2033 + unsigned long error_code, unsigned long address)
2034 + {
2035 +@@ -320,6 +319,9 @@ static void sanity_check_fault(bool is_write, bool is_user,
2036 + return;
2037 + }
2038 +
2039 ++ if (!IS_ENABLED(CONFIG_PPC_BOOK3S))
2040 ++ return;
2041 ++
2042 + /*
2043 + * For hash translation mode, we should never get a
2044 + * PROTFAULT. Any update to pte to reduce access will result in us
2045 +@@ -354,10 +356,6 @@ static void sanity_check_fault(bool is_write, bool is_user,
2046 +
2047 + WARN_ON_ONCE(error_code & DSISR_PROTFAULT);
2048 + }
2049 +-#else
2050 +-static void sanity_check_fault(bool is_write, bool is_user,
2051 +- unsigned long error_code, unsigned long address) { }
2052 +-#endif /* CONFIG_PPC_BOOK3S */
2053 +
2054 + /*
2055 + * Define the correct "is_write" bit in error_code based
2056 +diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
2057 +index 3fc325bebe4df..22eb1c718e622 100644
2058 +--- a/arch/powerpc/mm/mem.c
2059 ++++ b/arch/powerpc/mm/mem.c
2060 +@@ -532,7 +532,7 @@ void __flush_dcache_icache(void *p)
2061 + * space occurs, before returning to user space.
2062 + */
2063 +
2064 +- if (cpu_has_feature(MMU_FTR_TYPE_44x))
2065 ++ if (mmu_has_feature(MMU_FTR_TYPE_44x))
2066 + return;
2067 +
2068 + invalidate_icache_range(addr, addr + PAGE_SIZE);
2069 +diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
2070 +index 08643cba14948..43599e671d383 100644
2071 +--- a/arch/powerpc/perf/core-book3s.c
2072 ++++ b/arch/powerpc/perf/core-book3s.c
2073 +@@ -137,6 +137,9 @@ static void pmao_restore_workaround(bool ebb) { }
2074 +
2075 + bool is_sier_available(void)
2076 + {
2077 ++ if (!ppmu)
2078 ++ return false;
2079 ++
2080 + if (ppmu->flags & PPMU_HAS_SIER)
2081 + return true;
2082 +
2083 +@@ -2121,6 +2124,16 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
2084 + local64_set(&event->hw.period_left, left);
2085 + perf_event_update_userpage(event);
2086 +
2087 ++ /*
2088 ++ * Due to hardware limitation, sometimes SIAR could sample a kernel
2089 ++ * address even when freeze on supervisor state (kernel) is set in
2090 ++ * MMCR2. Check attr.exclude_kernel and address to drop the sample in
2091 ++ * these cases.
2092 ++ */
2093 ++ if (event->attr.exclude_kernel && record)
2094 ++ if (is_kernel_addr(mfspr(SPRN_SIAR)))
2095 ++ record = 0;
2096 ++
2097 + /*
2098 + * Finally record data if requested.
2099 + */
2100 +diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c
2101 +index 2848904df6383..e1a21d34c6e49 100644
2102 +--- a/arch/powerpc/perf/isa207-common.c
2103 ++++ b/arch/powerpc/perf/isa207-common.c
2104 +@@ -247,6 +247,9 @@ void isa207_get_mem_weight(u64 *weight)
2105 + u64 sier = mfspr(SPRN_SIER);
2106 + u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
2107 +
2108 ++ if (cpu_has_feature(CPU_FTR_ARCH_31))
2109 ++ mantissa = P10_MMCRA_THR_CTR_MANT(mmcra);
2110 ++
2111 + if (val == 0 || val == 7)
2112 + *weight = 0;
2113 + else
2114 +@@ -311,9 +314,11 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
2115 + }
2116 +
2117 + if (unit >= 6 && unit <= 9) {
2118 +- if (cpu_has_feature(CPU_FTR_ARCH_31) && (unit == 6)) {
2119 +- mask |= CNST_L2L3_GROUP_MASK;
2120 +- value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT);
2121 ++ if (cpu_has_feature(CPU_FTR_ARCH_31)) {
2122 ++ if (unit == 6) {
2123 ++ mask |= CNST_L2L3_GROUP_MASK;
2124 ++ value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT);
2125 ++ }
2126 + } else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
2127 + mask |= CNST_CACHE_GROUP_MASK;
2128 + value |= CNST_CACHE_GROUP_VAL(event & 0xff);
2129 +@@ -339,12 +344,22 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
2130 + value |= CNST_L1_QUAL_VAL(cache);
2131 + }
2132 +
2133 ++ if (cpu_has_feature(CPU_FTR_ARCH_31)) {
2134 ++ mask |= CNST_RADIX_SCOPE_GROUP_MASK;
2135 ++ value |= CNST_RADIX_SCOPE_GROUP_VAL(event >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT);
2136 ++ }
2137 ++
2138 + if (is_event_marked(event)) {
2139 + mask |= CNST_SAMPLE_MASK;
2140 + value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
2141 + }
2142 +
2143 +- if (cpu_has_feature(CPU_FTR_ARCH_300)) {
2144 ++ if (cpu_has_feature(CPU_FTR_ARCH_31)) {
2145 ++ if (event_is_threshold(event)) {
2146 ++ mask |= CNST_THRESH_CTL_SEL_MASK;
2147 ++ value |= CNST_THRESH_CTL_SEL_VAL(event >> EVENT_THRESH_SHIFT);
2148 ++ }
2149 ++ } else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
2150 + if (event_is_threshold(event) && is_thresh_cmp_valid(event)) {
2151 + mask |= CNST_THRESH_MASK;
2152 + value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
2153 +@@ -456,6 +471,13 @@ int isa207_compute_mmcr(u64 event[], int n_ev,
2154 + }
2155 + }
2156 +
2157 ++ /* Set RADIX_SCOPE_QUAL bit */
2158 ++ if (cpu_has_feature(CPU_FTR_ARCH_31)) {
2159 ++ val = (event[i] >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT) &
2160 ++ p10_EVENT_RADIX_SCOPE_QUAL_MASK;
2161 ++ mmcr1 |= val << p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT;
2162 ++ }
2163 ++
2164 + if (is_event_marked(event[i])) {
2165 + mmcra |= MMCRA_SAMPLE_ENABLE;
2166 +
2167 +diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h
2168 +index 7025de5e60e7d..454b32c314406 100644
2169 +--- a/arch/powerpc/perf/isa207-common.h
2170 ++++ b/arch/powerpc/perf/isa207-common.h
2171 +@@ -101,6 +101,9 @@
2172 + #define p10_EVENT_CACHE_SEL_MASK 0x3ull
2173 + #define p10_EVENT_MMCR3_MASK 0x7fffull
2174 + #define p10_EVENT_MMCR3_SHIFT 45
2175 ++#define p10_EVENT_RADIX_SCOPE_QUAL_SHIFT 9
2176 ++#define p10_EVENT_RADIX_SCOPE_QUAL_MASK 0x1
2177 ++#define p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT 45
2178 +
2179 + #define p10_EVENT_VALID_MASK \
2180 + ((p10_SDAR_MODE_MASK << p10_SDAR_MODE_SHIFT | \
2181 +@@ -112,6 +115,7 @@
2182 + (p9_EVENT_COMBINE_MASK << p9_EVENT_COMBINE_SHIFT) | \
2183 + (p10_EVENT_MMCR3_MASK << p10_EVENT_MMCR3_SHIFT) | \
2184 + (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \
2185 ++ (p10_EVENT_RADIX_SCOPE_QUAL_MASK << p10_EVENT_RADIX_SCOPE_QUAL_SHIFT) | \
2186 + EVENT_LINUX_MASK | \
2187 + EVENT_PSEL_MASK))
2188 + /*
2189 +@@ -125,9 +129,9 @@
2190 + *
2191 + * 28 24 20 16 12 8 4 0
2192 + * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
2193 +- * [ ] | [ ] [ sample ] [ ] [6] [5] [4] [3] [2] [1]
2194 +- * | | | |
2195 +- * BHRB IFM -* | | | Count of events for each PMC.
2196 ++ * [ ] | [ ] | [ sample ] [ ] [6] [5] [4] [3] [2] [1]
2197 ++ * | | | | |
2198 ++ * BHRB IFM -* | | |*radix_scope | Count of events for each PMC.
2199 + * EBB -* | | p1, p2, p3, p4, p5, p6.
2200 + * L1 I/D qualifier -* |
2201 + * nc - number of counters -*
2202 +@@ -145,6 +149,9 @@
2203 + #define CNST_THRESH_VAL(v) (((v) & EVENT_THRESH_MASK) << 32)
2204 + #define CNST_THRESH_MASK CNST_THRESH_VAL(EVENT_THRESH_MASK)
2205 +
2206 ++#define CNST_THRESH_CTL_SEL_VAL(v) (((v) & 0x7ffull) << 32)
2207 ++#define CNST_THRESH_CTL_SEL_MASK CNST_THRESH_CTL_SEL_VAL(0x7ff)
2208 ++
2209 + #define CNST_EBB_VAL(v) (((v) & EVENT_EBB_MASK) << 24)
2210 + #define CNST_EBB_MASK CNST_EBB_VAL(EVENT_EBB_MASK)
2211 +
2212 +@@ -165,6 +172,9 @@
2213 + #define CNST_L2L3_GROUP_VAL(v) (((v) & 0x1full) << 55)
2214 + #define CNST_L2L3_GROUP_MASK CNST_L2L3_GROUP_VAL(0x1f)
2215 +
2216 ++#define CNST_RADIX_SCOPE_GROUP_VAL(v) (((v) & 0x1ull) << 21)
2217 ++#define CNST_RADIX_SCOPE_GROUP_MASK CNST_RADIX_SCOPE_GROUP_VAL(1)
2218 ++
2219 + /*
2220 + * For NC we are counting up to 4 events. This requires three bits, and we need
2221 + * the fifth event to overflow and set the 4th bit. To achieve that we bias the
2222 +@@ -221,6 +231,10 @@
2223 + #define MMCRA_THR_CTR_EXP(v) (((v) >> MMCRA_THR_CTR_EXP_SHIFT) &\
2224 + MMCRA_THR_CTR_EXP_MASK)
2225 +
2226 ++#define P10_MMCRA_THR_CTR_MANT_MASK 0xFFul
2227 ++#define P10_MMCRA_THR_CTR_MANT(v) (((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\
2228 ++ P10_MMCRA_THR_CTR_MANT_MASK)
2229 ++
2230 + /* MMCRA Threshold Compare bit constant for power9 */
2231 + #define p9_MMCRA_THR_CMP_SHIFT 45
2232 +
2233 +diff --git a/arch/powerpc/perf/power10-pmu.c b/arch/powerpc/perf/power10-pmu.c
2234 +index 9dbe8f9b89b4f..cf44fb7446130 100644
2235 +--- a/arch/powerpc/perf/power10-pmu.c
2236 ++++ b/arch/powerpc/perf/power10-pmu.c
2237 +@@ -23,10 +23,10 @@
2238 + *
2239 + * 28 24 20 16 12 8 4 0
2240 + * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
2241 +- * [ ] [ sample ] [ ] [ ] [ pmc ] [unit ] [ ] m [ pmcxsel ]
2242 +- * | | | | | |
2243 +- * | | | | | *- mark
2244 +- * | | | *- L1/L2/L3 cache_sel |
2245 ++ * [ ] [ sample ] [ ] [ ] [ pmc ] [unit ] [ ] | m [ pmcxsel ]
2246 ++ * | | | | | | |
2247 ++ * | | | | | | *- mark
2248 ++ * | | | *- L1/L2/L3 cache_sel | |*-radix_scope_qual
2249 + * | | sdar_mode |
2250 + * | *- sampling mode for marked events *- combine
2251 + * |
2252 +@@ -59,6 +59,7 @@
2253 + *
2254 + * MMCR1[16] = cache_sel[0]
2255 + * MMCR1[17] = cache_sel[1]
2256 ++ * MMCR1[18] = radix_scope_qual
2257 + *
2258 + * if mark:
2259 + * MMCRA[63] = 1 (SAMPLE_ENABLE)
2260 +@@ -175,6 +176,7 @@ PMU_FORMAT_ATTR(src_sel, "config:45-46");
2261 + PMU_FORMAT_ATTR(invert_bit, "config:47");
2262 + PMU_FORMAT_ATTR(src_mask, "config:48-53");
2263 + PMU_FORMAT_ATTR(src_match, "config:54-59");
2264 ++PMU_FORMAT_ATTR(radix_scope, "config:9");
2265 +
2266 + static struct attribute *power10_pmu_format_attr[] = {
2267 + &format_attr_event.attr,
2268 +@@ -194,6 +196,7 @@ static struct attribute *power10_pmu_format_attr[] = {
2269 + &format_attr_invert_bit.attr,
2270 + &format_attr_src_mask.attr,
2271 + &format_attr_src_match.attr,
2272 ++ &format_attr_radix_scope.attr,
2273 + NULL,
2274 + };
2275 +
2276 +diff --git a/arch/powerpc/platforms/8xx/micropatch.c b/arch/powerpc/platforms/8xx/micropatch.c
2277 +index aed4bc75f3520..aef179fcbd4f8 100644
2278 +--- a/arch/powerpc/platforms/8xx/micropatch.c
2279 ++++ b/arch/powerpc/platforms/8xx/micropatch.c
2280 +@@ -360,6 +360,17 @@ void __init cpm_load_patch(cpm8xx_t *cp)
2281 + if (IS_ENABLED(CONFIG_SMC_UCODE_PATCH)) {
2282 + smc_uart_t *smp;
2283 +
2284 ++ if (IS_ENABLED(CONFIG_PPC_EARLY_DEBUG_CPM)) {
2285 ++ int i;
2286 ++
2287 ++ for (i = 0; i < sizeof(*smp); i += 4) {
2288 ++ u32 __iomem *src = (u32 __iomem *)&cp->cp_dparam[PROFF_SMC1 + i];
2289 ++ u32 __iomem *dst = (u32 __iomem *)&cp->cp_dparam[PROFF_DSP1 + i];
2290 ++
2291 ++ out_be32(dst, in_be32(src));
2292 ++ }
2293 ++ }
2294 ++
2295 + smp = (smc_uart_t *)&cp->cp_dparam[PROFF_SMC1];
2296 + out_be16(&smp->smc_rpbase, 0x1ec0);
2297 + smp = (smc_uart_t *)&cp->cp_dparam[PROFF_SMC2];
2298 +diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
2299 +index c194c4ae8bc7d..32a9c4c09b989 100644
2300 +--- a/arch/powerpc/platforms/Kconfig.cputype
2301 ++++ b/arch/powerpc/platforms/Kconfig.cputype
2302 +@@ -36,7 +36,7 @@ config PPC_BOOK3S_6xx
2303 + select PPC_HAVE_PMU_SUPPORT
2304 + select PPC_HAVE_KUEP
2305 + select PPC_HAVE_KUAP
2306 +- select HAVE_ARCH_VMAP_STACK if !ADB_PMU
2307 ++ select HAVE_ARCH_VMAP_STACK
2308 +
2309 + config PPC_85xx
2310 + bool "Freescale 85xx"
2311 +diff --git a/arch/powerpc/platforms/powermac/sleep.S b/arch/powerpc/platforms/powermac/sleep.S
2312 +index 7e0f8ba6e54a5..d497a60003d2d 100644
2313 +--- a/arch/powerpc/platforms/powermac/sleep.S
2314 ++++ b/arch/powerpc/platforms/powermac/sleep.S
2315 +@@ -44,7 +44,8 @@
2316 + #define SL_TB 0xa0
2317 + #define SL_R2 0xa8
2318 + #define SL_CR 0xac
2319 +-#define SL_R12 0xb0 /* r12 to r31 */
2320 ++#define SL_LR 0xb0
2321 ++#define SL_R12 0xb4 /* r12 to r31 */
2322 + #define SL_SIZE (SL_R12 + 80)
2323 +
2324 + .section .text
2325 +@@ -63,105 +64,107 @@ _GLOBAL(low_sleep_handler)
2326 + blr
2327 + #else
2328 + mflr r0
2329 +- stw r0,4(r1)
2330 +- stwu r1,-SL_SIZE(r1)
2331 ++ lis r11,sleep_storage@ha
2332 ++ addi r11,r11,sleep_storage@l
2333 ++ stw r0,SL_LR(r11)
2334 + mfcr r0
2335 +- stw r0,SL_CR(r1)
2336 +- stw r2,SL_R2(r1)
2337 +- stmw r12,SL_R12(r1)
2338 ++ stw r0,SL_CR(r11)
2339 ++ stw r1,SL_SP(r11)
2340 ++ stw r2,SL_R2(r11)
2341 ++ stmw r12,SL_R12(r11)
2342 +
2343 + /* Save MSR & SDR1 */
2344 + mfmsr r4
2345 +- stw r4,SL_MSR(r1)
2346 ++ stw r4,SL_MSR(r11)
2347 + mfsdr1 r4
2348 +- stw r4,SL_SDR1(r1)
2349 ++ stw r4,SL_SDR1(r11)
2350 +
2351 + /* Get a stable timebase and save it */
2352 + 1: mftbu r4
2353 +- stw r4,SL_TB(r1)
2354 ++ stw r4,SL_TB(r11)
2355 + mftb r5
2356 +- stw r5,SL_TB+4(r1)
2357 ++ stw r5,SL_TB+4(r11)
2358 + mftbu r3
2359 + cmpw r3,r4
2360 + bne 1b
2361 +
2362 + /* Save SPRGs */
2363 + mfsprg r4,0
2364 +- stw r4,SL_SPRG0(r1)
2365 ++ stw r4,SL_SPRG0(r11)
2366 + mfsprg r4,1
2367 +- stw r4,SL_SPRG0+4(r1)
2368 ++ stw r4,SL_SPRG0+4(r11)
2369 + mfsprg r4,2
2370 +- stw r4,SL_SPRG0+8(r1)
2371 ++ stw r4,SL_SPRG0+8(r11)
2372 + mfsprg r4,3
2373 +- stw r4,SL_SPRG0+12(r1)
2374 ++ stw r4,SL_SPRG0+12(r11)
2375 +
2376 + /* Save BATs */
2377 + mfdbatu r4,0
2378 +- stw r4,SL_DBAT0(r1)
2379 ++ stw r4,SL_DBAT0(r11)
2380 + mfdbatl r4,0
2381 +- stw r4,SL_DBAT0+4(r1)
2382 ++ stw r4,SL_DBAT0+4(r11)
2383 + mfdbatu r4,1
2384 +- stw r4,SL_DBAT1(r1)
2385 ++ stw r4,SL_DBAT1(r11)
2386 + mfdbatl r4,1
2387 +- stw r4,SL_DBAT1+4(r1)
2388 ++ stw r4,SL_DBAT1+4(r11)
2389 + mfdbatu r4,2
2390 +- stw r4,SL_DBAT2(r1)
2391 ++ stw r4,SL_DBAT2(r11)
2392 + mfdbatl r4,2
2393 +- stw r4,SL_DBAT2+4(r1)
2394 ++ stw r4,SL_DBAT2+4(r11)
2395 + mfdbatu r4,3
2396 +- stw r4,SL_DBAT3(r1)
2397 ++ stw r4,SL_DBAT3(r11)
2398 + mfdbatl r4,3
2399 +- stw r4,SL_DBAT3+4(r1)
2400 ++ stw r4,SL_DBAT3+4(r11)
2401 + mfibatu r4,0
2402 +- stw r4,SL_IBAT0(r1)
2403 ++ stw r4,SL_IBAT0(r11)
2404 + mfibatl r4,0
2405 +- stw r4,SL_IBAT0+4(r1)
2406 ++ stw r4,SL_IBAT0+4(r11)
2407 + mfibatu r4,1
2408 +- stw r4,SL_IBAT1(r1)
2409 ++ stw r4,SL_IBAT1(r11)
2410 + mfibatl r4,1
2411 +- stw r4,SL_IBAT1+4(r1)
2412 ++ stw r4,SL_IBAT1+4(r11)
2413 + mfibatu r4,2
2414 +- stw r4,SL_IBAT2(r1)
2415 ++ stw r4,SL_IBAT2(r11)
2416 + mfibatl r4,2
2417 +- stw r4,SL_IBAT2+4(r1)
2418 ++ stw r4,SL_IBAT2+4(r11)
2419 + mfibatu r4,3
2420 +- stw r4,SL_IBAT3(r1)
2421 ++ stw r4,SL_IBAT3(r11)
2422 + mfibatl r4,3
2423 +- stw r4,SL_IBAT3+4(r1)
2424 ++ stw r4,SL_IBAT3+4(r11)
2425 +
2426 + BEGIN_MMU_FTR_SECTION
2427 + mfspr r4,SPRN_DBAT4U
2428 +- stw r4,SL_DBAT4(r1)
2429 ++ stw r4,SL_DBAT4(r11)
2430 + mfspr r4,SPRN_DBAT4L
2431 +- stw r4,SL_DBAT4+4(r1)
2432 ++ stw r4,SL_DBAT4+4(r11)
2433 + mfspr r4,SPRN_DBAT5U
2434 +- stw r4,SL_DBAT5(r1)
2435 ++ stw r4,SL_DBAT5(r11)
2436 + mfspr r4,SPRN_DBAT5L
2437 +- stw r4,SL_DBAT5+4(r1)
2438 ++ stw r4,SL_DBAT5+4(r11)
2439 + mfspr r4,SPRN_DBAT6U
2440 +- stw r4,SL_DBAT6(r1)
2441 ++ stw r4,SL_DBAT6(r11)
2442 + mfspr r4,SPRN_DBAT6L
2443 +- stw r4,SL_DBAT6+4(r1)
2444 ++ stw r4,SL_DBAT6+4(r11)
2445 + mfspr r4,SPRN_DBAT7U
2446 +- stw r4,SL_DBAT7(r1)
2447 ++ stw r4,SL_DBAT7(r11)
2448 + mfspr r4,SPRN_DBAT7L
2449 +- stw r4,SL_DBAT7+4(r1)
2450 ++ stw r4,SL_DBAT7+4(r11)
2451 + mfspr r4,SPRN_IBAT4U
2452 +- stw r4,SL_IBAT4(r1)
2453 ++ stw r4,SL_IBAT4(r11)
2454 + mfspr r4,SPRN_IBAT4L
2455 +- stw r4,SL_IBAT4+4(r1)
2456 ++ stw r4,SL_IBAT4+4(r11)
2457 + mfspr r4,SPRN_IBAT5U
2458 +- stw r4,SL_IBAT5(r1)
2459 ++ stw r4,SL_IBAT5(r11)
2460 + mfspr r4,SPRN_IBAT5L
2461 +- stw r4,SL_IBAT5+4(r1)
2462 ++ stw r4,SL_IBAT5+4(r11)
2463 + mfspr r4,SPRN_IBAT6U
2464 +- stw r4,SL_IBAT6(r1)
2465 ++ stw r4,SL_IBAT6(r11)
2466 + mfspr r4,SPRN_IBAT6L
2467 +- stw r4,SL_IBAT6+4(r1)
2468 ++ stw r4,SL_IBAT6+4(r11)
2469 + mfspr r4,SPRN_IBAT7U
2470 +- stw r4,SL_IBAT7(r1)
2471 ++ stw r4,SL_IBAT7(r11)
2472 + mfspr r4,SPRN_IBAT7L
2473 +- stw r4,SL_IBAT7+4(r1)
2474 ++ stw r4,SL_IBAT7+4(r11)
2475 + END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
2476 +
2477 + /* Backup various CPU config stuffs */
2478 +@@ -180,9 +183,9 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
2479 + lis r5,grackle_wake_up@ha
2480 + addi r5,r5,grackle_wake_up@l
2481 + tophys(r5,r5)
2482 +- stw r5,SL_PC(r1)
2483 ++ stw r5,SL_PC(r11)
2484 + lis r4,KERNELBASE@h
2485 +- tophys(r5,r1)
2486 ++ tophys(r5,r11)
2487 + addi r5,r5,SL_PC
2488 + lis r6,MAGIC@ha
2489 + addi r6,r6,MAGIC@l
2490 +@@ -194,12 +197,6 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
2491 + tophys(r3,r3)
2492 + stw r3,0x80(r4)
2493 + stw r5,0x84(r4)
2494 +- /* Store a pointer to our backup storage into
2495 +- * a kernel global
2496 +- */
2497 +- lis r3,sleep_storage@ha
2498 +- addi r3,r3,sleep_storage@l
2499 +- stw r5,0(r3)
2500 +
2501 + .globl low_cpu_offline_self
2502 + low_cpu_offline_self:
2503 +@@ -279,7 +276,7 @@ _GLOBAL(core99_wake_up)
2504 + lis r3,sleep_storage@ha
2505 + addi r3,r3,sleep_storage@l
2506 + tophys(r3,r3)
2507 +- lwz r1,0(r3)
2508 ++ addi r1,r3,SL_PC
2509 +
2510 + /* Pass thru to older resume code ... */
2511 + _ASM_NOKPROBE_SYMBOL(core99_wake_up)
2512 +@@ -399,13 +396,6 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
2513 + blt 1b
2514 + sync
2515 +
2516 +- /* restore the MSR and turn on the MMU */
2517 +- lwz r3,SL_MSR(r1)
2518 +- bl turn_on_mmu
2519 +-
2520 +- /* get back the stack pointer */
2521 +- tovirt(r1,r1)
2522 +-
2523 + /* Restore TB */
2524 + li r3,0
2525 + mttbl r3
2526 +@@ -419,28 +409,24 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
2527 + mtcr r0
2528 + lwz r2,SL_R2(r1)
2529 + lmw r12,SL_R12(r1)
2530 +- addi r1,r1,SL_SIZE
2531 +- lwz r0,4(r1)
2532 +- mtlr r0
2533 +- blr
2534 +-_ASM_NOKPROBE_SYMBOL(grackle_wake_up)
2535 +
2536 +-turn_on_mmu:
2537 +- mflr r4
2538 +- tovirt(r4,r4)
2539 ++ /* restore the MSR and SP and turn on the MMU and return */
2540 ++ lwz r3,SL_MSR(r1)
2541 ++ lwz r4,SL_LR(r1)
2542 ++ lwz r1,SL_SP(r1)
2543 + mtsrr0 r4
2544 + mtsrr1 r3
2545 + sync
2546 + isync
2547 + rfi
2548 +-_ASM_NOKPROBE_SYMBOL(turn_on_mmu)
2549 ++_ASM_NOKPROBE_SYMBOL(grackle_wake_up)
2550 +
2551 + #endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */
2552 +
2553 +- .section .data
2554 ++ .section .bss
2555 + .balign L1_CACHE_BYTES
2556 + sleep_storage:
2557 +- .long 0
2558 ++ .space SL_SIZE
2559 + .balign L1_CACHE_BYTES, 0
2560 +
2561 + #endif /* CONFIG_PPC_BOOK3S_32 */
2562