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commit: e571947b96baf9928b009d774632f2f17dafe943 |
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Author: Mike Pagano <mpagano <AT> gentoo <DOT> org> |
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AuthorDate: Sat Aug 21 14:27:10 2021 +0000 |
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Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org> |
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CommitDate: Sat Aug 21 14:27:10 2021 +0000 |
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URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=e571947b |
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|
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Update to CPU Optimization patch (USE=experiental) |
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|
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Signed-off-by: Mike Pagano <mpagano <AT> gentoo.org> |
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|
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5010_enable-cpu-optimizations-universal.patch | 18 +++++++++--------- |
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1 file changed, 9 insertions(+), 9 deletions(-) |
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|
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diff --git a/5010_enable-cpu-optimizations-universal.patch b/5010_enable-cpu-optimizations-universal.patch |
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index c45d13b..e37528f 100644 |
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--- a/5010_enable-cpu-optimizations-universal.patch |
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+++ b/5010_enable-cpu-optimizations-universal.patch |
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@@ -219,7 +219,7 @@ index 814fe0d349b0..8acf6519d279 100644 |
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+ |
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+config MZEN3 |
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+ bool "AMD Zen 3" |
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-+ depends on ( CC_IS_GCC && GCC_VERSION >= 100300 ) || ( CC_IS_CLANG && CLANG_VERSION >= 120000 ) |
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++ depends on (CC_IS_GCC && GCC_VERSION >= 100300) || (CC_IS_CLANG && CLANG_VERSION >= 120000) |
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+ help |
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+ Select this for AMD Family 19h Zen 3 processors. |
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+ |
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@@ -378,7 +378,7 @@ index 814fe0d349b0..8acf6519d279 100644 |
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+ |
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+config MCOOPERLAKE |
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+ bool "Intel Cooper Lake" |
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-+ depends on ( CC_IS_GCC && GCC_VERSION > 100100 ) || ( CC_IS_CLANG && CLANG_VERSION >= 100000 ) |
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++ depends on (CC_IS_GCC && GCC_VERSION > 100100) || (CC_IS_CLANG && CLANG_VERSION >= 100000) |
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+ select X86_P6_NOP |
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+ help |
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+ |
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@@ -388,7 +388,7 @@ index 814fe0d349b0..8acf6519d279 100644 |
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+ |
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+config MTIGERLAKE |
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+ bool "Intel Tiger Lake" |
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-+ depends on ( CC_IS_GCC && GCC_VERSION > 100100 ) || ( CC_IS_CLANG && CLANG_VERSION >= 100000 ) |
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++ depends on (CC_IS_GCC && GCC_VERSION > 100100) || (CC_IS_CLANG && CLANG_VERSION >= 100000) |
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+ select X86_P6_NOP |
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+ help |
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+ |
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@@ -398,7 +398,7 @@ index 814fe0d349b0..8acf6519d279 100644 |
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+ |
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+config MSAPPHIRERAPIDS |
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+ bool "Intel Sapphire Rapids" |
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-+ depends on ( CC_IS_GCC && GCC_VERSION > 110000 ) || ( CC_IS_CLANG && CLANG_VERSION >= 120000 ) |
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++ depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000) |
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+ select X86_P6_NOP |
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+ help |
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+ |
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@@ -408,7 +408,7 @@ index 814fe0d349b0..8acf6519d279 100644 |
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+ |
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+config MROCKETLAKE |
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+ bool "Intel Rocket Lake" |
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-+ depends on ( CC_IS_GCC && GCC_VERSION > 110000 ) || ( CC_IS_CLANG && CLANG_VERSION >= 120000 ) |
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++ depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000) |
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+ select X86_P6_NOP |
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+ help |
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+ |
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@@ -418,7 +418,7 @@ index 814fe0d349b0..8acf6519d279 100644 |
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+ |
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+config MALDERLAKE |
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+ bool "Intel Alder Lake" |
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-+ depends on ( CC_IS_GCC && GCC_VERSION > 110000 ) || ( CC_IS_CLANG && CLANG_VERSION >= 120000 ) |
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++ depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000) |
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+ select X86_P6_NOP |
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+ help |
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+ |
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@@ -435,7 +435,7 @@ index 814fe0d349b0..8acf6519d279 100644 |
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|
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+config GENERIC_CPU2 |
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+ bool "Generic-x86-64-v2" |
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-+ depends on ( CC_IS_GCC && GCC_VERSION > 110000 ) || ( CC_IS_CLANG && LANG_VERSION >= 120000 ) |
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++ depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000) |
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+ depends on X86_64 |
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+ help |
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+ Generic x86-64 CPU. |
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@@ -443,7 +443,7 @@ index 814fe0d349b0..8acf6519d279 100644 |
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+ |
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+config GENERIC_CPU3 |
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+ bool "Generic-x86-64-v3" |
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-+ depends on ( CC_IS_GCC && GCC_VERSION > 110000 ) || ( CC_IS_CLANG && LANG_VERSION >= 120000 ) |
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++ depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000) |
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+ depends on X86_64 |
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+ help |
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+ Generic x86-64-v3 CPU with v3 instructions. |
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@@ -451,7 +451,7 @@ index 814fe0d349b0..8acf6519d279 100644 |
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+ |
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+config GENERIC_CPU4 |
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+ bool "Generic-x86-64-v4" |
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-+ depends on ( CC_IS_GCC && GCC_VERSION > 110000 ) || ( CC_IS_CLANG && LANG_VERSION >= 120000 ) |
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++ depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000) |
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+ depends on X86_64 |
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+ help |
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+ Generic x86-64 CPU with v4 instructions. |
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