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On 07/09/2014 01:40 PM, Anthony G. Basile wrote: |
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> On 07/09/14 05:09, Joshua Kinard wrote: |
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>> On 07/08/2014 21:48, Matthew Thode wrote: |
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>>> arm has a historical problem with stabilization, while keywording |
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>>> doesn't require access to all arm sub-arches the problem with the |
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>>> stabilization slowness causes running a full ~arm to become hard. By |
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>>> that I mean that if someone keywords something for arm because it works |
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>>> on armv7 and I run ~arm because stabilization takes forever then my |
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>>> system may break because of both non-stabilized packages and because I |
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>>> could be running armv6. |
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>>> |
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>>> In any case I propose splitting out arm into armv4, armv5, armv6 and |
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>>> armv7. armv8 seems to be here already as arm64. |
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>> Couldn't this be better handled with some profile work? These sound like |
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>> versions of Instruction Set Architectures. In the MIPS world, you |
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>> have your |
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>> original ISAs, mips1 through mips4, then you have the newer variants of |
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>> mips32r* (branches from mips2) and mips64r* (branches from mips4). |
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>> Anything |
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>> supporting mips4 could also support earlier ISAs. Throw in our three |
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>> supported ABIs (o32, n32, n64), and machine-specific curiosities (SGI, |
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>> Cobalt, Yeelong/Loongson, etc), and life can be quite fun. But we can |
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>> cover |
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>> all of this with just a single 'mips' keyword in the tree. |
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> |
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> Yes, this should be done via the profiles. Code requiring later ISAs |
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> and/or with extensions like thumb and neon will probably break on lower |
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> ISAs. These should be masked on the profiles. |
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> |
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>> Is that similar to how these ARM variants work? Can an armv7 run code |
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>> for |
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>> armv6 and earlier? |
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> |
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> Its a bit more complicated that MIPS. You can test for yourself. I did |
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> this via a chromebook (cortex-a15) using my hardened stages |
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> (march=armv7a) available at <mirror>/experimental/arm/hardened, so you |
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> can test too: |
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> |
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> chrome ~ # echo "int main() { return 0; }" > test.c |
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> chrome ~ # gcc -march=armv7-a -o test test.c |
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> chrome ~ # gcc -march=armv6 -o test test.c |
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> chrome ~ # gcc -march=armv5 -o test test.c |
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> chrome ~ # gcc -march=armv4 -o test test.c |
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> chrome ~ # gcc -march=armv3 -o test test.c |
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> /tmp/ccZjsI2O.s: Assembler messages: |
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> /tmp/ccZjsI2O.s:45: Error: selected processor does not support ARM mode |
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> `bx lr' |
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> chrome ~ # gcc -march=armv3m -o test test.c |
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> /tmp/cc1o59kQ.s: Assembler messages: |
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> /tmp/cc1o59kQ.s:45: Error: selected processor does not support ARM mode |
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> `bx lr' |
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> chrome ~ # gcc -march=armv2 -o test test.c |
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> /tmp/ccmTNSyh.s: Assembler messages: |
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> /tmp/ccmTNSyh.s:45: Error: selected processor does not support ARM mode |
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> `bx lr' |
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> chrome ~ # gcc -march=armv2a -o test test.c |
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> /tmp/ccTIXZ46.s: Assembler messages: |
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> /tmp/ccTIXZ46.s:45: Error: selected processor does not support ARM mode |
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> `bx lr' |
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> chrome ~ # gcc --version |
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> gcc (Gentoo Hardened 4.7.3-r1 p1.4, pie-0.5.5) 4.7.3 |
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> Copyright (C) 2012 Free Software Foundation, Inc. |
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> This is free software; see the source for copying conditions. There is NO |
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> warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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> |
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> |
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> So it looks like gcc can emit compat code back to armv4. This doesn't |
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> necessarily mean that armv2 code won't run on an armv7a, but that |
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> gcc-4.7.3-r1 can't produce such code, which is sufficient for our |
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> purposes of masking. |
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> |
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> |
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>> |
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>> Splitting 'arm' into four new keywords, on top of 'arm64' is just |
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>> going to |
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>> give you guys major headaches later. You might even consider |
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>> dedicated USE |
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>> flags for the arm subvariants and use those to control things in an |
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>> ebuild |
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>> where applicable. |
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> |
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> arm64 might as well be a totally different arch. There is no |
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> compatibility between 32-bit and 64-bit arm variants --- at least not |
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> that I know of, its a new arch that I'm just now getting familiar with. |
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> On the other hand ppc and ppc64 should never have been split, but that's |
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> another story. |
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> |
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> We do not want keywords for every subarch otherwise we'll go crazy |
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> stabilizing. We could adopt a policy of stabilizing on armv7a and when |
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> a package doesn't build on a lower ISA, just mask it in the profiles. |
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> |
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>> |
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>>> I think this would be beneficial because of not all developers that want |
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>>> to help with arm have or what all the sub-arches necessary. It also |
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>>> allows us to move faster on stabilization because most of us have access |
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>>> to armv7 a bit easier. This would take some pressure off of the people |
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>>> doing stabilization for older sub-arches, but not much. |
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>> What's the support status of Gentoo on the older variants, such as |
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>> armv4 and |
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>> armv5 stuff? How fast is the CPU clock on those? Do they include L2/L3 |
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>> cache? Lots of memory? Generally, anything that could be a |
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>> bottleneck or |
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>> severely increase the build time should be weighed against the potential |
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>> number of users and possibly support dropped if there aren't enough |
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>> developers or contributing users to maintain it. |
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>> |
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>> I.e., w/ MIPS, we don't support anything under the mips3 ISA, which |
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>> includes |
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>> DECStations (Debian does support those). Build times would just be |
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>> tremendously slow and I haven't seen a lot of desire to support those. |
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>> |
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> |
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> Regarding MIPS, this isn't totally true. I'm willing to support mips-I |
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> for embedded systems, although right now I'm just doing mipsel3 and |
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> mip32r2. I used to have mips-I big endian uclibc stages. Also, you |
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> don't have to hit slow build times because you can build mips-I on any |
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> mips system of the same endianness. |
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> |
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> |
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|
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I think arm64 is getting keyworded using qemu, because nobody owns any |
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hardware yet. Can't we use qemu for armv5, too? |
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You won't need any additional hardware to handle stabilization. Just |
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test on armv7 hw and in your qemu instance. |
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Cheers |
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|
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Manuel |