Gentoo Archives: gentoo-dev

From: Maurice Hilarius <maurice@××××××××.com>
To: gentoo-dev@g.o
Subject: [gentoo-dev] Amd "bug" myth
Date: Mon, 21 Jan 2002 20:46:53
Message-Id: MK53EAKF64KB8XUGAZJWSWSQMJHTN.3c4cce81@maurice2
1 I read the note on your web page with interest, however, I have the unpleasant task of correcting you:
3 Simply put, this is NOT a "bug in the CPU"
4 It simply means that the CPU responds to a certain, arcane, and Pentium-specific mode differently than a Pentium chip.
5 As this mode is processor model specific, unless it is used on a Pentium, is a bug in Linux code.
6 Older Intel chips do not respond to this mode, and this, among a slew of other differences is why we have "i386", "1586", "1686" and "Athlon" specific codes in the Linux tree.
8 The fact that up to now Linus and others have not addressed this difference does not make it a bug.
9 It DOES make it a Linux "oversight", or as Intel calls it, an "errata", or perhaps a "sighting"
11 It is a misconception that all CPUs have to perfectly emulate Pentiums.
12 Because an Alpha, Motorola, SPARC, or PA-RISC chip does not emulate Pentium architecture, are these CPUs somehow "flawed"?
14 If you want to see a REAL bug, and one that both severely cripples performance and is NOT fixable, look at this "errata" in the Intel 860 chipset ( the chipset for dual XEON P4 motherboards):
16 In the file found at:
19 Intel lists errata for the 860 chipset.
20 One of these states:
22 "5. Sustained PCI Bandwidth Problem:
23 During a memory read multiple operation, a PCI master will read more than one complete cache line from memory. In this situation, the MCH pre-fetches information from memory to provide
24 optimal performance. However, the MCH cannot provide information to the PCI master fast enough. Therefore, the ICH2 terminates the read cycle early to free up the PCI bus for other PCI
25 masters to claim.
27 Implication: The early termination limits the maximum bandwidth to ~90 MB/s.
29 Workaround: None
31 Status: Intel has no fix planned for this erratum."
33 This effectively limits the bandwidth of the PCI bus to 90MB per second.
34 Considering this is a chipset designed for servers, and is equipped with PCI slots at 64 bit, and 66MHz, it should have a bandwidth of over 300MB/sec.
35 If you buy one of these, and spend money on high performance SCSI, gigabit, or other devices, you are wasting your $$.
37 With our best regards,
39 Maurice W. Hilarius Telephone: 01-780-456-9771
40 Hard Data Ltd. FAX: 01-780-456-9772
41 11060 - 166 Avenue mailto:maurice@××××××××.com
42 Edmonton, AB, Canada
43 T5X 1Y3