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As someone else mentioned, my guess would be it's turned off on the board. If there's no bios setting, how about a jumper on the board? There has to be some way to turn it on/off. |
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-----Original Message----- |
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From: A. Khattri [mailto:ajai@××××.net] |
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Sent: Sun 9/25/2005 1:36 AM |
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To: gentoo-server@l.g.o |
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Cc: |
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Subject: Re: [gentoo-server] HT on P4? |
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On Fri, 23 Sep 2005, Joao Patricio wrote: |
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|
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> Did you enable SMP when you compiled your kernel? |
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|
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Both SMP and SMT are enabled in this kernel: |
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|
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# grep SMP /usr/src/linux/.config |
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|
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# CONFIG_X86_BIGSMP is not set |
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CONFIG_SMP=y |
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CONFIG_X86_FIND_SMP_CONFIG=y |
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CONFIG_X86_SMP=y |
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|
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# grep SMT /usr/src/linux/.config |
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|
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CONFIG_SCHED_SMT=y |
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|
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|
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|
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> |
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> Em Sexta, 23 de Setembro de 2005 23:05, o A. Khattri escreveu: |
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> > On Fri, 23 Sep 2005, kashani wrote: |
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> > > A. Khattri wrote: |
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> > > > I switched on SMP and HT when building my kernel but I see this among |
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> > > > the boot messages: |
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> > > > |
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> > > > CPU: After generic identify, caps: bfebfbff 00000000 00000000 00000000 |
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> > > > 0000441d 00000000 00000000 |
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> > > > CPU: After vendor identify, caps: bfebfbff 00000000 00000000 00000000 |
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> > > > 0000441d 00000000 00000000 |
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> > > > monitor/mwait feature present. |
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> > > > using mwait in idle threads. |
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> > > > CPU: Trace cache: 12K uops, L1 D cache: 16K |
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> > > > CPU: L2 cache: 1024K |
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> > > > CPU: Hyper-Threading is disabled |
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> > > |
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> > > Is it possible it's disabled in the Bios? Some servers shipped that way |
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> > > when they first came out IIRC. |
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> > |
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> > I didn't find any BIOS setting unfortunately... |
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> > |
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> > This is a Supermicro 5013C-T server with a P4 (P4SCE?) board in it. |
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> > |
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> > # cat /proc/cpuinfo |
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> > processor : 0 |
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> > vendor_id : GenuineIntel |
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> > cpu family : 15 |
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> > model : 4 |
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> > model name : Intel(R) Pentium(R) 4 CPU 2.40GHz |
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> > stepping : 1 |
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> > cpu MHz : 2395.003 |
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> > cache size : 1024 KB |
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> > fdiv_bug : no |
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> > hlt_bug : no |
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> > f00f_bug : no |
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> > coma_bug : no |
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> > fpu : yes |
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> > fpu_exception : yes |
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> > cpuid level : 5 |
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> > wp : yes |
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> > flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca |
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> > cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni monitor |
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> > ds_cpl cid xtpr |
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> > bogomips : 4718.59 |
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> > |
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> > |
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> > -- |
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> |
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|
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-- |
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wheel of reincarnation |
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|
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[coined in a paper by T. H. Myer |
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and I.E. Sutherland "On the Design of Display Processors", Comm. |
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ACM, Vol. 11, no. 6, June 1968)] Term used to refer to a well-known |
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effect whereby function in a computing system family is migrated |
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out to special-purpose peripheral hardware for speed, then the |
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peripheral evolves toward more computing power as it does its job, |
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then somebody notices that it is inefficient to support two |
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asymmetrical processors in the architecture and folds the function |
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back into the main CPU, at which point the cycle begins again. |
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|
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Several iterations of this cycle have been observed in |
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graphics-processor design, and at least one or two in |
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communications and floating-point processors. Also known as `the |
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Wheel of Life', `the Wheel of Samsara', and other variations of |
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the basic Hindu/Buddhist theological idea. See also blitter, |
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bit bang. |
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|
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-- |
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