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Did you enable SMP when you compiled your kernel? |
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Em Sexta, 23 de Setembro de 2005 23:05, o A. Khattri escreveu: |
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> On Fri, 23 Sep 2005, kashani wrote: |
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> > A. Khattri wrote: |
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> > > I switched on SMP and HT when building my kernel but I see this among |
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> > > the boot messages: |
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> > > |
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> > > CPU: After generic identify, caps: bfebfbff 00000000 00000000 00000000 |
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> > > 0000441d 00000000 00000000 |
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> > > CPU: After vendor identify, caps: bfebfbff 00000000 00000000 00000000 |
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> > > 0000441d 00000000 00000000 |
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> > > monitor/mwait feature present. |
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> > > using mwait in idle threads. |
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> > > CPU: Trace cache: 12K uops, L1 D cache: 16K |
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> > > CPU: L2 cache: 1024K |
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> > > CPU: Hyper-Threading is disabled |
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> > |
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> > Is it possible it's disabled in the Bios? Some servers shipped that way |
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> > when they first came out IIRC. |
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> |
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> I didn't find any BIOS setting unfortunately... |
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> |
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> This is a Supermicro 5013C-T server with a P4 (P4SCE?) board in it. |
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> |
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> # cat /proc/cpuinfo |
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> processor : 0 |
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> vendor_id : GenuineIntel |
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> cpu family : 15 |
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> model : 4 |
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> model name : Intel(R) Pentium(R) 4 CPU 2.40GHz |
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> stepping : 1 |
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> cpu MHz : 2395.003 |
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> cache size : 1024 KB |
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> fdiv_bug : no |
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> hlt_bug : no |
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> f00f_bug : no |
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> coma_bug : no |
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> fpu : yes |
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> fpu_exception : yes |
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> cpuid level : 5 |
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> wp : yes |
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> flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca |
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> cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni monitor |
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> ds_cpl cid xtpr |
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> bogomips : 4718.59 |
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> |
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> |
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> -- |
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-- |
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