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Nevermind, I found the bug. I subtly broke UltraSPARC-III and |
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later chips by accident. |
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|
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This patch should fix it: |
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|
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[SPARC64]: Fix __cheetah_flush_tlb_pending instruction count. |
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|
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The recent membar changes broke the UltraSPARC-III code patching. |
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|
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Signed-off-by: David S. Miller <davem@×××××××××.net> |
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|
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--- 1/arch/sparc64/mm/ultra.S.~1~ 2005-07-05 17:16:49.000000000 -0700 |
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+++ 2/arch/sparc64/mm/ultra.S 2005-07-05 18:32:05.000000000 -0700 |
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@@ -249,7 +249,7 @@ |
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retl |
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wrpr %g7, 0x0, %pstate |
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|
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-__cheetah_flush_tlb_pending: /* 22 insns */ |
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+__cheetah_flush_tlb_pending: /* 23 insns */ |
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/* %o0 = context, %o1 = nr, %o2 = vaddrs[] */ |
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rdpr %pstate, %g7 |
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sllx %o1, 3, %o1 |
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@@ -317,7 +317,7 @@ |
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sethi %hi(__cheetah_flush_tlb_pending), %o1 |
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or %o1, %lo(__cheetah_flush_tlb_pending), %o1 |
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call cheetah_patch_one |
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- mov 22, %o2 |
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+ mov 23, %o2 |
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|
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#ifdef DCACHE_ALIASING_POSSIBLE |
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sethi %hi(__flush_dcache_page), %o0 |
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-- |
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