Gentoo Archives: gentoo-user

From: james <garftd@×××××××.net>
To: gentoo-user@l.g.o
Subject: Re: [gentoo-user] march cflag for Intel Pentium Dual-Core E2160 SLA8Z Malay processor
Date: Mon, 24 Sep 2018 15:50:00
Message-Id: 633b6734-7306-b6a0-1525-5daa958fcd2c@verizon.net
In Reply to: Re: [gentoo-user] march cflag for Intel Pentium Dual-Core E2160 SLA8Z Malay processor by Walter Dnes
1 On 9/23/18 3:09 AM, Walter Dnes wrote:
2 > On Thu, Sep 20, 2018 at 01:00:39AM +0300, gevisz wrote
3 >> ????, 19 ????????. 2018 ??. ?? 11:38, Walter Dnes <waltdnes@××××××××.org>:
4 >
5 >>> According to
6 >>> http://www.cpu-world.com/sspec/SL/SLA8Z.html it has...
7 >>>
8 >>> MMX SSE SSE2 SSE3 SSSE3
9 >>
10 >> Do you mean that it would be enough to set
11 >> CFLAGS="-O2 -pipe mmx sse sse2 sse3 ssse3"
12 >> without setting the march cflag at all?
13 >
14 > Yes, that would work. Remember also to include in make.conf
15 >
16 > CPU_FLAGS_X86="mmx mmxext sse sse2 sse3 ssse3"
17 >
18 > In your jpeg image, I see that the flags include mmx, sse, sse2, pni,
19 > and ssse3. "pni" == "Prescott New Instructions" == "SSE3". Looking at
20 > https://gcc.gnu.org/onlinedocs/gcc-7.3.0/gcc/x86-Options.html#x86-Options
21 > I suggest "-march=core2" with CPU_FLAGS_X86 same as above. The "core2"
22 > option uses MMX, SSE, SSE2, SSE3 and SSSE3 instructions, all of which
23 > show up in the listing on your jpeg.
24 >
25 > https://en.wikipedia.org/wiki/SSE3
26 >> SSE3, Streaming SIMD Extensions 3, also known by its Intel code name
27 >> Prescott New Instructions (PNI), is the third iteration of the SSE
28 >> instruction set for the IA-32 (x86) architecture.
29 >
30
31
32 https://wiki.gentoo.org/wiki/CPU_FLAGS_X86
33
34 and similar wiki pages are good links to reference.
35 MG (M. Gorny) has blogged on this subject too::
36
37 https://nlug.ml1.co.uk/2016/09/gentoo-portage-cpu_flags_x86-introduction-2015-01-28/5332
38
39 I'd be interested in blogs, irc, docs, etc, where distcc is being used
40 as part of a (gentoo-centric) CI/CD and/or cross-compiling for
41 smaller/older target systems, of any architecture (arm or mips or x86 or ?).
42
43
44 James