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Deven Lahoti <deywos <at> mit.edu> writes: |
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> Gentoo has been ported to the RISC-V architecture, which you can run |
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> on an FPGA using Berkeley's free (as in freedom) implementation: |
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> https://github.com/palmer-dabbelt/riscv-gentoo |
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> https://github.com/ucb-bar/rocket-chip |
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All good to know. Have you actually installed Gentoo on a fpga dev-board |
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running any of the open source cores? |
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If so any blog, docs, or other postings or a how? |
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> the 4th annual RISC-V workshop was last week; hopefully the |
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> proceedings will be up soon. |
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Do post if you review them and have favourites or strong recommendations on |
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which ones to look at.... |
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Has anyone using the j-core or any other fpga(gentoo) board been successful |
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at using (hardware) components from opencores.org on such hardware? |
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Is there a repo for Rics-v (SH) extra modules, advance ram (multiport) etc? |
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I did find this reference on the various patent-free similar projects:: |
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https://lwn.net/Articles/647636/ |
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I sure hope the SH-4 core is ready for testing? SMP and multiport ram |
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are of keen interest to me, to port some distributed cluster codes and |
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Distributed File Systems (OrangeFS) for performance testing. Is there a |
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gentoo channel or ML on these patent-free cores, gentoo-emebedded the |
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default channel? |
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Is there a default fpga board the gentoo community is using on these |
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superH/riscv/openrisc projects? SH4 does sound very interesting (with mmu). |
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> deven |
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Thanks very much for your response, |
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James |
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> > http://j-core.org/?HN_20160716 |
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