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Strictly speaking, iWMMXt is a coprocessor of the ARM, not a CPU, so |
| 2 |
technically it is like an FPU except that it does not do floating |
| 3 |
point, so it is modelled as a cpu in GCC, with an instruction set that |
| 4 |
is a superset of the armv5te set. It's a bit like the difference |
| 5 |
between pentium and pentium MMX. It only exists in silicon as a |
| 6 |
coprocessor for armv5te cores as far as I know, hence "iwmmxt is |
| 7 |
armv5te with extra stuff". |
| 8 |
Yes, it has its own old-ABI, which requires 8-byte alignment of |
| 9 |
double words. EABI (v4) has this anyway so it may work. |
| 10 |
Furthermore, it hijacks the same coprocessor interface as the old |
| 11 |
FPA floating point accelerator, or in other words, the bit patterns of |
| 12 |
its instructions overlap with the FPA instruction set, so you must use |
| 13 |
soft float and cannot use kernel emulation of FPA instructions. That's |
| 14 |
not really a problem since no silicon exists with both iwmmxt coproc |
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and a real FPU of any kind, so you would want to use softfloat anyway. |
| 16 |
The main instructions that iwmmxt adds to the armv5te set are real |
| 17 |
64-bit integer operations and a slew of vector instructions for those |
| 18 |
tight inner loops. Whether it works, of course... have you tried |
| 19 |
building gcc for it and running the testsuite on iwmmxt hardware? Prod |
| 20 |
me if you need runes to do this. |
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| 22 |
> gcc fails saying that "-march=armv5te -mtune=iwmmxt" is not kosher |
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Indeed. iwmmxt is modeled as both a cpu and an ISA, but unless there |
| 25 |
are iwmmxt insns included, the tuning would be a no-op. It would be |
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like cpu=armv4 arch=armv4t - the armv4 can't run all armv4t |
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instructions. |
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Did you run into problems with cpu=iwmmxt? |
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M |
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